drivers/net/wireless/ath/ath9k/main.c

   1 /*
   2  * Copyright (c) 2008-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/nl80211.h>
  18 #include <linux/delay.h>
  19 #include "ath9k.h"
  20 #include "btcoex.h"
  21
  22 u8 ath9k_parse_mpdudensity(u8 mpdudensity)
  23 {
  24         /*
  25          * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
  26          *   0 for no restriction
  27          *   1 for 1/4 us
  28          *   2 for 1/2 us
  29          *   3 for 1 us
  30          *   4 for 2 us
  31          *   5 for 4 us
  32          *   6 for 8 us
  33          *   7 for 16 us
  34          */
  35         switch (mpdudensity) {
  36         case 0:
  37                 return 0;
  38         case 1:
  39         case 2:
  40         case 3:
  41                 /* Our lower layer calculations limit our precision to
  42                    1 microsecond */
  43                 return 1;
  44         case 4:
  45                 return 2;
  46         case 5:
  47                 return 4;
  48         case 6:
  49                 return 8;
  50         case 7:
  51                 return 16;
  52         default:
  53                 return 0;
  54         }
  55 }
  56
  57 static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq,
  58                                      bool sw_pending)
  59 {
  60         bool pending = false;
  61
  62         spin_lock_bh(&txq->axq_lock);
  63
  64         if (txq->axq_depth) {
  65                 pending = true;
  66                 goto out;
  67         }
  68
  69         if (!sw_pending)
  70                 goto out;
  71
  72         if (txq->mac80211_qnum >= 0) {
  73                 struct list_head *list;
  74
  75                 list = &sc->cur_chan->acq[txq->mac80211_qnum];
  76                 if (!list_empty(list))
  77                         pending = true;
  78         }
  79 out:
  80         spin_unlock_bh(&txq->axq_lock);
  81         return pending;
  82 }
  83
  84 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
  85 {
  86         unsigned long flags;
  87         bool ret;
  88
  89         spin_lock_irqsave(&sc->sc_pm_lock, flags);
  90         ret = ath9k_hw_setpower(sc->sc_ah, mode);
  91         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  92
  93         return ret;
  94 }
  95
  96 void ath_ps_full_sleep(unsigned long data)
  97 {
  98         struct ath_softc *sc = (struct ath_softc *) data;
  99         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 100         bool reset;
 101
 102         spin_lock(&common->cc_lock);
 103         ath_hw_cycle_counters_update(common);
 104         spin_unlock(&common->cc_lock);
 105
 106         ath9k_hw_setrxabort(sc->sc_ah, 1);
 107         ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
 108
 109         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
 110 }
 111
 112 void ath9k_ps_wakeup(struct ath_softc *sc)
 113 {
 114         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 115         unsigned long flags;
 116         enum ath9k_power_mode power_mode;
 117
 118         spin_lock_irqsave(&sc->sc_pm_lock, flags);
 119         if (++sc->ps_usecount != 1)
 120                 goto unlock;
 121
 122         del_timer_sync(&sc->sleep_timer);
 123         power_mode = sc->sc_ah->power_mode;
 124         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
 125
 126         /*
 127          * While the hardware is asleep, the cycle counters contain no
 128          * useful data. Better clear them now so that they don't mess up
 129          * survey data results.
 130          */
 131         if (power_mode != ATH9K_PM_AWAKE) {
 132                 spin_lock(&common->cc_lock);
 133                 ath_hw_cycle_counters_update(common);
 134                 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
 135                 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
 136                 spin_unlock(&common->cc_lock);
 137         }
 138
 139  unlock:
 140         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
 141 }
 142
 143 void ath9k_ps_restore(struct ath_softc *sc)
 144 {
 145         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 146         enum ath9k_power_mode mode;
 147         unsigned long flags;
 148
 149         spin_lock_irqsave(&sc->sc_pm_lock, flags);
 150         if (--sc->ps_usecount != 0)
 151                 goto unlock;
 152
 153         if (sc->ps_idle) {
 154                 mod_timer(&sc->sleep_timer, jiffies + HZ / 10);
 155                 goto unlock;
 156         }
 157
 158         if (sc->ps_enabled &&
 159                    !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
 160                                      PS_WAIT_FOR_CAB |
 161                                      PS_WAIT_FOR_PSPOLL_DATA |
 162                                      PS_WAIT_FOR_TX_ACK |
 163                                      PS_WAIT_FOR_ANI))) {
 164                 mode = ATH9K_PM_NETWORK_SLEEP;
 165                 if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
 166                         ath9k_btcoex_stop_gen_timer(sc);
 167         } else {
 168                 goto unlock;
 169         }
 170
 171         spin_lock(&common->cc_lock);
 172         ath_hw_cycle_counters_update(common);
 173         spin_unlock(&common->cc_lock);
 174
 175         ath9k_hw_setpower(sc->sc_ah, mode);
 176
 177  unlock:
 178         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
 179 }
 180
 181 static void __ath_cancel_work(struct ath_softc *sc)
 182 {
 183         cancel_work_sync(&sc->paprd_work);
 184         cancel_delayed_work_sync(&sc->tx_complete_work);
 185         cancel_delayed_work_sync(&sc->hw_pll_work);
 186
 187 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
 188         if (ath9k_hw_mci_is_enabled(sc->sc_ah))
 189                 cancel_work_sync(&sc->mci_work);
 190 #endif
 191 }
 192
 193 void ath_cancel_work(struct ath_softc *sc)
 194 {
 195         __ath_cancel_work(sc);
 196         cancel_work_sync(&sc->hw_reset_work);
 197 }
 198
 199 void ath_restart_work(struct ath_softc *sc)
 200 {
 201         ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
 202
 203         if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9330(sc->sc_ah))
 204                 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
 205                                      msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
 206
 207         ath_start_ani(sc);
 208 }
 209
 210 static bool ath_prepare_reset(struct ath_softc *sc)
 211 {
 212         struct ath_hw *ah = sc->sc_ah;
 213         bool ret = true;
 214
 215         ieee80211_stop_queues(sc->hw);
 216         ath_stop_ani(sc);
 217         ath9k_hw_disable_interrupts(ah);
 218
 219         if (!ath_drain_all_txq(sc))
 220                 ret = false;
 221
 222         if (!ath_stoprecv(sc))
 223                 ret = false;
 224
 225         return ret;
 226 }
 227
 228 static bool ath_complete_reset(struct ath_softc *sc, bool start)
 229 {
 230         struct ath_hw *ah = sc->sc_ah;
 231         struct ath_common *common = ath9k_hw_common(ah);
 232         unsigned long flags;
 233
 234         ath9k_calculate_summary_state(sc, sc->cur_chan);
 235         ath_startrecv(sc);
 236         ath9k_cmn_update_txpow(ah, sc->cur_chan->cur_txpower,
 237                                sc->cur_chan->txpower,
 238                                &sc->cur_chan->cur_txpower);
 239         clear_bit(ATH_OP_HW_RESET, &common->op_flags);
 240
 241         if (!sc->cur_chan->offchannel && start) {
 242                 /* restore per chanctx TSF timer */
 243                 if (sc->cur_chan->tsf_val) {
 244                         u32 offset;
 245
 246                         offset = ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts,
 247                                                          NULL);
 248                         ath9k_hw_settsf64(ah, sc->cur_chan->tsf_val + offset);
 249                 }
 250
 251
 252                 if (!test_bit(ATH_OP_BEACONS, &common->op_flags))
 253                         goto work;
 254
 255                 if (ah->opmode == NL80211_IFTYPE_STATION &&
 256                     test_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags)) {
 257                         spin_lock_irqsave(&sc->sc_pm_lock, flags);
 258                         sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
 259                         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
 260                 } else {
 261                         ath9k_set_beacon(sc);
 262                 }
 263         work:
 264                 ath_restart_work(sc);
 265                 ath_txq_schedule_all(sc);
 266         }
 267
 268         sc->gtt_cnt = 0;
 269
 270         ath9k_hw_set_interrupts(ah);
 271         ath9k_hw_enable_interrupts(ah);
 272         ieee80211_wake_queues(sc->hw);
 273         ath9k_p2p_ps_timer(sc);
 274
 275         return true;
 276 }
 277
 278 static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan)
 279 {
 280         struct ath_hw *ah = sc->sc_ah;
 281         struct ath_common *common = ath9k_hw_common(ah);
 282         struct ath9k_hw_cal_data *caldata = NULL;
 283         bool fastcc = true;
 284         int r;
 285
 286         __ath_cancel_work(sc);
 287
 288         tasklet_disable(&sc->intr_tq);
 289         tasklet_disable(&sc->bcon_tasklet);
 290         spin_lock_bh(&sc->sc_pcu_lock);
 291
 292         if (!sc->cur_chan->offchannel) {
 293                 fastcc = false;
 294                 caldata = &sc->cur_chan->caldata;
 295         }
 296
 297         if (!hchan) {
 298                 fastcc = false;
 299                 hchan = ah->curchan;
 300         }
 301
 302         if (!ath_prepare_reset(sc))
 303                 fastcc = false;
 304
 305         if (ath9k_is_chanctx_enabled())
 306                 fastcc = false;
 307
 308         spin_lock_bh(&sc->chan_lock);
 309         sc->cur_chandef = sc->cur_chan->chandef;
 310         spin_unlock_bh(&sc->chan_lock);
 311
 312         ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
 313                 hchan->channel, IS_CHAN_HT40(hchan), fastcc);
 314
 315         r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
 316         if (r) {
 317                 ath_err(common,
 318                         "Unable to reset channel, reset status %d\n", r);
 319
 320                 ath9k_hw_enable_interrupts(ah);
 321                 ath9k_queue_reset(sc, RESET_TYPE_BB_HANG);
 322
 323                 goto out;
 324         }
 325
 326         if (ath9k_hw_mci_is_enabled(sc->sc_ah) &&
 327             sc->cur_chan->offchannel)
 328                 ath9k_mci_set_txpower(sc, true, false);
 329
 330         if (!ath_complete_reset(sc, true))
 331                 r = -EIO;
 332
 333 out:
 334         spin_unlock_bh(&sc->sc_pcu_lock);
 335         tasklet_enable(&sc->bcon_tasklet);
 336         tasklet_enable(&sc->intr_tq);
 337
 338         return r;
 339 }
 340
 341 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
 342                             struct ieee80211_vif *vif)
 343 {
 344         struct ath_node *an;
 345         an = (struct ath_node *)sta->drv_priv;
 346
 347         an->sc = sc;
 348         an->sta = sta;
 349         an->vif = vif;
 350         memset(&an->key_idx, 0, sizeof(an->key_idx));
 351
 352         ath_tx_node_init(sc, an);
 353
 354         ath_dynack_node_init(sc->sc_ah, an);
 355 }
 356
 357 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
 358 {
 359         struct ath_node *an = (struct ath_node *)sta->drv_priv;
 360         ath_tx_node_cleanup(sc, an);
 361
 362         ath_dynack_node_deinit(sc->sc_ah, an);
 363 }
 364
 365 void ath9k_tasklet(unsigned long data)
 366 {
 367         struct ath_softc *sc = (struct ath_softc *)data;
 368         struct ath_hw *ah = sc->sc_ah;
 369         struct ath_common *common = ath9k_hw_common(ah);
 370         enum ath_reset_type type;
 371         unsigned long flags;
 372         u32 status = sc->intrstatus;
 373         u32 rxmask;
 374
 375         ath9k_ps_wakeup(sc);
 376         spin_lock(&sc->sc_pcu_lock);
 377
 378         if (status & ATH9K_INT_FATAL) {
 379                 type = RESET_TYPE_FATAL_INT;
 380                 ath9k_queue_reset(sc, type);
 381
 382                 /*
 383                  * Increment the ref. counter here so that
 384                  * interrupts are enabled in the reset routine.
 385                  */
 386                 atomic_inc(&ah->intr_ref_cnt);
 387                 ath_dbg(common, RESET, "FATAL: Skipping interrupts\n");
 388                 goto out;
 389         }
 390
 391         if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
 392             (status & ATH9K_INT_BB_WATCHDOG)) {
 393                 spin_lock(&common->cc_lock);
 394                 ath_hw_cycle_counters_update(common);
 395                 ar9003_hw_bb_watchdog_dbg_info(ah);
 396                 spin_unlock(&common->cc_lock);
 397
 398                 if (ar9003_hw_bb_watchdog_check(ah)) {
 399                         type = RESET_TYPE_BB_WATCHDOG;
 400                         ath9k_queue_reset(sc, type);
 401
 402                         /*
 403                          * Increment the ref. counter here so that
 404                          * interrupts are enabled in the reset routine.
 405                          */
 406                         atomic_inc(&ah->intr_ref_cnt);
 407                         ath_dbg(common, RESET,
 408                                 "BB_WATCHDOG: Skipping interrupts\n");
 409                         goto out;
 410                 }
 411         }
 412
 413         if (status & ATH9K_INT_GTT) {
 414                 sc->gtt_cnt++;
 415
 416                 if ((sc->gtt_cnt >= MAX_GTT_CNT) && !ath9k_hw_check_alive(ah)) {
 417                         type = RESET_TYPE_TX_GTT;
 418                         ath9k_queue_reset(sc, type);
 419                         atomic_inc(&ah->intr_ref_cnt);
 420                         ath_dbg(common, RESET,
 421                                 "GTT: Skipping interrupts\n");
 422                         goto out;
 423                 }
 424         }
 425
 426         spin_lock_irqsave(&sc->sc_pm_lock, flags);
 427         if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
 428                 /*
 429                  * TSF sync does not look correct; remain awake to sync with
 430                  * the next Beacon.
 431                  */
 432                 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
 433                 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
 434         }
 435         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
 436
 437         if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
 438                 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
 439                           ATH9K_INT_RXORN);
 440         else
 441                 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
 442
 443         if (status & rxmask) {
 444                 /* Check for high priority Rx first */
 445                 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
 446                     (status & ATH9K_INT_RXHP))
 447                         ath_rx_tasklet(sc, 0, true);
 448
 449                 ath_rx_tasklet(sc, 0, false);
 450         }
 451
 452         if (status & ATH9K_INT_TX) {
 453                 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
 454                         /*
 455                          * For EDMA chips, TX completion is enabled for the
 456                          * beacon queue, so if a beacon has been transmitted
 457                          * successfully after a GTT interrupt, the GTT counter
 458                          * gets reset to zero here.
 459                          */
 460                         sc->gtt_cnt = 0;
 461
 462                         ath_tx_edma_tasklet(sc);
 463                 } else {
 464                         ath_tx_tasklet(sc);
 465                 }
 466
 467                 wake_up(&sc->tx_wait);
 468         }
 469
 470         if (status & ATH9K_INT_GENTIMER)
 471                 ath_gen_timer_isr(sc->sc_ah);
 472
 473         ath9k_btcoex_handle_interrupt(sc, status);
 474
 475         /* re-enable hardware interrupt */
 476         ath9k_hw_enable_interrupts(ah);
 477 out:
 478         spin_unlock(&sc->sc_pcu_lock);
 479         ath9k_ps_restore(sc);
 480 }
 481
 482 irqreturn_t ath_isr(int irq, void *dev)
 483 {
 484 #define SCHED_INTR (                            \
 485                 ATH9K_INT_FATAL |               \
 486                 ATH9K_INT_BB_WATCHDOG |         \
 487                 ATH9K_INT_RXORN |               \
 488                 ATH9K_INT_RXEOL |               \
 489                 ATH9K_INT_RX |                  \
 490                 ATH9K_INT_RXLP |                \
 491                 ATH9K_INT_RXHP |                \
 492                 ATH9K_INT_TX |                  \
 493                 ATH9K_INT_BMISS |               \
 494                 ATH9K_INT_CST |                 \
 495                 ATH9K_INT_GTT |                 \
 496                 ATH9K_INT_TSFOOR |              \
 497                 ATH9K_INT_GENTIMER |            \
 498                 ATH9K_INT_MCI)
 499
 500         struct ath_softc *sc = dev;
 501         struct ath_hw *ah = sc->sc_ah;
 502         struct ath_common *common = ath9k_hw_common(ah);
 503         enum ath9k_int status;
 504         u32 sync_cause = 0;
 505         bool sched = false;
 506
 507         /*
 508          * The hardware is not ready/present, don't
 509          * touch anything. Note this can happen early
 510          * on if the IRQ is shared.
 511          */
 512         if (!ah || test_bit(ATH_OP_INVALID, &common->op_flags))
 513                 return IRQ_NONE;
 514
 515         /* shared irq, not for us */
 516
 517         if (!ath9k_hw_intrpend(ah))
 518                 return IRQ_NONE;
 519
 520         if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) {
 521                 ath9k_hw_kill_interrupts(ah);
 522                 return IRQ_HANDLED;
 523         }
 524
 525         /*
 526          * Figure out the reason(s) for the interrupt.  Note
 527          * that the hal returns a pseudo-ISR that may include
 528          * bits we haven't explicitly enabled so we mask the
 529          * value to insure we only process bits we requested.
 530          */
 531         ath9k_hw_getisr(ah, &status, &sync_cause); /* NB: clears ISR too */
 532         ath9k_debug_sync_cause(sc, sync_cause);
 533         status &= ah->imask;    /* discard unasked-for bits */
 534
 535         /*
 536          * If there are no status bits set, then this interrupt was not
 537          * for me (should have been caught above).
 538          */
 539         if (!status)
 540                 return IRQ_NONE;
 541
 542         /* Cache the status */
 543         sc->intrstatus = status;
 544
 545         if (status & SCHED_INTR)
 546                 sched = true;
 547
 548         /*
 549          * If a FATAL interrupt is received, we have to reset the chip
 550          * immediately.
 551          */
 552         if (status & ATH9K_INT_FATAL)
 553                 goto chip_reset;
 554
 555         if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
 556             (status & ATH9K_INT_BB_WATCHDOG))
 557                 goto chip_reset;
 558
 559 #ifdef CONFIG_ATH9K_WOW
 560         if (status & ATH9K_INT_BMISS) {
 561                 if (atomic_read(&sc->wow_sleep_proc_intr) == 0) {
 562                         atomic_inc(&sc->wow_got_bmiss_intr);
 563                         atomic_dec(&sc->wow_sleep_proc_intr);
 564                 }
 565         }
 566 #endif
 567
 568         if (status & ATH9K_INT_SWBA)
 569                 tasklet_schedule(&sc->bcon_tasklet);
 570
 571         if (status & ATH9K_INT_TXURN)
 572                 ath9k_hw_updatetxtriglevel(ah, true);
 573
 574         if (status & ATH9K_INT_RXEOL) {
 575                 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
 576                 ath9k_hw_set_interrupts(ah);
 577         }
 578
 579         if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
 580                 if (status & ATH9K_INT_TIM_TIMER) {
 581                         if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
 582                                 goto chip_reset;
 583                         /* Clear RxAbort bit so that we can
 584                          * receive frames */
 585                         ath9k_setpower(sc, ATH9K_PM_AWAKE);
 586                         spin_lock(&sc->sc_pm_lock);
 587                         ath9k_hw_setrxabort(sc->sc_ah, 0);
 588                         sc->ps_flags |= PS_WAIT_FOR_BEACON;
 589                         spin_unlock(&sc->sc_pm_lock);
 590                 }
 591
 592 chip_reset:
 593
 594         ath_debug_stat_interrupt(sc, status);
 595
 596         if (sched) {
 597                 /* turn off every interrupt */
 598                 ath9k_hw_disable_interrupts(ah);
 599                 tasklet_schedule(&sc->intr_tq);
 600         }
 601
 602         return IRQ_HANDLED;
 603
 604 #undef SCHED_INTR
 605 }
 606
 607 /*
 608  * This function is called when a HW reset cannot be deferred
 609  * and has to be immediate.
 610  */
 611 int ath_reset(struct ath_softc *sc, struct ath9k_channel *hchan)
 612 {
 613         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 614         int r;
 615
 616         set_bit(ATH_OP_HW_RESET, &common->op_flags);
 617
 618         ath9k_ps_wakeup(sc);
 619         r = ath_reset_internal(sc, hchan);
 620         ath9k_ps_restore(sc);
 621
 622         return r;
 623 }
 624
 625 /*
 626  * When a HW reset can be deferred, it is added to the
 627  * hw_reset_work workqueue, but we set ATH_OP_HW_RESET before
 628  * queueing.
 629  */
 630 void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)
 631 {
 632         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 633 #ifdef CONFIG_ATH9K_DEBUGFS
 634         RESET_STAT_INC(sc, type);
 635 #endif
 636         set_bit(ATH_OP_HW_RESET, &common->op_flags);
 637         ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
 638 }
 639
 640 void ath_reset_work(struct work_struct *work)
 641 {
 642         struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
 643
 644         ath9k_ps_wakeup(sc);
 645         ath_reset_internal(sc, NULL);
 646         ath9k_ps_restore(sc);
 647 }
 648
 649 /**********************/
 650 /* mac80211 callbacks */
 651 /**********************/
 652
 653 static int ath9k_start(struct ieee80211_hw *hw)
 654 {
 655         struct ath_softc *sc = hw->priv;
 656         struct ath_hw *ah = sc->sc_ah;
 657         struct ath_common *common = ath9k_hw_common(ah);
 658         struct ieee80211_channel *curchan = sc->cur_chan->chandef.chan;
 659         struct ath_chanctx *ctx = sc->cur_chan;
 660         struct ath9k_channel *init_channel;
 661         int r;
 662
 663         ath_dbg(common, CONFIG,
 664                 "Starting driver with initial channel: %d MHz\n",
 665                 curchan->center_freq);
 666
 667         ath9k_ps_wakeup(sc);
 668         mutex_lock(&sc->mutex);
 669
 670         init_channel = ath9k_cmn_get_channel(hw, ah, &ctx->chandef);
 671         sc->cur_chandef = hw->conf.chandef;
 672
 673         /* Reset SERDES registers */
 674         ath9k_hw_configpcipowersave(ah, false);
 675
 676         /*
 677          * The basic interface to setting the hardware in a good
 678          * state is ``reset''.  On return the hardware is known to
 679          * be powered up and with interrupts disabled.  This must
 680          * be followed by initialization of the appropriate bits
 681          * and then setup of the interrupt mask.
 682          */
 683         spin_lock_bh(&sc->sc_pcu_lock);
 684
 685         atomic_set(&ah->intr_ref_cnt, -1);
 686
 687         r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
 688         if (r) {
 689                 ath_err(common,
 690                         "Unable to reset hardware; reset status %d (freq %u MHz)\n",
 691                         r, curchan->center_freq);
 692                 ah->reset_power_on = false;
 693         }
 694
 695         /* Setup our intr mask. */
 696         ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
 697                     ATH9K_INT_RXORN | ATH9K_INT_FATAL |
 698                     ATH9K_INT_GLOBAL;
 699
 700         if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
 701                 ah->imask |= ATH9K_INT_RXHP |
 702                              ATH9K_INT_RXLP;
 703         else
 704                 ah->imask |= ATH9K_INT_RX;
 705
 706         if (ah->config.hw_hang_checks & HW_BB_WATCHDOG)
 707                 ah->imask |= ATH9K_INT_BB_WATCHDOG;
 708
 709         /*
 710          * Enable GTT interrupts only for AR9003/AR9004 chips
 711          * for now.
 712          */
 713         if (AR_SREV_9300_20_OR_LATER(ah))
 714                 ah->imask |= ATH9K_INT_GTT;
 715
 716         if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
 717                 ah->imask |= ATH9K_INT_CST;
 718
 719         ath_mci_enable(sc);
 720
 721         clear_bit(ATH_OP_INVALID, &common->op_flags);
 722         sc->sc_ah->is_monitoring = false;
 723
 724         if (!ath_complete_reset(sc, false))
 725                 ah->reset_power_on = false;
 726
 727         if (ah->led_pin >= 0) {
 728                 ath9k_hw_cfg_output(ah, ah->led_pin,
 729                                     AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
 730                 ath9k_hw_set_gpio(ah, ah->led_pin,
 731                                   (ah->config.led_active_high) ? 1 : 0);
 732         }
 733
 734         /*
 735          * Reset key cache to sane defaults (all entries cleared) instead of
 736          * semi-random values after suspend/resume.
 737          */
 738         ath9k_cmn_init_crypto(sc->sc_ah);
 739
 740         ath9k_hw_reset_tsf(ah);
 741
 742         spin_unlock_bh(&sc->sc_pcu_lock);
 743
 744         mutex_unlock(&sc->mutex);
 745
 746         ath9k_ps_restore(sc);
 747
 748         return 0;
 749 }
 750
 751 static void ath9k_tx(struct ieee80211_hw *hw,
 752                      struct ieee80211_tx_control *control,
 753                      struct sk_buff *skb)
 754 {
 755         struct ath_softc *sc = hw->priv;
 756         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 757         struct ath_tx_control txctl;
 758         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
 759         unsigned long flags;
 760
 761         if (sc->ps_enabled) {
 762                 /*
 763                  * mac80211 does not set PM field for normal data frames, so we
 764                  * need to update that based on the current PS mode.
 765                  */
 766                 if (ieee80211_is_data(hdr->frame_control) &&
 767                     !ieee80211_is_nullfunc(hdr->frame_control) &&
 768                     !ieee80211_has_pm(hdr->frame_control)) {
 769                         ath_dbg(common, PS,
 770                                 "Add PM=1 for a TX frame while in PS mode\n");
 771                         hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
 772                 }
 773         }
 774
 775         if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
 776                 /*
 777                  * We are using PS-Poll and mac80211 can request TX while in
 778                  * power save mode. Need to wake up hardware for the TX to be
 779                  * completed and if needed, also for RX of buffered frames.
 780                  */
 781                 ath9k_ps_wakeup(sc);
 782                 spin_lock_irqsave(&sc->sc_pm_lock, flags);
 783                 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
 784                         ath9k_hw_setrxabort(sc->sc_ah, 0);
 785                 if (ieee80211_is_pspoll(hdr->frame_control)) {
 786                         ath_dbg(common, PS,
 787                                 "Sending PS-Poll to pick a buffered frame\n");
 788                         sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
 789                 } else {
 790                         ath_dbg(common, PS, "Wake up to complete TX\n");
 791                         sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
 792                 }
 793                 /*
 794                  * The actual restore operation will happen only after
 795                  * the ps_flags bit is cleared. We are just dropping
 796                  * the ps_usecount here.
 797                  */
 798                 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
 799                 ath9k_ps_restore(sc);
 800         }
 801
 802         /*
 803          * Cannot tx while the hardware is in full sleep, it first needs a full
 804          * chip reset to recover from that
 805          */
 806         if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
 807                 ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
 808                 goto exit;
 809         }
 810
 811         memset(&txctl, 0, sizeof(struct ath_tx_control));
 812         txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
 813         txctl.sta = control->sta;
 814
 815         ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
 816
 817         if (ath_tx_start(hw, skb, &txctl) != 0) {
 818                 ath_dbg(common, XMIT, "TX failed\n");
 819                 TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
 820                 goto exit;
 821         }
 822
 823         return;
 824 exit:
 825         ieee80211_free_txskb(hw, skb);
 826 }
 827
 828 static void ath9k_stop(struct ieee80211_hw *hw)
 829 {
 830         struct ath_softc *sc = hw->priv;
 831         struct ath_hw *ah = sc->sc_ah;
 832         struct ath_common *common = ath9k_hw_common(ah);
 833         bool prev_idle;
 834
 835         ath9k_deinit_channel_context(sc);
 836
 837         mutex_lock(&sc->mutex);
 838
 839         ath_cancel_work(sc);
 840
 841         if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
 842                 ath_dbg(common, ANY, "Device not present\n");
 843                 mutex_unlock(&sc->mutex);
 844                 return;
 845         }
 846
 847         /* Ensure HW is awake when we try to shut it down. */
 848         ath9k_ps_wakeup(sc);
 849
 850         spin_lock_bh(&sc->sc_pcu_lock);
 851
 852         /* prevent tasklets to enable interrupts once we disable them */
 853         ah->imask &= ~ATH9K_INT_GLOBAL;
 854
 855         /* make sure h/w will not generate any interrupt
 856          * before setting the invalid flag. */
 857         ath9k_hw_disable_interrupts(ah);
 858
 859         spin_unlock_bh(&sc->sc_pcu_lock);
 860
 861         /* we can now sync irq and kill any running tasklets, since we already
 862          * disabled interrupts and not holding a spin lock */
 863         synchronize_irq(sc->irq);
 864         tasklet_kill(&sc->intr_tq);
 865         tasklet_kill(&sc->bcon_tasklet);
 866
 867         prev_idle = sc->ps_idle;
 868         sc->ps_idle = true;
 869
 870         spin_lock_bh(&sc->sc_pcu_lock);
 871
 872         if (ah->led_pin >= 0) {
 873                 ath9k_hw_set_gpio(ah, ah->led_pin,
 874                                   (ah->config.led_active_high) ? 0 : 1);
 875                 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
 876         }
 877
 878         ath_prepare_reset(sc);
 879
 880         if (sc->rx.frag) {
 881                 dev_kfree_skb_any(sc->rx.frag);
 882                 sc->rx.frag = NULL;
 883         }
 884
 885         if (!ah->curchan)
 886                 ah->curchan = ath9k_cmn_get_channel(hw, ah,
 887                                                     &sc->cur_chan->chandef);
 888
 889         ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
 890         ath9k_hw_phy_disable(ah);
 891
 892         ath9k_hw_configpcipowersave(ah, true);
 893
 894         spin_unlock_bh(&sc->sc_pcu_lock);
 895
 896         ath9k_ps_restore(sc);
 897
 898         set_bit(ATH_OP_INVALID, &common->op_flags);
 899         sc->ps_idle = prev_idle;
 900
 901         mutex_unlock(&sc->mutex);
 902
 903         ath_dbg(common, CONFIG, "Driver halt\n");
 904 }
 905
 906 static bool ath9k_uses_beacons(int type)
 907 {
 908         switch (type) {
 909         case NL80211_IFTYPE_AP:
 910         case NL80211_IFTYPE_ADHOC:
 911         case NL80211_IFTYPE_MESH_POINT:
 912                 return true;
 913         default:
 914                 return false;
 915         }
 916 }
 917
 918 static void ath9k_vif_iter(struct ath9k_vif_iter_data *iter_data,
 919                            u8 *mac, struct ieee80211_vif *vif)
 920 {
 921         struct ath_vif *avp = (struct ath_vif *)vif->drv_priv;
 922         int i;
 923
 924         if (iter_data->has_hw_macaddr) {
 925                 for (i = 0; i < ETH_ALEN; i++)
 926                         iter_data->mask[i] &=
 927                                 ~(iter_data->hw_macaddr[i] ^ mac[i]);
 928         } else {
 929                 memcpy(iter_data->hw_macaddr, mac, ETH_ALEN);
 930                 iter_data->has_hw_macaddr = true;
 931         }
 932
 933         if (!vif->bss_conf.use_short_slot)
 934                 iter_data->slottime = ATH9K_SLOT_TIME_20;
 935
 936         switch (vif->type) {
 937         case NL80211_IFTYPE_AP:
 938                 iter_data->naps++;
 939                 break;
 940         case NL80211_IFTYPE_STATION:
 941                 iter_data->nstations++;
 942                 if (avp->assoc && !iter_data->primary_sta)
 943                         iter_data->primary_sta = vif;
 944                 break;
 945         case NL80211_IFTYPE_ADHOC:
 946                 iter_data->nadhocs++;
 947                 if (vif->bss_conf.enable_beacon)
 948                         iter_data->beacons = true;
 949                 break;
 950         case NL80211_IFTYPE_MESH_POINT:
 951                 iter_data->nmeshes++;
 952                 if (vif->bss_conf.enable_beacon)
 953                         iter_data->beacons = true;
 954                 break;
 955         case NL80211_IFTYPE_WDS:
 956                 iter_data->nwds++;
 957                 break;
 958         default:
 959                 break;
 960         }
 961 }
 962
 963 static void ath9k_update_bssid_mask(struct ath_softc *sc,
 964                                     struct ath_chanctx *ctx,
 965                                     struct ath9k_vif_iter_data *iter_data)
 966 {
 967         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 968         struct ath_vif *avp;
 969         int i;
 970
 971         if (!ath9k_is_chanctx_enabled())
 972                 return;
 973
 974         list_for_each_entry(avp, &ctx->vifs, list) {
 975                 if (ctx->nvifs_assigned != 1)
 976                         continue;
 977
 978                 if (!avp->vif->p2p || !iter_data->has_hw_macaddr)
 979                         continue;
 980
 981                 ether_addr_copy(common->curbssid, avp->bssid);
 982
 983                 /* perm_addr will be used as the p2p device address. */
 984                 for (i = 0; i < ETH_ALEN; i++)
 985                         iter_data->mask[i] &=
 986                                 ~(iter_data->hw_macaddr[i] ^
 987                                   sc->hw->wiphy->perm_addr[i]);
 988         }
 989 }
 990
 991 /* Called with sc->mutex held. */
 992 void ath9k_calculate_iter_data(struct ath_softc *sc,
 993                                struct ath_chanctx *ctx,
 994                                struct ath9k_vif_iter_data *iter_data)
 995 {
 996         struct ath_vif *avp;
 997
 998         /*
 999          * Pick the MAC address of the first interface as the new hardware
1000          * MAC address. The hardware will use it together with the BSSID mask
1001          * when matching addresses.
1002          */
1003         memset(iter_data, 0, sizeof(*iter_data));
1004         memset(&iter_data->mask, 0xff, ETH_ALEN);
1005         iter_data->slottime = ATH9K_SLOT_TIME_9;
1006
1007         list_for_each_entry(avp, &ctx->vifs, list)
1008                 ath9k_vif_iter(iter_data, avp->vif->addr, avp->vif);
1009
1010         ath9k_update_bssid_mask(sc, ctx, iter_data);
1011 }
1012
1013 static void ath9k_set_assoc_state(struct ath_softc *sc,
1014                                   struct ieee80211_vif *vif, bool changed)
1015 {
1016         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1017         struct ath_vif *avp = (struct ath_vif *)vif->drv_priv;
1018         unsigned long flags;
1019
1020         set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1021
1022         ether_addr_copy(common->curbssid, avp->bssid);
1023         common->curaid = avp->aid;
1024         ath9k_hw_write_associd(sc->sc_ah);
1025
1026         if (changed) {
1027                 common->last_rssi = ATH_RSSI_DUMMY_MARKER;
1028                 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
1029
1030                 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1031                 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
1032                 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1033         }
1034
1035         if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1036                 ath9k_mci_update_wlan_channels(sc, false);
1037
1038         ath_dbg(common, CONFIG,
1039                 "Primary Station interface: %pM, BSSID: %pM\n",
1040                 vif->addr, common->curbssid);
1041 }
1042
1043 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1044 static void ath9k_set_offchannel_state(struct ath_softc *sc)
1045 {
1046         struct ath_hw *ah = sc->sc_ah;
1047         struct ath_common *common = ath9k_hw_common(ah);
1048         struct ieee80211_vif *vif = NULL;
1049
1050         ath9k_ps_wakeup(sc);
1051
1052         if (sc->offchannel.state < ATH_OFFCHANNEL_ROC_START)
1053                 vif = sc->offchannel.scan_vif;
1054         else
1055                 vif = sc->offchannel.roc_vif;
1056
1057         if (WARN_ON(!vif))
1058                 goto exit;
1059
1060         eth_zero_addr(common->curbssid);
1061         eth_broadcast_addr(common->bssidmask);
1062         memcpy(common->macaddr, vif->addr, ETH_ALEN);
1063         common->curaid = 0;
1064         ah->opmode = vif->type;
1065         ah->imask &= ~ATH9K_INT_SWBA;
1066         ah->imask &= ~ATH9K_INT_TSFOOR;
1067         ah->slottime = ATH9K_SLOT_TIME_9;
1068
1069         ath_hw_setbssidmask(common);
1070         ath9k_hw_setopmode(ah);
1071         ath9k_hw_write_associd(sc->sc_ah);
1072         ath9k_hw_set_interrupts(ah);
1073         ath9k_hw_init_global_settings(ah);
1074
1075 exit:
1076         ath9k_ps_restore(sc);
1077 }
1078 #endif
1079
1080 /* Called with sc->mutex held. */
1081 void ath9k_calculate_summary_state(struct ath_softc *sc,
1082                                    struct ath_chanctx *ctx)
1083 {
1084         struct ath_hw *ah = sc->sc_ah;
1085         struct ath_common *common = ath9k_hw_common(ah);
1086         struct ath9k_vif_iter_data iter_data;
1087         struct ath_beacon_config *cur_conf;
1088
1089         ath_chanctx_check_active(sc, ctx);
1090
1091         if (ctx != sc->cur_chan)
1092                 return;
1093
1094 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1095         if (ctx == &sc->offchannel.chan)
1096                 return ath9k_set_offchannel_state(sc);
1097 #endif
1098
1099         ath9k_ps_wakeup(sc);
1100         ath9k_calculate_iter_data(sc, ctx, &iter_data);
1101
1102         if (iter_data.has_hw_macaddr)
1103                 memcpy(common->macaddr, iter_data.hw_macaddr, ETH_ALEN);
1104
1105         memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
1106         ath_hw_setbssidmask(common);
1107
1108         if (iter_data.naps > 0) {
1109                 cur_conf = &ctx->beacon;
1110                 ath9k_hw_set_tsfadjust(ah, true);
1111                 ah->opmode = NL80211_IFTYPE_AP;
1112                 if (cur_conf->enable_beacon)
1113                         iter_data.beacons = true;
1114         } else {
1115                 ath9k_hw_set_tsfadjust(ah, false);
1116
1117                 if (iter_data.nmeshes)
1118                         ah->opmode = NL80211_IFTYPE_MESH_POINT;
1119                 else if (iter_data.nwds)
1120                         ah->opmode = NL80211_IFTYPE_AP;
1121                 else if (iter_data.nadhocs)
1122                         ah->opmode = NL80211_IFTYPE_ADHOC;
1123                 else
1124                         ah->opmode = NL80211_IFTYPE_STATION;
1125         }
1126
1127         ath9k_hw_setopmode(ah);
1128
1129         ctx->switch_after_beacon = false;
1130         if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
1131                 ah->imask |= ATH9K_INT_TSFOOR;
1132         else {
1133                 ah->imask &= ~ATH9K_INT_TSFOOR;
1134                 if (iter_data.naps == 1 && iter_data.beacons)
1135                         ctx->switch_after_beacon = true;
1136         }
1137
1138         ah->imask &= ~ATH9K_INT_SWBA;
1139         if (ah->opmode == NL80211_IFTYPE_STATION) {
1140                 bool changed = (iter_data.primary_sta != ctx->primary_sta);
1141
1142                 if (iter_data.primary_sta) {
1143                         iter_data.beacons = true;
1144                         ath9k_set_assoc_state(sc, iter_data.primary_sta,
1145                                               changed);
1146                         ctx->primary_sta = iter_data.primary_sta;
1147                 } else {
1148                         ctx->primary_sta = NULL;
1149                         memset(common->curbssid, 0, ETH_ALEN);
1150                         common->curaid = 0;
1151                         ath9k_hw_write_associd(sc->sc_ah);
1152                         if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1153                                 ath9k_mci_update_wlan_channels(sc, true);
1154                 }
1155         } else if (iter_data.beacons) {
1156                 ah->imask |= ATH9K_INT_SWBA;
1157         }
1158         ath9k_hw_set_interrupts(ah);
1159
1160         if (iter_data.beacons)
1161                 set_bit(ATH_OP_BEACONS, &common->op_flags);
1162         else
1163                 clear_bit(ATH_OP_BEACONS, &common->op_flags);
1164
1165         if (ah->slottime != iter_data.slottime) {
1166                 ah->slottime = iter_data.slottime;
1167                 ath9k_hw_init_global_settings(ah);
1168         }
1169
1170         if (iter_data.primary_sta)
1171                 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1172         else
1173                 clear_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1174
1175         ath_dbg(common, CONFIG,
1176                 "macaddr: %pM, bssid: %pM, bssidmask: %pM\n",
1177                 common->macaddr, common->curbssid, common->bssidmask);
1178
1179         ath9k_ps_restore(sc);
1180 }
1181
1182 static void ath9k_assign_hw_queues(struct ieee80211_hw *hw,
1183                                    struct ieee80211_vif *vif)
1184 {
1185         int i;
1186
1187         for (i = 0; i < IEEE80211_NUM_ACS; i++)
1188                 vif->hw_queue[i] = i;
1189
1190         if (vif->type == NL80211_IFTYPE_AP ||
1191             vif->type == NL80211_IFTYPE_MESH_POINT)
1192                 vif->cab_queue = hw->queues - 2;
1193         else
1194                 vif->cab_queue = IEEE80211_INVAL_HW_QUEUE;
1195 }
1196
1197 static int ath9k_add_interface(struct ieee80211_hw *hw,
1198                                struct ieee80211_vif *vif)
1199 {
1200         struct ath_softc *sc = hw->priv;
1201         struct ath_hw *ah = sc->sc_ah;
1202         struct ath_common *common = ath9k_hw_common(ah);
1203         struct ath_vif *avp = (void *)vif->drv_priv;
1204         struct ath_node *an = &avp->mcast_node;
1205
1206         mutex_lock(&sc->mutex);
1207
1208         if (config_enabled(CONFIG_ATH9K_TX99)) {
1209                 if (sc->cur_chan->nvifs >= 1) {
1210                         mutex_unlock(&sc->mutex);
1211                         return -EOPNOTSUPP;
1212                 }
1213                 sc->tx99_vif = vif;
1214         }
1215
1216         ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
1217         sc->cur_chan->nvifs++;
1218
1219         if (ath9k_uses_beacons(vif->type))
1220                 ath9k_beacon_assign_slot(sc, vif);
1221
1222         avp->vif = vif;
1223         if (!ath9k_is_chanctx_enabled()) {
1224                 avp->chanctx = sc->cur_chan;
1225                 list_add_tail(&avp->list, &avp->chanctx->vifs);
1226         }
1227
1228         ath9k_assign_hw_queues(hw, vif);
1229
1230         an->sc = sc;
1231         an->sta = NULL;
1232         an->vif = vif;
1233         an->no_ps_filter = true;
1234         ath_tx_node_init(sc, an);
1235
1236         mutex_unlock(&sc->mutex);
1237         return 0;
1238 }
1239
1240 static int ath9k_change_interface(struct ieee80211_hw *hw,
1241                                   struct ieee80211_vif *vif,
1242                                   enum nl80211_iftype new_type,
1243                                   bool p2p)
1244 {
1245         struct ath_softc *sc = hw->priv;
1246         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1247         struct ath_vif *avp = (void *)vif->drv_priv;
1248
1249         mutex_lock(&sc->mutex);
1250
1251         if (config_enabled(CONFIG_ATH9K_TX99)) {
1252                 mutex_unlock(&sc->mutex);
1253                 return -EOPNOTSUPP;
1254         }
1255
1256         ath_dbg(common, CONFIG, "Change Interface\n");
1257
1258         if (ath9k_uses_beacons(vif->type))
1259                 ath9k_beacon_remove_slot(sc, vif);
1260
1261         vif->type = new_type;
1262         vif->p2p = p2p;
1263
1264         if (ath9k_uses_beacons(vif->type))
1265                 ath9k_beacon_assign_slot(sc, vif);
1266
1267         ath9k_assign_hw_queues(hw, vif);
1268         ath9k_calculate_summary_state(sc, avp->chanctx);
1269
1270         mutex_unlock(&sc->mutex);
1271         return 0;
1272 }
1273
1274 static void ath9k_remove_interface(struct ieee80211_hw *hw,
1275                                    struct ieee80211_vif *vif)
1276 {
1277         struct ath_softc *sc = hw->priv;
1278         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1279         struct ath_vif *avp = (void *)vif->drv_priv;
1280
1281         ath_dbg(common, CONFIG, "Detach Interface\n");
1282
1283         mutex_lock(&sc->mutex);
1284
1285         ath9k_p2p_remove_vif(sc, vif);
1286
1287         sc->cur_chan->nvifs--;
1288         sc->tx99_vif = NULL;
1289         if (!ath9k_is_chanctx_enabled())
1290                 list_del(&avp->list);
1291
1292         if (ath9k_uses_beacons(vif->type))
1293                 ath9k_beacon_remove_slot(sc, vif);
1294
1295         ath_tx_node_cleanup(sc, &avp->mcast_node);
1296
1297         mutex_unlock(&sc->mutex);
1298 }
1299
1300 static void ath9k_enable_ps(struct ath_softc *sc)
1301 {
1302         struct ath_hw *ah = sc->sc_ah;
1303         struct ath_common *common = ath9k_hw_common(ah);
1304
1305         if (config_enabled(CONFIG_ATH9K_TX99))
1306                 return;
1307
1308         sc->ps_enabled = true;
1309         if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1310                 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1311                         ah->imask |= ATH9K_INT_TIM_TIMER;
1312                         ath9k_hw_set_interrupts(ah);
1313                 }
1314                 ath9k_hw_setrxabort(ah, 1);
1315         }
1316         ath_dbg(common, PS, "PowerSave enabled\n");
1317 }
1318
1319 static void ath9k_disable_ps(struct ath_softc *sc)
1320 {
1321         struct ath_hw *ah = sc->sc_ah;
1322         struct ath_common *common = ath9k_hw_common(ah);
1323
1324         if (config_enabled(CONFIG_ATH9K_TX99))
1325                 return;
1326
1327         sc->ps_enabled = false;
1328         ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1329         if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1330                 ath9k_hw_setrxabort(ah, 0);
1331                 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1332                                   PS_WAIT_FOR_CAB |
1333                                   PS_WAIT_FOR_PSPOLL_DATA |
1334                                   PS_WAIT_FOR_TX_ACK);
1335                 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1336                         ah->imask &= ~ATH9K_INT_TIM_TIMER;
1337                         ath9k_hw_set_interrupts(ah);
1338                 }
1339         }
1340         ath_dbg(common, PS, "PowerSave disabled\n");
1341 }
1342
1343 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
1344 {
1345         struct ath_softc *sc = hw->priv;
1346         struct ath_hw *ah = sc->sc_ah;
1347         struct ath_common *common = ath9k_hw_common(ah);
1348         struct ieee80211_conf *conf = &hw->conf;
1349         struct ath_chanctx *ctx = sc->cur_chan;
1350
1351         ath9k_ps_wakeup(sc);
1352         mutex_lock(&sc->mutex);
1353
1354         if (changed & IEEE80211_CONF_CHANGE_IDLE) {
1355                 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
1356                 if (sc->ps_idle) {
1357                         ath_cancel_work(sc);
1358                         ath9k_stop_btcoex(sc);
1359                 } else {
1360                         ath9k_start_btcoex(sc);
1361                         /*
1362                          * The chip needs a reset to properly wake up from
1363                          * full sleep
1364                          */
1365                         ath_chanctx_set_channel(sc, ctx, &ctx->chandef);
1366                 }
1367         }
1368
1369         /*
1370          * We just prepare to enable PS. We have to wait until our AP has
1371          * ACK'd our null data frame to disable RX otherwise we'll ignore
1372          * those ACKs and end up retransmitting the same null data frames.
1373          * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1374          */
1375         if (changed & IEEE80211_CONF_CHANGE_PS) {
1376                 unsigned long flags;
1377                 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1378                 if (conf->flags & IEEE80211_CONF_PS)
1379                         ath9k_enable_ps(sc);
1380                 else
1381                         ath9k_disable_ps(sc);
1382                 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1383         }
1384
1385         if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1386                 if (conf->flags & IEEE80211_CONF_MONITOR) {
1387                         ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
1388                         sc->sc_ah->is_monitoring = true;
1389                 } else {
1390                         ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
1391                         sc->sc_ah->is_monitoring = false;
1392                 }
1393         }
1394
1395         if (!ath9k_is_chanctx_enabled() && (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
1396                 ctx->offchannel = !!(conf->flags & IEEE80211_CONF_OFFCHANNEL);
1397                 ath_chanctx_set_channel(sc, ctx, &hw->conf.chandef);
1398         }
1399
1400         if (changed & IEEE80211_CONF_CHANGE_POWER) {
1401                 ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level);
1402                 sc->cur_chan->txpower = 2 * conf->power_level;
1403                 ath9k_cmn_update_txpow(ah, sc->cur_chan->cur_txpower,
1404                                        sc->cur_chan->txpower,
1405                                        &sc->cur_chan->cur_txpower);
1406         }
1407
1408         mutex_unlock(&sc->mutex);
1409         ath9k_ps_restore(sc);
1410
1411         return 0;
1412 }
1413
1414 #define SUPPORTED_FILTERS                       \
1415         (FIF_PROMISC_IN_BSS |                   \
1416         FIF_ALLMULTI |                          \
1417         FIF_CONTROL |                           \
1418         FIF_PSPOLL |                            \
1419         FIF_OTHER_BSS |                         \
1420         FIF_BCN_PRBRESP_PROMISC |               \
1421         FIF_PROBE_REQ |                         \
1422         FIF_FCSFAIL)
1423
1424 /* FIXME: sc->sc_full_reset ? */
1425 static void ath9k_configure_filter(struct ieee80211_hw *hw,
1426                                    unsigned int changed_flags,
1427                                    unsigned int *total_flags,
1428                                    u64 multicast)
1429 {
1430         struct ath_softc *sc = hw->priv;
1431         u32 rfilt;
1432
1433         changed_flags &= SUPPORTED_FILTERS;
1434         *total_flags &= SUPPORTED_FILTERS;
1435
1436         spin_lock_bh(&sc->chan_lock);
1437         sc->cur_chan->rxfilter = *total_flags;
1438         spin_unlock_bh(&sc->chan_lock);
1439
1440         ath9k_ps_wakeup(sc);
1441         rfilt = ath_calcrxfilter(sc);
1442         ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
1443         ath9k_ps_restore(sc);
1444
1445         ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
1446                 rfilt);
1447 }
1448
1449 static int ath9k_sta_add(struct ieee80211_hw *hw,
1450                          struct ieee80211_vif *vif,
1451                          struct ieee80211_sta *sta)
1452 {
1453         struct ath_softc *sc = hw->priv;
1454         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1455         struct ath_node *an = (struct ath_node *) sta->drv_priv;
1456         struct ieee80211_key_conf ps_key = { };
1457         int key;
1458
1459         ath_node_attach(sc, sta, vif);
1460
1461         if (vif->type != NL80211_IFTYPE_AP &&
1462             vif->type != NL80211_IFTYPE_AP_VLAN)
1463                 return 0;
1464
1465         key = ath_key_config(common, vif, sta, &ps_key);
1466         if (key > 0) {
1467                 an->ps_key = key;
1468                 an->key_idx[0] = key;
1469         }
1470
1471         return 0;
1472 }
1473
1474 static void ath9k_del_ps_key(struct ath_softc *sc,
1475                              struct ieee80211_vif *vif,
1476                              struct ieee80211_sta *sta)
1477 {
1478         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1479         struct ath_node *an = (struct ath_node *) sta->drv_priv;
1480         struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
1481
1482         if (!an->ps_key)
1483             return;
1484
1485         ath_key_delete(common, &ps_key);
1486         an->ps_key = 0;
1487         an->key_idx[0] = 0;
1488 }
1489
1490 static int ath9k_sta_remove(struct ieee80211_hw *hw,
1491                             struct ieee80211_vif *vif,
1492                             struct ieee80211_sta *sta)
1493 {
1494         struct ath_softc *sc = hw->priv;
1495
1496         ath9k_del_ps_key(sc, vif, sta);
1497         ath_node_detach(sc, sta);
1498
1499         return 0;
1500 }
1501
1502 static int ath9k_sta_state(struct ieee80211_hw *hw,
1503                            struct ieee80211_vif *vif,
1504                            struct ieee80211_sta *sta,
1505                            enum ieee80211_sta_state old_state,
1506                            enum ieee80211_sta_state new_state)
1507 {
1508         struct ath_softc *sc = hw->priv;
1509         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1510         int ret = 0;
1511
1512         if (old_state == IEEE80211_STA_AUTH &&
1513             new_state == IEEE80211_STA_ASSOC) {
1514                 ret = ath9k_sta_add(hw, vif, sta);
1515                 ath_dbg(common, CONFIG,
1516                         "Add station: %pM\n", sta->addr);
1517         } else if (old_state == IEEE80211_STA_ASSOC &&
1518                    new_state == IEEE80211_STA_AUTH) {
1519                 ret = ath9k_sta_remove(hw, vif, sta);
1520                 ath_dbg(common, CONFIG,
1521                         "Remove station: %pM\n", sta->addr);
1522         }
1523
1524         if (ath9k_is_chanctx_enabled()) {
1525                 if (vif->type == NL80211_IFTYPE_STATION) {
1526                         if (old_state == IEEE80211_STA_ASSOC &&
1527                             new_state == IEEE80211_STA_AUTHORIZED)
1528                                 ath_chanctx_event(sc, vif,
1529                                                   ATH_CHANCTX_EVENT_AUTHORIZED);
1530                 }
1531         }
1532
1533         return ret;
1534 }
1535
1536 static void ath9k_sta_set_tx_filter(struct ath_hw *ah,
1537                                     struct ath_node *an,
1538                                     bool set)
1539 {
1540         int i;
1541
1542         for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1543                 if (!an->key_idx[i])
1544                         continue;
1545                 ath9k_hw_set_tx_filter(ah, an->key_idx[i], set);
1546         }
1547 }
1548
1549 static void ath9k_sta_notify(struct ieee80211_hw *hw,
1550                          struct ieee80211_vif *vif,
1551                          enum sta_notify_cmd cmd,
1552                          struct ieee80211_sta *sta)
1553 {
1554         struct ath_softc *sc = hw->priv;
1555         struct ath_node *an = (struct ath_node *) sta->drv_priv;
1556
1557         switch (cmd) {
1558         case STA_NOTIFY_SLEEP:
1559                 an->sleeping = true;
1560                 ath_tx_aggr_sleep(sta, sc, an);
1561                 ath9k_sta_set_tx_filter(sc->sc_ah, an, true);
1562                 break;
1563         case STA_NOTIFY_AWAKE:
1564                 ath9k_sta_set_tx_filter(sc->sc_ah, an, false);
1565                 an->sleeping = false;
1566                 ath_tx_aggr_wakeup(sc, an);
1567                 break;
1568         }
1569 }
1570
1571 static int ath9k_conf_tx(struct ieee80211_hw *hw,
1572                          struct ieee80211_vif *vif, u16 queue,
1573                          const struct ieee80211_tx_queue_params *params)
1574 {
1575         struct ath_softc *sc = hw->priv;
1576         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1577         struct ath_txq *txq;
1578         struct ath9k_tx_queue_info qi;
1579         int ret = 0;
1580
1581         if (queue >= IEEE80211_NUM_ACS)
1582                 return 0;
1583
1584         txq = sc->tx.txq_map[queue];
1585
1586         ath9k_ps_wakeup(sc);
1587         mutex_lock(&sc->mutex);
1588
1589         memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1590
1591         qi.tqi_aifs = params->aifs;
1592         qi.tqi_cwmin = params->cw_min;
1593         qi.tqi_cwmax = params->cw_max;
1594         qi.tqi_burstTime = params->txop * 32;
1595
1596         ath_dbg(common, CONFIG,
1597                 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1598                 queue, txq->axq_qnum, params->aifs, params->cw_min,
1599                 params->cw_max, params->txop);
1600
1601         ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
1602         ret = ath_txq_update(sc, txq->axq_qnum, &qi);
1603         if (ret)
1604                 ath_err(common, "TXQ Update failed\n");
1605
1606         mutex_unlock(&sc->mutex);
1607         ath9k_ps_restore(sc);
1608
1609         return ret;
1610 }
1611
1612 static int ath9k_set_key(struct ieee80211_hw *hw,
1613                          enum set_key_cmd cmd,
1614                          struct ieee80211_vif *vif,
1615                          struct ieee80211_sta *sta,
1616                          struct ieee80211_key_conf *key)
1617 {
1618         struct ath_softc *sc = hw->priv;
1619         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1620         struct ath_node *an = NULL;
1621         int ret = 0, i;
1622
1623         if (ath9k_modparam_nohwcrypt)
1624                 return -ENOSPC;
1625
1626         if ((vif->type == NL80211_IFTYPE_ADHOC ||
1627              vif->type == NL80211_IFTYPE_MESH_POINT) &&
1628             (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
1629              key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
1630             !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
1631                 /*
1632                  * For now, disable hw crypto for the RSN IBSS group keys. This
1633                  * could be optimized in the future to use a modified key cache
1634                  * design to support per-STA RX GTK, but until that gets
1635                  * implemented, use of software crypto for group addressed
1636                  * frames is a acceptable to allow RSN IBSS to be used.
1637                  */
1638                 return -EOPNOTSUPP;
1639         }
1640
1641         mutex_lock(&sc->mutex);
1642         ath9k_ps_wakeup(sc);
1643         ath_dbg(common, CONFIG, "Set HW Key %d\n", cmd);
1644         if (sta)
1645                 an = (struct ath_node *)sta->drv_priv;
1646
1647         switch (cmd) {
1648         case SET_KEY:
1649                 if (sta)
1650                         ath9k_del_ps_key(sc, vif, sta);
1651
1652                 key->hw_key_idx = 0;
1653                 ret = ath_key_config(common, vif, sta, key);
1654                 if (ret >= 0) {
1655                         key->hw_key_idx = ret;
1656                         /* push IV and Michael MIC generation to stack */
1657                         key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
1658                         if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
1659                                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
1660                         if (sc->sc_ah->sw_mgmt_crypto_tx &&
1661                             key->cipher == WLAN_CIPHER_SUITE_CCMP)
1662                                 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
1663                         ret = 0;
1664                 }
1665                 if (an && key->hw_key_idx) {
1666                         for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1667                                 if (an->key_idx[i])
1668                                         continue;
1669                                 an->key_idx[i] = key->hw_key_idx;
1670                                 break;
1671                         }
1672                         WARN_ON(i == ARRAY_SIZE(an->key_idx));
1673                 }
1674                 break;
1675         case DISABLE_KEY:
1676                 ath_key_delete(common, key);
1677                 if (an) {
1678                         for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1679                                 if (an->key_idx[i] != key->hw_key_idx)
1680                                         continue;
1681                                 an->key_idx[i] = 0;
1682                                 break;
1683                         }
1684                 }
1685                 key->hw_key_idx = 0;
1686                 break;
1687         default:
1688                 ret = -EINVAL;
1689         }
1690
1691         ath9k_ps_restore(sc);
1692         mutex_unlock(&sc->mutex);
1693
1694         return ret;
1695 }
1696
1697 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1698                                    struct ieee80211_vif *vif,
1699                                    struct ieee80211_bss_conf *bss_conf,
1700                                    u32 changed)
1701 {
1702 #define CHECK_ANI                               \
1703         (BSS_CHANGED_ASSOC |                    \
1704          BSS_CHANGED_IBSS |                     \
1705          BSS_CHANGED_BEACON_ENABLED)
1706
1707         struct ath_softc *sc = hw->priv;
1708         struct ath_hw *ah = sc->sc_ah;
1709         struct ath_common *common = ath9k_hw_common(ah);
1710         struct ath_vif *avp = (void *)vif->drv_priv;
1711         int slottime;
1712
1713         ath9k_ps_wakeup(sc);
1714         mutex_lock(&sc->mutex);
1715
1716         if (changed & BSS_CHANGED_ASSOC) {
1717                 ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
1718                         bss_conf->bssid, bss_conf->assoc);
1719
1720                 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
1721                 avp->aid = bss_conf->aid;
1722                 avp->assoc = bss_conf->assoc;
1723
1724                 ath9k_calculate_summary_state(sc, avp->chanctx);
1725         }
1726
1727         if (changed & BSS_CHANGED_IBSS) {
1728                 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1729                 common->curaid = bss_conf->aid;
1730                 ath9k_hw_write_associd(sc->sc_ah);
1731         }
1732
1733         if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
1734             (changed & BSS_CHANGED_BEACON_INT) ||
1735             (changed & BSS_CHANGED_BEACON_INFO)) {
1736                 ath9k_beacon_config(sc, vif, changed);
1737                 if (changed & BSS_CHANGED_BEACON_ENABLED)
1738                         ath9k_calculate_summary_state(sc, avp->chanctx);
1739         }
1740
1741         if ((avp->chanctx == sc->cur_chan) &&
1742             (changed & BSS_CHANGED_ERP_SLOT)) {
1743                 if (bss_conf->use_short_slot)
1744                         slottime = 9;
1745                 else
1746                         slottime = 20;
1747                 if (vif->type == NL80211_IFTYPE_AP) {
1748                         /*
1749                          * Defer update, so that connected stations can adjust
1750                          * their settings at the same time.
1751                          * See beacon.c for more details
1752                          */
1753                         sc->beacon.slottime = slottime;
1754                         sc->beacon.updateslot = UPDATE;
1755                 } else {
1756                         ah->slottime = slottime;
1757                         ath9k_hw_init_global_settings(ah);
1758                 }
1759         }
1760
1761         if (changed & BSS_CHANGED_P2P_PS)
1762                 ath9k_p2p_bss_info_changed(sc, vif);
1763
1764         if (changed & CHECK_ANI)
1765                 ath_check_ani(sc);
1766
1767         mutex_unlock(&sc->mutex);
1768         ath9k_ps_restore(sc);
1769
1770 #undef CHECK_ANI
1771 }
1772
1773 static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1774 {
1775         struct ath_softc *sc = hw->priv;
1776         u64 tsf;
1777
1778         mutex_lock(&sc->mutex);
1779         ath9k_ps_wakeup(sc);
1780         tsf = ath9k_hw_gettsf64(sc->sc_ah);
1781         ath9k_ps_restore(sc);
1782         mutex_unlock(&sc->mutex);
1783
1784         return tsf;
1785 }
1786
1787 static void ath9k_set_tsf(struct ieee80211_hw *hw,
1788                           struct ieee80211_vif *vif,
1789                           u64 tsf)
1790 {
1791         struct ath_softc *sc = hw->priv;
1792
1793         mutex_lock(&sc->mutex);
1794         ath9k_ps_wakeup(sc);
1795         ath9k_hw_settsf64(sc->sc_ah, tsf);
1796         ath9k_ps_restore(sc);
1797         mutex_unlock(&sc->mutex);
1798 }
1799
1800 static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1801 {
1802         struct ath_softc *sc = hw->priv;
1803
1804         mutex_lock(&sc->mutex);
1805
1806         ath9k_ps_wakeup(sc);
1807         ath9k_hw_reset_tsf(sc->sc_ah);
1808         ath9k_ps_restore(sc);
1809
1810         mutex_unlock(&sc->mutex);
1811 }
1812
1813 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
1814                               struct ieee80211_vif *vif,
1815                               enum ieee80211_ampdu_mlme_action action,
1816                               struct ieee80211_sta *sta,
1817                               u16 tid, u16 *ssn, u8 buf_size)
1818 {
1819         struct ath_softc *sc = hw->priv;
1820         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1821         bool flush = false;
1822         int ret = 0;
1823
1824         mutex_lock(&sc->mutex);
1825
1826         switch (action) {
1827         case IEEE80211_AMPDU_RX_START:
1828                 break;
1829         case IEEE80211_AMPDU_RX_STOP:
1830                 break;
1831         case IEEE80211_AMPDU_TX_START:
1832                 if (ath9k_is_chanctx_enabled()) {
1833                         if (test_bit(ATH_OP_SCANNING, &common->op_flags)) {
1834                                 ret = -EBUSY;
1835                                 break;
1836                         }
1837                 }
1838                 ath9k_ps_wakeup(sc);
1839                 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
1840                 if (!ret)
1841                         ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1842                 ath9k_ps_restore(sc);
1843                 break;
1844         case IEEE80211_AMPDU_TX_STOP_FLUSH:
1845         case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
1846                 flush = true;
1847         case IEEE80211_AMPDU_TX_STOP_CONT:
1848                 ath9k_ps_wakeup(sc);
1849                 ath_tx_aggr_stop(sc, sta, tid);
1850                 if (!flush)
1851                         ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1852                 ath9k_ps_restore(sc);
1853                 break;
1854         case IEEE80211_AMPDU_TX_OPERATIONAL:
1855                 ath9k_ps_wakeup(sc);
1856                 ath_tx_aggr_resume(sc, sta, tid);
1857                 ath9k_ps_restore(sc);
1858                 break;
1859         default:
1860                 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
1861         }
1862
1863         mutex_unlock(&sc->mutex);
1864
1865         return ret;
1866 }
1867
1868 static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
1869                              struct survey_info *survey)
1870 {
1871         struct ath_softc *sc = hw->priv;
1872         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1873         struct ieee80211_supported_band *sband;
1874         struct ieee80211_channel *chan;
1875         int pos;
1876
1877         if (config_enabled(CONFIG_ATH9K_TX99))
1878                 return -EOPNOTSUPP;
1879
1880         spin_lock_bh(&common->cc_lock);
1881         if (idx == 0)
1882                 ath_update_survey_stats(sc);
1883
1884         sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
1885         if (sband && idx >= sband->n_channels) {
1886                 idx -= sband->n_channels;
1887                 sband = NULL;
1888         }
1889
1890         if (!sband)
1891                 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
1892
1893         if (!sband || idx >= sband->n_channels) {
1894                 spin_unlock_bh(&common->cc_lock);
1895                 return -ENOENT;
1896         }
1897
1898         chan = &sband->channels[idx];
1899         pos = chan->hw_value;
1900         memcpy(survey, &sc->survey[pos], sizeof(*survey));
1901         survey->channel = chan;
1902         spin_unlock_bh(&common->cc_lock);
1903
1904         return 0;
1905 }
1906
1907 static void ath9k_enable_dynack(struct ath_softc *sc)
1908 {
1909 #ifdef CONFIG_ATH9K_DYNACK
1910         u32 rfilt;
1911         struct ath_hw *ah = sc->sc_ah;
1912
1913         ath_dynack_reset(ah);
1914
1915         ah->dynack.enabled = true;
1916         rfilt = ath_calcrxfilter(sc);
1917         ath9k_hw_setrxfilter(ah, rfilt);
1918 #endif
1919 }
1920
1921 static void ath9k_set_coverage_class(struct ieee80211_hw *hw,
1922                                      s16 coverage_class)
1923 {
1924         struct ath_softc *sc = hw->priv;
1925         struct ath_hw *ah = sc->sc_ah;
1926
1927         if (config_enabled(CONFIG_ATH9K_TX99))
1928                 return;
1929
1930         mutex_lock(&sc->mutex);
1931
1932         if (coverage_class >= 0) {
1933                 ah->coverage_class = coverage_class;
1934                 if (ah->dynack.enabled) {
1935                         u32 rfilt;
1936
1937                         ah->dynack.enabled = false;
1938                         rfilt = ath_calcrxfilter(sc);
1939                         ath9k_hw_setrxfilter(ah, rfilt);
1940                 }
1941                 ath9k_ps_wakeup(sc);
1942                 ath9k_hw_init_global_settings(ah);
1943                 ath9k_ps_restore(sc);
1944         } else if (!ah->dynack.enabled) {
1945                 ath9k_enable_dynack(sc);
1946         }
1947
1948         mutex_unlock(&sc->mutex);
1949 }
1950
1951 static bool ath9k_has_tx_pending(struct ath_softc *sc,
1952                                  bool sw_pending)
1953 {
1954         int i, npend = 0;
1955
1956         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1957                 if (!ATH_TXQ_SETUP(sc, i))
1958                         continue;
1959
1960                 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i],
1961                                                  sw_pending);
1962                 if (npend)
1963                         break;
1964         }
1965
1966         return !!npend;
1967 }
1968
1969 static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1970                         u32 queues, bool drop)
1971 {
1972         struct ath_softc *sc = hw->priv;
1973         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1974
1975         if (ath9k_is_chanctx_enabled()) {
1976                 if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags))
1977                         goto flush;
1978
1979                 /*
1980                  * If MCC is active, extend the flush timeout
1981                  * and wait for the HW/SW queues to become
1982                  * empty. This needs to be done outside the
1983                  * sc->mutex lock to allow the channel scheduler
1984                  * to switch channel contexts.
1985                  *
1986                  * The vif queues have been stopped in mac80211,
1987                  * so there won't be any incoming frames.
1988                  */
1989                 __ath9k_flush(hw, queues, drop, true, true);
1990                 return;
1991         }
1992 flush:
1993         mutex_lock(&sc->mutex);
1994         __ath9k_flush(hw, queues, drop, true, false);
1995         mutex_unlock(&sc->mutex);
1996 }
1997
1998 void __ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop,
1999                    bool sw_pending, bool timeout_override)
2000 {
2001         struct ath_softc *sc = hw->priv;
2002         struct ath_hw *ah = sc->sc_ah;
2003         struct ath_common *common = ath9k_hw_common(ah);
2004         int timeout;
2005         bool drain_txq;
2006
2007         cancel_delayed_work_sync(&sc->tx_complete_work);
2008
2009         if (ah->ah_flags & AH_UNPLUGGED) {
2010                 ath_dbg(common, ANY, "Device has been unplugged!\n");
2011                 return;
2012         }
2013
2014         if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
2015                 ath_dbg(common, ANY, "Device not present\n");
2016                 return;
2017         }
2018
2019         spin_lock_bh(&sc->chan_lock);
2020         if (timeout_override)
2021                 timeout = HZ / 5;
2022         else
2023                 timeout = sc->cur_chan->flush_timeout;
2024         spin_unlock_bh(&sc->chan_lock);
2025
2026         ath_dbg(common, CHAN_CTX,
2027                 "Flush timeout: %d\n", jiffies_to_msecs(timeout));
2028
2029         if (wait_event_timeout(sc->tx_wait, !ath9k_has_tx_pending(sc, sw_pending),
2030                                timeout) > 0)
2031                 drop = false;
2032
2033         if (drop) {
2034                 ath9k_ps_wakeup(sc);
2035                 spin_lock_bh(&sc->sc_pcu_lock);
2036                 drain_txq = ath_drain_all_txq(sc);
2037                 spin_unlock_bh(&sc->sc_pcu_lock);
2038
2039                 if (!drain_txq)
2040                         ath_reset(sc, NULL);
2041
2042                 ath9k_ps_restore(sc);
2043         }
2044
2045         ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
2046 }
2047
2048 static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
2049 {
2050         struct ath_softc *sc = hw->priv;
2051
2052         return ath9k_has_tx_pending(sc, true);
2053 }
2054
2055 static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
2056 {
2057         struct ath_softc *sc = hw->priv;
2058         struct ath_hw *ah = sc->sc_ah;
2059         struct ieee80211_vif *vif;
2060         struct ath_vif *avp;
2061         struct ath_buf *bf;
2062         struct ath_tx_status ts;
2063         bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
2064         int status;
2065
2066         vif = sc->beacon.bslot[0];
2067         if (!vif)
2068                 return 0;
2069
2070         if (!vif->bss_conf.enable_beacon)
2071                 return 0;
2072
2073         avp = (void *)vif->drv_priv;
2074
2075         if (!sc->beacon.tx_processed && !edma) {
2076                 tasklet_disable(&sc->bcon_tasklet);
2077
2078                 bf = avp->av_bcbuf;
2079                 if (!bf || !bf->bf_mpdu)
2080                         goto skip;
2081
2082                 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
2083                 if (status == -EINPROGRESS)
2084                         goto skip;
2085
2086                 sc->beacon.tx_processed = true;
2087                 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2088
2089 skip:
2090                 tasklet_enable(&sc->bcon_tasklet);
2091         }
2092
2093         return sc->beacon.tx_last;
2094 }
2095
2096 static int ath9k_get_stats(struct ieee80211_hw *hw,
2097                            struct ieee80211_low_level_stats *stats)
2098 {
2099         struct ath_softc *sc = hw->priv;
2100         struct ath_hw *ah = sc->sc_ah;
2101         struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
2102
2103         stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
2104         stats->dot11RTSFailureCount = mib_stats->rts_bad;
2105         stats->dot11FCSErrorCount = mib_stats->fcs_bad;
2106         stats->dot11RTSSuccessCount = mib_stats->rts_good;
2107         return 0;
2108 }
2109
2110 static u32 fill_chainmask(u32 cap, u32 new)
2111 {
2112         u32 filled = 0;
2113         int i;
2114
2115         for (i = 0; cap && new; i++, cap >>= 1) {
2116                 if (!(cap & BIT(0)))
2117                         continue;
2118
2119                 if (new & BIT(0))
2120                         filled |= BIT(i);
2121
2122                 new >>= 1;
2123         }
2124
2125         return filled;
2126 }
2127
2128 static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
2129 {
2130         if (AR_SREV_9300_20_OR_LATER(ah))
2131                 return true;
2132
2133         switch (val & 0x7) {
2134         case 0x1:
2135         case 0x3:
2136         case 0x7:
2137                 return true;
2138         case 0x2:
2139                 return (ah->caps.rx_chainmask == 1);
2140         default:
2141                 return false;
2142         }
2143 }
2144
2145 static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
2146 {
2147         struct ath_softc *sc = hw->priv;
2148         struct ath_hw *ah = sc->sc_ah;
2149
2150         if (ah->caps.rx_chainmask != 1)
2151                 rx_ant |= tx_ant;
2152
2153         if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
2154                 return -EINVAL;
2155
2156         sc->ant_rx = rx_ant;
2157         sc->ant_tx = tx_ant;
2158
2159         if (ah->caps.rx_chainmask == 1)
2160                 return 0;
2161
2162         /* AR9100 runs into calibration issues if not all rx chains are enabled */
2163         if (AR_SREV_9100(ah))
2164                 ah->rxchainmask = 0x7;
2165         else
2166                 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
2167
2168         ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
2169         ath9k_cmn_reload_chainmask(ah);
2170
2171         return 0;
2172 }
2173
2174 static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
2175 {
2176         struct ath_softc *sc = hw->priv;
2177
2178         *tx_ant = sc->ant_tx;
2179         *rx_ant = sc->ant_rx;
2180         return 0;
2181 }
2182
2183 static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2184 {
2185         struct ath_softc *sc = hw->priv;
2186         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2187         set_bit(ATH_OP_SCANNING, &common->op_flags);
2188 }
2189
2190 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2191 {
2192         struct ath_softc *sc = hw->priv;
2193         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2194         clear_bit(ATH_OP_SCANNING, &common->op_flags);
2195 }
2196
2197 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
2198
2199 static void ath9k_cancel_pending_offchannel(struct ath_softc *sc)
2200 {
2201         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2202
2203         if (sc->offchannel.roc_vif) {
2204                 ath_dbg(common, CHAN_CTX,
2205                         "%s: Aborting RoC\n", __func__);
2206
2207                 del_timer_sync(&sc->offchannel.timer);
2208                 if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START)
2209                         ath_roc_complete(sc, true);
2210         }
2211
2212         if (test_bit(ATH_OP_SCANNING, &common->op_flags)) {
2213                 ath_dbg(common, CHAN_CTX,
2214                         "%s: Aborting HW scan\n", __func__);
2215
2216                 del_timer_sync(&sc->offchannel.timer);
2217                 ath_scan_complete(sc, true);
2218         }
2219 }
2220
2221 static int ath9k_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2222                          struct ieee80211_scan_request *hw_req)
2223 {
2224         struct cfg80211_scan_request *req = &hw_req->req;
2225         struct ath_softc *sc = hw->priv;
2226         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2227         int ret = 0;
2228
2229         mutex_lock(&sc->mutex);
2230
2231         if (WARN_ON(sc->offchannel.scan_req)) {
2232                 ret = -EBUSY;
2233                 goto out;
2234         }
2235
2236         ath9k_ps_wakeup(sc);
2237         set_bit(ATH_OP_SCANNING, &common->op_flags);
2238         sc->offchannel.scan_vif = vif;
2239         sc->offchannel.scan_req = req;
2240         sc->offchannel.scan_idx = 0;
2241
2242         ath_dbg(common, CHAN_CTX, "HW scan request received on vif: %pM\n",
2243                 vif->addr);
2244
2245         if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
2246                 ath_dbg(common, CHAN_CTX, "Starting HW scan\n");
2247                 ath_offchannel_next(sc);
2248         }
2249
2250 out:
2251         mutex_unlock(&sc->mutex);
2252
2253         return ret;
2254 }
2255
2256 static void ath9k_cancel_hw_scan(struct ieee80211_hw *hw,
2257                                  struct ieee80211_vif *vif)
2258 {
2259         struct ath_softc *sc = hw->priv;
2260         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2261
2262         ath_dbg(common, CHAN_CTX, "Cancel HW scan on vif: %pM\n", vif->addr);
2263
2264         mutex_lock(&sc->mutex);
2265         del_timer_sync(&sc->offchannel.timer);
2266         ath_scan_complete(sc, true);
2267         mutex_unlock(&sc->mutex);
2268 }
2269
2270 static int ath9k_remain_on_channel(struct ieee80211_hw *hw,
2271                                    struct ieee80211_vif *vif,
2272                                    struct ieee80211_channel *chan, int duration,
2273                                    enum ieee80211_roc_type type)
2274 {
2275         struct ath_softc *sc = hw->priv;
2276         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2277         int ret = 0;
2278
2279         mutex_lock(&sc->mutex);
2280
2281         if (WARN_ON(sc->offchannel.roc_vif)) {
2282                 ret = -EBUSY;
2283                 goto out;
2284         }
2285
2286         ath9k_ps_wakeup(sc);
2287         sc->offchannel.roc_vif = vif;
2288         sc->offchannel.roc_chan = chan;
2289         sc->offchannel.roc_duration = duration;
2290
2291         ath_dbg(common, CHAN_CTX,
2292                 "RoC request on vif: %pM, type: %d duration: %d\n",
2293                 vif->addr, type, duration);
2294
2295         if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
2296                 ath_dbg(common, CHAN_CTX, "Starting RoC period\n");
2297                 ath_offchannel_next(sc);
2298         }
2299
2300 out:
2301         mutex_unlock(&sc->mutex);
2302
2303         return ret;
2304 }
2305
2306 static int ath9k_cancel_remain_on_channel(struct ieee80211_hw *hw)
2307 {
2308         struct ath_softc *sc = hw->priv;
2309         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2310
2311         mutex_lock(&sc->mutex);
2312
2313         ath_dbg(common, CHAN_CTX, "Cancel RoC\n");
2314         del_timer_sync(&sc->offchannel.timer);
2315
2316         if (sc->offchannel.roc_vif) {
2317                 if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START)
2318                         ath_roc_complete(sc, true);
2319         }
2320
2321         mutex_unlock(&sc->mutex);
2322
2323         return 0;
2324 }
2325
2326 static int ath9k_add_chanctx(struct ieee80211_hw *hw,
2327                              struct ieee80211_chanctx_conf *conf)
2328 {
2329         struct ath_softc *sc = hw->priv;
2330         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2331         struct ath_chanctx *ctx, **ptr;
2332         int pos;
2333
2334         mutex_lock(&sc->mutex);
2335
2336         ath_for_each_chanctx(sc, ctx) {
2337                 if (ctx->assigned)
2338                         continue;
2339
2340                 ptr = (void *) conf->drv_priv;
2341                 *ptr = ctx;
2342                 ctx->assigned = true;
2343                 pos = ctx - &sc->chanctx[0];
2344                 ctx->hw_queue_base = pos * IEEE80211_NUM_ACS;
2345
2346                 ath_dbg(common, CHAN_CTX,
2347                         "Add channel context: %d MHz\n",
2348                         conf->def.chan->center_freq);
2349
2350                 ath_chanctx_set_channel(sc, ctx, &conf->def);
2351
2352                 mutex_unlock(&sc->mutex);
2353                 return 0;
2354         }
2355
2356         mutex_unlock(&sc->mutex);
2357         return -ENOSPC;
2358 }
2359
2360
2361 static void ath9k_remove_chanctx(struct ieee80211_hw *hw,
2362                                  struct ieee80211_chanctx_conf *conf)
2363 {
2364         struct ath_softc *sc = hw->priv;
2365         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2366         struct ath_chanctx *ctx = ath_chanctx_get(conf);
2367
2368         mutex_lock(&sc->mutex);
2369
2370         ath_dbg(common, CHAN_CTX,
2371                 "Remove channel context: %d MHz\n",
2372                 conf->def.chan->center_freq);
2373
2374         ctx->assigned = false;
2375         ctx->hw_queue_base = 0;
2376         ath_chanctx_event(sc, NULL, ATH_CHANCTX_EVENT_UNASSIGN);
2377
2378         mutex_unlock(&sc->mutex);
2379 }
2380
2381 static void ath9k_change_chanctx(struct ieee80211_hw *hw,
2382                                  struct ieee80211_chanctx_conf *conf,
2383                                  u32 changed)
2384 {
2385         struct ath_softc *sc = hw->priv;
2386         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2387         struct ath_chanctx *ctx = ath_chanctx_get(conf);
2388
2389         mutex_lock(&sc->mutex);
2390         ath_dbg(common, CHAN_CTX,
2391                 "Change channel context: %d MHz\n",
2392                 conf->def.chan->center_freq);
2393         ath_chanctx_set_channel(sc, ctx, &conf->def);
2394         mutex_unlock(&sc->mutex);
2395 }
2396
2397 static int ath9k_assign_vif_chanctx(struct ieee80211_hw *hw,
2398                                     struct ieee80211_vif *vif,
2399                                     struct ieee80211_chanctx_conf *conf)
2400 {
2401         struct ath_softc *sc = hw->priv;
2402         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2403         struct ath_vif *avp = (void *)vif->drv_priv;
2404         struct ath_chanctx *ctx = ath_chanctx_get(conf);
2405         int i;
2406
2407         ath9k_cancel_pending_offchannel(sc);
2408
2409         mutex_lock(&sc->mutex);
2410
2411         ath_dbg(common, CHAN_CTX,
2412                 "Assign VIF (addr: %pM, type: %d, p2p: %d) to channel context: %d MHz\n",
2413                 vif->addr, vif->type, vif->p2p,
2414                 conf->def.chan->center_freq);
2415
2416         avp->chanctx = ctx;
2417         ctx->nvifs_assigned++;
2418         list_add_tail(&avp->list, &ctx->vifs);
2419         ath9k_calculate_summary_state(sc, ctx);
2420         for (i = 0; i < IEEE80211_NUM_ACS; i++)
2421                 vif->hw_queue[i] = ctx->hw_queue_base + i;
2422
2423         mutex_unlock(&sc->mutex);
2424
2425         return 0;
2426 }
2427
2428 static void ath9k_unassign_vif_chanctx(struct ieee80211_hw *hw,
2429                                        struct ieee80211_vif *vif,
2430                                        struct ieee80211_chanctx_conf *conf)
2431 {
2432         struct ath_softc *sc = hw->priv;
2433         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2434         struct ath_vif *avp = (void *)vif->drv_priv;
2435         struct ath_chanctx *ctx = ath_chanctx_get(conf);
2436         int ac;
2437
2438         ath9k_cancel_pending_offchannel(sc);
2439
2440         mutex_lock(&sc->mutex);
2441
2442         ath_dbg(common, CHAN_CTX,
2443                 "Remove VIF (addr: %pM, type: %d, p2p: %d) from channel context: %d MHz\n",
2444                 vif->addr, vif->type, vif->p2p,
2445                 conf->def.chan->center_freq);
2446
2447         avp->chanctx = NULL;
2448         ctx->nvifs_assigned--;
2449         list_del(&avp->list);
2450         ath9k_calculate_summary_state(sc, ctx);
2451         for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
2452                 vif->hw_queue[ac] = IEEE80211_INVAL_HW_QUEUE;
2453
2454         mutex_unlock(&sc->mutex);
2455 }
2456
2457 static void ath9k_mgd_prepare_tx(struct ieee80211_hw *hw,
2458                                  struct ieee80211_vif *vif)
2459 {
2460         struct ath_softc *sc = hw->priv;
2461         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2462         struct ath_vif *avp = (struct ath_vif *) vif->drv_priv;
2463         struct ath_beacon_config *cur_conf;
2464         struct ath_chanctx *go_ctx;
2465         unsigned long timeout;
2466         bool changed = false;
2467         u32 beacon_int;
2468
2469         if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags))
2470                 return;
2471
2472         if (!avp->chanctx)
2473                 return;
2474
2475         mutex_lock(&sc->mutex);
2476
2477         spin_lock_bh(&sc->chan_lock);
2478         if (sc->next_chan || (sc->cur_chan != avp->chanctx))
2479                 changed = true;
2480         spin_unlock_bh(&sc->chan_lock);
2481
2482         if (!changed)
2483                 goto out;
2484
2485         ath9k_cancel_pending_offchannel(sc);
2486
2487         go_ctx = ath_is_go_chanctx_present(sc);
2488
2489         if (go_ctx) {
2490                 /*
2491                  * Wait till the GO interface gets a chance
2492                  * to send out an NoA.
2493                  */
2494                 spin_lock_bh(&sc->chan_lock);
2495                 sc->sched.mgd_prepare_tx = true;
2496                 cur_conf = &go_ctx->beacon;
2497                 beacon_int = TU_TO_USEC(cur_conf->beacon_interval);
2498                 spin_unlock_bh(&sc->chan_lock);
2499
2500                 timeout = usecs_to_jiffies(beacon_int * 2);
2501                 init_completion(&sc->go_beacon);
2502
2503                 mutex_unlock(&sc->mutex);
2504                 if (wait_for_completion_timeout(&sc->go_beacon,
2505                                                 timeout) == 0)
2506                         ath_dbg(common, CHAN_CTX,
2507                                 "Failed to send new NoA\n");
2508                 mutex_lock(&sc->mutex);
2509         }
2510
2511         ath_dbg(common, CHAN_CTX,
2512                 "%s: Set chanctx state to FORCE_ACTIVE for vif: %pM\n",
2513                 __func__, vif->addr);
2514
2515         spin_lock_bh(&sc->chan_lock);
2516         sc->next_chan = avp->chanctx;
2517         sc->sched.state = ATH_CHANCTX_STATE_FORCE_ACTIVE;
2518         spin_unlock_bh(&sc->chan_lock);
2519
2520         ath_chanctx_set_next(sc, true);
2521 out:
2522         mutex_unlock(&sc->mutex);
2523 }
2524
2525 void ath9k_fill_chanctx_ops(void)
2526 {
2527         if (!ath9k_is_chanctx_enabled())
2528                 return;
2529
2530         ath9k_ops.hw_scan                  = ath9k_hw_scan;
2531         ath9k_ops.cancel_hw_scan           = ath9k_cancel_hw_scan;
2532         ath9k_ops.remain_on_channel        = ath9k_remain_on_channel;
2533         ath9k_ops.cancel_remain_on_channel = ath9k_cancel_remain_on_channel;
2534         ath9k_ops.add_chanctx              = ath9k_add_chanctx;
2535         ath9k_ops.remove_chanctx           = ath9k_remove_chanctx;
2536         ath9k_ops.change_chanctx           = ath9k_change_chanctx;
2537         ath9k_ops.assign_vif_chanctx       = ath9k_assign_vif_chanctx;
2538         ath9k_ops.unassign_vif_chanctx     = ath9k_unassign_vif_chanctx;
2539         ath9k_ops.mgd_prepare_tx           = ath9k_mgd_prepare_tx;
2540 }
2541
2542 #endif
2543
2544 static int ath9k_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2545                              int *dbm)
2546 {
2547         struct ath_softc *sc = hw->priv;
2548         struct ath_vif *avp = (void *)vif->drv_priv;
2549
2550         mutex_lock(&sc->mutex);
2551         if (avp->chanctx)
2552                 *dbm = avp->chanctx->cur_txpower;
2553         else
2554                 *dbm = sc->cur_chan->cur_txpower;
2555         mutex_unlock(&sc->mutex);
2556
2557         *dbm /= 2;
2558
2559         return 0;
2560 }
2561
2562 struct ieee80211_ops ath9k_ops = {
2563         .tx                 = ath9k_tx,
2564         .start              = ath9k_start,
2565         .stop               = ath9k_stop,
2566         .add_interface      = ath9k_add_interface,
2567         .change_interface   = ath9k_change_interface,
2568         .remove_interface   = ath9k_remove_interface,
2569         .config             = ath9k_config,
2570         .configure_filter   = ath9k_configure_filter,
2571         .sta_state          = ath9k_sta_state,
2572         .sta_notify         = ath9k_sta_notify,
2573         .conf_tx            = ath9k_conf_tx,
2574         .bss_info_changed   = ath9k_bss_info_changed,
2575         .set_key            = ath9k_set_key,
2576         .get_tsf            = ath9k_get_tsf,
2577         .set_tsf            = ath9k_set_tsf,
2578         .reset_tsf          = ath9k_reset_tsf,
2579         .ampdu_action       = ath9k_ampdu_action,
2580         .get_survey         = ath9k_get_survey,
2581         .rfkill_poll        = ath9k_rfkill_poll_state,
2582         .set_coverage_class = ath9k_set_coverage_class,
2583         .flush              = ath9k_flush,
2584         .tx_frames_pending  = ath9k_tx_frames_pending,
2585         .tx_last_beacon     = ath9k_tx_last_beacon,
2586         .release_buffered_frames = ath9k_release_buffered_frames,
2587         .get_stats          = ath9k_get_stats,
2588         .set_antenna        = ath9k_set_antenna,
2589         .get_antenna        = ath9k_get_antenna,
2590
2591 #ifdef CONFIG_ATH9K_WOW
2592         .suspend            = ath9k_suspend,
2593         .resume             = ath9k_resume,
2594         .set_wakeup         = ath9k_set_wakeup,
2595 #endif
2596
2597 #ifdef CONFIG_ATH9K_DEBUGFS
2598         .get_et_sset_count  = ath9k_get_et_sset_count,
2599         .get_et_stats       = ath9k_get_et_stats,
2600         .get_et_strings     = ath9k_get_et_strings,
2601 #endif
2602
2603 #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_STATION_STATISTICS)
2604         .sta_add_debugfs    = ath9k_sta_add_debugfs,
2605 #endif
2606         .sw_scan_start      = ath9k_sw_scan_start,
2607         .sw_scan_complete   = ath9k_sw_scan_complete,
2608         .get_txpower        = ath9k_get_txpower,
2609 };