2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 #define BITS_PER_BYTE 8
20 #define OFDM_PLCP_BITS 22
21 #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f)
22 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
28 #define HT_LTF(_ns) (4 * (_ns))
29 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
30 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
31 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
32 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
34 #define OFDM_SIFS_TIME 16
36 static u32 bits_per_symbol[][2] = {
38 { 26, 54 }, /* 0: BPSK */
39 { 52, 108 }, /* 1: QPSK 1/2 */
40 { 78, 162 }, /* 2: QPSK 3/4 */
41 { 104, 216 }, /* 3: 16-QAM 1/2 */
42 { 156, 324 }, /* 4: 16-QAM 3/4 */
43 { 208, 432 }, /* 5: 64-QAM 2/3 */
44 { 234, 486 }, /* 6: 64-QAM 3/4 */
45 { 260, 540 }, /* 7: 64-QAM 5/6 */
46 { 52, 108 }, /* 8: BPSK */
47 { 104, 216 }, /* 9: QPSK 1/2 */
48 { 156, 324 }, /* 10: QPSK 3/4 */
49 { 208, 432 }, /* 11: 16-QAM 1/2 */
50 { 312, 648 }, /* 12: 16-QAM 3/4 */
51 { 416, 864 }, /* 13: 64-QAM 2/3 */
52 { 468, 972 }, /* 14: 64-QAM 3/4 */
53 { 520, 1080 }, /* 15: 64-QAM 5/6 */
56 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
58 static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq,
59 struct ath_atx_tid *tid,
60 struct list_head *bf_head);
61 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
62 struct list_head *bf_q,
63 int txok, int sendbar);
64 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
65 struct list_head *head);
66 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf);
67 static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf,
69 static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds,
70 int nbad, int txok, bool update_rc);
72 /*********************/
73 /* Aggregation logic */
74 /*********************/
76 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
78 struct ath_atx_ac *ac = tid->ac;
87 list_add_tail(&tid->list, &ac->tid_q);
93 list_add_tail(&ac->list, &txq->axq_acq);
96 static void ath_tx_pause_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
98 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
100 spin_lock_bh(&txq->axq_lock);
102 spin_unlock_bh(&txq->axq_lock);
105 static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
107 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
109 ASSERT(tid->paused > 0);
110 spin_lock_bh(&txq->axq_lock);
117 if (list_empty(&tid->buf_q))
120 ath_tx_queue_tid(txq, tid);
121 ath_txq_schedule(sc, txq);
123 spin_unlock_bh(&txq->axq_lock);
126 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
128 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
130 struct list_head bf_head;
131 INIT_LIST_HEAD(&bf_head);
133 ASSERT(tid->paused > 0);
134 spin_lock_bh(&txq->axq_lock);
138 if (tid->paused > 0) {
139 spin_unlock_bh(&txq->axq_lock);
143 while (!list_empty(&tid->buf_q)) {
144 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
145 ASSERT(!bf_isretried(bf));
146 list_move_tail(&bf->list, &bf_head);
147 ath_tx_send_ht_normal(sc, txq, tid, &bf_head);
150 spin_unlock_bh(&txq->axq_lock);
153 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
158 index = ATH_BA_INDEX(tid->seq_start, seqno);
159 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
161 tid->tx_buf[cindex] = NULL;
163 while (tid->baw_head != tid->baw_tail && !tid->tx_buf[tid->baw_head]) {
164 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
165 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
169 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
174 if (bf_isretried(bf))
177 index = ATH_BA_INDEX(tid->seq_start, bf->bf_seqno);
178 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
180 ASSERT(tid->tx_buf[cindex] == NULL);
181 tid->tx_buf[cindex] = bf;
183 if (index >= ((tid->baw_tail - tid->baw_head) &
184 (ATH_TID_MAX_BUFS - 1))) {
185 tid->baw_tail = cindex;
186 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
191 * TODO: For frame(s) that are in the retry state, we will reuse the
192 * sequence number(s) without setting the retry bit. The
193 * alternative is to give up on these and BAR the receiver's window
196 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
197 struct ath_atx_tid *tid)
201 struct list_head bf_head;
202 INIT_LIST_HEAD(&bf_head);
205 if (list_empty(&tid->buf_q))
208 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
209 list_move_tail(&bf->list, &bf_head);
211 if (bf_isretried(bf))
212 ath_tx_update_baw(sc, tid, bf->bf_seqno);
214 spin_unlock(&txq->axq_lock);
215 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
216 spin_lock(&txq->axq_lock);
219 tid->seq_next = tid->seq_start;
220 tid->baw_tail = tid->baw_head;
223 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_buf *bf)
226 struct ieee80211_hdr *hdr;
228 bf->bf_state.bf_type |= BUF_RETRY;
232 hdr = (struct ieee80211_hdr *)skb->data;
233 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
236 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
240 spin_lock_bh(&sc->tx.txbuflock);
241 if (WARN_ON(list_empty(&sc->tx.txbuf))) {
242 spin_unlock_bh(&sc->tx.txbuflock);
245 tbf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
246 list_del(&tbf->list);
247 spin_unlock_bh(&sc->tx.txbuflock);
249 ATH_TXBUF_RESET(tbf);
251 tbf->bf_mpdu = bf->bf_mpdu;
252 tbf->bf_buf_addr = bf->bf_buf_addr;
253 *(tbf->bf_desc) = *(bf->bf_desc);
254 tbf->bf_state = bf->bf_state;
255 tbf->bf_dmacontext = bf->bf_dmacontext;
260 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
261 struct ath_buf *bf, struct list_head *bf_q,
264 struct ath_node *an = NULL;
266 struct ieee80211_sta *sta;
267 struct ieee80211_hdr *hdr;
268 struct ath_atx_tid *tid = NULL;
269 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
270 struct ath_desc *ds = bf_last->bf_desc;
271 struct list_head bf_head, bf_pending;
272 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0;
273 u32 ba[WME_BA_BMP_SIZE >> 5];
274 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
275 bool rc_update = true;
278 hdr = (struct ieee80211_hdr *)skb->data;
282 sta = ieee80211_find_sta(sc->hw, hdr->addr1);
288 an = (struct ath_node *)sta->drv_priv;
289 tid = ATH_AN_2_TID(an, bf->bf_tidno);
291 isaggr = bf_isaggr(bf);
292 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
294 if (isaggr && txok) {
295 if (ATH_DS_TX_BA(ds)) {
296 seq_st = ATH_DS_BA_SEQ(ds);
297 memcpy(ba, ATH_DS_BA_BITMAP(ds),
298 WME_BA_BMP_SIZE >> 3);
301 * AR5416 can become deaf/mute when BA
302 * issue happens. Chip needs to be reset.
303 * But AP code may have sychronization issues
304 * when perform internal reset in this routine.
305 * Only enable reset in STA mode for now.
307 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
312 INIT_LIST_HEAD(&bf_pending);
313 INIT_LIST_HEAD(&bf_head);
315 nbad = ath_tx_num_badfrms(sc, bf, txok);
317 txfail = txpending = 0;
318 bf_next = bf->bf_next;
320 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, bf->bf_seqno))) {
321 /* transmit completion, subframe is
322 * acked by block ack */
324 } else if (!isaggr && txok) {
325 /* transmit completion */
328 if (!(tid->state & AGGR_CLEANUP) &&
329 ds->ds_txstat.ts_flags != ATH9K_TX_SW_ABORTED) {
330 if (bf->bf_retries < ATH_MAX_SW_RETRIES) {
331 ath_tx_set_retry(sc, bf);
334 bf->bf_state.bf_type |= BUF_XRETRY;
341 * cleanup in progress, just fail
342 * the un-acked sub-frames
348 if (bf_next == NULL) {
350 * Make sure the last desc is reclaimed if it
351 * not a holding desc.
353 if (!bf_last->bf_stale)
354 list_move_tail(&bf->list, &bf_head);
356 INIT_LIST_HEAD(&bf_head);
358 ASSERT(!list_empty(bf_q));
359 list_move_tail(&bf->list, &bf_head);
364 * complete the acked-ones/xretried ones; update
367 spin_lock_bh(&txq->axq_lock);
368 ath_tx_update_baw(sc, tid, bf->bf_seqno);
369 spin_unlock_bh(&txq->axq_lock);
371 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
372 ath_tx_rc_status(bf, ds, nbad, txok, true);
375 ath_tx_rc_status(bf, ds, nbad, txok, false);
378 ath_tx_complete_buf(sc, bf, &bf_head, !txfail, sendbar);
380 /* retry the un-acked ones */
381 if (bf->bf_next == NULL && bf_last->bf_stale) {
384 tbf = ath_clone_txbuf(sc, bf_last);
386 * Update tx baw and complete the frame with
387 * failed status if we run out of tx buf
390 spin_lock_bh(&txq->axq_lock);
391 ath_tx_update_baw(sc, tid,
393 spin_unlock_bh(&txq->axq_lock);
395 bf->bf_state.bf_type |= BUF_XRETRY;
396 ath_tx_rc_status(bf, ds, nbad,
398 ath_tx_complete_buf(sc, bf, &bf_head,
403 ath9k_hw_cleartxdesc(sc->sc_ah, tbf->bf_desc);
404 list_add_tail(&tbf->list, &bf_head);
407 * Clear descriptor status words for
410 ath9k_hw_cleartxdesc(sc->sc_ah, bf->bf_desc);
414 * Put this buffer to the temporary pending
415 * queue to retain ordering
417 list_splice_tail_init(&bf_head, &bf_pending);
423 if (tid->state & AGGR_CLEANUP) {
424 if (tid->baw_head == tid->baw_tail) {
425 tid->state &= ~AGGR_ADDBA_COMPLETE;
426 tid->state &= ~AGGR_CLEANUP;
428 /* send buffered frames as singles */
429 ath_tx_flush_tid(sc, tid);
435 /* prepend un-acked frames to the beginning of the pending frame queue */
436 if (!list_empty(&bf_pending)) {
437 spin_lock_bh(&txq->axq_lock);
438 list_splice(&bf_pending, &tid->buf_q);
439 ath_tx_queue_tid(txq, tid);
440 spin_unlock_bh(&txq->axq_lock);
446 ath_reset(sc, false);
449 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
450 struct ath_atx_tid *tid)
452 const struct ath_rate_table *rate_table = sc->cur_rate_table;
454 struct ieee80211_tx_info *tx_info;
455 struct ieee80211_tx_rate *rates;
456 struct ath_tx_info_priv *tx_info_priv;
457 u32 max_4ms_framelen, frmlen;
458 u16 aggr_limit, legacy = 0, maxampdu;
462 tx_info = IEEE80211_SKB_CB(skb);
463 rates = tx_info->control.rates;
464 tx_info_priv = (struct ath_tx_info_priv *)tx_info->rate_driver_data[0];
467 * Find the lowest frame length among the rate series that will have a
468 * 4ms transmit duration.
469 * TODO - TXOP limit needs to be considered.
471 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
473 for (i = 0; i < 4; i++) {
474 if (rates[i].count) {
475 if (!WLAN_RC_PHY_HT(rate_table->info[rates[i].idx].phy)) {
480 frmlen = rate_table->info[rates[i].idx].max_4ms_framelen;
481 max_4ms_framelen = min(max_4ms_framelen, frmlen);
486 * limit aggregate size by the minimum rate if rate selected is
487 * not a probe rate, if rate selected is a probe rate then
488 * avoid aggregation of this packet.
490 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
493 aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_DEFAULT);
496 * h/w can accept aggregates upto 16 bit lengths (65535).
497 * The IE, however can hold upto 65536, which shows up here
498 * as zero. Ignore 65536 since we are constrained by hw.
500 maxampdu = tid->an->maxampdu;
502 aggr_limit = min(aggr_limit, maxampdu);
508 * Returns the number of delimiters to be added to
509 * meet the minimum required mpdudensity.
510 * caller should make sure that the rate is HT rate .
512 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
513 struct ath_buf *bf, u16 frmlen)
515 const struct ath_rate_table *rt = sc->cur_rate_table;
516 struct sk_buff *skb = bf->bf_mpdu;
517 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
518 u32 nsymbits, nsymbols, mpdudensity;
521 int width, half_gi, ndelim, mindelim;
523 /* Select standard number of delimiters based on frame length alone */
524 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
527 * If encryption enabled, hardware requires some more padding between
529 * TODO - this could be improved to be dependent on the rate.
530 * The hardware can keep up at lower rates, but not higher rates
532 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR)
533 ndelim += ATH_AGGR_ENCRYPTDELIM;
536 * Convert desired mpdu density from microeconds to bytes based
537 * on highest rate in rate series (i.e. first rate) to determine
538 * required minimum length for subframe. Take into account
539 * whether high rate is 20 or 40Mhz and half or full GI.
541 mpdudensity = tid->an->mpdudensity;
544 * If there is no mpdu density restriction, no further calculation
547 if (mpdudensity == 0)
550 rix = tx_info->control.rates[0].idx;
551 flags = tx_info->control.rates[0].flags;
552 rc = rt->info[rix].ratecode;
553 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
554 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
557 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(mpdudensity);
559 nsymbols = NUM_SYMBOLS_PER_USEC(mpdudensity);
564 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width];
565 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
567 if (frmlen < minlen) {
568 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
569 ndelim = max(mindelim, ndelim);
575 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
576 struct ath_atx_tid *tid,
577 struct list_head *bf_q)
579 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
580 struct ath_buf *bf, *bf_first, *bf_prev = NULL;
581 int rl = 0, nframes = 0, ndelim, prev_al = 0;
582 u16 aggr_limit = 0, al = 0, bpad = 0,
583 al_delta, h_baw = tid->baw_size / 2;
584 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
586 bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list);
589 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
591 /* do not step over block-ack window */
592 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno)) {
593 status = ATH_AGGR_BAW_CLOSED;
598 aggr_limit = ath_lookup_rate(sc, bf, tid);
602 /* do not exceed aggregation limit */
603 al_delta = ATH_AGGR_DELIM_SZ + bf->bf_frmlen;
606 (aggr_limit < (al + bpad + al_delta + prev_al))) {
607 status = ATH_AGGR_LIMITED;
611 /* do not exceed subframe limit */
612 if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
613 status = ATH_AGGR_LIMITED;
618 /* add padding for previous frame to aggregation length */
619 al += bpad + al_delta;
622 * Get the delimiters needed to meet the MPDU
623 * density for this node.
625 ndelim = ath_compute_num_delims(sc, tid, bf_first, bf->bf_frmlen);
626 bpad = PADBYTES(al_delta) + (ndelim << 2);
629 bf->bf_desc->ds_link = 0;
631 /* link buffers of this frame to the aggregate */
632 ath_tx_addto_baw(sc, tid, bf);
633 ath9k_hw_set11n_aggr_middle(sc->sc_ah, bf->bf_desc, ndelim);
634 list_move_tail(&bf->list, bf_q);
636 bf_prev->bf_next = bf;
637 bf_prev->bf_desc->ds_link = bf->bf_daddr;
640 } while (!list_empty(&tid->buf_q));
642 bf_first->bf_al = al;
643 bf_first->bf_nframes = nframes;
649 static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
650 struct ath_atx_tid *tid)
653 enum ATH_AGGR_STATUS status;
654 struct list_head bf_q;
657 if (list_empty(&tid->buf_q))
660 INIT_LIST_HEAD(&bf_q);
662 status = ath_tx_form_aggr(sc, tid, &bf_q);
665 * no frames picked up to be aggregated;
666 * block-ack window is not open.
668 if (list_empty(&bf_q))
671 bf = list_first_entry(&bf_q, struct ath_buf, list);
672 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
674 /* if only one frame, send as non-aggregate */
675 if (bf->bf_nframes == 1) {
676 bf->bf_state.bf_type &= ~BUF_AGGR;
677 ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc);
678 ath_buf_set_rate(sc, bf);
679 ath_tx_txqaddbuf(sc, txq, &bf_q);
683 /* setup first desc of aggregate */
684 bf->bf_state.bf_type |= BUF_AGGR;
685 ath_buf_set_rate(sc, bf);
686 ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al);
688 /* anchor last desc of aggregate */
689 ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc);
691 txq->axq_aggr_depth++;
692 ath_tx_txqaddbuf(sc, txq, &bf_q);
694 } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH &&
695 status != ATH_AGGR_BAW_CLOSED);
698 void ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
701 struct ath_atx_tid *txtid;
704 an = (struct ath_node *)sta->drv_priv;
705 txtid = ATH_AN_2_TID(an, tid);
706 txtid->state |= AGGR_ADDBA_PROGRESS;
707 ath_tx_pause_tid(sc, txtid);
708 *ssn = txtid->seq_start;
711 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
713 struct ath_node *an = (struct ath_node *)sta->drv_priv;
714 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
715 struct ath_txq *txq = &sc->tx.txq[txtid->ac->qnum];
717 struct list_head bf_head;
718 INIT_LIST_HEAD(&bf_head);
720 if (txtid->state & AGGR_CLEANUP)
723 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
724 txtid->state &= ~AGGR_ADDBA_PROGRESS;
728 ath_tx_pause_tid(sc, txtid);
730 /* drop all software retried frames and mark this TID */
731 spin_lock_bh(&txq->axq_lock);
732 while (!list_empty(&txtid->buf_q)) {
733 bf = list_first_entry(&txtid->buf_q, struct ath_buf, list);
734 if (!bf_isretried(bf)) {
736 * NB: it's based on the assumption that
737 * software retried frame will always stay
738 * at the head of software queue.
742 list_move_tail(&bf->list, &bf_head);
743 ath_tx_update_baw(sc, txtid, bf->bf_seqno);
744 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
746 spin_unlock_bh(&txq->axq_lock);
748 if (txtid->baw_head != txtid->baw_tail) {
749 txtid->state |= AGGR_CLEANUP;
751 txtid->state &= ~AGGR_ADDBA_COMPLETE;
752 ath_tx_flush_tid(sc, txtid);
756 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
758 struct ath_atx_tid *txtid;
761 an = (struct ath_node *)sta->drv_priv;
763 if (sc->sc_flags & SC_OP_TXAGGR) {
764 txtid = ATH_AN_2_TID(an, tid);
766 IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
767 txtid->state |= AGGR_ADDBA_COMPLETE;
768 txtid->state &= ~AGGR_ADDBA_PROGRESS;
769 ath_tx_resume_tid(sc, txtid);
773 bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno)
775 struct ath_atx_tid *txtid;
777 if (!(sc->sc_flags & SC_OP_TXAGGR))
780 txtid = ATH_AN_2_TID(an, tidno);
782 if (!(txtid->state & (AGGR_ADDBA_COMPLETE | AGGR_ADDBA_PROGRESS)))
787 /********************/
788 /* Queue Management */
789 /********************/
791 static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
794 struct ath_atx_ac *ac, *ac_tmp;
795 struct ath_atx_tid *tid, *tid_tmp;
797 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
800 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
801 list_del(&tid->list);
803 ath_tid_drain(sc, txq, tid);
808 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
810 struct ath_hw *ah = sc->sc_ah;
811 struct ath9k_tx_queue_info qi;
814 memset(&qi, 0, sizeof(qi));
815 qi.tqi_subtype = subtype;
816 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
817 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
818 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
819 qi.tqi_physCompBuf = 0;
822 * Enable interrupts only for EOL and DESC conditions.
823 * We mark tx descriptors to receive a DESC interrupt
824 * when a tx queue gets deep; otherwise waiting for the
825 * EOL to reap descriptors. Note that this is done to
826 * reduce interrupt load and this only defers reaping
827 * descriptors, never transmitting frames. Aside from
828 * reducing interrupts this also permits more concurrency.
829 * The only potential downside is if the tx queue backs
830 * up in which case the top half of the kernel may backup
831 * due to a lack of tx descriptors.
833 * The UAPSD queue is an exception, since we take a desc-
834 * based intr on the EOSP frames.
836 if (qtype == ATH9K_TX_QUEUE_UAPSD)
837 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
839 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
840 TXQ_FLAG_TXDESCINT_ENABLE;
841 qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
844 * NB: don't print a message, this happens
845 * normally on parts with too few tx queues
849 if (qnum >= ARRAY_SIZE(sc->tx.txq)) {
850 DPRINTF(sc, ATH_DBG_FATAL,
851 "qnum %u out of range, max %u!\n",
852 qnum, (unsigned int)ARRAY_SIZE(sc->tx.txq));
853 ath9k_hw_releasetxqueue(ah, qnum);
856 if (!ATH_TXQ_SETUP(sc, qnum)) {
857 struct ath_txq *txq = &sc->tx.txq[qnum];
859 txq->axq_qnum = qnum;
860 txq->axq_link = NULL;
861 INIT_LIST_HEAD(&txq->axq_q);
862 INIT_LIST_HEAD(&txq->axq_acq);
863 spin_lock_init(&txq->axq_lock);
865 txq->axq_aggr_depth = 0;
866 txq->axq_totalqueued = 0;
867 txq->axq_linkbuf = NULL;
868 txq->axq_tx_inprogress = false;
869 sc->tx.txqsetup |= 1<<qnum;
871 return &sc->tx.txq[qnum];
874 static int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype)
879 case ATH9K_TX_QUEUE_DATA:
880 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
881 DPRINTF(sc, ATH_DBG_FATAL,
882 "HAL AC %u out of range, max %zu!\n",
883 haltype, ARRAY_SIZE(sc->tx.hwq_map));
886 qnum = sc->tx.hwq_map[haltype];
888 case ATH9K_TX_QUEUE_BEACON:
889 qnum = sc->beacon.beaconq;
891 case ATH9K_TX_QUEUE_CAB:
892 qnum = sc->beacon.cabq->axq_qnum;
900 struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb)
902 struct ath_txq *txq = NULL;
905 qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc);
906 txq = &sc->tx.txq[qnum];
908 spin_lock_bh(&txq->axq_lock);
910 if (txq->axq_depth >= (ATH_TXBUF - 20)) {
911 DPRINTF(sc, ATH_DBG_XMIT,
912 "TX queue: %d is full, depth: %d\n",
913 qnum, txq->axq_depth);
914 ieee80211_stop_queue(sc->hw, skb_get_queue_mapping(skb));
916 spin_unlock_bh(&txq->axq_lock);
920 spin_unlock_bh(&txq->axq_lock);
925 int ath_txq_update(struct ath_softc *sc, int qnum,
926 struct ath9k_tx_queue_info *qinfo)
928 struct ath_hw *ah = sc->sc_ah;
930 struct ath9k_tx_queue_info qi;
932 if (qnum == sc->beacon.beaconq) {
934 * XXX: for beacon queue, we just save the parameter.
935 * It will be picked up by ath_beaconq_config when
938 sc->beacon.beacon_qi = *qinfo;
942 ASSERT(sc->tx.txq[qnum].axq_qnum == qnum);
944 ath9k_hw_get_txq_props(ah, qnum, &qi);
945 qi.tqi_aifs = qinfo->tqi_aifs;
946 qi.tqi_cwmin = qinfo->tqi_cwmin;
947 qi.tqi_cwmax = qinfo->tqi_cwmax;
948 qi.tqi_burstTime = qinfo->tqi_burstTime;
949 qi.tqi_readyTime = qinfo->tqi_readyTime;
951 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
952 DPRINTF(sc, ATH_DBG_FATAL,
953 "Unable to update hardware queue %u!\n", qnum);
956 ath9k_hw_resettxqueue(ah, qnum);
962 int ath_cabq_update(struct ath_softc *sc)
964 struct ath9k_tx_queue_info qi;
965 int qnum = sc->beacon.cabq->axq_qnum;
967 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
969 * Ensure the readytime % is within the bounds.
971 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
972 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
973 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
974 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
976 qi.tqi_readyTime = (sc->beacon_interval *
977 sc->config.cabqReadytime) / 100;
978 ath_txq_update(sc, qnum, &qi);
984 * Drain a given TX queue (could be Beacon or Data)
986 * This assumes output has been stopped and
987 * we do not need to block ath_tx_tasklet.
989 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
991 struct ath_buf *bf, *lastbf;
992 struct list_head bf_head;
994 INIT_LIST_HEAD(&bf_head);
997 spin_lock_bh(&txq->axq_lock);
999 if (list_empty(&txq->axq_q)) {
1000 txq->axq_link = NULL;
1001 txq->axq_linkbuf = NULL;
1002 spin_unlock_bh(&txq->axq_lock);
1006 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
1009 list_del(&bf->list);
1010 spin_unlock_bh(&txq->axq_lock);
1012 spin_lock_bh(&sc->tx.txbuflock);
1013 list_add_tail(&bf->list, &sc->tx.txbuf);
1014 spin_unlock_bh(&sc->tx.txbuflock);
1018 lastbf = bf->bf_lastbf;
1020 lastbf->bf_desc->ds_txstat.ts_flags =
1021 ATH9K_TX_SW_ABORTED;
1023 /* remove ath_buf's of the same mpdu from txq */
1024 list_cut_position(&bf_head, &txq->axq_q, &lastbf->list);
1027 spin_unlock_bh(&txq->axq_lock);
1030 ath_tx_complete_aggr(sc, txq, bf, &bf_head, 0);
1032 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
1035 spin_lock_bh(&txq->axq_lock);
1036 txq->axq_tx_inprogress = false;
1037 spin_unlock_bh(&txq->axq_lock);
1039 /* flush any pending frames if aggregation is enabled */
1040 if (sc->sc_flags & SC_OP_TXAGGR) {
1042 spin_lock_bh(&txq->axq_lock);
1043 ath_txq_drain_pending_buffers(sc, txq);
1044 spin_unlock_bh(&txq->axq_lock);
1049 void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1051 struct ath_hw *ah = sc->sc_ah;
1052 struct ath_txq *txq;
1055 if (sc->sc_flags & SC_OP_INVALID)
1058 /* Stop beacon queue */
1059 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
1061 /* Stop data queues */
1062 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1063 if (ATH_TXQ_SETUP(sc, i)) {
1064 txq = &sc->tx.txq[i];
1065 ath9k_hw_stoptxdma(ah, txq->axq_qnum);
1066 npend += ath9k_hw_numtxpending(ah, txq->axq_qnum);
1073 DPRINTF(sc, ATH_DBG_XMIT, "Unable to stop TxDMA. Reset HAL!\n");
1075 spin_lock_bh(&sc->sc_resetlock);
1076 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, true);
1078 DPRINTF(sc, ATH_DBG_FATAL,
1079 "Unable to reset hardware; reset status %d\n",
1081 spin_unlock_bh(&sc->sc_resetlock);
1084 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1085 if (ATH_TXQ_SETUP(sc, i))
1086 ath_draintxq(sc, &sc->tx.txq[i], retry_tx);
1090 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1092 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1093 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1096 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1098 struct ath_atx_ac *ac;
1099 struct ath_atx_tid *tid;
1101 if (list_empty(&txq->axq_acq))
1104 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1105 list_del(&ac->list);
1109 if (list_empty(&ac->tid_q))
1112 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, list);
1113 list_del(&tid->list);
1119 ath_tx_sched_aggr(sc, txq, tid);
1122 * add tid to round-robin queue if more frames
1123 * are pending for the tid
1125 if (!list_empty(&tid->buf_q))
1126 ath_tx_queue_tid(txq, tid);
1129 } while (!list_empty(&ac->tid_q));
1131 if (!list_empty(&ac->tid_q)) {
1134 list_add_tail(&ac->list, &txq->axq_acq);
1139 int ath_tx_setup(struct ath_softc *sc, int haltype)
1141 struct ath_txq *txq;
1143 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
1144 DPRINTF(sc, ATH_DBG_FATAL,
1145 "HAL AC %u out of range, max %zu!\n",
1146 haltype, ARRAY_SIZE(sc->tx.hwq_map));
1149 txq = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, haltype);
1151 sc->tx.hwq_map[haltype] = txq->axq_qnum;
1162 * Insert a chain of ath_buf (descriptors) on a txq and
1163 * assume the descriptors are already chained together by caller.
1165 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1166 struct list_head *head)
1168 struct ath_hw *ah = sc->sc_ah;
1172 * Insert the frame on the outbound list and
1173 * pass it on to the hardware.
1176 if (list_empty(head))
1179 bf = list_first_entry(head, struct ath_buf, list);
1181 list_splice_tail_init(head, &txq->axq_q);
1183 txq->axq_totalqueued++;
1184 txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list);
1186 DPRINTF(sc, ATH_DBG_QUEUE,
1187 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
1189 if (txq->axq_link == NULL) {
1190 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1191 DPRINTF(sc, ATH_DBG_XMIT,
1192 "TXDP[%u] = %llx (%p)\n",
1193 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1195 *txq->axq_link = bf->bf_daddr;
1196 DPRINTF(sc, ATH_DBG_XMIT, "link[%u] (%p)=%llx (%p)\n",
1197 txq->axq_qnum, txq->axq_link,
1198 ito64(bf->bf_daddr), bf->bf_desc);
1200 txq->axq_link = &(bf->bf_lastbf->bf_desc->ds_link);
1201 ath9k_hw_txstart(ah, txq->axq_qnum);
1204 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
1206 struct ath_buf *bf = NULL;
1208 spin_lock_bh(&sc->tx.txbuflock);
1210 if (unlikely(list_empty(&sc->tx.txbuf))) {
1211 spin_unlock_bh(&sc->tx.txbuflock);
1215 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
1216 list_del(&bf->list);
1218 spin_unlock_bh(&sc->tx.txbuflock);
1223 static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
1224 struct list_head *bf_head,
1225 struct ath_tx_control *txctl)
1229 bf = list_first_entry(bf_head, struct ath_buf, list);
1230 bf->bf_state.bf_type |= BUF_AMPDU;
1233 * Do not queue to h/w when any of the following conditions is true:
1234 * - there are pending frames in software queue
1235 * - the TID is currently paused for ADDBA/BAR request
1236 * - seqno is not within block-ack window
1237 * - h/w queue depth exceeds low water mark
1239 if (!list_empty(&tid->buf_q) || tid->paused ||
1240 !BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno) ||
1241 txctl->txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) {
1243 * Add this frame to software queue for scheduling later
1246 list_move_tail(&bf->list, &tid->buf_q);
1247 ath_tx_queue_tid(txctl->txq, tid);
1251 /* Add sub-frame to BAW */
1252 ath_tx_addto_baw(sc, tid, bf);
1254 /* Queue to h/w without aggregation */
1257 ath_buf_set_rate(sc, bf);
1258 ath_tx_txqaddbuf(sc, txctl->txq, bf_head);
1261 static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq,
1262 struct ath_atx_tid *tid,
1263 struct list_head *bf_head)
1267 bf = list_first_entry(bf_head, struct ath_buf, list);
1268 bf->bf_state.bf_type &= ~BUF_AMPDU;
1270 /* update starting sequence number for subsequent ADDBA request */
1271 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1275 ath_buf_set_rate(sc, bf);
1276 ath_tx_txqaddbuf(sc, txq, bf_head);
1279 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1280 struct list_head *bf_head)
1284 bf = list_first_entry(bf_head, struct ath_buf, list);
1288 ath_buf_set_rate(sc, bf);
1289 ath_tx_txqaddbuf(sc, txq, bf_head);
1292 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1294 struct ieee80211_hdr *hdr;
1295 enum ath9k_pkt_type htype;
1298 hdr = (struct ieee80211_hdr *)skb->data;
1299 fc = hdr->frame_control;
1301 if (ieee80211_is_beacon(fc))
1302 htype = ATH9K_PKT_TYPE_BEACON;
1303 else if (ieee80211_is_probe_resp(fc))
1304 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1305 else if (ieee80211_is_atim(fc))
1306 htype = ATH9K_PKT_TYPE_ATIM;
1307 else if (ieee80211_is_pspoll(fc))
1308 htype = ATH9K_PKT_TYPE_PSPOLL;
1310 htype = ATH9K_PKT_TYPE_NORMAL;
1315 static bool is_pae(struct sk_buff *skb)
1317 struct ieee80211_hdr *hdr;
1320 hdr = (struct ieee80211_hdr *)skb->data;
1321 fc = hdr->frame_control;
1323 if (ieee80211_is_data(fc)) {
1324 if (ieee80211_is_nullfunc(fc) ||
1325 /* Port Access Entity (IEEE 802.1X) */
1326 (skb->protocol == cpu_to_be16(ETH_P_PAE))) {
1334 static int get_hw_crypto_keytype(struct sk_buff *skb)
1336 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1338 if (tx_info->control.hw_key) {
1339 if (tx_info->control.hw_key->alg == ALG_WEP)
1340 return ATH9K_KEY_TYPE_WEP;
1341 else if (tx_info->control.hw_key->alg == ALG_TKIP)
1342 return ATH9K_KEY_TYPE_TKIP;
1343 else if (tx_info->control.hw_key->alg == ALG_CCMP)
1344 return ATH9K_KEY_TYPE_AES;
1347 return ATH9K_KEY_TYPE_CLEAR;
1350 static void assign_aggr_tid_seqno(struct sk_buff *skb,
1353 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1354 struct ieee80211_hdr *hdr;
1355 struct ath_node *an;
1356 struct ath_atx_tid *tid;
1360 if (!tx_info->control.sta)
1363 an = (struct ath_node *)tx_info->control.sta->drv_priv;
1364 hdr = (struct ieee80211_hdr *)skb->data;
1365 fc = hdr->frame_control;
1367 if (ieee80211_is_data_qos(fc)) {
1368 qc = ieee80211_get_qos_ctl(hdr);
1369 bf->bf_tidno = qc[0] & 0xf;
1373 * For HT capable stations, we save tidno for later use.
1374 * We also override seqno set by upper layer with the one
1375 * in tx aggregation state.
1377 * If fragmentation is on, the sequence number is
1378 * not overridden, since it has been
1379 * incremented by the fragmentation routine.
1381 * FIXME: check if the fragmentation threshold exceeds
1384 tid = ATH_AN_2_TID(an, bf->bf_tidno);
1385 hdr->seq_ctrl = cpu_to_le16(tid->seq_next <<
1386 IEEE80211_SEQ_SEQ_SHIFT);
1387 bf->bf_seqno = tid->seq_next;
1388 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
1391 static int setup_tx_flags(struct ath_softc *sc, struct sk_buff *skb,
1392 struct ath_txq *txq)
1394 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1397 flags |= ATH9K_TXDESC_CLRDMASK; /* needed for crypto errors */
1398 flags |= ATH9K_TXDESC_INTREQ;
1400 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1401 flags |= ATH9K_TXDESC_NOACK;
1408 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1409 * width - 0 for 20 MHz, 1 for 40 MHz
1410 * half_gi - to use 4us v/s 3.6 us for symbol time
1412 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf,
1413 int width, int half_gi, bool shortPreamble)
1415 const struct ath_rate_table *rate_table = sc->cur_rate_table;
1416 u32 nbits, nsymbits, duration, nsymbols;
1418 int streams, pktlen;
1420 pktlen = bf_isaggr(bf) ? bf->bf_al : bf->bf_frmlen;
1421 rc = rate_table->info[rix].ratecode;
1423 /* for legacy rates, use old function to compute packet duration */
1424 if (!IS_HT_RATE(rc))
1425 return ath9k_hw_computetxtime(sc->sc_ah, rate_table, pktlen,
1426 rix, shortPreamble);
1428 /* find number of symbols: PLCP + data */
1429 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1430 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width];
1431 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1434 duration = SYMBOL_TIME(nsymbols);
1436 duration = SYMBOL_TIME_HALFGI(nsymbols);
1438 /* addup duration for legacy/ht training and signal fields */
1439 streams = HT_RC_2_STREAMS(rc);
1440 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1445 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
1447 const struct ath_rate_table *rt = sc->cur_rate_table;
1448 struct ath9k_11n_rate_series series[4];
1449 struct sk_buff *skb;
1450 struct ieee80211_tx_info *tx_info;
1451 struct ieee80211_tx_rate *rates;
1452 struct ieee80211_hdr *hdr;
1454 u8 rix = 0, ctsrate = 0;
1457 memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4);
1460 tx_info = IEEE80211_SKB_CB(skb);
1461 rates = tx_info->control.rates;
1462 hdr = (struct ieee80211_hdr *)skb->data;
1463 is_pspoll = ieee80211_is_pspoll(hdr->frame_control);
1466 * We check if Short Preamble is needed for the CTS rate by
1467 * checking the BSS's global flag.
1468 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
1470 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
1471 ctsrate = rt->info[tx_info->control.rts_cts_rate_idx].ratecode |
1472 rt->info[tx_info->control.rts_cts_rate_idx].short_preamble;
1474 ctsrate = rt->info[tx_info->control.rts_cts_rate_idx].ratecode;
1477 * ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive.
1478 * Check the first rate in the series to decide whether RTS/CTS
1479 * or CTS-to-self has to be used.
1481 if (rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT)
1482 flags = ATH9K_TXDESC_CTSENA;
1483 else if (rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS)
1484 flags = ATH9K_TXDESC_RTSENA;
1486 /* FIXME: Handle aggregation protection */
1487 if (sc->config.ath_aggr_prot &&
1488 (!bf_isaggr(bf) || (bf_isaggr(bf) && bf->bf_al < 8192))) {
1489 flags = ATH9K_TXDESC_RTSENA;
1492 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1493 if (bf_isaggr(bf) && (bf->bf_al > sc->sc_ah->caps.rts_aggr_limit))
1494 flags &= ~(ATH9K_TXDESC_RTSENA);
1496 for (i = 0; i < 4; i++) {
1497 if (!rates[i].count || (rates[i].idx < 0))
1501 series[i].Tries = rates[i].count;
1502 series[i].ChSel = sc->tx_chainmask;
1504 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1505 series[i].Rate = rt->info[rix].ratecode |
1506 rt->info[rix].short_preamble;
1508 series[i].Rate = rt->info[rix].ratecode;
1510 if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS)
1511 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1512 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1513 series[i].RateFlags |= ATH9K_RATESERIES_2040;
1514 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1515 series[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1517 series[i].PktDuration = ath_pkt_duration(sc, rix, bf,
1518 (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) != 0,
1519 (rates[i].flags & IEEE80211_TX_RC_SHORT_GI),
1520 (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE));
1523 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1524 ath9k_hw_set11n_ratescenario(sc->sc_ah, bf->bf_desc,
1525 bf->bf_lastbf->bf_desc,
1526 !is_pspoll, ctsrate,
1527 0, series, 4, flags);
1529 if (sc->config.ath_aggr_prot && flags)
1530 ath9k_hw_set11n_burstduration(sc->sc_ah, bf->bf_desc, 8192);
1533 static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf,
1534 struct sk_buff *skb,
1535 struct ath_tx_control *txctl)
1537 struct ath_wiphy *aphy = hw->priv;
1538 struct ath_softc *sc = aphy->sc;
1539 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1540 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1541 struct ath_tx_info_priv *tx_info_priv;
1545 tx_info_priv = kzalloc(sizeof(*tx_info_priv), GFP_ATOMIC);
1546 if (unlikely(!tx_info_priv))
1548 tx_info->rate_driver_data[0] = tx_info_priv;
1549 tx_info_priv->aphy = aphy;
1550 tx_info_priv->frame_type = txctl->frame_type;
1551 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1552 fc = hdr->frame_control;
1554 ATH_TXBUF_RESET(bf);
1556 bf->bf_frmlen = skb->len + FCS_LEN - (hdrlen & 3);
1558 if (conf_is_ht(&sc->hw->conf) && !is_pae(skb))
1559 bf->bf_state.bf_type |= BUF_HT;
1561 bf->bf_flags = setup_tx_flags(sc, skb, txctl->txq);
1563 bf->bf_keytype = get_hw_crypto_keytype(skb);
1564 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) {
1565 bf->bf_frmlen += tx_info->control.hw_key->icv_len;
1566 bf->bf_keyix = tx_info->control.hw_key->hw_key_idx;
1568 bf->bf_keyix = ATH9K_TXKEYIX_INVALID;
1571 if (ieee80211_is_data_qos(fc) && (sc->sc_flags & SC_OP_TXAGGR))
1572 assign_aggr_tid_seqno(skb, bf);
1576 bf->bf_dmacontext = dma_map_single(sc->dev, skb->data,
1577 skb->len, DMA_TO_DEVICE);
1578 if (unlikely(dma_mapping_error(sc->dev, bf->bf_dmacontext))) {
1580 kfree(tx_info_priv);
1581 tx_info->rate_driver_data[0] = NULL;
1582 DPRINTF(sc, ATH_DBG_FATAL, "dma_mapping_error() on TX\n");
1586 bf->bf_buf_addr = bf->bf_dmacontext;
1590 /* FIXME: tx power */
1591 static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
1592 struct ath_tx_control *txctl)
1594 struct sk_buff *skb = bf->bf_mpdu;
1595 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1596 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1597 struct ath_node *an = NULL;
1598 struct list_head bf_head;
1599 struct ath_desc *ds;
1600 struct ath_atx_tid *tid;
1601 struct ath_hw *ah = sc->sc_ah;
1605 frm_type = get_hw_packet_type(skb);
1606 fc = hdr->frame_control;
1608 INIT_LIST_HEAD(&bf_head);
1609 list_add_tail(&bf->list, &bf_head);
1613 ds->ds_data = bf->bf_buf_addr;
1615 ath9k_hw_set11n_txdesc(ah, ds, bf->bf_frmlen, frm_type, MAX_RATE_POWER,
1616 bf->bf_keyix, bf->bf_keytype, bf->bf_flags);
1618 ath9k_hw_filltxdesc(ah, ds,
1619 skb->len, /* segment length */
1620 true, /* first segment */
1621 true, /* last segment */
1622 ds); /* first descriptor */
1624 spin_lock_bh(&txctl->txq->axq_lock);
1626 if (bf_isht(bf) && (sc->sc_flags & SC_OP_TXAGGR) &&
1627 tx_info->control.sta) {
1628 an = (struct ath_node *)tx_info->control.sta->drv_priv;
1629 tid = ATH_AN_2_TID(an, bf->bf_tidno);
1631 if (!ieee80211_is_data_qos(fc)) {
1632 ath_tx_send_normal(sc, txctl->txq, &bf_head);
1636 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
1638 * Try aggregation if it's a unicast data frame
1639 * and the destination is HT capable.
1641 ath_tx_send_ampdu(sc, tid, &bf_head, txctl);
1644 * Send this frame as regular when ADDBA
1645 * exchange is neither complete nor pending.
1647 ath_tx_send_ht_normal(sc, txctl->txq,
1651 ath_tx_send_normal(sc, txctl->txq, &bf_head);
1655 spin_unlock_bh(&txctl->txq->axq_lock);
1658 /* Upon failure caller should free skb */
1659 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1660 struct ath_tx_control *txctl)
1662 struct ath_wiphy *aphy = hw->priv;
1663 struct ath_softc *sc = aphy->sc;
1667 bf = ath_tx_get_buffer(sc);
1669 DPRINTF(sc, ATH_DBG_XMIT, "TX buffers are full\n");
1673 r = ath_tx_setup_buffer(hw, bf, skb, txctl);
1675 struct ath_txq *txq = txctl->txq;
1677 DPRINTF(sc, ATH_DBG_FATAL, "TX mem alloc failure\n");
1679 /* upon ath_tx_processq() this TX queue will be resumed, we
1680 * guarantee this will happen by knowing beforehand that
1681 * we will at least have to run TX completionon one buffer
1683 spin_lock_bh(&txq->axq_lock);
1684 if (sc->tx.txq[txq->axq_qnum].axq_depth > 1) {
1685 ieee80211_stop_queue(sc->hw,
1686 skb_get_queue_mapping(skb));
1689 spin_unlock_bh(&txq->axq_lock);
1691 spin_lock_bh(&sc->tx.txbuflock);
1692 list_add_tail(&bf->list, &sc->tx.txbuf);
1693 spin_unlock_bh(&sc->tx.txbuflock);
1698 ath_tx_start_dma(sc, bf, txctl);
1703 void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
1705 struct ath_wiphy *aphy = hw->priv;
1706 struct ath_softc *sc = aphy->sc;
1707 int hdrlen, padsize;
1708 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1709 struct ath_tx_control txctl;
1711 memset(&txctl, 0, sizeof(struct ath_tx_control));
1714 * As a temporary workaround, assign seq# here; this will likely need
1715 * to be cleaned up to work better with Beacon transmission and virtual
1718 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1719 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1720 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1721 sc->tx.seq_no += 0x10;
1722 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1723 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1726 /* Add the padding after the header if this is not already done */
1727 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1729 padsize = hdrlen % 4;
1730 if (skb_headroom(skb) < padsize) {
1731 DPRINTF(sc, ATH_DBG_XMIT, "TX CABQ padding failed\n");
1732 dev_kfree_skb_any(skb);
1735 skb_push(skb, padsize);
1736 memmove(skb->data, skb->data + padsize, hdrlen);
1739 txctl.txq = sc->beacon.cabq;
1741 DPRINTF(sc, ATH_DBG_XMIT, "transmitting CABQ packet, skb: %p\n", skb);
1743 if (ath_tx_start(hw, skb, &txctl) != 0) {
1744 DPRINTF(sc, ATH_DBG_XMIT, "CABQ TX failed\n");
1750 dev_kfree_skb_any(skb);
1757 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1760 struct ieee80211_hw *hw = sc->hw;
1761 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1762 struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info);
1763 int hdrlen, padsize;
1764 int frame_type = ATH9K_NOT_INTERNAL;
1766 DPRINTF(sc, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
1769 hw = tx_info_priv->aphy->hw;
1770 frame_type = tx_info_priv->frame_type;
1773 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK ||
1774 tx_info->flags & IEEE80211_TX_STAT_TX_FILTERED) {
1775 kfree(tx_info_priv);
1776 tx_info->rate_driver_data[0] = NULL;
1779 if (tx_flags & ATH_TX_BAR)
1780 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1782 if (!(tx_flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) {
1783 /* Frame was ACKed */
1784 tx_info->flags |= IEEE80211_TX_STAT_ACK;
1787 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1788 padsize = hdrlen & 3;
1789 if (padsize && hdrlen >= 24) {
1791 * Remove MAC header padding before giving the frame back to
1794 memmove(skb->data + padsize, skb->data, hdrlen);
1795 skb_pull(skb, padsize);
1798 if (sc->sc_flags & SC_OP_WAIT_FOR_TX_ACK) {
1799 sc->sc_flags &= ~SC_OP_WAIT_FOR_TX_ACK;
1800 DPRINTF(sc, ATH_DBG_PS, "Going back to sleep after having "
1801 "received TX status (0x%x)\n",
1802 sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
1803 SC_OP_WAIT_FOR_CAB |
1804 SC_OP_WAIT_FOR_PSPOLL_DATA |
1805 SC_OP_WAIT_FOR_TX_ACK));
1808 if (frame_type == ATH9K_NOT_INTERNAL)
1809 ieee80211_tx_status(hw, skb);
1811 ath9k_tx_status(hw, skb);
1814 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
1815 struct list_head *bf_q,
1816 int txok, int sendbar)
1818 struct sk_buff *skb = bf->bf_mpdu;
1819 unsigned long flags;
1824 tx_flags = ATH_TX_BAR;
1827 tx_flags |= ATH_TX_ERROR;
1829 if (bf_isxretried(bf))
1830 tx_flags |= ATH_TX_XRETRY;
1833 dma_unmap_single(sc->dev, bf->bf_dmacontext, skb->len, DMA_TO_DEVICE);
1834 ath_tx_complete(sc, skb, tx_flags);
1837 * Return the list of ath_buf of this mpdu to free queue
1839 spin_lock_irqsave(&sc->tx.txbuflock, flags);
1840 list_splice_tail_init(bf_q, &sc->tx.txbuf);
1841 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
1844 static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf,
1847 struct ath_buf *bf_last = bf->bf_lastbf;
1848 struct ath_desc *ds = bf_last->bf_desc;
1850 u32 ba[WME_BA_BMP_SIZE >> 5];
1855 if (ds->ds_txstat.ts_flags == ATH9K_TX_SW_ABORTED)
1858 isaggr = bf_isaggr(bf);
1860 seq_st = ATH_DS_BA_SEQ(ds);
1861 memcpy(ba, ATH_DS_BA_BITMAP(ds), WME_BA_BMP_SIZE >> 3);
1865 ba_index = ATH_BA_INDEX(seq_st, bf->bf_seqno);
1866 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
1875 static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds,
1876 int nbad, int txok, bool update_rc)
1878 struct sk_buff *skb = bf->bf_mpdu;
1879 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1880 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1881 struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info);
1882 struct ieee80211_hw *hw = tx_info_priv->aphy->hw;
1886 tx_info->status.ack_signal = ds->ds_txstat.ts_rssi;
1888 tx_rateindex = ds->ds_txstat.ts_rateindex;
1889 WARN_ON(tx_rateindex >= hw->max_rates);
1891 tx_info_priv->update_rc = update_rc;
1892 if (ds->ds_txstat.ts_status & ATH9K_TXERR_FILT)
1893 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1895 if ((ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) == 0 &&
1896 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) {
1897 if (ieee80211_is_data(hdr->frame_control)) {
1898 memcpy(&tx_info_priv->tx, &ds->ds_txstat,
1899 sizeof(tx_info_priv->tx));
1900 tx_info_priv->n_frames = bf->bf_nframes;
1901 tx_info_priv->n_bad_frames = nbad;
1905 for (i = tx_rateindex + 1; i < hw->max_rates; i++)
1906 tx_info->status.rates[i].count = 0;
1908 tx_info->status.rates[tx_rateindex].count = bf->bf_retries + 1;
1911 static void ath_wake_mac80211_queue(struct ath_softc *sc, struct ath_txq *txq)
1915 spin_lock_bh(&txq->axq_lock);
1917 sc->tx.txq[txq->axq_qnum].axq_depth <= (ATH_TXBUF - 20)) {
1918 qnum = ath_get_mac80211_qnum(txq->axq_qnum, sc);
1920 ieee80211_wake_queue(sc->hw, qnum);
1924 spin_unlock_bh(&txq->axq_lock);
1927 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
1929 struct ath_hw *ah = sc->sc_ah;
1930 struct ath_buf *bf, *lastbf, *bf_held = NULL;
1931 struct list_head bf_head;
1932 struct ath_desc *ds;
1936 DPRINTF(sc, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
1937 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
1941 spin_lock_bh(&txq->axq_lock);
1942 if (list_empty(&txq->axq_q)) {
1943 txq->axq_link = NULL;
1944 txq->axq_linkbuf = NULL;
1945 spin_unlock_bh(&txq->axq_lock);
1948 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
1951 * There is a race condition that a BH gets scheduled
1952 * after sw writes TxE and before hw re-load the last
1953 * descriptor to get the newly chained one.
1954 * Software must keep the last DONE descriptor as a
1955 * holding descriptor - software does so by marking
1956 * it with the STALE flag.
1961 if (list_is_last(&bf_held->list, &txq->axq_q)) {
1962 spin_unlock_bh(&txq->axq_lock);
1965 bf = list_entry(bf_held->list.next,
1966 struct ath_buf, list);
1970 lastbf = bf->bf_lastbf;
1971 ds = lastbf->bf_desc;
1973 status = ath9k_hw_txprocdesc(ah, ds);
1974 if (status == -EINPROGRESS) {
1975 spin_unlock_bh(&txq->axq_lock);
1978 if (bf->bf_desc == txq->axq_lastdsWithCTS)
1979 txq->axq_lastdsWithCTS = NULL;
1980 if (ds == txq->axq_gatingds)
1981 txq->axq_gatingds = NULL;
1984 * Remove ath_buf's of the same transmit unit from txq,
1985 * however leave the last descriptor back as the holding
1986 * descriptor for hw.
1988 lastbf->bf_stale = true;
1989 INIT_LIST_HEAD(&bf_head);
1990 if (!list_is_singular(&lastbf->list))
1991 list_cut_position(&bf_head,
1992 &txq->axq_q, lastbf->list.prev);
1996 txq->axq_aggr_depth--;
1998 txok = (ds->ds_txstat.ts_status == 0);
1999 txq->axq_tx_inprogress = false;
2000 spin_unlock_bh(&txq->axq_lock);
2003 spin_lock_bh(&sc->tx.txbuflock);
2004 list_move_tail(&bf_held->list, &sc->tx.txbuf);
2005 spin_unlock_bh(&sc->tx.txbuflock);
2008 if (!bf_isampdu(bf)) {
2010 * This frame is sent out as a single frame.
2011 * Use hardware retry status for this frame.
2013 bf->bf_retries = ds->ds_txstat.ts_longretry;
2014 if (ds->ds_txstat.ts_status & ATH9K_TXERR_XRETRY)
2015 bf->bf_state.bf_type |= BUF_XRETRY;
2016 ath_tx_rc_status(bf, ds, 0, txok, true);
2020 ath_tx_complete_aggr(sc, txq, bf, &bf_head, txok);
2022 ath_tx_complete_buf(sc, bf, &bf_head, txok, 0);
2024 ath_wake_mac80211_queue(sc, txq);
2026 spin_lock_bh(&txq->axq_lock);
2027 if (sc->sc_flags & SC_OP_TXAGGR)
2028 ath_txq_schedule(sc, txq);
2029 spin_unlock_bh(&txq->axq_lock);
2033 static void ath_tx_complete_poll_work(struct work_struct *work)
2035 struct ath_softc *sc = container_of(work, struct ath_softc,
2036 tx_complete_work.work);
2037 struct ath_txq *txq;
2039 bool needreset = false;
2041 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
2042 if (ATH_TXQ_SETUP(sc, i)) {
2043 txq = &sc->tx.txq[i];
2044 spin_lock_bh(&txq->axq_lock);
2045 if (txq->axq_depth) {
2046 if (txq->axq_tx_inprogress) {
2048 spin_unlock_bh(&txq->axq_lock);
2051 txq->axq_tx_inprogress = true;
2054 spin_unlock_bh(&txq->axq_lock);
2058 DPRINTF(sc, ATH_DBG_RESET, "tx hung, resetting the chip\n");
2059 ath_reset(sc, false);
2062 queue_delayed_work(sc->hw->workqueue, &sc->tx_complete_work,
2063 msecs_to_jiffies(ATH_TX_COMPLETE_POLL_INT));
2068 void ath_tx_tasklet(struct ath_softc *sc)
2071 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1);
2073 ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
2075 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2076 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2077 ath_tx_processq(sc, &sc->tx.txq[i]);
2085 int ath_tx_init(struct ath_softc *sc, int nbufs)
2089 spin_lock_init(&sc->tx.txbuflock);
2091 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2094 DPRINTF(sc, ATH_DBG_FATAL,
2095 "Failed to allocate tx descriptors: %d\n", error);
2099 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2100 "beacon", ATH_BCBUF, 1);
2102 DPRINTF(sc, ATH_DBG_FATAL,
2103 "Failed to allocate beacon descriptors: %d\n", error);
2107 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2116 void ath_tx_cleanup(struct ath_softc *sc)
2118 if (sc->beacon.bdma.dd_desc_len != 0)
2119 ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf);
2121 if (sc->tx.txdma.dd_desc_len != 0)
2122 ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf);
2125 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2127 struct ath_atx_tid *tid;
2128 struct ath_atx_ac *ac;
2131 for (tidno = 0, tid = &an->tid[tidno];
2132 tidno < WME_NUM_TID;
2136 tid->seq_start = tid->seq_next = 0;
2137 tid->baw_size = WME_MAX_BA;
2138 tid->baw_head = tid->baw_tail = 0;
2140 tid->paused = false;
2141 tid->state &= ~AGGR_CLEANUP;
2142 INIT_LIST_HEAD(&tid->buf_q);
2143 acno = TID_TO_WME_AC(tidno);
2144 tid->ac = &an->ac[acno];
2145 tid->state &= ~AGGR_ADDBA_COMPLETE;
2146 tid->state &= ~AGGR_ADDBA_PROGRESS;
2149 for (acno = 0, ac = &an->ac[acno];
2150 acno < WME_NUM_AC; acno++, ac++) {
2152 INIT_LIST_HEAD(&ac->tid_q);
2156 ac->qnum = ath_tx_get_qnum(sc,
2157 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
2160 ac->qnum = ath_tx_get_qnum(sc,
2161 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BK);
2164 ac->qnum = ath_tx_get_qnum(sc,
2165 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VI);
2168 ac->qnum = ath_tx_get_qnum(sc,
2169 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VO);
2175 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2178 struct ath_atx_ac *ac, *ac_tmp;
2179 struct ath_atx_tid *tid, *tid_tmp;
2180 struct ath_txq *txq;
2182 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2183 if (ATH_TXQ_SETUP(sc, i)) {
2184 txq = &sc->tx.txq[i];
2186 spin_lock(&txq->axq_lock);
2188 list_for_each_entry_safe(ac,
2189 ac_tmp, &txq->axq_acq, list) {
2190 tid = list_first_entry(&ac->tid_q,
2191 struct ath_atx_tid, list);
2192 if (tid && tid->an != an)
2194 list_del(&ac->list);
2197 list_for_each_entry_safe(tid,
2198 tid_tmp, &ac->tid_q, list) {
2199 list_del(&tid->list);
2201 ath_tid_drain(sc, txq, tid);
2202 tid->state &= ~AGGR_ADDBA_COMPLETE;
2203 tid->state &= ~AGGR_CLEANUP;
2207 spin_unlock(&txq->axq_lock);