2 * Copyright (c) 2008 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/nl80211.h>
18 #include <linux/pci.h>
21 static struct pci_device_id ath_pci_id_table[] __devinitdata = {
22 { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
23 { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
24 { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
25 { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */
26 { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
27 { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
31 /* return bus cachesize in 4B word units */
32 static void ath_pci_read_cachesize(struct ath_softc *sc, int *csz)
36 pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE,
41 * This check was put in to avoid "unplesant" consequences if
42 * the bootrom has not fully initialized all PCI devices.
43 * Sometimes the cache line size register is not set
47 *csz = DEFAULT_CACHELINE >> 2; /* Use the default size */
50 static void ath_pci_cleanup(struct ath_softc *sc)
52 struct pci_dev *pdev = to_pci_dev(sc->dev);
54 pci_iounmap(pdev, sc->mem);
55 pci_release_region(pdev, 0);
56 pci_disable_device(pdev);
59 static bool ath_pci_eeprom_read(struct ath_hw *ah, u32 off, u16 *data)
61 (void)REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
63 if (!ath9k_hw_wait(ah,
64 AR_EEPROM_STATUS_DATA,
65 AR_EEPROM_STATUS_DATA_BUSY |
66 AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0)) {
70 *data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA),
71 AR_EEPROM_STATUS_DATA_VAL);
76 static struct ath_bus_ops ath_pci_bus_ops = {
77 .read_cachesize = ath_pci_read_cachesize,
78 .cleanup = ath_pci_cleanup,
79 .eeprom_read = ath_pci_eeprom_read,
82 static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
86 struct ieee80211_hw *hw;
92 if (pci_enable_device(pdev))
95 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
98 printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
102 ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
105 printk(KERN_ERR "ath9k: 32-bit DMA consistent "
106 "DMA enable failed\n");
111 * Cache line size is used to size and align various
112 * structures used to communicate with the hardware.
114 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
117 * Linux 2.4.18 (at least) writes the cache line size
118 * register as a 16-bit wide register which is wrong.
119 * We must have this setup properly for rx buffer
120 * DMA to work so force a reasonable value here if it
123 csz = L1_CACHE_BYTES / sizeof(u32);
124 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
127 * The default setting of latency timer yields poor results,
128 * set it to the value used by other systems. It may be worth
129 * tweaking this setting more.
131 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
133 pci_set_master(pdev);
136 * Disable the RETRY_TIMEOUT register (0x41) to keep
137 * PCI Tx retries from interfering with C3 CPU state.
139 pci_read_config_dword(pdev, 0x40, &val);
140 if ((val & 0x0000ff00) != 0)
141 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
143 ret = pci_request_region(pdev, 0, "ath9k");
145 dev_err(&pdev->dev, "PCI memory region reserve error\n");
150 mem = pci_iomap(pdev, 0, 0);
152 printk(KERN_ERR "PCI memory map error\n") ;
157 hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
159 printk(KERN_ERR "ath_pci: no memory for ieee80211_hw\n");
163 SET_IEEE80211_DEV(hw, &pdev->dev);
164 pci_set_drvdata(pdev, hw);
168 sc->dev = &pdev->dev;
170 sc->bus_ops = &ath_pci_bus_ops;
172 if (ath_attach(id->device, sc) != 0) {
177 /* setup interrupt service routine */
179 if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) {
180 printk(KERN_ERR "%s: request_irq failed\n",
181 wiphy_name(hw->wiphy));
190 "%s: Atheros AR%s MAC/BB Rev:%x "
191 "AR%s RF Rev:%x: mem=0x%lx, irq=%d\n",
192 wiphy_name(hw->wiphy),
193 ath_mac_bb_name(ah->hw_version.macVersion),
194 ah->hw_version.macRev,
195 ath_rf_name((ah->hw_version.analog5GhzRev & AR_RADIO_SREV_MAJOR)),
196 ah->hw_version.phyRev,
197 (unsigned long)mem, pdev->irq);
203 ieee80211_free_hw(hw);
205 pci_iounmap(pdev, mem);
207 pci_release_region(pdev, 0);
209 pci_disable_device(pdev);
213 static void ath_pci_remove(struct pci_dev *pdev)
215 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
216 struct ath_softc *sc = hw->priv;
223 static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
225 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
226 struct ath_softc *sc = hw->priv;
228 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
230 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
231 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
232 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
235 pci_save_state(pdev);
236 pci_disable_device(pdev);
237 pci_set_power_state(pdev, PCI_D3hot);
242 static int ath_pci_resume(struct pci_dev *pdev)
244 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
245 struct ath_softc *sc = hw->priv;
249 err = pci_enable_device(pdev);
252 pci_restore_state(pdev);
254 * Suspend/Resume resets the PCI configuration space, so we have to
255 * re-disable the RETRY_TIMEOUT register (0x41) to keep
256 * PCI Tx retries from interfering with C3 CPU state
258 pci_read_config_dword(pdev, 0x40, &val);
259 if ((val & 0x0000ff00) != 0)
260 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
263 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
264 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
265 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
267 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
269 * check the h/w rfkill state on resume
270 * and start the rfkill poll timer
272 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
273 queue_delayed_work(sc->hw->workqueue,
274 &sc->rf_kill.rfkill_poll, 0);
280 #endif /* CONFIG_PM */
282 MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
284 static struct pci_driver ath_pci_driver = {
286 .id_table = ath_pci_id_table,
287 .probe = ath_pci_probe,
288 .remove = ath_pci_remove,
290 .suspend = ath_pci_suspend,
291 .resume = ath_pci_resume,
292 #endif /* CONFIG_PM */
295 int __init ath_pci_init(void)
297 return pci_register_driver(&ath_pci_driver);
300 void ath_pci_exit(void)
302 pci_unregister_driver(&ath_pci_driver);