2 * Copyright (c) 2008 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 ath9k_hw_write_regs(struct ath_hal *ah, u32 modesIndex, u32 freqIndex,
23 struct ath_hal_5416 *ahp = AH5416(ah);
25 REG_WRITE_ARRAY(&ahp->ah_iniBB_RfGain, freqIndex, regWrites);
29 ath9k_hw_set_channel(struct ath_hal *ah, struct ath9k_channel *chan)
36 struct chan_centers centers;
38 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
39 freq = centers.synth_center;
44 if (((freq - 2192) % 5) == 0) {
45 channelSel = ((freq - 672) * 2 - 3040) / 10;
47 } else if (((freq - 2224) % 5) == 0) {
48 channelSel = ((freq - 704) * 2 - 3040) / 10;
51 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
52 "Invalid channel %u MHz\n", freq);
56 channelSel = (channelSel << 2) & 0xff;
57 channelSel = ath9k_hw_reverse_bits(channelSel, 8);
59 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
62 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
63 txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
65 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
66 txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
69 } else if ((freq % 20) == 0 && freq >= 5120) {
71 ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8);
72 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
73 } else if ((freq % 10) == 0) {
75 ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8);
76 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
77 aModeRefSel = ath9k_hw_reverse_bits(2, 2);
79 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
80 } else if ((freq % 5) == 0) {
81 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
82 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
84 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
85 "Invalid channel %u MHz\n", freq);
90 (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) |
93 REG_WRITE(ah, AR_PHY(0x37), reg32);
95 ah->ah_curchan = chan;
97 AH5416(ah)->ah_curchanRadIndex = -1;
103 ath9k_hw_ar9280_set_channel(struct ath_hal *ah,
104 struct ath9k_channel *chan)
106 u16 bMode, fracMode, aModeRefSel = 0;
107 u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0;
108 struct chan_centers centers;
111 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
112 freq = centers.synth_center;
114 reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL);
123 channelSel = (freq * 0x10000) / 15;
125 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
128 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
129 txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
131 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
132 txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
138 if ((freq % 20) == 0) {
140 } else if ((freq % 10) == 0) {
147 channelSel = (freq * 0x8000) / 15;
149 REG_RMW_FIELD(ah, AR_AN_SYNTH9,
150 AR_AN_SYNTH9_REFDIVA, refDivA);
153 ndiv = (freq * (refDivA >> aModeRefSel)) / 60;
154 channelSel = ndiv & 0x1ff;
155 channelFrac = (ndiv & 0xfffffe00) * 2;
156 channelSel = (channelSel << 17) | channelFrac;
162 (fracMode << 28) | (aModeRefSel << 26) | (channelSel);
164 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
166 ah->ah_curchan = chan;
168 AH5416(ah)->ah_curchanRadIndex = -1;
174 ath9k_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32,
175 u32 numBits, u32 firstBit,
178 u32 tmp32, mask, arrayEntry, lastBit;
179 int32_t bitPosition, bitsLeft;
181 tmp32 = ath9k_hw_reverse_bits(reg32, numBits);
182 arrayEntry = (firstBit - 1) / 8;
183 bitPosition = (firstBit - 1) % 8;
185 while (bitsLeft > 0) {
186 lastBit = (bitPosition + bitsLeft > 8) ?
187 8 : bitPosition + bitsLeft;
188 mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) <<
190 rfBuf[arrayEntry] &= ~mask;
191 rfBuf[arrayEntry] |= ((tmp32 << bitPosition) <<
192 (column * 8)) & mask;
193 bitsLeft -= 8 - bitPosition;
194 tmp32 = tmp32 >> (8 - bitPosition);
201 ath9k_hw_set_rf_regs(struct ath_hal *ah, struct ath9k_channel *chan,
204 struct ath_hal_5416 *ahp = AH5416(ah);
207 u32 ob5GHz = 0, db5GHz = 0;
208 u32 ob2GHz = 0, db2GHz = 0;
211 if (AR_SREV_9280_10_OR_LATER(ah))
214 eepMinorRev = ath9k_hw_get_eeprom(ah, EEP_MINOR_REV);
216 RF_BANK_SETUP(ahp->ah_analogBank0Data, &ahp->ah_iniBank0, 1);
218 RF_BANK_SETUP(ahp->ah_analogBank1Data, &ahp->ah_iniBank1, 1);
220 RF_BANK_SETUP(ahp->ah_analogBank2Data, &ahp->ah_iniBank2, 1);
222 RF_BANK_SETUP(ahp->ah_analogBank3Data, &ahp->ah_iniBank3,
226 for (i = 0; i < ahp->ah_iniBank6TPC.ia_rows; i++) {
227 ahp->ah_analogBank6Data[i] =
228 INI_RA(&ahp->ah_iniBank6TPC, i, modesIndex);
232 if (eepMinorRev >= 2) {
233 if (IS_CHAN_2GHZ(chan)) {
234 ob2GHz = ath9k_hw_get_eeprom(ah, EEP_OB_2);
235 db2GHz = ath9k_hw_get_eeprom(ah, EEP_DB_2);
236 ath9k_phy_modify_rx_buffer(ahp->ah_analogBank6Data,
238 ath9k_phy_modify_rx_buffer(ahp->ah_analogBank6Data,
241 ob5GHz = ath9k_hw_get_eeprom(ah, EEP_OB_5);
242 db5GHz = ath9k_hw_get_eeprom(ah, EEP_DB_5);
243 ath9k_phy_modify_rx_buffer(ahp->ah_analogBank6Data,
245 ath9k_phy_modify_rx_buffer(ahp->ah_analogBank6Data,
250 RF_BANK_SETUP(ahp->ah_analogBank7Data, &ahp->ah_iniBank7, 1);
252 REG_WRITE_RF_ARRAY(&ahp->ah_iniBank0, ahp->ah_analogBank0Data,
254 REG_WRITE_RF_ARRAY(&ahp->ah_iniBank1, ahp->ah_analogBank1Data,
256 REG_WRITE_RF_ARRAY(&ahp->ah_iniBank2, ahp->ah_analogBank2Data,
258 REG_WRITE_RF_ARRAY(&ahp->ah_iniBank3, ahp->ah_analogBank3Data,
260 REG_WRITE_RF_ARRAY(&ahp->ah_iniBank6TPC, ahp->ah_analogBank6Data,
262 REG_WRITE_RF_ARRAY(&ahp->ah_iniBank7, ahp->ah_analogBank7Data,
269 ath9k_hw_rfdetach(struct ath_hal *ah)
271 struct ath_hal_5416 *ahp = AH5416(ah);
273 if (ahp->ah_analogBank0Data != NULL) {
274 kfree(ahp->ah_analogBank0Data);
275 ahp->ah_analogBank0Data = NULL;
277 if (ahp->ah_analogBank1Data != NULL) {
278 kfree(ahp->ah_analogBank1Data);
279 ahp->ah_analogBank1Data = NULL;
281 if (ahp->ah_analogBank2Data != NULL) {
282 kfree(ahp->ah_analogBank2Data);
283 ahp->ah_analogBank2Data = NULL;
285 if (ahp->ah_analogBank3Data != NULL) {
286 kfree(ahp->ah_analogBank3Data);
287 ahp->ah_analogBank3Data = NULL;
289 if (ahp->ah_analogBank6Data != NULL) {
290 kfree(ahp->ah_analogBank6Data);
291 ahp->ah_analogBank6Data = NULL;
293 if (ahp->ah_analogBank6TPCData != NULL) {
294 kfree(ahp->ah_analogBank6TPCData);
295 ahp->ah_analogBank6TPCData = NULL;
297 if (ahp->ah_analogBank7Data != NULL) {
298 kfree(ahp->ah_analogBank7Data);
299 ahp->ah_analogBank7Data = NULL;
301 if (ahp->ah_addac5416_21 != NULL) {
302 kfree(ahp->ah_addac5416_21);
303 ahp->ah_addac5416_21 = NULL;
305 if (ahp->ah_bank6Temp != NULL) {
306 kfree(ahp->ah_bank6Temp);
307 ahp->ah_bank6Temp = NULL;
311 bool ath9k_hw_init_rf(struct ath_hal *ah, int *status)
313 struct ath_hal_5416 *ahp = AH5416(ah);
315 if (!AR_SREV_9280_10_OR_LATER(ah)) {
317 ahp->ah_analogBank0Data =
318 kzalloc((sizeof(u32) *
319 ahp->ah_iniBank0.ia_rows), GFP_KERNEL);
320 ahp->ah_analogBank1Data =
321 kzalloc((sizeof(u32) *
322 ahp->ah_iniBank1.ia_rows), GFP_KERNEL);
323 ahp->ah_analogBank2Data =
324 kzalloc((sizeof(u32) *
325 ahp->ah_iniBank2.ia_rows), GFP_KERNEL);
326 ahp->ah_analogBank3Data =
327 kzalloc((sizeof(u32) *
328 ahp->ah_iniBank3.ia_rows), GFP_KERNEL);
329 ahp->ah_analogBank6Data =
330 kzalloc((sizeof(u32) *
331 ahp->ah_iniBank6.ia_rows), GFP_KERNEL);
332 ahp->ah_analogBank6TPCData =
333 kzalloc((sizeof(u32) *
334 ahp->ah_iniBank6TPC.ia_rows), GFP_KERNEL);
335 ahp->ah_analogBank7Data =
336 kzalloc((sizeof(u32) *
337 ahp->ah_iniBank7.ia_rows), GFP_KERNEL);
339 if (ahp->ah_analogBank0Data == NULL
340 || ahp->ah_analogBank1Data == NULL
341 || ahp->ah_analogBank2Data == NULL
342 || ahp->ah_analogBank3Data == NULL
343 || ahp->ah_analogBank6Data == NULL
344 || ahp->ah_analogBank6TPCData == NULL
345 || ahp->ah_analogBank7Data == NULL) {
346 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
347 "Cannot allocate RF banks\n");
352 ahp->ah_addac5416_21 =
353 kzalloc((sizeof(u32) *
354 ahp->ah_iniAddac.ia_rows *
355 ahp->ah_iniAddac.ia_columns), GFP_KERNEL);
356 if (ahp->ah_addac5416_21 == NULL) {
357 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
358 "Cannot allocate ah_addac5416_21\n");
364 kzalloc((sizeof(u32) *
365 ahp->ah_iniBank6.ia_rows), GFP_KERNEL);
366 if (ahp->ah_bank6Temp == NULL) {
367 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
368 "Cannot allocate ah_bank6Temp\n");
378 ath9k_hw_decrease_chain_power(struct ath_hal *ah, struct ath9k_channel *chan)
380 int i, regWrites = 0;
381 struct ath_hal_5416 *ahp = AH5416(ah);
383 u32 *bank6Temp = ahp->ah_bank6Temp;
385 switch (ahp->ah_diversityControl) {
386 case ATH9K_ANT_FIXED_A:
389 ah_antennaSwitchSwap & ANTSWAP_AB) ? REDUCE_CHAIN_0 :
392 case ATH9K_ANT_FIXED_B:
395 ah_antennaSwitchSwap & ANTSWAP_AB) ? REDUCE_CHAIN_1 :
398 case ATH9K_ANT_VARIABLE:
406 for (i = 0; i < ahp->ah_iniBank6.ia_rows; i++)
407 bank6Temp[i] = ahp->ah_analogBank6Data[i];
409 REG_WRITE(ah, AR_PHY_BASE + 0xD8, bank6SelMask);
411 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 189, 0);
412 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 190, 0);
413 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 191, 0);
414 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 192, 0);
415 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 193, 0);
416 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 222, 0);
417 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 245, 0);
418 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 246, 0);
419 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 247, 0);
421 REG_WRITE_RF_ARRAY(&ahp->ah_iniBank6, bank6Temp, regWrites);
423 REG_WRITE(ah, AR_PHY_BASE + 0xD8, 0x00000053);
425 REG_WRITE(ah, PHY_SWITCH_CHAIN_0,
426 (REG_READ(ah, PHY_SWITCH_CHAIN_0) & ~0x38)
427 | ((REG_READ(ah, PHY_SWITCH_CHAIN_0) >> 3) & 0x38));