drivers/net/wireless/b43/phy_n.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4   IEEE 802.11n PHY support
   5
   6   Copyright (c) 2008 Michael Buesch <mb@bu3sch.de>
   7
   8   This program is free software; you can redistribute it and/or modify
   9   it under the terms of the GNU General Public License as published by
  10   the Free Software Foundation; either version 2 of the License, or
  11   (at your option) any later version.
  12
  13   This program is distributed in the hope that it will be useful,
  14   but WITHOUT ANY WARRANTY; without even the implied warranty of
  15   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16   GNU General Public License for more details.
  17
  18   You should have received a copy of the GNU General Public License
  19   along with this program; see the file COPYING.  If not, write to
  20   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  21   Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #include <linux/delay.h>
  26 #include <linux/types.h>
  27
  28 #include "b43.h"
  29 #include "phy_n.h"
  30 #include "tables_nphy.h"
  31 #include "main.h"
  32
  33 struct nphy_txgains {
  34         u16 txgm[2];
  35         u16 pga[2];
  36         u16 pad[2];
  37         u16 ipa[2];
  38 };
  39
  40 struct nphy_iqcal_params {
  41         u16 txgm;
  42         u16 pga;
  43         u16 pad;
  44         u16 ipa;
  45         u16 cal_gain;
  46         u16 ncorr[5];
  47 };
  48
  49 struct nphy_iq_est {
  50         s32 iq0_prod;
  51         u32 i0_pwr;
  52         u32 q0_pwr;
  53         s32 iq1_prod;
  54         u32 i1_pwr;
  55         u32 q1_pwr;
  56 };
  57
  58 enum b43_nphy_rf_sequence {
  59         B43_RFSEQ_RX2TX,
  60         B43_RFSEQ_TX2RX,
  61         B43_RFSEQ_RESET2RX,
  62         B43_RFSEQ_UPDATE_GAINH,
  63         B43_RFSEQ_UPDATE_GAINL,
  64         B43_RFSEQ_UPDATE_GAINU,
  65 };
  66
  67 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
  68                                         u8 *events, u8 *delays, u8 length);
  69 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
  70                                        enum b43_nphy_rf_sequence seq);
  71 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
  72                                                 u16 value, u8 core, bool off);
  73 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
  74                                                 u16 value, u8 core);
  75
  76 void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
  77 {//TODO
  78 }
  79
  80 static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
  81 {//TODO
  82 }
  83
  84 static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
  85                                                         bool ignore_tssi)
  86 {//TODO
  87         return B43_TXPWR_RES_DONE;
  88 }
  89
  90 static void b43_chantab_radio_upload(struct b43_wldev *dev,
  91                                      const struct b43_nphy_channeltab_entry *e)
  92 {
  93         b43_radio_write16(dev, B2055_PLL_REF, e->radio_pll_ref);
  94         b43_radio_write16(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
  95         b43_radio_write16(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
  96         b43_radio_write16(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
  97         b43_radio_write16(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
  98         b43_radio_write16(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
  99         b43_radio_write16(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
 100         b43_radio_write16(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
 101         b43_radio_write16(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
 102         b43_radio_write16(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
 103         b43_radio_write16(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
 104         b43_radio_write16(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
 105         b43_radio_write16(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
 106         b43_radio_write16(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
 107         b43_radio_write16(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
 108         b43_radio_write16(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
 109         b43_radio_write16(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
 110         b43_radio_write16(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
 111         b43_radio_write16(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
 112         b43_radio_write16(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
 113         b43_radio_write16(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
 114         b43_radio_write16(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
 115 }
 116
 117 static void b43_chantab_phy_upload(struct b43_wldev *dev,
 118                                    const struct b43_nphy_channeltab_entry *e)
 119 {
 120         b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
 121         b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
 122         b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
 123         b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
 124         b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
 125         b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
 126 }
 127
 128 static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
 129 {
 130         //TODO
 131 }
 132
 133 /* Tune the hardware to a new channel. */
 134 static int nphy_channel_switch(struct b43_wldev *dev, unsigned int channel)
 135 {
 136         const struct b43_nphy_channeltab_entry *tabent;
 137
 138         tabent = b43_nphy_get_chantabent(dev, channel);
 139         if (!tabent)
 140                 return -ESRCH;
 141
 142         //FIXME enable/disable band select upper20 in RXCTL
 143         if (0 /*FIXME 5Ghz*/)
 144                 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x20);
 145         else
 146                 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x50);
 147         b43_chantab_radio_upload(dev, tabent);
 148         udelay(50);
 149         b43_radio_write16(dev, B2055_VCO_CAL10, 5);
 150         b43_radio_write16(dev, B2055_VCO_CAL10, 45);
 151         b43_radio_write16(dev, B2055_VCO_CAL10, 65);
 152         udelay(300);
 153         if (0 /*FIXME 5Ghz*/)
 154                 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
 155         else
 156                 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
 157         b43_chantab_phy_upload(dev, tabent);
 158         b43_nphy_tx_power_fix(dev);
 159
 160         return 0;
 161 }
 162
 163 static void b43_radio_init2055_pre(struct b43_wldev *dev)
 164 {
 165         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 166                      ~B43_NPHY_RFCTL_CMD_PORFORCE);
 167         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 168                     B43_NPHY_RFCTL_CMD_CHIP0PU |
 169                     B43_NPHY_RFCTL_CMD_OEPORFORCE);
 170         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 171                     B43_NPHY_RFCTL_CMD_PORFORCE);
 172 }
 173
 174 static void b43_radio_init2055_post(struct b43_wldev *dev)
 175 {
 176         struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
 177         struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo);
 178         int i;
 179         u16 val;
 180
 181         b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
 182         msleep(1);
 183         if ((sprom->revision != 4) ||
 184            !(sprom->boardflags_hi & B43_BFH_RSSIINV)) {
 185                 if ((binfo->vendor != PCI_VENDOR_ID_BROADCOM) ||
 186                     (binfo->type != 0x46D) ||
 187                     (binfo->rev < 0x41)) {
 188                         b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
 189                         b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
 190                         msleep(1);
 191                 }
 192         }
 193         b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0x3F, 0x2C);
 194         msleep(1);
 195         b43_radio_write16(dev, B2055_CAL_MISC, 0x3C);
 196         msleep(1);
 197         b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
 198         msleep(1);
 199         b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
 200         msleep(1);
 201         b43_radio_set(dev, B2055_CAL_MISC, 0x1);
 202         msleep(1);
 203         b43_radio_set(dev, B2055_CAL_MISC, 0x40);
 204         msleep(1);
 205         for (i = 0; i < 100; i++) {
 206                 val = b43_radio_read16(dev, B2055_CAL_COUT2);
 207                 if (val & 0x80)
 208                         break;
 209                 udelay(10);
 210         }
 211         msleep(1);
 212         b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
 213         msleep(1);
 214         nphy_channel_switch(dev, dev->phy.channel);
 215         b43_radio_write16(dev, B2055_C1_RX_BB_LPF, 0x9);
 216         b43_radio_write16(dev, B2055_C2_RX_BB_LPF, 0x9);
 217         b43_radio_write16(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
 218         b43_radio_write16(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
 219 }
 220
 221 /* Initialize a Broadcom 2055 N-radio */
 222 static void b43_radio_init2055(struct b43_wldev *dev)
 223 {
 224         b43_radio_init2055_pre(dev);
 225         if (b43_status(dev) < B43_STAT_INITIALIZED)
 226                 b2055_upload_inittab(dev, 0, 1);
 227         else
 228                 b2055_upload_inittab(dev, 0/*FIXME on 5ghz band*/, 0);
 229         b43_radio_init2055_post(dev);
 230 }
 231
 232 void b43_nphy_radio_turn_on(struct b43_wldev *dev)
 233 {
 234         b43_radio_init2055(dev);
 235 }
 236
 237 void b43_nphy_radio_turn_off(struct b43_wldev *dev)
 238 {
 239         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 240                      ~B43_NPHY_RFCTL_CMD_EN);
 241 }
 242
 243 /*
 244  * Upload the N-PHY tables.
 245  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
 246  */
 247 static void b43_nphy_tables_init(struct b43_wldev *dev)
 248 {
 249         if (dev->phy.rev < 3)
 250                 b43_nphy_rev0_1_2_tables_init(dev);
 251         else
 252                 b43_nphy_rev3plus_tables_init(dev);
 253 }
 254
 255 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
 256 static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
 257 {
 258         struct b43_phy_n *nphy = dev->phy.n;
 259         enum ieee80211_band band;
 260         u16 tmp;
 261
 262         if (!enable) {
 263                 nphy->rfctrl_intc1_save = b43_phy_read(dev,
 264                                                        B43_NPHY_RFCTL_INTC1);
 265                 nphy->rfctrl_intc2_save = b43_phy_read(dev,
 266                                                        B43_NPHY_RFCTL_INTC2);
 267                 band = b43_current_band(dev->wl);
 268                 if (dev->phy.rev >= 3) {
 269                         if (band == IEEE80211_BAND_5GHZ)
 270                                 tmp = 0x600;
 271                         else
 272                                 tmp = 0x480;
 273                 } else {
 274                         if (band == IEEE80211_BAND_5GHZ)
 275                                 tmp = 0x180;
 276                         else
 277                                 tmp = 0x120;
 278                 }
 279                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
 280                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
 281         } else {
 282                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
 283                                 nphy->rfctrl_intc1_save);
 284                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
 285                                 nphy->rfctrl_intc2_save);
 286         }
 287 }
 288
 289 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
 290 static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
 291 {
 292         struct b43_phy_n *nphy = dev->phy.n;
 293         u16 tmp;
 294         enum ieee80211_band band = b43_current_band(dev->wl);
 295         bool ipa = (nphy->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
 296                         (nphy->ipa5g_on && band == IEEE80211_BAND_5GHZ);
 297
 298         if (dev->phy.rev >= 3) {
 299                 if (ipa) {
 300                         tmp = 4;
 301                         b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
 302                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
 303                 }
 304
 305                 tmp = 1;
 306                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
 307                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
 308         }
 309 }
 310
 311 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
 312 static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force)
 313 {
 314         u32 tmslow;
 315
 316         if (dev->phy.type != B43_PHYTYPE_N)
 317                 return;
 318
 319         tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
 320         if (force)
 321                 tmslow |= SSB_TMSLOW_FGC;
 322         else
 323                 tmslow &= ~SSB_TMSLOW_FGC;
 324         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
 325 }
 326
 327 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
 328 static void b43_nphy_reset_cca(struct b43_wldev *dev)
 329 {
 330         u16 bbcfg;
 331
 332         b43_nphy_bmac_clock_fgc(dev, 1);
 333         bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
 334         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
 335         udelay(1);
 336         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
 337         b43_nphy_bmac_clock_fgc(dev, 0);
 338         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
 339 }
 340
 341 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
 342 static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
 343 {
 344         u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
 345
 346         mimocfg |= B43_NPHY_MIMOCFG_AUTO;
 347         if (preamble == 1)
 348                 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
 349         else
 350                 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
 351
 352         b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
 353 }
 354
 355 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
 356 static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
 357 {
 358         struct b43_phy_n *nphy = dev->phy.n;
 359
 360         bool override = false;
 361         u16 chain = 0x33;
 362
 363         if (nphy->txrx_chain == 0) {
 364                 chain = 0x11;
 365                 override = true;
 366         } else if (nphy->txrx_chain == 1) {
 367                 chain = 0x22;
 368                 override = true;
 369         }
 370
 371         b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
 372                         ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
 373                         chain);
 374
 375         if (override)
 376                 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
 377                                 B43_NPHY_RFSEQMODE_CAOVER);
 378         else
 379                 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
 380                                 ~B43_NPHY_RFSEQMODE_CAOVER);
 381 }
 382
 383 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
 384 static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
 385                                 u16 samps, u8 time, bool wait)
 386 {
 387         int i;
 388         u16 tmp;
 389
 390         b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
 391         b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
 392         if (wait)
 393                 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
 394         else
 395                 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
 396
 397         b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
 398
 399         for (i = 1000; i; i--) {
 400                 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
 401                 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
 402                         est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
 403                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
 404                         est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
 405                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
 406                         est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
 407                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
 408
 409                         est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
 410                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
 411                         est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
 412                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
 413                         est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
 414                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
 415                         return;
 416                 }
 417                 udelay(10);
 418         }
 419         memset(est, 0, sizeof(*est));
 420 }
 421
 422 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
 423 static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
 424                                         struct b43_phy_n_iq_comp *pcomp)
 425 {
 426         if (write) {
 427                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
 428                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
 429                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
 430                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
 431         } else {
 432                 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
 433                 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
 434                 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
 435                 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
 436         }
 437 }
 438
 439 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
 440 static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
 441 {
 442         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
 443
 444         b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
 445         if (core == 0) {
 446                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
 447                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
 448         } else {
 449                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
 450                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
 451         }
 452         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
 453         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
 454         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
 455         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
 456         b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
 457         b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
 458         b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
 459         b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
 460 }
 461
 462 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
 463 static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
 464 {
 465         u8 rxval, txval;
 466         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
 467
 468         regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
 469         if (core == 0) {
 470                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
 471                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
 472         } else {
 473                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
 474                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
 475         }
 476         regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
 477         regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
 478         regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
 479         regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
 480         regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
 481         regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
 482         regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
 483         regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
 484
 485         b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
 486         b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
 487
 488         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, (u16)~B43_NPHY_RFSEQCA_RXDIS,
 489                         ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
 490         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
 491                         ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
 492         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
 493                         (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
 494         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
 495                         (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
 496
 497         if (core == 0) {
 498                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
 499                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
 500         } else {
 501                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
 502                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
 503         }
 504
 505         b43_nphy_rf_control_intc_override(dev, 2, 0, 3);
 506         b43_nphy_rf_control_override(dev, 8, 0, 3, false);
 507         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
 508
 509         if (core == 0) {
 510                 rxval = 1;
 511                 txval = 8;
 512         } else {
 513                 rxval = 4;
 514                 txval = 2;
 515         }
 516         b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
 517         b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
 518 }
 519
 520 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
 521 static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
 522 {
 523         int i;
 524         s32 iq;
 525         u32 ii;
 526         u32 qq;
 527         int iq_nbits, qq_nbits;
 528         int arsh, brsh;
 529         u16 tmp, a, b;
 530
 531         struct nphy_iq_est est;
 532         struct b43_phy_n_iq_comp old;
 533         struct b43_phy_n_iq_comp new = { };
 534         bool error = false;
 535
 536         if (mask == 0)
 537                 return;
 538
 539         b43_nphy_rx_iq_coeffs(dev, false, &old);
 540         b43_nphy_rx_iq_coeffs(dev, true, &new);
 541         b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
 542         new = old;
 543
 544         for (i = 0; i < 2; i++) {
 545                 if (i == 0 && (mask & 1)) {
 546                         iq = est.iq0_prod;
 547                         ii = est.i0_pwr;
 548                         qq = est.q0_pwr;
 549                 } else if (i == 1 && (mask & 2)) {
 550                         iq = est.iq1_prod;
 551                         ii = est.i1_pwr;
 552                         qq = est.q1_pwr;
 553                 } else {
 554                         B43_WARN_ON(1);
 555                         continue;
 556                 }
 557
 558                 if (ii + qq < 2) {
 559                         error = true;
 560                         break;
 561                 }
 562
 563                 iq_nbits = fls(abs(iq));
 564                 qq_nbits = fls(qq);
 565
 566                 arsh = iq_nbits - 20;
 567                 if (arsh >= 0) {
 568                         a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
 569                         tmp = ii >> arsh;
 570                 } else {
 571                         a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
 572                         tmp = ii << -arsh;
 573                 }
 574                 if (tmp == 0) {
 575                         error = true;
 576                         break;
 577                 }
 578                 a /= tmp;
 579
 580                 brsh = qq_nbits - 11;
 581                 if (brsh >= 0) {
 582                         b = (qq << (31 - qq_nbits));
 583                         tmp = ii >> brsh;
 584                 } else {
 585                         b = (qq << (31 - qq_nbits));
 586                         tmp = ii << -brsh;
 587                 }
 588                 if (tmp == 0) {
 589                         error = true;
 590                         break;
 591                 }
 592                 b = int_sqrt(b / tmp - a * a) - (1 << 10);
 593
 594                 if (i == 0 && (mask & 0x1)) {
 595                         if (dev->phy.rev >= 3) {
 596                                 new.a0 = a & 0x3FF;
 597                                 new.b0 = b & 0x3FF;
 598                         } else {
 599                                 new.a0 = b & 0x3FF;
 600                                 new.b0 = a & 0x3FF;
 601                         }
 602                 } else if (i == 1 && (mask & 0x2)) {
 603                         if (dev->phy.rev >= 3) {
 604                                 new.a1 = a & 0x3FF;
 605                                 new.b1 = b & 0x3FF;
 606                         } else {
 607                                 new.a1 = b & 0x3FF;
 608                                 new.b1 = a & 0x3FF;
 609                         }
 610                 }
 611         }
 612
 613         if (error)
 614                 new = old;
 615
 616         b43_nphy_rx_iq_coeffs(dev, true, &new);
 617 }
 618
 619 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
 620 static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
 621 {
 622         u16 array[4];
 623         int i;
 624
 625         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C50);
 626         for (i = 0; i < 4; i++)
 627                 array[i] = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
 628
 629         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
 630         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
 631         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
 632         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
 633 }
 634
 635 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 636 static void b43_nphy_write_clip_detection(struct b43_wldev *dev, u16 *clip_st)
 637 {
 638         b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
 639         b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
 640 }
 641
 642 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 643 static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
 644 {
 645         clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
 646         clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
 647 }
 648
 649 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
 650 static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
 651 {
 652         if (dev->phy.rev >= 3) {
 653                 if (!init)
 654                         return;
 655                 if (0 /* FIXME */) {
 656                         b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
 657                         b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
 658                         b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
 659                         b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
 660                 }
 661         } else {
 662                 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
 663                 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
 664
 665                 ssb_chipco_gpio_control(&dev->dev->bus->chipco, 0xFC00,
 666                                         0xFC00);
 667                 b43_write32(dev, B43_MMIO_MACCTL,
 668                         b43_read32(dev, B43_MMIO_MACCTL) &
 669                         ~B43_MACCTL_GPOUTSMSK);
 670                 b43_write16(dev, B43_MMIO_GPIO_MASK,
 671                         b43_read16(dev, B43_MMIO_GPIO_MASK) | 0xFC00);
 672                 b43_write16(dev, B43_MMIO_GPIO_CONTROL,
 673                         b43_read16(dev, B43_MMIO_GPIO_CONTROL) & ~0xFC00);
 674
 675                 if (init) {
 676                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
 677                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
 678                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
 679                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
 680                 }
 681         }
 682 }
 683
 684 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
 685 static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
 686 {
 687         u16 tmp;
 688
 689         if (dev->dev->id.revision == 16)
 690                 b43_mac_suspend(dev);
 691
 692         tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
 693         tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
 694                 B43_NPHY_CLASSCTL_WAITEDEN);
 695         tmp &= ~mask;
 696         tmp |= (val & mask);
 697         b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
 698
 699         if (dev->dev->id.revision == 16)
 700                 b43_mac_enable(dev);
 701
 702         return tmp;
 703 }
 704
 705 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
 706 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
 707 {
 708         struct b43_phy *phy = &dev->phy;
 709         struct b43_phy_n *nphy = phy->n;
 710
 711         if (enable) {
 712                 u16 clip[] = { 0xFFFF, 0xFFFF };
 713                 if (nphy->deaf_count++ == 0) {
 714                         nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
 715                         b43_nphy_classifier(dev, 0x7, 0);
 716                         b43_nphy_read_clip_detection(dev, nphy->clip_state);
 717                         b43_nphy_write_clip_detection(dev, clip);
 718                 }
 719                 b43_nphy_reset_cca(dev);
 720         } else {
 721                 if (--nphy->deaf_count == 0) {
 722                         b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
 723                         b43_nphy_write_clip_detection(dev, nphy->clip_state);
 724                 }
 725         }
 726 }
 727
 728 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
 729 static void b43_nphy_stop_playback(struct b43_wldev *dev)
 730 {
 731         struct b43_phy_n *nphy = dev->phy.n;
 732         u16 tmp;
 733
 734         if (nphy->hang_avoid)
 735                 b43_nphy_stay_in_carrier_search(dev, 1);
 736
 737         tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
 738         if (tmp & 0x1)
 739                 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
 740         else if (tmp & 0x2)
 741                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, (u16)~0x8000);
 742
 743         b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
 744
 745         if (nphy->bb_mult_save & 0x80000000) {
 746                 tmp = nphy->bb_mult_save & 0xFFFF;
 747                 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
 748                 nphy->bb_mult_save = 0;
 749         }
 750
 751         if (nphy->hang_avoid)
 752                 b43_nphy_stay_in_carrier_search(dev, 0);
 753 }
 754
 755 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
 756 static void b43_nphy_spur_workaround(struct b43_wldev *dev)
 757 {
 758         struct b43_phy_n *nphy = dev->phy.n;
 759
 760         unsigned int channel;
 761         int tone[2] = { 57, 58 };
 762         u32 noise[2] = { 0x3FF, 0x3FF };
 763
 764         B43_WARN_ON(dev->phy.rev < 3);
 765
 766         if (nphy->hang_avoid)
 767                 b43_nphy_stay_in_carrier_search(dev, 1);
 768
 769         /* FIXME: channel = radio_chanspec */
 770
 771         if (nphy->gband_spurwar_en) {
 772                 /* TODO: N PHY Adjust Analog Pfbw (7) */
 773                 if (channel == 11 && dev->phy.is_40mhz)
 774                         ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
 775                 else
 776                         ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
 777                 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
 778         }
 779
 780         if (nphy->aband_spurwar_en) {
 781                 if (channel == 54) {
 782                         tone[0] = 0x20;
 783                         noise[0] = 0x25F;
 784                 } else if (channel == 38 || channel == 102 || channel == 118) {
 785                         if (0 /* FIXME */) {
 786                                 tone[0] = 0x20;
 787                                 noise[0] = 0x21F;
 788                         } else {
 789                                 tone[0] = 0;
 790                                 noise[0] = 0;
 791                         }
 792                 } else if (channel == 134) {
 793                         tone[0] = 0x20;
 794                         noise[0] = 0x21F;
 795                 } else if (channel == 151) {
 796                         tone[0] = 0x10;
 797                         noise[0] = 0x23F;
 798                 } else if (channel == 153 || channel == 161) {
 799                         tone[0] = 0x30;
 800                         noise[0] = 0x23F;
 801                 } else {
 802                         tone[0] = 0;
 803                         noise[0] = 0;
 804                 }
 805
 806                 if (!tone[0] && !noise[0])
 807                         ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
 808                 else
 809                         ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
 810         }
 811
 812         if (nphy->hang_avoid)
 813                 b43_nphy_stay_in_carrier_search(dev, 0);
 814 }
 815
 816 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
 817 static void b43_nphy_gain_crtl_workarounds(struct b43_wldev *dev)
 818 {
 819         struct b43_phy_n *nphy = dev->phy.n;
 820         u8 i, j;
 821         u8 code;
 822
 823         /* TODO: for PHY >= 3
 824         s8 *lna1_gain, *lna2_gain;
 825         u8 *gain_db, *gain_bits;
 826         u16 *rfseq_init;
 827         u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
 828         u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
 829         */
 830
 831         u8 rfseq_events[3] = { 6, 8, 7 };
 832         u8 rfseq_delays[3] = { 10, 30, 1 };
 833
 834         if (dev->phy.rev >= 3) {
 835                 /* TODO */
 836         } else {
 837                 /* Set Clip 2 detect */
 838                 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
 839                                 B43_NPHY_C1_CGAINI_CL2DETECT);
 840                 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
 841                                 B43_NPHY_C2_CGAINI_CL2DETECT);
 842
 843                 /* Set narrowband clip threshold */
 844                 b43_phy_set(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
 845                 b43_phy_set(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
 846
 847                 if (!dev->phy.is_40mhz) {
 848                         /* Set dwell lengths */
 849                         b43_phy_set(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
 850                         b43_phy_set(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
 851                         b43_phy_set(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
 852                         b43_phy_set(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
 853                 }
 854
 855                 /* Set wideband clip 2 threshold */
 856                 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
 857                                 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
 858                                 21);
 859                 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
 860                                 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
 861                                 21);
 862
 863                 if (!dev->phy.is_40mhz) {
 864                         b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
 865                                 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
 866                         b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
 867                                 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
 868                         b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
 869                                 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
 870                         b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
 871                                 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
 872                 }
 873
 874                 b43_phy_set(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
 875
 876                 if (nphy->gain_boost) {
 877                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
 878                             dev->phy.is_40mhz)
 879                                 code = 4;
 880                         else
 881                                 code = 5;
 882                 } else {
 883                         code = dev->phy.is_40mhz ? 6 : 7;
 884                 }
 885
 886                 /* Set HPVGA2 index */
 887                 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
 888                                 ~B43_NPHY_C1_INITGAIN_HPVGA2,
 889                                 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
 890                 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
 891                                 ~B43_NPHY_C2_INITGAIN_HPVGA2,
 892                                 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
 893
 894                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
 895                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
 896                                         (code << 8 | 0x7C));
 897                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
 898                                         (code << 8 | 0x7C));
 899
 900                 /* TODO: b43_nphy_adjust_lna_gain_table(dev); */
 901
 902                 if (nphy->elna_gain_config) {
 903                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
 904                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
 905                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 906                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 907                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 908
 909                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
 910                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
 911                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 912                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 913                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 914
 915                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
 916                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
 917                                         (code << 8 | 0x74));
 918                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
 919                                         (code << 8 | 0x74));
 920                 }
 921
 922                 if (dev->phy.rev == 2) {
 923                         for (i = 0; i < 4; i++) {
 924                                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
 925                                                 (0x0400 * i) + 0x0020);
 926                                 for (j = 0; j < 21; j++)
 927                                         b43_phy_write(dev,
 928                                                 B43_NPHY_TABLE_DATALO, 3 * j);
 929                         }
 930
 931                         b43_nphy_set_rf_sequence(dev, 5,
 932                                         rfseq_events, rfseq_delays, 3);
 933                         b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
 934                                 (u16)~B43_NPHY_OVER_DGAIN_CCKDGECV,
 935                                 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
 936
 937                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
 938                                 b43_phy_maskset(dev, B43_PHY_N(0xC5D),
 939                                                 0xFF80, 4);
 940                 }
 941         }
 942 }
 943
 944 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
 945 static void b43_nphy_workarounds(struct b43_wldev *dev)
 946 {
 947         struct ssb_bus *bus = dev->dev->bus;
 948         struct b43_phy *phy = &dev->phy;
 949         struct b43_phy_n *nphy = phy->n;
 950
 951         u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
 952         u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
 953
 954         u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
 955         u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
 956
 957         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
 958                 b43_nphy_classifier(dev, 1, 0);
 959         else
 960                 b43_nphy_classifier(dev, 1, 1);
 961
 962         if (nphy->hang_avoid)
 963                 b43_nphy_stay_in_carrier_search(dev, 1);
 964
 965         b43_phy_set(dev, B43_NPHY_IQFLIP,
 966                     B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
 967
 968         if (dev->phy.rev >= 3) {
 969                 /* TODO */
 970         } else {
 971                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
 972                     nphy->band5g_pwrgain) {
 973                         b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
 974                         b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
 975                 } else {
 976                         b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
 977                         b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
 978                 }
 979
 980                 /* TODO: convert to b43_ntab_write? */
 981                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2000);
 982                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A);
 983                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2010);
 984                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A);
 985                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2002);
 986                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA);
 987                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2012);
 988                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA);
 989
 990                 if (dev->phy.rev < 2) {
 991                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2008);
 992                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000);
 993                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2018);
 994                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000);
 995                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2007);
 996                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB);
 997                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2017);
 998                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB);
 999                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2006);
1000                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800);
1001                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2016);
1002                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800);
1003                 }
1004
1005                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
1006                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
1007                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
1008                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
1009
1010                 if (bus->sprom.boardflags2_lo & 0x100 &&
1011                     bus->boardinfo.type == 0x8B) {
1012                         delays1[0] = 0x1;
1013                         delays1[5] = 0x14;
1014                 }
1015                 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
1016                 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
1017
1018                 b43_nphy_gain_crtl_workarounds(dev);
1019
1020                 if (dev->phy.rev < 2) {
1021                         if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
1022                                 ; /*TODO: b43_mhf(dev, 2, 0x0010, 0x0010, 3);*/
1023                 } else if (dev->phy.rev == 2) {
1024                         b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
1025                         b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
1026                 }
1027
1028                 if (dev->phy.rev < 2)
1029                         b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
1030                                         ~B43_NPHY_SCRAM_SIGCTL_SCM);
1031
1032                 /* Set phase track alpha and beta */
1033                 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
1034                 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
1035                 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
1036                 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
1037                 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
1038                 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
1039
1040                 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
1041                                 (u16)~B43_NPHY_PIL_DW_64QAM);
1042                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
1043                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
1044                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
1045
1046                 if (dev->phy.rev == 2)
1047                         b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
1048                                         B43_NPHY_FINERX2_CGC_DECGC);
1049         }
1050
1051         if (nphy->hang_avoid)
1052                 b43_nphy_stay_in_carrier_search(dev, 0);
1053 }
1054
1055 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
1056 static int b43_nphy_load_samples(struct b43_wldev *dev,
1057                                         struct b43_c32 *samples, u16 len) {
1058         struct b43_phy_n *nphy = dev->phy.n;
1059         u16 i;
1060         u32 *data;
1061
1062         data = kzalloc(len * sizeof(u32), GFP_KERNEL);
1063         if (!data) {
1064                 b43err(dev->wl, "allocation for samples loading failed\n");
1065                 return -ENOMEM;
1066         }
1067         if (nphy->hang_avoid)
1068                 b43_nphy_stay_in_carrier_search(dev, 1);
1069
1070         for (i = 0; i < len; i++) {
1071                 data[i] = (samples[i].i & 0x3FF << 10);
1072                 data[i] |= samples[i].q & 0x3FF;
1073         }
1074         b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
1075
1076         kfree(data);
1077         if (nphy->hang_avoid)
1078                 b43_nphy_stay_in_carrier_search(dev, 0);
1079         return 0;
1080 }
1081
1082 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
1083 static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1084                                         bool test)
1085 {
1086         int i;
1087         u16 bw, len, rot, angle;
1088         struct b43_c32 *samples;
1089
1090
1091         bw = (dev->phy.is_40mhz) ? 40 : 20;
1092         len = bw << 3;
1093
1094         if (test) {
1095                 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
1096                         bw = 82;
1097                 else
1098                         bw = 80;
1099
1100                 if (dev->phy.is_40mhz)
1101                         bw <<= 1;
1102
1103                 len = bw << 1;
1104         }
1105
1106         samples = kzalloc(len * sizeof(struct b43_c32), GFP_KERNEL);
1107         if (!samples) {
1108                 b43err(dev->wl, "allocation for samples generation failed\n");
1109                 return 0;
1110         }
1111         rot = (((freq * 36) / bw) << 16) / 100;
1112         angle = 0;
1113
1114         for (i = 0; i < len; i++) {
1115                 samples[i] = b43_cordic(angle);
1116                 angle += rot;
1117                 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
1118                 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
1119         }
1120
1121         i = b43_nphy_load_samples(dev, samples, len);
1122         kfree(samples);
1123         return (i < 0) ? 0 : len;
1124 }
1125
1126 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
1127 static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1128                                         u16 wait, bool iqmode, bool dac_test)
1129 {
1130         struct b43_phy_n *nphy = dev->phy.n;
1131         int i;
1132         u16 seq_mode;
1133         u32 tmp;
1134
1135         if (nphy->hang_avoid)
1136                 b43_nphy_stay_in_carrier_search(dev, true);
1137
1138         if ((nphy->bb_mult_save & 0x80000000) == 0) {
1139                 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1140                 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1141         }
1142
1143         if (!dev->phy.is_40mhz)
1144                 tmp = 0x6464;
1145         else
1146                 tmp = 0x4747;
1147         b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1148
1149         if (nphy->hang_avoid)
1150                 b43_nphy_stay_in_carrier_search(dev, false);
1151
1152         b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
1153
1154         if (loops != 0xFFFF)
1155                 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1156         else
1157                 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
1158
1159         b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
1160
1161         seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1162
1163         b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1164         if (iqmode) {
1165                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1166                 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1167         } else {
1168                 if (dac_test)
1169                         b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
1170                 else
1171                         b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
1172         }
1173         for (i = 0; i < 100; i++) {
1174                 if (b43_phy_read(dev, B43_NPHY_RFSEQST) & 1) {
1175                         i = 0;
1176                         break;
1177                 }
1178                 udelay(10);
1179         }
1180         if (i)
1181                 b43err(dev->wl, "run samples timeout\n");
1182
1183         b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1184 }
1185
1186 /*
1187  * Transmits a known value for LO calibration
1188  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
1189  */
1190 static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
1191                                 bool iqmode, bool dac_test)
1192 {
1193         u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
1194         if (samp == 0)
1195                 return -1;
1196         b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
1197         return 0;
1198 }
1199
1200 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
1201 static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
1202 {
1203         struct b43_phy_n *nphy = dev->phy.n;
1204         int i, j;
1205         u32 tmp;
1206         u32 cur_real, cur_imag, real_part, imag_part;
1207
1208         u16 buffer[7];
1209
1210         if (nphy->hang_avoid)
1211                 b43_nphy_stay_in_carrier_search(dev, true);
1212
1213         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
1214
1215         for (i = 0; i < 2; i++) {
1216                 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
1217                         (buffer[i * 2 + 1] & 0x3FF);
1218                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1219                                 (((i + 26) << 10) | 320));
1220                 for (j = 0; j < 128; j++) {
1221                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1222                                         ((tmp >> 16) & 0xFFFF));
1223                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1224                                         (tmp & 0xFFFF));
1225                 }
1226         }
1227
1228         for (i = 0; i < 2; i++) {
1229                 tmp = buffer[5 + i];
1230                 real_part = (tmp >> 8) & 0xFF;
1231                 imag_part = (tmp & 0xFF);
1232                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1233                                 (((i + 26) << 10) | 448));
1234
1235                 if (dev->phy.rev >= 3) {
1236                         cur_real = real_part;
1237                         cur_imag = imag_part;
1238                         tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
1239                 }
1240
1241                 for (j = 0; j < 128; j++) {
1242                         if (dev->phy.rev < 3) {
1243                                 cur_real = (real_part * loscale[j] + 128) >> 8;
1244                                 cur_imag = (imag_part * loscale[j] + 128) >> 8;
1245                                 tmp = ((cur_real & 0xFF) << 8) |
1246                                         (cur_imag & 0xFF);
1247                         }
1248                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1249                                         ((tmp >> 16) & 0xFFFF));
1250                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1251                                         (tmp & 0xFFFF));
1252                 }
1253         }
1254
1255         if (dev->phy.rev >= 3) {
1256                 b43_shm_write16(dev, B43_SHM_SHARED,
1257                                 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
1258                 b43_shm_write16(dev, B43_SHM_SHARED,
1259                                 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
1260         }
1261
1262         if (nphy->hang_avoid)
1263                 b43_nphy_stay_in_carrier_search(dev, false);
1264 }
1265
1266 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
1267 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
1268                                         u8 *events, u8 *delays, u8 length)
1269 {
1270         struct b43_phy_n *nphy = dev->phy.n;
1271         u8 i;
1272         u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
1273         u16 offset1 = cmd << 4;
1274         u16 offset2 = offset1 + 0x80;
1275
1276         if (nphy->hang_avoid)
1277                 b43_nphy_stay_in_carrier_search(dev, true);
1278
1279         b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
1280         b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
1281
1282         for (i = length; i < 16; i++) {
1283                 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
1284                 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
1285         }
1286
1287         if (nphy->hang_avoid)
1288                 b43_nphy_stay_in_carrier_search(dev, false);
1289 }
1290
1291 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
1292 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
1293                                        enum b43_nphy_rf_sequence seq)
1294 {
1295         static const u16 trigger[] = {
1296                 [B43_RFSEQ_RX2TX]               = B43_NPHY_RFSEQTR_RX2TX,
1297                 [B43_RFSEQ_TX2RX]               = B43_NPHY_RFSEQTR_TX2RX,
1298                 [B43_RFSEQ_RESET2RX]            = B43_NPHY_RFSEQTR_RST2RX,
1299                 [B43_RFSEQ_UPDATE_GAINH]        = B43_NPHY_RFSEQTR_UPGH,
1300                 [B43_RFSEQ_UPDATE_GAINL]        = B43_NPHY_RFSEQTR_UPGL,
1301                 [B43_RFSEQ_UPDATE_GAINU]        = B43_NPHY_RFSEQTR_UPGU,
1302         };
1303         int i;
1304         u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1305
1306         B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
1307
1308         b43_phy_set(dev, B43_NPHY_RFSEQMODE,
1309                     B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
1310         b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
1311         for (i = 0; i < 200; i++) {
1312                 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
1313                         goto ok;
1314                 msleep(1);
1315         }
1316         b43err(dev->wl, "RF sequence status timeout\n");
1317 ok:
1318         b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1319 }
1320
1321 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
1322 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
1323                                                 u16 value, u8 core, bool off)
1324 {
1325         int i;
1326         u8 index = fls(field);
1327         u8 addr, en_addr, val_addr;
1328         /* we expect only one bit set */
1329         B43_WARN_ON(field & (~(1 << (index - 1))));
1330
1331         if (dev->phy.rev >= 3) {
1332                 const struct nphy_rf_control_override_rev3 *rf_ctrl;
1333                 for (i = 0; i < 2; i++) {
1334                         if (index == 0 || index == 16) {
1335                                 b43err(dev->wl,
1336                                         "Unsupported RF Ctrl Override call\n");
1337                                 return;
1338                         }
1339
1340                         rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
1341                         en_addr = B43_PHY_N((i == 0) ?
1342                                 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
1343                         val_addr = B43_PHY_N((i == 0) ?
1344                                 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
1345
1346                         if (off) {
1347                                 b43_phy_mask(dev, en_addr, ~(field));
1348                                 b43_phy_mask(dev, val_addr,
1349                                                 ~(rf_ctrl->val_mask));
1350                         } else {
1351                                 if (core == 0 || ((1 << core) & i) != 0) {
1352                                         b43_phy_set(dev, en_addr, field);
1353                                         b43_phy_maskset(dev, val_addr,
1354                                                 ~(rf_ctrl->val_mask),
1355                                                 (value << rf_ctrl->val_shift));
1356                                 }
1357                         }
1358                 }
1359         } else {
1360                 const struct nphy_rf_control_override_rev2 *rf_ctrl;
1361                 if (off) {
1362                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
1363                         value = 0;
1364                 } else {
1365                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
1366                 }
1367
1368                 for (i = 0; i < 2; i++) {
1369                         if (index <= 1 || index == 16) {
1370                                 b43err(dev->wl,
1371                                         "Unsupported RF Ctrl Override call\n");
1372                                 return;
1373                         }
1374
1375                         if (index == 2 || index == 10 ||
1376                             (index >= 13 && index <= 15)) {
1377                                 core = 1;
1378                         }
1379
1380                         rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
1381                         addr = B43_PHY_N((i == 0) ?
1382                                 rf_ctrl->addr0 : rf_ctrl->addr1);
1383
1384                         if ((core & (1 << i)) != 0)
1385                                 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
1386                                                 (value << rf_ctrl->shift));
1387
1388                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
1389                         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1390                                         B43_NPHY_RFCTL_CMD_START);
1391                         udelay(1);
1392                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
1393                 }
1394         }
1395 }
1396
1397 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
1398 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
1399                                                 u16 value, u8 core)
1400 {
1401         u8 i, j;
1402         u16 reg, tmp, val;
1403
1404         B43_WARN_ON(dev->phy.rev < 3);
1405         B43_WARN_ON(field > 4);
1406
1407         for (i = 0; i < 2; i++) {
1408                 if ((core == 1 && i == 1) || (core == 2 && !i))
1409                         continue;
1410
1411                 reg = (i == 0) ?
1412                         B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
1413                 b43_phy_mask(dev, reg, 0xFBFF);
1414
1415                 switch (field) {
1416                 case 0:
1417                         b43_phy_write(dev, reg, 0);
1418                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
1419                         break;
1420                 case 1:
1421                         if (!i) {
1422                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
1423                                                 0xFC3F, (value << 6));
1424                                 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
1425                                                 0xFFFE, 1);
1426                                 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1427                                                 B43_NPHY_RFCTL_CMD_START);
1428                                 for (j = 0; j < 100; j++) {
1429                                         if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START) {
1430                                                 j = 0;
1431                                                 break;
1432                                         }
1433                                         udelay(10);
1434                                 }
1435                                 if (j)
1436                                         b43err(dev->wl,
1437                                                 "intc override timeout\n");
1438                                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
1439                                                 0xFFFE);
1440                         } else {
1441                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
1442                                                 0xFC3F, (value << 6));
1443                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1444                                                 0xFFFE, 1);
1445                                 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1446                                                 B43_NPHY_RFCTL_CMD_RXTX);
1447                                 for (j = 0; j < 100; j++) {
1448                                         if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX) {
1449                                                 j = 0;
1450                                                 break;
1451                                         }
1452                                         udelay(10);
1453                                 }
1454                                 if (j)
1455                                         b43err(dev->wl,
1456                                                 "intc override timeout\n");
1457                                 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1458                                                 0xFFFE);
1459                         }
1460                         break;
1461                 case 2:
1462                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1463                                 tmp = 0x0020;
1464                                 val = value << 5;
1465                         } else {
1466                                 tmp = 0x0010;
1467                                 val = value << 4;
1468                         }
1469                         b43_phy_maskset(dev, reg, ~tmp, val);
1470                         break;
1471                 case 3:
1472                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1473                                 tmp = 0x0001;
1474                                 val = value;
1475                         } else {
1476                                 tmp = 0x0004;
1477                                 val = value << 2;
1478                         }
1479                         b43_phy_maskset(dev, reg, ~tmp, val);
1480                         break;
1481                 case 4:
1482                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1483                                 tmp = 0x0002;
1484                                 val = value << 1;
1485                         } else {
1486                                 tmp = 0x0008;
1487                                 val = value << 3;
1488                         }
1489                         b43_phy_maskset(dev, reg, ~tmp, val);
1490                         break;
1491                 }
1492         }
1493 }
1494
1495 static void b43_nphy_bphy_init(struct b43_wldev *dev)
1496 {
1497         unsigned int i;
1498         u16 val;
1499
1500         val = 0x1E1F;
1501         for (i = 0; i < 14; i++) {
1502                 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
1503                 val -= 0x202;
1504         }
1505         val = 0x3E3F;
1506         for (i = 0; i < 16; i++) {
1507                 b43_phy_write(dev, B43_PHY_N_BMODE(0x97 + i), val);
1508                 val -= 0x202;
1509         }
1510         b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
1511 }
1512
1513 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
1514 static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
1515                                        s8 offset, u8 core, u8 rail, u8 type)
1516 {
1517         u16 tmp;
1518         bool core1or5 = (core == 1) || (core == 5);
1519         bool core2or5 = (core == 2) || (core == 5);
1520
1521         offset = clamp_val(offset, -32, 31);
1522         tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
1523
1524         if (core1or5 && (rail == 0) && (type == 2))
1525                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
1526         if (core1or5 && (rail == 1) && (type == 2))
1527                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
1528         if (core2or5 && (rail == 0) && (type == 2))
1529                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
1530         if (core2or5 && (rail == 1) && (type == 2))
1531                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
1532         if (core1or5 && (rail == 0) && (type == 0))
1533                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
1534         if (core1or5 && (rail == 1) && (type == 0))
1535                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
1536         if (core2or5 && (rail == 0) && (type == 0))
1537                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
1538         if (core2or5 && (rail == 1) && (type == 0))
1539                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
1540         if (core1or5 && (rail == 0) && (type == 1))
1541                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
1542         if (core1or5 && (rail == 1) && (type == 1))
1543                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
1544         if (core2or5 && (rail == 0) && (type == 1))
1545                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
1546         if (core2or5 && (rail == 1) && (type == 1))
1547                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
1548         if (core1or5 && (rail == 0) && (type == 6))
1549                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
1550         if (core1or5 && (rail == 1) && (type == 6))
1551                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
1552         if (core2or5 && (rail == 0) && (type == 6))
1553                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
1554         if (core2or5 && (rail == 1) && (type == 6))
1555                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
1556         if (core1or5 && (rail == 0) && (type == 3))
1557                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
1558         if (core1or5 && (rail == 1) && (type == 3))
1559                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
1560         if (core2or5 && (rail == 0) && (type == 3))
1561                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
1562         if (core2or5 && (rail == 1) && (type == 3))
1563                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
1564         if (core1or5 && (type == 4))
1565                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
1566         if (core2or5 && (type == 4))
1567                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
1568         if (core1or5 && (type == 5))
1569                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
1570         if (core2or5 && (type == 5))
1571                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
1572 }
1573
1574 static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1575 {
1576         u16 val;
1577
1578         if (type < 3)
1579                 val = 0;
1580         else if (type == 6)
1581                 val = 1;
1582         else if (type == 3)
1583                 val = 2;
1584         else
1585                 val = 3;
1586
1587         val = (val << 12) | (val << 14);
1588         b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1589         b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
1590
1591         if (type < 3) {
1592                 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
1593                                 (type + 1) << 4);
1594                 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
1595                                 (type + 1) << 4);
1596         }
1597
1598         /* TODO use some definitions */
1599         if (code == 0) {
1600                 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF, 0);
1601                 if (type < 3) {
1602                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFEC7, 0);
1603                         b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xEFDC, 0);
1604                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFFFE, 0);
1605                         udelay(20);
1606                         b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xFFFE, 0);
1607                 }
1608         } else {
1609                 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF,
1610                                 0x3000);
1611                 if (type < 3) {
1612                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1613                                         0xFEC7, 0x0180);
1614                         b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1615                                         0xEFDC, (code << 1 | 0x1021));
1616                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFFFE, 0x1);
1617                         udelay(20);
1618                         b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xFFFE, 0);
1619                 }
1620         }
1621 }
1622
1623 static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1624 {
1625         struct b43_phy_n *nphy = dev->phy.n;
1626         u8 i;
1627         u16 reg, val;
1628
1629         if (code == 0) {
1630                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
1631                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
1632                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
1633                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
1634                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
1635                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
1636                 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
1637                 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
1638         } else {
1639                 for (i = 0; i < 2; i++) {
1640                         if ((code == 1 && i == 1) || (code == 2 && !i))
1641                                 continue;
1642
1643                         reg = (i == 0) ?
1644                                 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
1645                         b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
1646
1647                         if (type < 3) {
1648                                 reg = (i == 0) ?
1649                                         B43_NPHY_AFECTL_C1 :
1650                                         B43_NPHY_AFECTL_C2;
1651                                 b43_phy_maskset(dev, reg, 0xFCFF, 0);
1652
1653                                 reg = (i == 0) ?
1654                                         B43_NPHY_RFCTL_LUT_TRSW_UP1 :
1655                                         B43_NPHY_RFCTL_LUT_TRSW_UP2;
1656                                 b43_phy_maskset(dev, reg, 0xFFC3, 0);
1657
1658                                 if (type == 0)
1659                                         val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
1660                                 else if (type == 1)
1661                                         val = 16;
1662                                 else
1663                                         val = 32;
1664                                 b43_phy_set(dev, reg, val);
1665
1666                                 reg = (i == 0) ?
1667                                         B43_NPHY_TXF_40CO_B1S0 :
1668                                         B43_NPHY_TXF_40CO_B32S1;
1669                                 b43_phy_set(dev, reg, 0x0020);
1670                         } else {
1671                                 if (type == 6)
1672                                         val = 0x0100;
1673                                 else if (type == 3)
1674                                         val = 0x0200;
1675                                 else
1676                                         val = 0x0300;
1677
1678                                 reg = (i == 0) ?
1679                                         B43_NPHY_AFECTL_C1 :
1680                                         B43_NPHY_AFECTL_C2;
1681
1682                                 b43_phy_maskset(dev, reg, 0xFCFF, val);
1683                                 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
1684
1685                                 if (type != 3 && type != 6) {
1686                                         enum ieee80211_band band =
1687                                                 b43_current_band(dev->wl);
1688
1689                                         if ((nphy->ipa2g_on &&
1690                                                 band == IEEE80211_BAND_2GHZ) ||
1691                                                 (nphy->ipa5g_on &&
1692                                                 band == IEEE80211_BAND_5GHZ))
1693                                                 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
1694                                         else
1695                                                 val = 0x11;
1696                                         reg = (i == 0) ? 0x2000 : 0x3000;
1697                                         reg |= B2055_PADDRV;
1698                                         b43_radio_write16(dev, reg, val);
1699
1700                                         reg = (i == 0) ?
1701                                                 B43_NPHY_AFECTL_OVER1 :
1702                                                 B43_NPHY_AFECTL_OVER;
1703                                         b43_phy_set(dev, reg, 0x0200);
1704                                 }
1705                         }
1706                 }
1707         }
1708 }
1709
1710 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
1711 static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1712 {
1713         if (dev->phy.rev >= 3)
1714                 b43_nphy_rev3_rssi_select(dev, code, type);
1715         else
1716                 b43_nphy_rev2_rssi_select(dev, code, type);
1717 }
1718
1719 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
1720 static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
1721 {
1722         int i;
1723         for (i = 0; i < 2; i++) {
1724                 if (type == 2) {
1725                         if (i == 0) {
1726                                 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
1727                                                   0xFC, buf[0]);
1728                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1729                                                   0xFC, buf[1]);
1730                         } else {
1731                                 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
1732                                                   0xFC, buf[2 * i]);
1733                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1734                                                   0xFC, buf[2 * i + 1]);
1735                         }
1736                 } else {
1737                         if (i == 0)
1738                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1739                                                   0xF3, buf[0] << 2);
1740                         else
1741                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1742                                                   0xF3, buf[2 * i + 1] << 2);
1743                 }
1744         }
1745 }
1746
1747 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
1748 static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
1749                                 u8 nsamp)
1750 {
1751         int i;
1752         int out;
1753         u16 save_regs_phy[9];
1754         u16 s[2];
1755
1756         if (dev->phy.rev >= 3) {
1757                 save_regs_phy[0] = b43_phy_read(dev,
1758                                                 B43_NPHY_RFCTL_LUT_TRSW_UP1);
1759                 save_regs_phy[1] = b43_phy_read(dev,
1760                                                 B43_NPHY_RFCTL_LUT_TRSW_UP2);
1761                 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1762                 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1763                 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1764                 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1765                 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
1766                 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
1767         }
1768
1769         b43_nphy_rssi_select(dev, 5, type);
1770
1771         if (dev->phy.rev < 2) {
1772                 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
1773                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
1774         }
1775
1776         for (i = 0; i < 4; i++)
1777                 buf[i] = 0;
1778
1779         for (i = 0; i < nsamp; i++) {
1780                 if (dev->phy.rev < 2) {
1781                         s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
1782                         s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
1783                 } else {
1784                         s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
1785                         s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
1786                 }
1787
1788                 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
1789                 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
1790                 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
1791                 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
1792         }
1793         out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
1794                 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
1795
1796         if (dev->phy.rev < 2)
1797                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
1798
1799         if (dev->phy.rev >= 3) {
1800                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
1801                                 save_regs_phy[0]);
1802                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1803                                 save_regs_phy[1]);
1804                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
1805                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
1806                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
1807                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
1808                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
1809                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
1810         }
1811
1812         return out;
1813 }
1814
1815 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
1816 static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
1817 {
1818         int i, j;
1819         u8 state[4];
1820         u8 code, val;
1821         u16 class, override;
1822         u8 regs_save_radio[2];
1823         u16 regs_save_phy[2];
1824         s8 offset[4];
1825
1826         u16 clip_state[2];
1827         u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1828         s32 results_min[4] = { };
1829         u8 vcm_final[4] = { };
1830         s32 results[4][4] = { };
1831         s32 miniq[4][2] = { };
1832
1833         if (type == 2) {
1834                 code = 0;
1835                 val = 6;
1836         } else if (type < 2) {
1837                 code = 25;
1838                 val = 4;
1839         } else {
1840                 B43_WARN_ON(1);
1841                 return;
1842         }
1843
1844         class = b43_nphy_classifier(dev, 0, 0);
1845         b43_nphy_classifier(dev, 7, 4);
1846         b43_nphy_read_clip_detection(dev, clip_state);
1847         b43_nphy_write_clip_detection(dev, clip_off);
1848
1849         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1850                 override = 0x140;
1851         else
1852                 override = 0x110;
1853
1854         regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1855         regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
1856         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
1857         b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
1858
1859         regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1860         regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
1861         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
1862         b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
1863
1864         state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
1865         state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
1866         b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
1867         b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
1868         state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
1869         state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
1870
1871         b43_nphy_rssi_select(dev, 5, type);
1872         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
1873         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
1874
1875         for (i = 0; i < 4; i++) {
1876                 u8 tmp[4];
1877                 for (j = 0; j < 4; j++)
1878                         tmp[j] = i;
1879                 if (type != 1)
1880                         b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
1881                 b43_nphy_poll_rssi(dev, type, results[i], 8);
1882                 if (type < 2)
1883                         for (j = 0; j < 2; j++)
1884                                 miniq[i][j] = min(results[i][2 * j],
1885                                                 results[i][2 * j + 1]);
1886         }
1887
1888         for (i = 0; i < 4; i++) {
1889                 s32 mind = 40;
1890                 u8 minvcm = 0;
1891                 s32 minpoll = 249;
1892                 s32 curr;
1893                 for (j = 0; j < 4; j++) {
1894                         if (type == 2)
1895                                 curr = abs(results[j][i]);
1896                         else
1897                                 curr = abs(miniq[j][i / 2] - code * 8);
1898
1899                         if (curr < mind) {
1900                                 mind = curr;
1901                                 minvcm = j;
1902                         }
1903
1904                         if (results[j][i] < minpoll)
1905                                 minpoll = results[j][i];
1906                 }
1907                 results_min[i] = minpoll;
1908                 vcm_final[i] = minvcm;
1909         }
1910
1911         if (type != 1)
1912                 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
1913
1914         for (i = 0; i < 4; i++) {
1915                 offset[i] = (code * 8) - results[vcm_final[i]][i];
1916
1917                 if (offset[i] < 0)
1918                         offset[i] = -((abs(offset[i]) + 4) / 8);
1919                 else
1920                         offset[i] = (offset[i] + 4) / 8;
1921
1922                 if (results_min[i] == 248)
1923                         offset[i] = code - 32;
1924
1925                 if (i % 2 == 0)
1926                         b43_nphy_scale_offset_rssi(dev, 0, offset[i], 1, 0,
1927                                                         type);
1928                 else
1929                         b43_nphy_scale_offset_rssi(dev, 0, offset[i], 2, 1,
1930                                                         type);
1931         }
1932
1933         b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
1934         b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[1]);
1935
1936         switch (state[2]) {
1937         case 1:
1938                 b43_nphy_rssi_select(dev, 1, 2);
1939                 break;
1940         case 4:
1941                 b43_nphy_rssi_select(dev, 1, 0);
1942                 break;
1943         case 2:
1944                 b43_nphy_rssi_select(dev, 1, 1);
1945                 break;
1946         default:
1947                 b43_nphy_rssi_select(dev, 1, 1);
1948                 break;
1949         }
1950
1951         switch (state[3]) {
1952         case 1:
1953                 b43_nphy_rssi_select(dev, 2, 2);
1954                 break;
1955         case 4:
1956                 b43_nphy_rssi_select(dev, 2, 0);
1957                 break;
1958         default:
1959                 b43_nphy_rssi_select(dev, 2, 1);
1960                 break;
1961         }
1962
1963         b43_nphy_rssi_select(dev, 0, type);
1964
1965         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
1966         b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
1967         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
1968         b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
1969
1970         b43_nphy_classifier(dev, 7, class);
1971         b43_nphy_write_clip_detection(dev, clip_state);
1972 }
1973
1974 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
1975 static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
1976 {
1977         /* TODO */
1978 }
1979
1980 /*
1981  * RSSI Calibration
1982  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
1983  */
1984 static void b43_nphy_rssi_cal(struct b43_wldev *dev)
1985 {
1986         if (dev->phy.rev >= 3) {
1987                 b43_nphy_rev3_rssi_cal(dev);
1988         } else {
1989                 b43_nphy_rev2_rssi_cal(dev, 2);
1990                 b43_nphy_rev2_rssi_cal(dev, 0);
1991                 b43_nphy_rev2_rssi_cal(dev, 1);
1992         }
1993 }
1994
1995 /*
1996  * Restore RSSI Calibration
1997  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
1998  */
1999 static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
2000 {
2001         struct b43_phy_n *nphy = dev->phy.n;
2002
2003         u16 *rssical_radio_regs = NULL;
2004         u16 *rssical_phy_regs = NULL;
2005
2006         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2007                 if (!nphy->rssical_chanspec_2G)
2008                         return;
2009                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
2010                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
2011         } else {
2012                 if (!nphy->rssical_chanspec_5G)
2013                         return;
2014                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
2015                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
2016         }
2017
2018         /* TODO use some definitions */
2019         b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
2020         b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
2021
2022         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
2023         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
2024         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
2025         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
2026
2027         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
2028         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
2029         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
2030         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
2031
2032         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
2033         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
2034         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
2035         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
2036 }
2037
2038 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
2039 static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
2040 {
2041         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2042                 if (dev->phy.rev >= 6) {
2043                         /* TODO If the chip is 47162
2044                                 return txpwrctrl_tx_gain_ipa_rev5 */
2045                         return txpwrctrl_tx_gain_ipa_rev6;
2046                 } else if (dev->phy.rev >= 5) {
2047                         return txpwrctrl_tx_gain_ipa_rev5;
2048                 } else {
2049                         return txpwrctrl_tx_gain_ipa;
2050                 }
2051         } else {
2052                 return txpwrctrl_tx_gain_ipa_5g;
2053         }
2054 }
2055
2056 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
2057 static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
2058 {
2059         struct b43_phy_n *nphy = dev->phy.n;
2060         u16 *save = nphy->tx_rx_cal_radio_saveregs;
2061         u16 tmp;
2062         u8 offset, i;
2063
2064         if (dev->phy.rev >= 3) {
2065             for (i = 0; i < 2; i++) {
2066                 tmp = (i == 0) ? 0x2000 : 0x3000;
2067                 offset = i * 11;
2068
2069                 save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL);
2070                 save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL);
2071                 save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS);
2072                 save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS);
2073                 save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS);
2074                 save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV);
2075                 save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1);
2076                 save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2);
2077                 save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL);
2078                 save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC);
2079                 save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1);
2080
2081                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2082                         b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
2083                         b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2084                         b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2085                         b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2086                         b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2087                         if (nphy->ipa5g_on) {
2088                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 4);
2089                                 b43_radio_write16(dev, tmp | B2055_XOCTL1, 1);
2090                         } else {
2091                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2092                                 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F);
2093                         }
2094                         b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2095                 } else {
2096                         b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06);
2097                         b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2098                         b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2099                         b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2100                         b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2101                         b43_radio_write16(dev, tmp | B2055_XOCTL1, 0);
2102                         if (nphy->ipa2g_on) {
2103                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 6);
2104                                 b43_radio_write16(dev, tmp | B2055_XOCTL2,
2105                                         (dev->phy.rev < 5) ? 0x11 : 0x01);
2106                         } else {
2107                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2108                                 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2109                         }
2110                 }
2111                 b43_radio_write16(dev, tmp | B2055_XOREGUL, 0);
2112                 b43_radio_write16(dev, tmp | B2055_XOMISC, 0);
2113                 b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0);
2114             }
2115         } else {
2116                 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
2117                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
2118
2119                 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
2120                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
2121
2122                 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
2123                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
2124
2125                 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
2126                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
2127
2128                 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
2129                 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
2130
2131                 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
2132                     B43_NPHY_BANDCTL_5GHZ)) {
2133                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
2134                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
2135                 } else {
2136                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
2137                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
2138                 }
2139
2140                 if (dev->phy.rev < 2) {
2141                         b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
2142                         b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
2143                 } else {
2144                         b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
2145                         b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
2146                 }
2147         }
2148 }
2149
2150 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
2151 static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
2152                                         struct nphy_txgains target,
2153                                         struct nphy_iqcal_params *params)
2154 {
2155         int i, j, indx;
2156         u16 gain;
2157
2158         if (dev->phy.rev >= 3) {
2159                 params->txgm = target.txgm[core];
2160                 params->pga = target.pga[core];
2161                 params->pad = target.pad[core];
2162                 params->ipa = target.ipa[core];
2163                 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
2164                                         (params->pad << 4) | (params->ipa);
2165                 for (j = 0; j < 5; j++)
2166                         params->ncorr[j] = 0x79;
2167         } else {
2168                 gain = (target.pad[core]) | (target.pga[core] << 4) |
2169                         (target.txgm[core] << 8);
2170
2171                 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
2172                         1 : 0;
2173                 for (i = 0; i < 9; i++)
2174                         if (tbl_iqcal_gainparams[indx][i][0] == gain)
2175                                 break;
2176                 i = min(i, 8);
2177
2178                 params->txgm = tbl_iqcal_gainparams[indx][i][1];
2179                 params->pga = tbl_iqcal_gainparams[indx][i][2];
2180                 params->pad = tbl_iqcal_gainparams[indx][i][3];
2181                 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
2182                                         (params->pad << 2);
2183                 for (j = 0; j < 4; j++)
2184                         params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
2185         }
2186 }
2187
2188 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
2189 static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
2190 {
2191         struct b43_phy_n *nphy = dev->phy.n;
2192         int i;
2193         u16 scale, entry;
2194
2195         u16 tmp = nphy->txcal_bbmult;
2196         if (core == 0)
2197                 tmp >>= 8;
2198         tmp &= 0xff;
2199
2200         for (i = 0; i < 18; i++) {
2201                 scale = (ladder_lo[i].percent * tmp) / 100;
2202                 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
2203                 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
2204
2205                 scale = (ladder_iq[i].percent * tmp) / 100;
2206                 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
2207                 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
2208         }
2209 }
2210
2211 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
2212 static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
2213 {
2214         int i;
2215         for (i = 0; i < 15; i++)
2216                 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
2217                                 tbl_tx_filter_coef_rev4[2][i]);
2218 }
2219
2220 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
2221 static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
2222 {
2223         int i, j;
2224         /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
2225         u16 offset[] = { 0x186, 0x195, 0x2C5 };
2226
2227         for (i = 0; i < 3; i++)
2228                 for (j = 0; j < 15; j++)
2229                         b43_phy_write(dev, B43_PHY_N(offset[i] + j),
2230                                         tbl_tx_filter_coef_rev4[i][j]);
2231
2232         if (dev->phy.is_40mhz) {
2233                 for (j = 0; j < 15; j++)
2234                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2235                                         tbl_tx_filter_coef_rev4[3][j]);
2236         } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2237                 for (j = 0; j < 15; j++)
2238                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2239                                         tbl_tx_filter_coef_rev4[5][j]);
2240         }
2241
2242         if (dev->phy.channel == 14)
2243                 for (j = 0; j < 15; j++)
2244                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2245                                         tbl_tx_filter_coef_rev4[6][j]);
2246 }
2247
2248 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
2249 static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
2250 {
2251         struct b43_phy_n *nphy = dev->phy.n;
2252
2253         u16 curr_gain[2];
2254         struct nphy_txgains target;
2255         const u32 *table = NULL;
2256
2257         if (nphy->txpwrctrl == 0) {
2258                 int i;
2259
2260                 if (nphy->hang_avoid)
2261                         b43_nphy_stay_in_carrier_search(dev, true);
2262                 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
2263                 if (nphy->hang_avoid)
2264                         b43_nphy_stay_in_carrier_search(dev, false);
2265
2266                 for (i = 0; i < 2; ++i) {
2267                         if (dev->phy.rev >= 3) {
2268                                 target.ipa[i] = curr_gain[i] & 0x000F;
2269                                 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
2270                                 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
2271                                 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
2272                         } else {
2273                                 target.ipa[i] = curr_gain[i] & 0x0003;
2274                                 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
2275                                 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
2276                                 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
2277                         }
2278                 }
2279         } else {
2280                 int i;
2281                 u16 index[2];
2282                 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
2283                         B43_NPHY_TXPCTL_STAT_BIDX) >>
2284                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2285                 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
2286                         B43_NPHY_TXPCTL_STAT_BIDX) >>
2287                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2288
2289                 for (i = 0; i < 2; ++i) {
2290                         if (dev->phy.rev >= 3) {
2291                                 enum ieee80211_band band =
2292                                         b43_current_band(dev->wl);
2293
2294                                 if ((nphy->ipa2g_on &&
2295                                      band == IEEE80211_BAND_2GHZ) ||
2296                                     (nphy->ipa5g_on &&
2297                                      band == IEEE80211_BAND_5GHZ)) {
2298                                         table = b43_nphy_get_ipa_gain_table(dev);
2299                                 } else {
2300                                         if (band == IEEE80211_BAND_5GHZ) {
2301                                                 if (dev->phy.rev == 3)
2302                                                         table = b43_ntab_tx_gain_rev3_5ghz;
2303                                                 else if (dev->phy.rev == 4)
2304                                                         table = b43_ntab_tx_gain_rev4_5ghz;
2305                                                 else
2306                                                         table = b43_ntab_tx_gain_rev5plus_5ghz;
2307                                         } else {
2308                                                 table = b43_ntab_tx_gain_rev3plus_2ghz;
2309                                         }
2310                                 }
2311
2312                                 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
2313                                 target.pad[i] = (table[index[i]] >> 20) & 0xF;
2314                                 target.pga[i] = (table[index[i]] >> 24) & 0xF;
2315                                 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
2316                         } else {
2317                                 table = b43_ntab_tx_gain_rev0_1_2;
2318
2319                                 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
2320                                 target.pad[i] = (table[index[i]] >> 18) & 0x3;
2321                                 target.pga[i] = (table[index[i]] >> 20) & 0x7;
2322                                 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
2323                         }
2324                 }
2325         }
2326
2327         return target;
2328 }
2329
2330 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
2331 static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
2332 {
2333         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2334
2335         if (dev->phy.rev >= 3) {
2336                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
2337                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
2338                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
2339                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
2340                 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
2341                 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
2342                 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
2343                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
2344                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
2345                 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
2346                 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
2347                 b43_nphy_reset_cca(dev);
2348         } else {
2349                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
2350                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
2351                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
2352                 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
2353                 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
2354                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
2355                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
2356         }
2357 }
2358
2359 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
2360 static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
2361 {
2362         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2363         u16 tmp;
2364
2365         regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2366         regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2367         if (dev->phy.rev >= 3) {
2368                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
2369                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
2370
2371                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
2372                 regs[2] = tmp;
2373                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
2374
2375                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2376                 regs[3] = tmp;
2377                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
2378
2379                 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
2380                 b43_phy_mask(dev, B43_NPHY_BBCFG, (u16)~B43_NPHY_BBCFG_RSTRX);
2381
2382                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
2383                 regs[5] = tmp;
2384                 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
2385
2386                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
2387                 regs[6] = tmp;
2388                 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
2389                 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2390                 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2391
2392                 b43_nphy_rf_control_intc_override(dev, 2, 1, 3);
2393                 b43_nphy_rf_control_intc_override(dev, 1, 2, 1);
2394                 b43_nphy_rf_control_intc_override(dev, 1, 8, 2);
2395
2396                 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
2397                 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
2398                 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
2399                 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
2400         } else {
2401                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
2402                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
2403                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2404                 regs[2] = tmp;
2405                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
2406                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
2407                 regs[3] = tmp;
2408                 tmp |= 0x2000;
2409                 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
2410                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
2411                 regs[4] = tmp;
2412                 tmp |= 0x2000;
2413                 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
2414                 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2415                 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2416                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2417                         tmp = 0x0180;
2418                 else
2419                         tmp = 0x0120;
2420                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
2421                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
2422         }
2423 }
2424
2425 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
2426 static void b43_nphy_save_cal(struct b43_wldev *dev)
2427 {
2428         struct b43_phy_n *nphy = dev->phy.n;
2429
2430         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
2431         u16 *txcal_radio_regs = NULL;
2432         u8 *iqcal_chanspec;
2433         u16 *table = NULL;
2434
2435         if (nphy->hang_avoid)
2436                 b43_nphy_stay_in_carrier_search(dev, 1);
2437
2438         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2439                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
2440                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
2441                 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
2442                 table = nphy->cal_cache.txcal_coeffs_2G;
2443         } else {
2444                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
2445                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
2446                 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
2447                 table = nphy->cal_cache.txcal_coeffs_5G;
2448         }
2449
2450         b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
2451         /* TODO use some definitions */
2452         if (dev->phy.rev >= 3) {
2453                 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
2454                 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
2455                 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
2456                 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
2457                 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
2458                 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
2459                 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
2460                 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
2461         } else {
2462                 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
2463                 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
2464                 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
2465                 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
2466         }
2467         *iqcal_chanspec = nphy->radio_chanspec;
2468         b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 8, table);
2469
2470         if (nphy->hang_avoid)
2471                 b43_nphy_stay_in_carrier_search(dev, 0);
2472 }
2473
2474 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
2475 static void b43_nphy_restore_cal(struct b43_wldev *dev)
2476 {
2477         struct b43_phy_n *nphy = dev->phy.n;
2478
2479         u16 coef[4];
2480         u16 *loft = NULL;
2481         u16 *table = NULL;
2482
2483         int i;
2484         u16 *txcal_radio_regs = NULL;
2485         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
2486
2487         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2488                 if (nphy->iqcal_chanspec_2G == 0)
2489                         return;
2490                 table = nphy->cal_cache.txcal_coeffs_2G;
2491                 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
2492         } else {
2493                 if (nphy->iqcal_chanspec_5G == 0)
2494                         return;
2495                 table = nphy->cal_cache.txcal_coeffs_5G;
2496                 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
2497         }
2498
2499         b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
2500
2501         for (i = 0; i < 4; i++) {
2502                 if (dev->phy.rev >= 3)
2503                         table[i] = coef[i];
2504                 else
2505                         coef[i] = 0;
2506         }
2507
2508         b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
2509         b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
2510         b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
2511
2512         if (dev->phy.rev < 2)
2513                 b43_nphy_tx_iq_workaround(dev);
2514
2515         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2516                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
2517                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
2518         } else {
2519                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
2520                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
2521         }
2522
2523         /* TODO use some definitions */
2524         if (dev->phy.rev >= 3) {
2525                 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
2526                 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
2527                 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
2528                 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
2529                 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
2530                 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
2531                 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
2532                 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
2533         } else {
2534                 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
2535                 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
2536                 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
2537                 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
2538         }
2539         b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
2540 }
2541
2542 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
2543 static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
2544                                 struct nphy_txgains target,
2545                                 bool full, bool mphase)
2546 {
2547         struct b43_phy_n *nphy = dev->phy.n;
2548         int i;
2549         int error = 0;
2550         int freq;
2551         bool avoid = false;
2552         u8 length;
2553         u16 tmp, core, type, count, max, numb, last, cmd;
2554         const u16 *table;
2555         bool phy6or5x;
2556
2557         u16 buffer[11];
2558         u16 diq_start = 0;
2559         u16 save[2];
2560         u16 gain[2];
2561         struct nphy_iqcal_params params[2];
2562         bool updated[2] = { };
2563
2564         b43_nphy_stay_in_carrier_search(dev, true);
2565
2566         if (dev->phy.rev >= 4) {
2567                 avoid = nphy->hang_avoid;
2568                 nphy->hang_avoid = 0;
2569         }
2570
2571         b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
2572
2573         for (i = 0; i < 2; i++) {
2574                 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
2575                 gain[i] = params[i].cal_gain;
2576         }
2577
2578         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
2579
2580         b43_nphy_tx_cal_radio_setup(dev);
2581         b43_nphy_tx_cal_phy_setup(dev);
2582
2583         phy6or5x = dev->phy.rev >= 6 ||
2584                 (dev->phy.rev == 5 && nphy->ipa2g_on &&
2585                 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
2586         if (phy6or5x) {
2587                 if (dev->phy.is_40mhz) {
2588                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
2589                                         tbl_tx_iqlo_cal_loft_ladder_40);
2590                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
2591                                         tbl_tx_iqlo_cal_iqimb_ladder_40);
2592                 } else {
2593                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
2594                                         tbl_tx_iqlo_cal_loft_ladder_20);
2595                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
2596                                         tbl_tx_iqlo_cal_iqimb_ladder_20);
2597                 }
2598         }
2599
2600         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
2601
2602         if (!dev->phy.is_40mhz)
2603                 freq = 2500;
2604         else
2605                 freq = 5000;
2606
2607         if (nphy->mphase_cal_phase_id > 2)
2608                 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
2609                                         0xFFFF, 0, true, false);
2610         else
2611                 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
2612
2613         if (error == 0) {
2614                 if (nphy->mphase_cal_phase_id > 2) {
2615                         table = nphy->mphase_txcal_bestcoeffs;
2616                         length = 11;
2617                         if (dev->phy.rev < 3)
2618                                 length -= 2;
2619                 } else {
2620                         if (!full && nphy->txiqlocal_coeffsvalid) {
2621                                 table = nphy->txiqlocal_bestc;
2622                                 length = 11;
2623                                 if (dev->phy.rev < 3)
2624                                         length -= 2;
2625                         } else {
2626                                 full = true;
2627                                 if (dev->phy.rev >= 3) {
2628                                         table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
2629                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
2630                                 } else {
2631                                         table = tbl_tx_iqlo_cal_startcoefs;
2632                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
2633                                 }
2634                         }
2635                 }
2636
2637                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
2638
2639                 if (full) {
2640                         if (dev->phy.rev >= 3)
2641                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
2642                         else
2643                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
2644                 } else {
2645                         if (dev->phy.rev >= 3)
2646                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
2647                         else
2648                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
2649                 }
2650
2651                 if (mphase) {
2652                         count = nphy->mphase_txcal_cmdidx;
2653                         numb = min(max,
2654                                 (u16)(count + nphy->mphase_txcal_numcmds));
2655                 } else {
2656                         count = 0;
2657                         numb = max;
2658                 }
2659
2660                 for (; count < numb; count++) {
2661                         if (full) {
2662                                 if (dev->phy.rev >= 3)
2663                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
2664                                 else
2665                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
2666                         } else {
2667                                 if (dev->phy.rev >= 3)
2668                                         cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
2669                                 else
2670                                         cmd = tbl_tx_iqlo_cal_cmds_recal[count];
2671                         }
2672
2673                         core = (cmd & 0x3000) >> 12;
2674                         type = (cmd & 0x0F00) >> 8;
2675
2676                         if (phy6or5x && updated[core] == 0) {
2677                                 b43_nphy_update_tx_cal_ladder(dev, core);
2678                                 updated[core] = 1;
2679                         }
2680
2681                         tmp = (params[core].ncorr[type] << 8) | 0x66;
2682                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
2683
2684                         if (type == 1 || type == 3 || type == 4) {
2685                                 buffer[0] = b43_ntab_read(dev,
2686                                                 B43_NTAB16(15, 69 + core));
2687                                 diq_start = buffer[0];
2688                                 buffer[0] = 0;
2689                                 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
2690                                                 0);
2691                         }
2692
2693                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
2694                         for (i = 0; i < 2000; i++) {
2695                                 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
2696                                 if (tmp & 0xC000)
2697                                         break;
2698                                 udelay(10);
2699                         }
2700
2701                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2702                                                 buffer);
2703                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
2704                                                 buffer);
2705
2706                         if (type == 1 || type == 3 || type == 4)
2707                                 buffer[0] = diq_start;
2708                 }
2709
2710                 if (mphase)
2711                         nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
2712
2713                 last = (dev->phy.rev < 3) ? 6 : 7;
2714
2715                 if (!mphase || nphy->mphase_cal_phase_id == last) {
2716                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
2717                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
2718                         if (dev->phy.rev < 3) {
2719                                 buffer[0] = 0;
2720                                 buffer[1] = 0;
2721                                 buffer[2] = 0;
2722                                 buffer[3] = 0;
2723                         }
2724                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
2725                                                 buffer);
2726                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 101), 2,
2727                                                 buffer);
2728                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
2729                                                 buffer);
2730                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
2731                                                 buffer);
2732                         length = 11;
2733                         if (dev->phy.rev < 3)
2734                                 length -= 2;
2735                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2736                                                 nphy->txiqlocal_bestc);
2737                         nphy->txiqlocal_coeffsvalid = true;
2738                         /* TODO: Set nphy->txiqlocal_chanspec to
2739                                 the current channel */
2740                 } else {
2741                         length = 11;
2742                         if (dev->phy.rev < 3)
2743                                 length -= 2;
2744                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2745                                                 nphy->mphase_txcal_bestcoeffs);
2746                 }
2747
2748                 b43_nphy_stop_playback(dev);
2749                 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
2750         }
2751
2752         b43_nphy_tx_cal_phy_cleanup(dev);
2753         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
2754
2755         if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
2756                 b43_nphy_tx_iq_workaround(dev);
2757
2758         if (dev->phy.rev >= 4)
2759                 nphy->hang_avoid = avoid;
2760
2761         b43_nphy_stay_in_carrier_search(dev, false);
2762
2763         return error;
2764 }
2765
2766 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
2767 static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
2768 {
2769         struct b43_phy_n *nphy = dev->phy.n;
2770         u8 i;
2771         u16 buffer[7];
2772         bool equal = true;
2773
2774         if (!nphy->txiqlocal_coeffsvalid || 1 /* FIXME */)
2775                 return;
2776
2777         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
2778         for (i = 0; i < 4; i++) {
2779                 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
2780                         equal = false;
2781                         break;
2782                 }
2783         }
2784
2785         if (!equal) {
2786                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
2787                                         nphy->txiqlocal_bestc);
2788                 for (i = 0; i < 4; i++)
2789                         buffer[i] = 0;
2790                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
2791                                         buffer);
2792                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
2793                                         &nphy->txiqlocal_bestc[5]);
2794                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
2795                                         &nphy->txiqlocal_bestc[5]);
2796         }
2797 }
2798
2799 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
2800 static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
2801                         struct nphy_txgains target, u8 type, bool debug)
2802 {
2803         struct b43_phy_n *nphy = dev->phy.n;
2804         int i, j, index;
2805         u8 rfctl[2];
2806         u8 afectl_core;
2807         u16 tmp[6];
2808         u16 cur_hpf1, cur_hpf2, cur_lna;
2809         u32 real, imag;
2810         enum ieee80211_band band;
2811
2812         u8 use;
2813         u16 cur_hpf;
2814         u16 lna[3] = { 3, 3, 1 };
2815         u16 hpf1[3] = { 7, 2, 0 };
2816         u16 hpf2[3] = { 2, 0, 0 };
2817         u32 power[3] = { };
2818         u16 gain_save[2];
2819         u16 cal_gain[2];
2820         struct nphy_iqcal_params cal_params[2];
2821         struct nphy_iq_est est;
2822         int ret = 0;
2823         bool playtone = true;
2824         int desired = 13;
2825
2826         b43_nphy_stay_in_carrier_search(dev, 1);
2827
2828         if (dev->phy.rev < 2)
2829                 b43_nphy_reapply_tx_cal_coeffs(dev);
2830         b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
2831         for (i = 0; i < 2; i++) {
2832                 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
2833                 cal_gain[i] = cal_params[i].cal_gain;
2834         }
2835         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
2836
2837         for (i = 0; i < 2; i++) {
2838                 if (i == 0) {
2839                         rfctl[0] = B43_NPHY_RFCTL_INTC1;
2840                         rfctl[1] = B43_NPHY_RFCTL_INTC2;
2841                         afectl_core = B43_NPHY_AFECTL_C1;
2842                 } else {
2843                         rfctl[0] = B43_NPHY_RFCTL_INTC2;
2844                         rfctl[1] = B43_NPHY_RFCTL_INTC1;
2845                         afectl_core = B43_NPHY_AFECTL_C2;
2846                 }
2847
2848                 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
2849                 tmp[2] = b43_phy_read(dev, afectl_core);
2850                 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2851                 tmp[4] = b43_phy_read(dev, rfctl[0]);
2852                 tmp[5] = b43_phy_read(dev, rfctl[1]);
2853
2854                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
2855                                 (u16)~B43_NPHY_RFSEQCA_RXDIS,
2856                                 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
2857                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
2858                                 (1 - i));
2859                 b43_phy_set(dev, afectl_core, 0x0006);
2860                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
2861
2862                 band = b43_current_band(dev->wl);
2863
2864                 if (nphy->rxcalparams & 0xFF000000) {
2865                         if (band == IEEE80211_BAND_5GHZ)
2866                                 b43_phy_write(dev, rfctl[0], 0x140);
2867                         else
2868                                 b43_phy_write(dev, rfctl[0], 0x110);
2869                 } else {
2870                         if (band == IEEE80211_BAND_5GHZ)
2871                                 b43_phy_write(dev, rfctl[0], 0x180);
2872                         else
2873                                 b43_phy_write(dev, rfctl[0], 0x120);
2874                 }
2875
2876                 if (band == IEEE80211_BAND_5GHZ)
2877                         b43_phy_write(dev, rfctl[1], 0x148);
2878                 else
2879                         b43_phy_write(dev, rfctl[1], 0x114);
2880
2881                 if (nphy->rxcalparams & 0x10000) {
2882                         b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
2883                                         (i + 1));
2884                         b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
2885                                         (2 - i));
2886                 }
2887
2888                 for (j = 0; i < 4; j++) {
2889                         if (j < 3) {
2890                                 cur_lna = lna[j];
2891                                 cur_hpf1 = hpf1[j];
2892                                 cur_hpf2 = hpf2[j];
2893                         } else {
2894                                 if (power[1] > 10000) {
2895                                         use = 1;
2896                                         cur_hpf = cur_hpf1;
2897                                         index = 2;
2898                                 } else {
2899                                         if (power[0] > 10000) {
2900                                                 use = 1;
2901                                                 cur_hpf = cur_hpf1;
2902                                                 index = 1;
2903                                         } else {
2904                                                 index = 0;
2905                                                 use = 2;
2906                                                 cur_hpf = cur_hpf2;
2907                                         }
2908                                 }
2909                                 cur_lna = lna[index];
2910                                 cur_hpf1 = hpf1[index];
2911                                 cur_hpf2 = hpf2[index];
2912                                 cur_hpf += desired - hweight32(power[index]);
2913                                 cur_hpf = clamp_val(cur_hpf, 0, 10);
2914                                 if (use == 1)
2915                                         cur_hpf1 = cur_hpf;
2916                                 else
2917                                         cur_hpf2 = cur_hpf;
2918                         }
2919
2920                         tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
2921                                         (cur_lna << 2));
2922                         b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3,
2923                                                                         false);
2924                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
2925                         b43_nphy_stop_playback(dev);
2926
2927                         if (playtone) {
2928                                 ret = b43_nphy_tx_tone(dev, 4000,
2929                                                 (nphy->rxcalparams & 0xFFFF),
2930                                                 false, false);
2931                                 playtone = false;
2932                         } else {
2933                                 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
2934                                                         false, false);
2935                         }
2936
2937                         if (ret == 0) {
2938                                 if (j < 3) {
2939                                         b43_nphy_rx_iq_est(dev, &est, 1024, 32,
2940                                                                         false);
2941                                         if (i == 0) {
2942                                                 real = est.i0_pwr;
2943                                                 imag = est.q0_pwr;
2944                                         } else {
2945                                                 real = est.i1_pwr;
2946                                                 imag = est.q1_pwr;
2947                                         }
2948                                         power[i] = ((real + imag) / 1024) + 1;
2949                                 } else {
2950                                         b43_nphy_calc_rx_iq_comp(dev, 1 << i);
2951                                 }
2952                                 b43_nphy_stop_playback(dev);
2953                         }
2954
2955                         if (ret != 0)
2956                                 break;
2957                 }
2958
2959                 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
2960                 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
2961                 b43_phy_write(dev, rfctl[1], tmp[5]);
2962                 b43_phy_write(dev, rfctl[0], tmp[4]);
2963                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
2964                 b43_phy_write(dev, afectl_core, tmp[2]);
2965                 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
2966
2967                 if (ret != 0)
2968                         break;
2969         }
2970
2971         b43_nphy_rf_control_override(dev, 0x400, 0, 3, true);
2972         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
2973         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
2974
2975         b43_nphy_stay_in_carrier_search(dev, 0);
2976
2977         return ret;
2978 }
2979
2980 static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
2981                         struct nphy_txgains target, u8 type, bool debug)
2982 {
2983         return -1;
2984 }
2985
2986 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
2987 static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
2988                         struct nphy_txgains target, u8 type, bool debug)
2989 {
2990         if (dev->phy.rev >= 3)
2991                 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
2992         else
2993                 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
2994 }
2995
2996 /*
2997  * Init N-PHY
2998  * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
2999  */
3000 int b43_phy_initn(struct b43_wldev *dev)
3001 {
3002         struct ssb_bus *bus = dev->dev->bus;
3003         struct b43_phy *phy = &dev->phy;
3004         struct b43_phy_n *nphy = phy->n;
3005         u8 tx_pwr_state;
3006         struct nphy_txgains target;
3007         u16 tmp;
3008         enum ieee80211_band tmp2;
3009         bool do_rssi_cal;
3010
3011         u16 clip[2];
3012         bool do_cal = false;
3013
3014         if ((dev->phy.rev >= 3) &&
3015            (bus->sprom.boardflags_lo & B43_BFL_EXTLNA) &&
3016            (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
3017                 chipco_set32(&dev->dev->bus->chipco, SSB_CHIPCO_CHIPCTL, 0x40);
3018         }
3019         nphy->deaf_count = 0;
3020         b43_nphy_tables_init(dev);
3021         nphy->crsminpwr_adjusted = false;
3022         nphy->noisevars_adjusted = false;
3023
3024         /* Clear all overrides */
3025         if (dev->phy.rev >= 3) {
3026                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
3027                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3028                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
3029                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
3030         } else {
3031                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3032         }
3033         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
3034         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
3035         if (dev->phy.rev < 6) {
3036                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
3037                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
3038         }
3039         b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
3040                      ~(B43_NPHY_RFSEQMODE_CAOVER |
3041                        B43_NPHY_RFSEQMODE_TROVER));
3042         if (dev->phy.rev >= 3)
3043                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
3044         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
3045
3046         if (dev->phy.rev <= 2) {
3047                 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
3048                 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3049                                 ~B43_NPHY_BPHY_CTL3_SCALE,
3050                                 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
3051         }
3052         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
3053         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
3054
3055         if (bus->sprom.boardflags2_lo & 0x100 ||
3056             (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3057              bus->boardinfo.type == 0x8B))
3058                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
3059         else
3060                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
3061         b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
3062         b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
3063         b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
3064
3065         b43_nphy_update_mimo_config(dev, nphy->preamble_override);
3066         b43_nphy_update_txrx_chain(dev);
3067
3068         if (phy->rev < 2) {
3069                 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
3070                 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
3071         }
3072
3073         tmp2 = b43_current_band(dev->wl);
3074         if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) ||
3075             (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) {
3076                 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
3077                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
3078                                 nphy->papd_epsilon_offset[0] << 7);
3079                 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
3080                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
3081                                 nphy->papd_epsilon_offset[1] << 7);
3082                 b43_nphy_int_pa_set_tx_dig_filters(dev);
3083         } else if (phy->rev >= 5) {
3084                 b43_nphy_ext_pa_set_tx_dig_filters(dev);
3085         }
3086
3087         b43_nphy_workarounds(dev);
3088
3089         /* Reset CCA, in init code it differs a little from standard way */
3090         b43_nphy_bmac_clock_fgc(dev, 1);
3091         tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
3092         b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
3093         b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
3094         b43_nphy_bmac_clock_fgc(dev, 0);
3095
3096         /* TODO N PHY MAC PHY Clock Set with argument 1 */
3097
3098         b43_nphy_pa_override(dev, false);
3099         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
3100         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3101         b43_nphy_pa_override(dev, true);
3102
3103         b43_nphy_classifier(dev, 0, 0);
3104         b43_nphy_read_clip_detection(dev, clip);
3105         tx_pwr_state = nphy->txpwrctrl;
3106         /* TODO N PHY TX power control with argument 0
3107                 (turning off power control) */
3108         /* TODO Fix the TX Power Settings */
3109         /* TODO N PHY TX Power Control Idle TSSI */
3110         /* TODO N PHY TX Power Control Setup */
3111
3112         if (phy->rev >= 3) {
3113                 /* TODO */
3114         } else {
3115                 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128,
3116                                         b43_ntab_tx_gain_rev0_1_2);
3117                 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128,
3118                                         b43_ntab_tx_gain_rev0_1_2);
3119         }
3120
3121         if (nphy->phyrxchain != 3)
3122                 ;/* TODO N PHY RX Core Set State with phyrxchain as argument */
3123         if (nphy->mphase_cal_phase_id > 0)
3124                 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
3125
3126         do_rssi_cal = false;
3127         if (phy->rev >= 3) {
3128                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3129                         do_rssi_cal = (nphy->rssical_chanspec_2G == 0);
3130                 else
3131                         do_rssi_cal = (nphy->rssical_chanspec_5G == 0);
3132
3133                 if (do_rssi_cal)
3134                         b43_nphy_rssi_cal(dev);
3135                 else
3136                         b43_nphy_restore_rssi_cal(dev);
3137         } else {
3138                 b43_nphy_rssi_cal(dev);
3139         }
3140
3141         if (!((nphy->measure_hold & 0x6) != 0)) {
3142                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3143                         do_cal = (nphy->iqcal_chanspec_2G == 0);
3144                 else
3145                         do_cal = (nphy->iqcal_chanspec_5G == 0);
3146
3147                 if (nphy->mute)
3148                         do_cal = false;
3149
3150                 if (do_cal) {
3151                         target = b43_nphy_get_tx_gains(dev);
3152
3153                         if (nphy->antsel_type == 2)
3154                                 b43_nphy_superswitch_init(dev, true);
3155                         if (nphy->perical != 2) {
3156                                 b43_nphy_rssi_cal(dev);
3157                                 if (phy->rev >= 3) {
3158                                         nphy->cal_orig_pwr_idx[0] =
3159                                             nphy->txpwrindex[0].index_internal;
3160                                         nphy->cal_orig_pwr_idx[1] =
3161                                             nphy->txpwrindex[1].index_internal;
3162                                         /* TODO N PHY Pre Calibrate TX Gain */
3163                                         target = b43_nphy_get_tx_gains(dev);
3164                                 }
3165                         }
3166                 }
3167         }
3168
3169         if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false)) {
3170                 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
3171                         b43_nphy_save_cal(dev);
3172                 else if (nphy->mphase_cal_phase_id == 0)
3173                         ;/* N PHY Periodic Calibration with argument 3 */
3174         } else {
3175                 b43_nphy_restore_cal(dev);
3176         }
3177
3178         b43_nphy_tx_pwr_ctrl_coef_setup(dev);
3179         /* TODO N PHY TX Power Control Enable with argument tx_pwr_state */
3180         b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
3181         b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
3182         if (phy->rev >= 3 && phy->rev <= 6)
3183                 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
3184         b43_nphy_tx_lp_fbw(dev);
3185         if (phy->rev >= 3)
3186                 b43_nphy_spur_workaround(dev);
3187
3188         b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n");
3189         return 0;
3190 }
3191
3192 static int b43_nphy_op_allocate(struct b43_wldev *dev)
3193 {
3194         struct b43_phy_n *nphy;
3195
3196         nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
3197         if (!nphy)
3198                 return -ENOMEM;
3199         dev->phy.n = nphy;
3200
3201         return 0;
3202 }
3203
3204 static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
3205 {
3206         struct b43_phy *phy = &dev->phy;
3207         struct b43_phy_n *nphy = phy->n;
3208
3209         memset(nphy, 0, sizeof(*nphy));
3210
3211         //TODO init struct b43_phy_n
3212 }
3213
3214 static void b43_nphy_op_free(struct b43_wldev *dev)
3215 {
3216         struct b43_phy *phy = &dev->phy;
3217         struct b43_phy_n *nphy = phy->n;
3218
3219         kfree(nphy);
3220         phy->n = NULL;
3221 }
3222
3223 static int b43_nphy_op_init(struct b43_wldev *dev)
3224 {
3225         return b43_phy_initn(dev);
3226 }
3227
3228 static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
3229 {
3230 #if B43_DEBUG
3231         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
3232                 /* OFDM registers are onnly available on A/G-PHYs */
3233                 b43err(dev->wl, "Invalid OFDM PHY access at "
3234                        "0x%04X on N-PHY\n", offset);
3235                 dump_stack();
3236         }
3237         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
3238                 /* Ext-G registers are only available on G-PHYs */
3239                 b43err(dev->wl, "Invalid EXT-G PHY access at "
3240                        "0x%04X on N-PHY\n", offset);
3241                 dump_stack();
3242         }
3243 #endif /* B43_DEBUG */
3244 }
3245
3246 static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
3247 {
3248         check_phyreg(dev, reg);
3249         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3250         return b43_read16(dev, B43_MMIO_PHY_DATA);
3251 }
3252
3253 static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
3254 {
3255         check_phyreg(dev, reg);
3256         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3257         b43_write16(dev, B43_MMIO_PHY_DATA, value);
3258 }
3259
3260 static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
3261 {
3262         /* Register 1 is a 32-bit register. */
3263         B43_WARN_ON(reg == 1);
3264         /* N-PHY needs 0x100 for read access */
3265         reg |= 0x100;
3266
3267         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
3268         return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3269 }
3270
3271 static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
3272 {
3273         /* Register 1 is a 32-bit register. */
3274         B43_WARN_ON(reg == 1);
3275
3276         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
3277         b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
3278 }
3279
3280 static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
3281                                         bool blocked)
3282 {//TODO
3283 }
3284
3285 static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
3286 {
3287         b43_phy_write(dev, B43_NPHY_AFECTL_OVER,
3288                       on ? 0 : 0x7FFF);
3289 }
3290
3291 static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
3292                                       unsigned int new_channel)
3293 {
3294         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3295                 if ((new_channel < 1) || (new_channel > 14))
3296                         return -EINVAL;
3297         } else {
3298                 if (new_channel > 200)
3299                         return -EINVAL;
3300         }
3301
3302         return nphy_channel_switch(dev, new_channel);
3303 }
3304
3305 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
3306 {
3307         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3308                 return 1;
3309         return 36;
3310 }
3311
3312 const struct b43_phy_operations b43_phyops_n = {
3313         .allocate               = b43_nphy_op_allocate,
3314         .free                   = b43_nphy_op_free,
3315         .prepare_structs        = b43_nphy_op_prepare_structs,
3316         .init                   = b43_nphy_op_init,
3317         .phy_read               = b43_nphy_op_read,
3318         .phy_write              = b43_nphy_op_write,
3319         .radio_read             = b43_nphy_op_radio_read,
3320         .radio_write            = b43_nphy_op_radio_write,
3321         .software_rfkill        = b43_nphy_op_software_rfkill,
3322         .switch_analog          = b43_nphy_op_switch_analog,
3323         .switch_channel         = b43_nphy_op_switch_channel,
3324         .get_default_chan       = b43_nphy_op_get_default_chan,
3325         .recalc_txpower         = b43_nphy_op_recalc_txpower,
3326         .adjust_txpower         = b43_nphy_op_adjust_txpower,
3327 };