2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/types.h>
18 #include <linux/kernel.h>
19 #include <linux/kthread.h>
20 #include <linux/printk.h>
21 #include <linux/pci_ids.h>
22 #include <linux/netdevice.h>
23 #include <linux/interrupt.h>
24 #include <linux/sched.h>
25 #include <linux/mmc/sdio.h>
26 #include <linux/mmc/sdio_ids.h>
27 #include <linux/mmc/sdio_func.h>
28 #include <linux/mmc/card.h>
29 #include <linux/semaphore.h>
30 #include <linux/firmware.h>
31 #include <linux/module.h>
32 #include <linux/bcma/bcma.h>
33 #include <linux/debugfs.h>
34 #include <linux/vmalloc.h>
35 #include <linux/platform_data/brcmfmac-sdio.h>
36 #include <linux/moduleparam.h>
37 #include <asm/unaligned.h>
39 #include <brcmu_wifi.h>
40 #include <brcmu_utils.h>
41 #include <brcm_hw_ids.h>
47 #define DCMD_RESP_TIMEOUT 2000 /* In milli second */
48 #define CTL_DONE_TIMEOUT 2000 /* In milli second */
52 #define BRCMF_TRAP_INFO_SIZE 80
54 #define CBUF_LEN (128)
56 /* Device console log buffer state */
57 #define CONSOLE_BUFFER_MAX 2024
60 __le32 buf; /* Can't be pointer on (64-bit) hosts */
63 char *_buf_compat; /* Redundant pointer for backward compat. */
68 * When there is no UART (e.g. Quickturn),
69 * the host should write a complete
70 * input line directly into cbuf and then write
71 * the length into vcons_in.
72 * This may also be used when there is a real UART
73 * (at risk of conflicting with
74 * the real UART). vcons_out is currently unused.
79 /* Output (logging) buffer
80 * Console output is written to a ring buffer log_buf at index log_idx.
81 * The host may read the output when it sees log_idx advance.
82 * Output will be lost if the output wraps around faster than the host
85 struct rte_log_le log_le;
87 /* Console input line buffer
88 * Characters are read one at a time into cbuf
89 * until <CR> is received, then
90 * the buffer is processed as a command line.
91 * Also used for virtual UART.
98 #include <chipcommon.h>
102 #include "tracepoint.h"
104 #define TXQLEN 2048 /* bulk tx queue length */
105 #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */
106 #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */
109 #define TXRETRIES 2 /* # of retries for tx frames */
111 #define BRCMF_RXBOUND 50 /* Default for max rx frames in
114 #define BRCMF_TXBOUND 20 /* Default for max tx frames in
117 #define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */
119 #define MEMBLOCK 2048 /* Block size used for downloading
121 #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
122 biggest possible glom */
124 #define BRCMF_FIRSTREAD (1 << 6)
127 /* SBSDIO_DEVICE_CTL */
129 /* 1: device will assert busy signal when receiving CMD53 */
130 #define SBSDIO_DEVCTL_SETBUSY 0x01
131 /* 1: assertion of sdio interrupt is synchronous to the sdio clock */
132 #define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02
133 /* 1: mask all interrupts to host except the chipActive (rev 8) */
134 #define SBSDIO_DEVCTL_CA_INT_ONLY 0x04
135 /* 1: isolate internal sdio signals, put external pads in tri-state; requires
136 * sdio bus power cycle to clear (rev 9) */
137 #define SBSDIO_DEVCTL_PADS_ISO 0x08
138 /* Force SD->SB reset mapping (rev 11) */
139 #define SBSDIO_DEVCTL_SB_RST_CTL 0x30
140 /* Determined by CoreControl bit */
141 #define SBSDIO_DEVCTL_RST_CORECTL 0x00
142 /* Force backplane reset */
143 #define SBSDIO_DEVCTL_RST_BPRESET 0x10
144 /* Force no backplane reset */
145 #define SBSDIO_DEVCTL_RST_NOBPRESET 0x20
147 /* direct(mapped) cis space */
149 /* MAPPED common CIS address */
150 #define SBSDIO_CIS_BASE_COMMON 0x1000
151 /* maximum bytes in one CIS */
152 #define SBSDIO_CIS_SIZE_LIMIT 0x200
153 /* cis offset addr is < 17 bits */
154 #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF
156 /* manfid tuple length, include tuple, link bytes */
157 #define SBSDIO_CIS_MANFID_TUPLE_LEN 6
159 #define CORE_BUS_REG(base, field) \
160 (base + offsetof(struct sdpcmd_regs, field))
162 /* SDIO function 1 register CHIPCLKCSR */
163 /* Force ALP request to backplane */
164 #define SBSDIO_FORCE_ALP 0x01
165 /* Force HT request to backplane */
166 #define SBSDIO_FORCE_HT 0x02
167 /* Force ILP request to backplane */
168 #define SBSDIO_FORCE_ILP 0x04
169 /* Make ALP ready (power up xtal) */
170 #define SBSDIO_ALP_AVAIL_REQ 0x08
171 /* Make HT ready (power up PLL) */
172 #define SBSDIO_HT_AVAIL_REQ 0x10
173 /* Squelch clock requests from HW */
174 #define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20
175 /* Status: ALP is ready */
176 #define SBSDIO_ALP_AVAIL 0x40
177 /* Status: HT is ready */
178 #define SBSDIO_HT_AVAIL 0x80
179 #define SBSDIO_CSR_MASK 0x1F
180 #define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL)
181 #define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS)
182 #define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
183 #define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
184 #define SBSDIO_CLKAV(regval, alponly) \
185 (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval)))
188 #define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */
189 #define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */
190 #define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */
191 #define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */
192 #define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */
193 #define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */
194 #define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */
195 #define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */
196 #define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */
197 #define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */
198 #define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */
199 #define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */
200 #define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */
201 #define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */
202 #define I_PC (1 << 10) /* descriptor error */
203 #define I_PD (1 << 11) /* data error */
204 #define I_DE (1 << 12) /* Descriptor protocol Error */
205 #define I_RU (1 << 13) /* Receive descriptor Underflow */
206 #define I_RO (1 << 14) /* Receive fifo Overflow */
207 #define I_XU (1 << 15) /* Transmit fifo Underflow */
208 #define I_RI (1 << 16) /* Receive Interrupt */
209 #define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */
210 #define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */
211 #define I_XI (1 << 24) /* Transmit Interrupt */
212 #define I_RF_TERM (1 << 25) /* Read Frame Terminate */
213 #define I_WF_TERM (1 << 26) /* Write Frame Terminate */
214 #define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */
215 #define I_SBINT (1 << 28) /* sbintstatus Interrupt */
216 #define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */
217 #define I_SRESET (1 << 30) /* CCCR RES interrupt */
218 #define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */
219 #define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU)
220 #define I_DMA (I_RI | I_XI | I_ERRORS)
223 #define CC_CISRDY (1 << 0) /* CIS Ready */
224 #define CC_BPRESEN (1 << 1) /* CCCR RES signal */
225 #define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */
226 #define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */
227 #define CC_XMTDATAAVAIL_MODE (1 << 4)
228 #define CC_XMTDATAAVAIL_CTRL (1 << 5)
231 #define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */
232 #define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */
233 #define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */
234 #define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */
237 * Software allocation of To SB Mailbox resources
240 /* tosbmailbox bits corresponding to intstatus bits */
241 #define SMB_NAK (1 << 0) /* Frame NAK */
242 #define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */
243 #define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */
244 #define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */
246 /* tosbmailboxdata */
247 #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */
250 * Software allocation of To Host Mailbox resources
254 #define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */
255 #define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */
256 #define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */
257 #define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */
259 /* tohostmailboxdata */
260 #define HMB_DATA_NAKHANDLED 1 /* retransmit NAK'd frame */
261 #define HMB_DATA_DEVREADY 2 /* talk to host after enable */
262 #define HMB_DATA_FC 4 /* per prio flowcontrol update flag */
263 #define HMB_DATA_FWREADY 8 /* fw ready for protocol activity */
265 #define HMB_DATA_FCDATA_MASK 0xff000000
266 #define HMB_DATA_FCDATA_SHIFT 24
268 #define HMB_DATA_VERSION_MASK 0x00ff0000
269 #define HMB_DATA_VERSION_SHIFT 16
272 * Software-defined protocol header
275 /* Current protocol version */
276 #define SDPCM_PROT_VERSION 4
279 * Shared structure between dongle and the host.
280 * The structure contains pointers to trap or assert information.
282 #define SDPCM_SHARED_VERSION 0x0003
283 #define SDPCM_SHARED_VERSION_MASK 0x00FF
284 #define SDPCM_SHARED_ASSERT_BUILT 0x0100
285 #define SDPCM_SHARED_ASSERT 0x0200
286 #define SDPCM_SHARED_TRAP 0x0400
288 /* Space for header read, limit for data packets */
289 #define MAX_HDR_READ (1 << 6)
290 #define MAX_RX_DATASZ 2048
292 /* Bump up limit on waiting for HT to account for first startup;
293 * if the image is doing a CRC calculation before programming the PMU
294 * for HT availability, it could take a couple hundred ms more, so
295 * max out at a 1 second (1000000us).
297 #undef PMU_MAX_TRANSITION_DLY
298 #define PMU_MAX_TRANSITION_DLY 1000000
300 /* Value for ChipClockCSR during initial setup */
301 #define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
302 SBSDIO_ALP_AVAIL_REQ)
304 /* Flags for SDH calls */
305 #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
307 #define BRCMF_IDLE_ACTIVE 0 /* Do not request any SD clock change
310 #define BRCMF_IDLE_INTERVAL 1
312 #define KSO_WAIT_US 50
313 #define MAX_KSO_ATTEMPTS (PMU_MAX_TRANSITION_DLY/KSO_WAIT_US)
316 * Conversion of 802.1D priority to precedence level
318 static uint prio2prec(u32 prio)
320 return (prio == PRIO_8021D_NONE || prio == PRIO_8021D_BE) ?
325 /* Device console log buffer state */
326 struct brcmf_console {
327 uint count; /* Poll interval msec counter */
328 uint log_addr; /* Log struct address (fixed) */
329 struct rte_log_le log_le; /* Log struct (host copy) */
330 uint bufsize; /* Size of log buffer */
331 u8 *buf; /* Log buffer (host copy) */
332 uint last; /* Last buffer read index */
335 struct brcmf_trap_info {
349 __le32 r9; /* sb/v6 */
350 __le32 r10; /* sl/v7 */
351 __le32 r11; /* fp/v8 */
359 struct sdpcm_shared {
363 u32 assert_file_addr;
365 u32 console_addr; /* Address of struct rte_console */
371 struct sdpcm_shared_le {
374 __le32 assert_exp_addr;
375 __le32 assert_file_addr;
377 __le32 console_addr; /* Address of struct rte_console */
378 __le32 msgtrace_addr;
383 /* dongle SDIO bus specific header info */
384 struct brcmf_sdio_hdrinfo {
396 * hold counter variables
398 struct brcmf_sdio_count {
399 uint intrcount; /* Count of device interrupt callbacks */
400 uint lastintrs; /* Count as of last watchdog timer */
401 uint pollcnt; /* Count of active polls */
402 uint regfails; /* Count of R_REG failures */
403 uint tx_sderrs; /* Count of tx attempts with sd errors */
404 uint fcqueued; /* Tx packets that got queued */
405 uint rxrtx; /* Count of rtx requests (NAK to dongle) */
406 uint rx_toolong; /* Receive frames too long to receive */
407 uint rxc_errors; /* SDIO errors when reading control frames */
408 uint rx_hdrfail; /* SDIO errors on header reads */
409 uint rx_badhdr; /* Bad received headers (roosync?) */
410 uint rx_badseq; /* Mismatched rx sequence number */
411 uint fc_rcvd; /* Number of flow-control events received */
412 uint fc_xoff; /* Number which turned on flow-control */
413 uint fc_xon; /* Number which turned off flow-control */
414 uint rxglomfail; /* Failed deglom attempts */
415 uint rxglomframes; /* Number of glom frames (superframes) */
416 uint rxglompkts; /* Number of packets from glom frames */
417 uint f2rxhdrs; /* Number of header reads */
418 uint f2rxdata; /* Number of frame data reads */
419 uint f2txdata; /* Number of f2 frame writes */
420 uint f1regdata; /* Number of f1 register accesses */
421 uint tickcnt; /* Number of watchdog been schedule */
422 ulong tx_ctlerrs; /* Err of sending ctrl frames */
423 ulong tx_ctlpkts; /* Ctrl frames sent to dongle */
424 ulong rx_ctlerrs; /* Err of processing rx ctrl frames */
425 ulong rx_ctlpkts; /* Ctrl frames processed from dongle */
426 ulong rx_readahead_cnt; /* packets where header read-ahead was used */
429 /* misc chip info needed by some of the routines */
430 /* Private data for SDIO bus interaction */
432 struct brcmf_sdio_dev *sdiodev; /* sdio device handler */
433 struct brcmf_chip *ci; /* Chip info struct */
435 u32 hostintmask; /* Copy of Host Interrupt Mask */
436 atomic_t intstatus; /* Intstatus bits (events) pending */
437 atomic_t fcstate; /* State of dongle flow-control */
439 uint blocksize; /* Block size of SDIO transfers */
440 uint roundup; /* Max roundup limit */
442 struct pktq txq; /* Queue length used for flow-control */
443 u8 flowcontrol; /* per prio flow control bitmask */
444 u8 tx_seq; /* Transmit sequence number (next) */
445 u8 tx_max; /* Maximum transmit sequence allowed */
447 u8 *hdrbuf; /* buffer for handling rx frame */
448 u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
449 u8 rx_seq; /* Receive sequence number (expected) */
450 struct brcmf_sdio_hdrinfo cur_read;
451 /* info of current read frame */
452 bool rxskip; /* Skip receive (awaiting NAK ACK) */
453 bool rxpending; /* Data frame pending in dongle */
455 uint rxbound; /* Rx frames to read before resched */
456 uint txbound; /* Tx frames to send before resched */
459 struct sk_buff *glomd; /* Packet containing glomming descriptor */
460 struct sk_buff_head glom; /* Packet list for glommed superframe */
461 uint glomerr; /* Glom packet read errors */
463 u8 *rxbuf; /* Buffer for receiving control packets */
464 uint rxblen; /* Allocated length of rxbuf */
465 u8 *rxctl; /* Aligned pointer into rxbuf */
466 u8 *rxctl_orig; /* pointer for freeing rxctl */
467 uint rxlen; /* Length of valid data in buffer */
468 spinlock_t rxctl_lock; /* protection lock for ctrl frame resources */
470 u8 sdpcm_ver; /* Bus protocol reported by dongle */
472 bool intr; /* Use interrupts */
473 bool poll; /* Use polling */
474 atomic_t ipend; /* Device interrupt is pending */
475 uint spurious; /* Count of spurious interrupts */
476 uint pollrate; /* Ticks between device polls */
477 uint polltick; /* Tick counter */
480 uint console_interval;
481 struct brcmf_console console; /* Console output polling support */
482 uint console_addr; /* Console address from shared struct */
485 uint clkstate; /* State of sd and backplane clock(s) */
486 s32 idletime; /* Control for activity timeout */
487 s32 idlecount; /* Activity timeout counter */
488 s32 idleclock; /* How to set bus driver when idle */
489 bool rxflow_mode; /* Rx flow control mode */
490 bool rxflow; /* Is rx flow control on */
491 bool alp_only; /* Don't use HT clock (ALP only) */
495 bool ctrl_frame_stat;
498 spinlock_t txq_lock; /* protect bus->txq */
499 wait_queue_head_t ctrl_wait;
500 wait_queue_head_t dcmd_resp_wait;
502 struct timer_list timer;
503 struct completion watchdog_wait;
504 struct task_struct *watchdog_tsk;
508 struct workqueue_struct *brcmf_wq;
509 struct work_struct datawork;
511 atomic_t dpc_running;
513 bool txoff; /* Transmit flow-controlled */
514 struct brcmf_sdio_count sdcnt;
515 bool sr_enabled; /* SaveRestore enabled */
518 u8 tx_hdrlen; /* sdio bus header length for tx packet */
519 bool txglom; /* host tx glomming enable flag */
520 u16 head_align; /* buffer pointer alignment */
521 u16 sgentry_align; /* scatter-gather buffer alignment */
527 #define CLK_PENDING 2
531 static int qcount[NUMPRIO];
534 #define DEFAULT_SDIO_DRIVE_STRENGTH 6 /* in milliamps */
536 #define RETRYCHAN(chan) ((chan) == SDPCM_EVENT_CHANNEL)
538 /* Retry count for register access failures */
539 static const uint retry_limit = 2;
541 /* Limit on rounding up frames */
542 static const uint max_roundup = 512;
546 enum brcmf_sdio_frmtype {
547 BRCMF_SDIO_FT_NORMAL,
552 #define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu))
554 /* SDIO Pad drive strength to select value mappings */
555 struct sdiod_drive_str {
556 u8 strength; /* Pad Drive Strength in mA */
557 u8 sel; /* Chip-specific select value */
560 /* SDIO Drive Strength to sel value table for PMU Rev 11 (1.8V) */
561 static const struct sdiod_drive_str sdiod_drvstr_tab1_1v8[] = {
572 /* SDIO Drive Strength to sel value table for PMU Rev 13 (1.8v) */
573 static const struct sdiod_drive_str sdiod_drive_strength_tab5_1v8[] = {
583 /* SDIO Drive Strength to sel value table for PMU Rev 17 (1.8v) */
584 static const struct sdiod_drive_str sdiod_drvstr_tab6_1v8[] = {
590 /* SDIO Drive Strength to sel value table for 43143 PMU Rev 17 (3.3V) */
591 static const struct sdiod_drive_str sdiod_drvstr_tab2_3v3[] = {
598 #define BCM43143_FIRMWARE_NAME "brcm/brcmfmac43143-sdio.bin"
599 #define BCM43143_NVRAM_NAME "brcm/brcmfmac43143-sdio.txt"
600 #define BCM43241B0_FIRMWARE_NAME "brcm/brcmfmac43241b0-sdio.bin"
601 #define BCM43241B0_NVRAM_NAME "brcm/brcmfmac43241b0-sdio.txt"
602 #define BCM43241B4_FIRMWARE_NAME "brcm/brcmfmac43241b4-sdio.bin"
603 #define BCM43241B4_NVRAM_NAME "brcm/brcmfmac43241b4-sdio.txt"
604 #define BCM4329_FIRMWARE_NAME "brcm/brcmfmac4329-sdio.bin"
605 #define BCM4329_NVRAM_NAME "brcm/brcmfmac4329-sdio.txt"
606 #define BCM4330_FIRMWARE_NAME "brcm/brcmfmac4330-sdio.bin"
607 #define BCM4330_NVRAM_NAME "brcm/brcmfmac4330-sdio.txt"
608 #define BCM4334_FIRMWARE_NAME "brcm/brcmfmac4334-sdio.bin"
609 #define BCM4334_NVRAM_NAME "brcm/brcmfmac4334-sdio.txt"
610 #define BCM43340_FIRMWARE_NAME "brcm/brcmfmac43340-sdio.bin"
611 #define BCM43340_NVRAM_NAME "brcm/brcmfmac43340-sdio.txt"
612 #define BCM4335_FIRMWARE_NAME "brcm/brcmfmac4335-sdio.bin"
613 #define BCM4335_NVRAM_NAME "brcm/brcmfmac4335-sdio.txt"
614 #define BCM43362_FIRMWARE_NAME "brcm/brcmfmac43362-sdio.bin"
615 #define BCM43362_NVRAM_NAME "brcm/brcmfmac43362-sdio.txt"
616 #define BCM4339_FIRMWARE_NAME "brcm/brcmfmac4339-sdio.bin"
617 #define BCM4339_NVRAM_NAME "brcm/brcmfmac4339-sdio.txt"
618 #define BCM4345_FIRMWARE_NAME "brcm/brcmfmac4345-sdio.bin"
619 #define BCM4345_NVRAM_NAME "brcm/brcmfmac4345-sdio.txt"
620 #define BCM4354_FIRMWARE_NAME "brcm/brcmfmac4354-sdio.bin"
621 #define BCM4354_NVRAM_NAME "brcm/brcmfmac4354-sdio.txt"
623 MODULE_FIRMWARE(BCM43143_FIRMWARE_NAME);
624 MODULE_FIRMWARE(BCM43143_NVRAM_NAME);
625 MODULE_FIRMWARE(BCM43241B0_FIRMWARE_NAME);
626 MODULE_FIRMWARE(BCM43241B0_NVRAM_NAME);
627 MODULE_FIRMWARE(BCM43241B4_FIRMWARE_NAME);
628 MODULE_FIRMWARE(BCM43241B4_NVRAM_NAME);
629 MODULE_FIRMWARE(BCM4329_FIRMWARE_NAME);
630 MODULE_FIRMWARE(BCM4329_NVRAM_NAME);
631 MODULE_FIRMWARE(BCM4330_FIRMWARE_NAME);
632 MODULE_FIRMWARE(BCM4330_NVRAM_NAME);
633 MODULE_FIRMWARE(BCM4334_FIRMWARE_NAME);
634 MODULE_FIRMWARE(BCM4334_NVRAM_NAME);
635 MODULE_FIRMWARE(BCM43340_FIRMWARE_NAME);
636 MODULE_FIRMWARE(BCM43340_NVRAM_NAME);
637 MODULE_FIRMWARE(BCM4335_FIRMWARE_NAME);
638 MODULE_FIRMWARE(BCM4335_NVRAM_NAME);
639 MODULE_FIRMWARE(BCM43362_FIRMWARE_NAME);
640 MODULE_FIRMWARE(BCM43362_NVRAM_NAME);
641 MODULE_FIRMWARE(BCM4339_FIRMWARE_NAME);
642 MODULE_FIRMWARE(BCM4339_NVRAM_NAME);
643 MODULE_FIRMWARE(BCM4345_FIRMWARE_NAME);
644 MODULE_FIRMWARE(BCM4345_NVRAM_NAME);
645 MODULE_FIRMWARE(BCM4354_FIRMWARE_NAME);
646 MODULE_FIRMWARE(BCM4354_NVRAM_NAME);
648 struct brcmf_firmware_names {
655 enum brcmf_firmware_type {
660 #define BRCMF_FIRMWARE_NVRAM(name) \
661 name ## _FIRMWARE_NAME, name ## _NVRAM_NAME
663 static const struct brcmf_firmware_names brcmf_fwname_data[] = {
664 { BRCM_CC_43143_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM43143) },
665 { BRCM_CC_43241_CHIP_ID, 0x0000001F, BRCMF_FIRMWARE_NVRAM(BCM43241B0) },
666 { BRCM_CC_43241_CHIP_ID, 0xFFFFFFE0, BRCMF_FIRMWARE_NVRAM(BCM43241B4) },
667 { BRCM_CC_4329_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4329) },
668 { BRCM_CC_4330_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4330) },
669 { BRCM_CC_4334_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4334) },
670 { BRCM_CC_43340_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM43340) },
671 { BRCM_CC_4335_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4335) },
672 { BRCM_CC_43362_CHIP_ID, 0xFFFFFFFE, BRCMF_FIRMWARE_NVRAM(BCM43362) },
673 { BRCM_CC_4339_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4339) },
674 { BRCM_CC_4345_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4345) },
675 { BRCM_CC_4354_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4354) }
678 static int brcmf_sdio_get_fwnames(struct brcmf_chip *ci,
679 struct brcmf_sdio_dev *sdiodev)
684 for (i = 0; i < ARRAY_SIZE(brcmf_fwname_data); i++) {
685 if (brcmf_fwname_data[i].chipid == ci->chip &&
686 brcmf_fwname_data[i].revmsk & BIT(ci->chiprev))
690 if (i == ARRAY_SIZE(brcmf_fwname_data)) {
691 brcmf_err("Unknown chipid %d [%d]\n", ci->chip, ci->chiprev);
695 /* check if firmware path is provided by module parameter */
696 if (brcmf_firmware_path[0] != '\0') {
697 strlcpy(sdiodev->fw_name, brcmf_firmware_path,
698 sizeof(sdiodev->fw_name));
699 strlcpy(sdiodev->nvram_name, brcmf_firmware_path,
700 sizeof(sdiodev->nvram_name));
702 end = brcmf_firmware_path[strlen(brcmf_firmware_path) - 1];
704 strlcat(sdiodev->fw_name, "/",
705 sizeof(sdiodev->fw_name));
706 strlcat(sdiodev->nvram_name, "/",
707 sizeof(sdiodev->nvram_name));
710 strlcat(sdiodev->fw_name, brcmf_fwname_data[i].bin,
711 sizeof(sdiodev->fw_name));
712 strlcat(sdiodev->nvram_name, brcmf_fwname_data[i].nv,
713 sizeof(sdiodev->nvram_name));
718 static void pkt_align(struct sk_buff *p, int len, int align)
721 datalign = (unsigned long)(p->data);
722 datalign = roundup(datalign, (align)) - datalign;
724 skb_pull(p, datalign);
728 /* To check if there's window offered */
729 static bool data_ok(struct brcmf_sdio *bus)
731 return (u8)(bus->tx_max - bus->tx_seq) != 0 &&
732 ((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0;
736 * Reads a register in the SDIO hardware block. This block occupies a series of
737 * adresses on the 32 bit backplane bus.
739 static int r_sdreg32(struct brcmf_sdio *bus, u32 *regvar, u32 offset)
741 struct brcmf_core *core;
744 core = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV);
745 *regvar = brcmf_sdiod_regrl(bus->sdiodev, core->base + offset, &ret);
750 static int w_sdreg32(struct brcmf_sdio *bus, u32 regval, u32 reg_offset)
752 struct brcmf_core *core;
755 core = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV);
756 brcmf_sdiod_regwl(bus->sdiodev, core->base + reg_offset, regval, &ret);
762 brcmf_sdio_kso_control(struct brcmf_sdio *bus, bool on)
764 u8 wr_val = 0, rd_val, cmp_val, bmask;
768 brcmf_dbg(TRACE, "Enter: on=%d\n", on);
770 wr_val = (on << SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT);
771 /* 1st KSO write goes to AOS wake up core if device is asleep */
772 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
776 /* device WAKEUP through KSO:
777 * write bit 0 & read back until
778 * both bits 0 (kso bit) & 1 (dev on status) are set
780 cmp_val = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK |
781 SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK;
783 usleep_range(2000, 3000);
785 /* Put device to sleep, turn off KSO */
787 /* only check for bit0, bit1(dev on status) may not
788 * get cleared right away
790 bmask = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK;
794 /* reliable KSO bit set/clr:
795 * the sdiod sleep write access is synced to PMU 32khz clk
796 * just one write attempt may fail,
797 * read it back until it matches written value
799 rd_val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
801 if (((rd_val & bmask) == cmp_val) && !err)
805 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
807 } while (try_cnt++ < MAX_KSO_ATTEMPTS);
810 brcmf_dbg(SDIO, "try_cnt=%d rd_val=0x%x err=%d\n", try_cnt,
813 if (try_cnt > MAX_KSO_ATTEMPTS)
814 brcmf_err("max tries: rd_val=0x%x err=%d\n", rd_val, err);
819 #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
821 /* Turn backplane clock on or off */
822 static int brcmf_sdio_htclk(struct brcmf_sdio *bus, bool on, bool pendok)
825 u8 clkctl, clkreq, devctl;
826 unsigned long timeout;
828 brcmf_dbg(SDIO, "Enter\n");
832 if (bus->sr_enabled) {
833 bus->clkstate = (on ? CLK_AVAIL : CLK_SDONLY);
838 /* Request HT Avail */
840 bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
842 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
845 brcmf_err("HT Avail request error: %d\n", err);
849 /* Check current status */
850 clkctl = brcmf_sdiod_regrb(bus->sdiodev,
851 SBSDIO_FUNC1_CHIPCLKCSR, &err);
853 brcmf_err("HT Avail read error: %d\n", err);
857 /* Go to pending and await interrupt if appropriate */
858 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
859 /* Allow only clock-available interrupt */
860 devctl = brcmf_sdiod_regrb(bus->sdiodev,
861 SBSDIO_DEVICE_CTL, &err);
863 brcmf_err("Devctl error setting CA: %d\n",
868 devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
869 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
871 brcmf_dbg(SDIO, "CLKCTL: set PENDING\n");
872 bus->clkstate = CLK_PENDING;
875 } else if (bus->clkstate == CLK_PENDING) {
876 /* Cancel CA-only interrupt filter */
877 devctl = brcmf_sdiod_regrb(bus->sdiodev,
878 SBSDIO_DEVICE_CTL, &err);
879 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
880 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
884 /* Otherwise, wait here (polling) for HT Avail */
886 msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000);
887 while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
888 clkctl = brcmf_sdiod_regrb(bus->sdiodev,
889 SBSDIO_FUNC1_CHIPCLKCSR,
891 if (time_after(jiffies, timeout))
894 usleep_range(5000, 10000);
897 brcmf_err("HT Avail request error: %d\n", err);
900 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
901 brcmf_err("HT Avail timeout (%d): clkctl 0x%02x\n",
902 PMU_MAX_TRANSITION_DLY, clkctl);
906 /* Mark clock available */
907 bus->clkstate = CLK_AVAIL;
908 brcmf_dbg(SDIO, "CLKCTL: turned ON\n");
911 if (!bus->alp_only) {
912 if (SBSDIO_ALPONLY(clkctl))
913 brcmf_err("HT Clock should be on\n");
915 #endif /* defined (DEBUG) */
920 if (bus->clkstate == CLK_PENDING) {
921 /* Cancel CA-only interrupt filter */
922 devctl = brcmf_sdiod_regrb(bus->sdiodev,
923 SBSDIO_DEVICE_CTL, &err);
924 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
925 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
929 bus->clkstate = CLK_SDONLY;
930 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
932 brcmf_dbg(SDIO, "CLKCTL: turned OFF\n");
934 brcmf_err("Failed access turning clock off: %d\n",
942 /* Change idle/active SD state */
943 static int brcmf_sdio_sdclk(struct brcmf_sdio *bus, bool on)
945 brcmf_dbg(SDIO, "Enter\n");
948 bus->clkstate = CLK_SDONLY;
950 bus->clkstate = CLK_NONE;
955 /* Transition SD and backplane clock readiness */
956 static int brcmf_sdio_clkctl(struct brcmf_sdio *bus, uint target, bool pendok)
959 uint oldstate = bus->clkstate;
962 brcmf_dbg(SDIO, "Enter\n");
964 /* Early exit if we're already there */
965 if (bus->clkstate == target)
970 /* Make sure SD clock is available */
971 if (bus->clkstate == CLK_NONE)
972 brcmf_sdio_sdclk(bus, true);
973 /* Now request HT Avail on the backplane */
974 brcmf_sdio_htclk(bus, true, pendok);
975 brcmf_sdio_wd_timer(bus, BRCMF_WD_POLL_MS);
979 /* Remove HT request, or bring up SD clock */
980 if (bus->clkstate == CLK_NONE)
981 brcmf_sdio_sdclk(bus, true);
982 else if (bus->clkstate == CLK_AVAIL)
983 brcmf_sdio_htclk(bus, false, false);
985 brcmf_err("request for %d -> %d\n",
986 bus->clkstate, target);
987 brcmf_sdio_wd_timer(bus, BRCMF_WD_POLL_MS);
991 /* Make sure to remove HT request */
992 if (bus->clkstate == CLK_AVAIL)
993 brcmf_sdio_htclk(bus, false, false);
994 /* Now remove the SD clock */
995 brcmf_sdio_sdclk(bus, false);
996 brcmf_sdio_wd_timer(bus, 0);
1000 brcmf_dbg(SDIO, "%d -> %d\n", oldstate, bus->clkstate);
1007 brcmf_sdio_bus_sleep(struct brcmf_sdio *bus, bool sleep, bool pendok)
1012 brcmf_dbg(SDIO, "Enter: request %s currently %s\n",
1013 (sleep ? "SLEEP" : "WAKE"),
1014 (bus->sleeping ? "SLEEP" : "WAKE"));
1016 /* If SR is enabled control bus state with KSO */
1017 if (bus->sr_enabled) {
1018 /* Done if we're already in the requested state */
1019 if (sleep == bus->sleeping)
1022 /* Going to sleep */
1024 clkcsr = brcmf_sdiod_regrb(bus->sdiodev,
1025 SBSDIO_FUNC1_CHIPCLKCSR,
1027 if ((clkcsr & SBSDIO_CSR_MASK) == 0) {
1028 brcmf_dbg(SDIO, "no clock, set ALP\n");
1029 brcmf_sdiod_regwb(bus->sdiodev,
1030 SBSDIO_FUNC1_CHIPCLKCSR,
1031 SBSDIO_ALP_AVAIL_REQ, &err);
1033 err = brcmf_sdio_kso_control(bus, false);
1035 err = brcmf_sdio_kso_control(bus, true);
1038 brcmf_err("error while changing bus sleep state %d\n",
1045 /* control clocks */
1047 if (!bus->sr_enabled)
1048 brcmf_sdio_clkctl(bus, CLK_NONE, pendok);
1050 brcmf_sdio_clkctl(bus, CLK_AVAIL, pendok);
1052 bus->sleeping = sleep;
1053 brcmf_dbg(SDIO, "new state %s\n",
1054 (sleep ? "SLEEP" : "WAKE"));
1056 brcmf_dbg(SDIO, "Exit: err=%d\n", err);
1062 static inline bool brcmf_sdio_valid_shared_address(u32 addr)
1064 return !(addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff));
1067 static int brcmf_sdio_readshared(struct brcmf_sdio *bus,
1068 struct sdpcm_shared *sh)
1073 struct sdpcm_shared_le sh_le;
1076 shaddr = bus->ci->rambase + bus->ci->ramsize - 4;
1079 * Read last word in socram to determine
1080 * address of sdpcm_shared structure
1082 sdio_claim_host(bus->sdiodev->func[1]);
1083 brcmf_sdio_bus_sleep(bus, false, false);
1084 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, shaddr, (u8 *)&addr_le, 4);
1085 sdio_release_host(bus->sdiodev->func[1]);
1089 addr = le32_to_cpu(addr_le);
1091 brcmf_dbg(SDIO, "sdpcm_shared address 0x%08X\n", addr);
1094 * Check if addr is valid.
1095 * NVRAM length at the end of memory should have been overwritten.
1097 if (!brcmf_sdio_valid_shared_address(addr)) {
1098 brcmf_err("invalid sdpcm_shared address 0x%08X\n",
1103 /* Read hndrte_shared structure */
1104 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&sh_le,
1105 sizeof(struct sdpcm_shared_le));
1110 sh->flags = le32_to_cpu(sh_le.flags);
1111 sh->trap_addr = le32_to_cpu(sh_le.trap_addr);
1112 sh->assert_exp_addr = le32_to_cpu(sh_le.assert_exp_addr);
1113 sh->assert_file_addr = le32_to_cpu(sh_le.assert_file_addr);
1114 sh->assert_line = le32_to_cpu(sh_le.assert_line);
1115 sh->console_addr = le32_to_cpu(sh_le.console_addr);
1116 sh->msgtrace_addr = le32_to_cpu(sh_le.msgtrace_addr);
1118 if ((sh->flags & SDPCM_SHARED_VERSION_MASK) > SDPCM_SHARED_VERSION) {
1119 brcmf_err("sdpcm shared version unsupported: dhd %d dongle %d\n",
1120 SDPCM_SHARED_VERSION,
1121 sh->flags & SDPCM_SHARED_VERSION_MASK);
1128 static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus)
1130 struct sdpcm_shared sh;
1132 if (brcmf_sdio_readshared(bus, &sh) == 0)
1133 bus->console_addr = sh.console_addr;
1136 static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus)
1141 static u32 brcmf_sdio_hostmail(struct brcmf_sdio *bus)
1148 brcmf_dbg(SDIO, "Enter\n");
1150 /* Read mailbox data and ack that we did so */
1151 ret = r_sdreg32(bus, &hmb_data,
1152 offsetof(struct sdpcmd_regs, tohostmailboxdata));
1155 w_sdreg32(bus, SMB_INT_ACK,
1156 offsetof(struct sdpcmd_regs, tosbmailbox));
1157 bus->sdcnt.f1regdata += 2;
1159 /* Dongle recomposed rx frames, accept them again */
1160 if (hmb_data & HMB_DATA_NAKHANDLED) {
1161 brcmf_dbg(SDIO, "Dongle reports NAK handled, expect rtx of %d\n",
1164 brcmf_err("unexpected NAKHANDLED!\n");
1166 bus->rxskip = false;
1167 intstatus |= I_HMB_FRAME_IND;
1171 * DEVREADY does not occur with gSPI.
1173 if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
1175 (hmb_data & HMB_DATA_VERSION_MASK) >>
1176 HMB_DATA_VERSION_SHIFT;
1177 if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
1178 brcmf_err("Version mismatch, dongle reports %d, "
1180 bus->sdpcm_ver, SDPCM_PROT_VERSION);
1182 brcmf_dbg(SDIO, "Dongle ready, protocol version %d\n",
1186 * Retrieve console state address now that firmware should have
1189 brcmf_sdio_get_console_addr(bus);
1193 * Flow Control has been moved into the RX headers and this out of band
1194 * method isn't used any more.
1195 * remaining backward compatible with older dongles.
1197 if (hmb_data & HMB_DATA_FC) {
1198 fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >>
1199 HMB_DATA_FCDATA_SHIFT;
1201 if (fcbits & ~bus->flowcontrol)
1202 bus->sdcnt.fc_xoff++;
1204 if (bus->flowcontrol & ~fcbits)
1205 bus->sdcnt.fc_xon++;
1207 bus->sdcnt.fc_rcvd++;
1208 bus->flowcontrol = fcbits;
1211 /* Shouldn't be any others */
1212 if (hmb_data & ~(HMB_DATA_DEVREADY |
1213 HMB_DATA_NAKHANDLED |
1216 HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK))
1217 brcmf_err("Unknown mailbox data content: 0x%02x\n",
1223 static void brcmf_sdio_rxfail(struct brcmf_sdio *bus, bool abort, bool rtx)
1230 brcmf_err("%sterminate frame%s\n",
1231 abort ? "abort command, " : "",
1232 rtx ? ", send NAK" : "");
1235 brcmf_sdiod_abort(bus->sdiodev, SDIO_FUNC_2);
1237 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL,
1239 bus->sdcnt.f1regdata++;
1241 /* Wait until the packet has been flushed (device/FIFO stable) */
1242 for (lastrbc = retries = 0xffff; retries > 0; retries--) {
1243 hi = brcmf_sdiod_regrb(bus->sdiodev,
1244 SBSDIO_FUNC1_RFRAMEBCHI, &err);
1245 lo = brcmf_sdiod_regrb(bus->sdiodev,
1246 SBSDIO_FUNC1_RFRAMEBCLO, &err);
1247 bus->sdcnt.f1regdata += 2;
1249 if ((hi == 0) && (lo == 0))
1252 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
1253 brcmf_err("count growing: last 0x%04x now 0x%04x\n",
1254 lastrbc, (hi << 8) + lo);
1256 lastrbc = (hi << 8) + lo;
1260 brcmf_err("count never zeroed: last 0x%04x\n", lastrbc);
1262 brcmf_dbg(SDIO, "flush took %d iterations\n", 0xffff - retries);
1266 err = w_sdreg32(bus, SMB_NAK,
1267 offsetof(struct sdpcmd_regs, tosbmailbox));
1269 bus->sdcnt.f1regdata++;
1274 /* Clear partial in any case */
1275 bus->cur_read.len = 0;
1278 static void brcmf_sdio_txfail(struct brcmf_sdio *bus)
1280 struct brcmf_sdio_dev *sdiodev = bus->sdiodev;
1283 /* On failure, abort the command and terminate the frame */
1284 brcmf_err("sdio error, abort command and terminate frame\n");
1285 bus->sdcnt.tx_sderrs++;
1287 brcmf_sdiod_abort(sdiodev, SDIO_FUNC_2);
1288 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM, NULL);
1289 bus->sdcnt.f1regdata++;
1291 for (i = 0; i < 3; i++) {
1292 hi = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_WFRAMEBCHI, NULL);
1293 lo = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_WFRAMEBCLO, NULL);
1294 bus->sdcnt.f1regdata += 2;
1295 if ((hi == 0) && (lo == 0))
1300 /* return total length of buffer chain */
1301 static uint brcmf_sdio_glom_len(struct brcmf_sdio *bus)
1307 skb_queue_walk(&bus->glom, p)
1312 static void brcmf_sdio_free_glom(struct brcmf_sdio *bus)
1314 struct sk_buff *cur, *next;
1316 skb_queue_walk_safe(&bus->glom, cur, next) {
1317 skb_unlink(cur, &bus->glom);
1318 brcmu_pkt_buf_free_skb(cur);
1323 * brcmfmac sdio bus specific header
1324 * This is the lowest layer header wrapped on the packets transmitted between
1325 * host and WiFi dongle which contains information needed for SDIO core and
1328 * It consists of 3 parts: hardware header, hardware extension header and
1330 * hardware header (frame tag) - 4 bytes
1331 * Byte 0~1: Frame length
1332 * Byte 2~3: Checksum, bit-wise inverse of frame length
1333 * hardware extension header - 8 bytes
1334 * Tx glom mode only, N/A for Rx or normal Tx
1335 * Byte 0~1: Packet length excluding hw frame tag
1337 * Byte 3: Frame flags, bit 0: last frame indication
1338 * Byte 4~5: Reserved
1339 * Byte 6~7: Tail padding length
1340 * software header - 8 bytes
1341 * Byte 0: Rx/Tx sequence number
1342 * Byte 1: 4 MSB Channel number, 4 LSB arbitrary flag
1343 * Byte 2: Length of next data frame, reserved for Tx
1344 * Byte 3: Data offset
1345 * Byte 4: Flow control bits, reserved for Tx
1346 * Byte 5: Maximum Sequence number allowed by firmware for Tx, N/A for Tx packet
1347 * Byte 6~7: Reserved
1349 #define SDPCM_HWHDR_LEN 4
1350 #define SDPCM_HWEXT_LEN 8
1351 #define SDPCM_SWHDR_LEN 8
1352 #define SDPCM_HDRLEN (SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN)
1353 /* software header */
1354 #define SDPCM_SEQ_MASK 0x000000ff
1355 #define SDPCM_SEQ_WRAP 256
1356 #define SDPCM_CHANNEL_MASK 0x00000f00
1357 #define SDPCM_CHANNEL_SHIFT 8
1358 #define SDPCM_CONTROL_CHANNEL 0 /* Control */
1359 #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication */
1360 #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv */
1361 #define SDPCM_GLOM_CHANNEL 3 /* Coalesced packets */
1362 #define SDPCM_TEST_CHANNEL 15 /* Test/debug packets */
1363 #define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80)
1364 #define SDPCM_NEXTLEN_MASK 0x00ff0000
1365 #define SDPCM_NEXTLEN_SHIFT 16
1366 #define SDPCM_DOFFSET_MASK 0xff000000
1367 #define SDPCM_DOFFSET_SHIFT 24
1368 #define SDPCM_FCMASK_MASK 0x000000ff
1369 #define SDPCM_WINDOW_MASK 0x0000ff00
1370 #define SDPCM_WINDOW_SHIFT 8
1372 static inline u8 brcmf_sdio_getdatoffset(u8 *swheader)
1375 hdrvalue = *(u32 *)swheader;
1376 return (u8)((hdrvalue & SDPCM_DOFFSET_MASK) >> SDPCM_DOFFSET_SHIFT);
1379 static int brcmf_sdio_hdparse(struct brcmf_sdio *bus, u8 *header,
1380 struct brcmf_sdio_hdrinfo *rd,
1381 enum brcmf_sdio_frmtype type)
1384 u8 rx_seq, fc, tx_seq_max;
1387 trace_brcmf_sdpcm_hdr(SDPCM_RX, header);
1390 len = get_unaligned_le16(header);
1391 checksum = get_unaligned_le16(header + sizeof(u16));
1392 /* All zero means no more to read */
1393 if (!(len | checksum)) {
1394 bus->rxpending = false;
1397 if ((u16)(~(len ^ checksum))) {
1398 brcmf_err("HW header checksum error\n");
1399 bus->sdcnt.rx_badhdr++;
1400 brcmf_sdio_rxfail(bus, false, false);
1403 if (len < SDPCM_HDRLEN) {
1404 brcmf_err("HW header length error\n");
1407 if (type == BRCMF_SDIO_FT_SUPER &&
1408 (roundup(len, bus->blocksize) != rd->len)) {
1409 brcmf_err("HW superframe header length error\n");
1412 if (type == BRCMF_SDIO_FT_SUB && len > rd->len) {
1413 brcmf_err("HW subframe header length error\n");
1418 /* software header */
1419 header += SDPCM_HWHDR_LEN;
1420 swheader = le32_to_cpu(*(__le32 *)header);
1421 if (type == BRCMF_SDIO_FT_SUPER && SDPCM_GLOMDESC(header)) {
1422 brcmf_err("Glom descriptor found in superframe head\n");
1426 rx_seq = (u8)(swheader & SDPCM_SEQ_MASK);
1427 rd->channel = (swheader & SDPCM_CHANNEL_MASK) >> SDPCM_CHANNEL_SHIFT;
1428 if (len > MAX_RX_DATASZ && rd->channel != SDPCM_CONTROL_CHANNEL &&
1429 type != BRCMF_SDIO_FT_SUPER) {
1430 brcmf_err("HW header length too long\n");
1431 bus->sdcnt.rx_toolong++;
1432 brcmf_sdio_rxfail(bus, false, false);
1436 if (type == BRCMF_SDIO_FT_SUPER && rd->channel != SDPCM_GLOM_CHANNEL) {
1437 brcmf_err("Wrong channel for superframe\n");
1441 if (type == BRCMF_SDIO_FT_SUB && rd->channel != SDPCM_DATA_CHANNEL &&
1442 rd->channel != SDPCM_EVENT_CHANNEL) {
1443 brcmf_err("Wrong channel for subframe\n");
1447 rd->dat_offset = brcmf_sdio_getdatoffset(header);
1448 if (rd->dat_offset < SDPCM_HDRLEN || rd->dat_offset > rd->len) {
1449 brcmf_err("seq %d: bad data offset\n", rx_seq);
1450 bus->sdcnt.rx_badhdr++;
1451 brcmf_sdio_rxfail(bus, false, false);
1455 if (rd->seq_num != rx_seq) {
1456 brcmf_err("seq %d: sequence number error, expect %d\n",
1457 rx_seq, rd->seq_num);
1458 bus->sdcnt.rx_badseq++;
1459 rd->seq_num = rx_seq;
1461 /* no need to check the reset for subframe */
1462 if (type == BRCMF_SDIO_FT_SUB)
1464 rd->len_nxtfrm = (swheader & SDPCM_NEXTLEN_MASK) >> SDPCM_NEXTLEN_SHIFT;
1465 if (rd->len_nxtfrm << 4 > MAX_RX_DATASZ) {
1466 /* only warm for NON glom packet */
1467 if (rd->channel != SDPCM_GLOM_CHANNEL)
1468 brcmf_err("seq %d: next length error\n", rx_seq);
1471 swheader = le32_to_cpu(*(__le32 *)(header + 4));
1472 fc = swheader & SDPCM_FCMASK_MASK;
1473 if (bus->flowcontrol != fc) {
1474 if (~bus->flowcontrol & fc)
1475 bus->sdcnt.fc_xoff++;
1476 if (bus->flowcontrol & ~fc)
1477 bus->sdcnt.fc_xon++;
1478 bus->sdcnt.fc_rcvd++;
1479 bus->flowcontrol = fc;
1481 tx_seq_max = (swheader & SDPCM_WINDOW_MASK) >> SDPCM_WINDOW_SHIFT;
1482 if ((u8)(tx_seq_max - bus->tx_seq) > 0x40) {
1483 brcmf_err("seq %d: max tx seq number error\n", rx_seq);
1484 tx_seq_max = bus->tx_seq + 2;
1486 bus->tx_max = tx_seq_max;
1491 static inline void brcmf_sdio_update_hwhdr(u8 *header, u16 frm_length)
1493 *(__le16 *)header = cpu_to_le16(frm_length);
1494 *(((__le16 *)header) + 1) = cpu_to_le16(~frm_length);
1497 static void brcmf_sdio_hdpack(struct brcmf_sdio *bus, u8 *header,
1498 struct brcmf_sdio_hdrinfo *hd_info)
1503 brcmf_sdio_update_hwhdr(header, hd_info->len);
1504 hdr_offset = SDPCM_HWHDR_LEN;
1507 hdrval = (hd_info->len - hdr_offset) | (hd_info->lastfrm << 24);
1508 *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval);
1509 hdrval = (u16)hd_info->tail_pad << 16;
1510 *(((__le32 *)(header + hdr_offset)) + 1) = cpu_to_le32(hdrval);
1511 hdr_offset += SDPCM_HWEXT_LEN;
1514 hdrval = hd_info->seq_num;
1515 hdrval |= (hd_info->channel << SDPCM_CHANNEL_SHIFT) &
1517 hdrval |= (hd_info->dat_offset << SDPCM_DOFFSET_SHIFT) &
1519 *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval);
1520 *(((__le32 *)(header + hdr_offset)) + 1) = 0;
1521 trace_brcmf_sdpcm_hdr(SDPCM_TX + !!(bus->txglom), header);
1524 static u8 brcmf_sdio_rxglom(struct brcmf_sdio *bus, u8 rxseq)
1529 struct sk_buff *pfirst, *pnext;
1534 struct brcmf_sdio_hdrinfo rd_new;
1536 /* If packets, issue read(s) and send up packet chain */
1537 /* Return sequence numbers consumed? */
1539 brcmf_dbg(SDIO, "start: glomd %p glom %p\n",
1540 bus->glomd, skb_peek(&bus->glom));
1542 /* If there's a descriptor, generate the packet chain */
1544 pfirst = pnext = NULL;
1545 dlen = (u16) (bus->glomd->len);
1546 dptr = bus->glomd->data;
1547 if (!dlen || (dlen & 1)) {
1548 brcmf_err("bad glomd len(%d), ignore descriptor\n",
1553 for (totlen = num = 0; dlen; num++) {
1554 /* Get (and move past) next length */
1555 sublen = get_unaligned_le16(dptr);
1556 dlen -= sizeof(u16);
1557 dptr += sizeof(u16);
1558 if ((sublen < SDPCM_HDRLEN) ||
1559 ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
1560 brcmf_err("descriptor len %d bad: %d\n",
1565 if (sublen % bus->sgentry_align) {
1566 brcmf_err("sublen %d not multiple of %d\n",
1567 sublen, bus->sgentry_align);
1571 /* For last frame, adjust read len so total
1572 is a block multiple */
1575 (roundup(totlen, bus->blocksize) - totlen);
1576 totlen = roundup(totlen, bus->blocksize);
1579 /* Allocate/chain packet for next subframe */
1580 pnext = brcmu_pkt_buf_get_skb(sublen + bus->sgentry_align);
1581 if (pnext == NULL) {
1582 brcmf_err("bcm_pkt_buf_get_skb failed, num %d len %d\n",
1586 skb_queue_tail(&bus->glom, pnext);
1588 /* Adhere to start alignment requirements */
1589 pkt_align(pnext, sublen, bus->sgentry_align);
1592 /* If all allocations succeeded, save packet chain
1595 brcmf_dbg(GLOM, "allocated %d-byte packet chain for %d subframes\n",
1597 if (BRCMF_GLOM_ON() && bus->cur_read.len &&
1598 totlen != bus->cur_read.len) {
1599 brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n",
1600 bus->cur_read.len, totlen, rxseq);
1602 pfirst = pnext = NULL;
1604 brcmf_sdio_free_glom(bus);
1608 /* Done with descriptor packet */
1609 brcmu_pkt_buf_free_skb(bus->glomd);
1611 bus->cur_read.len = 0;
1614 /* Ok -- either we just generated a packet chain,
1615 or had one from before */
1616 if (!skb_queue_empty(&bus->glom)) {
1617 if (BRCMF_GLOM_ON()) {
1618 brcmf_dbg(GLOM, "try superframe read, packet chain:\n");
1619 skb_queue_walk(&bus->glom, pnext) {
1620 brcmf_dbg(GLOM, " %p: %p len 0x%04x (%d)\n",
1621 pnext, (u8 *) (pnext->data),
1622 pnext->len, pnext->len);
1626 pfirst = skb_peek(&bus->glom);
1627 dlen = (u16) brcmf_sdio_glom_len(bus);
1629 /* Do an SDIO read for the superframe. Configurable iovar to
1630 * read directly into the chained packet, or allocate a large
1631 * packet and and copy into the chain.
1633 sdio_claim_host(bus->sdiodev->func[1]);
1634 errcode = brcmf_sdiod_recv_chain(bus->sdiodev,
1636 sdio_release_host(bus->sdiodev->func[1]);
1637 bus->sdcnt.f2rxdata++;
1639 /* On failure, kill the superframe, allow a couple retries */
1641 brcmf_err("glom read of %d bytes failed: %d\n",
1644 sdio_claim_host(bus->sdiodev->func[1]);
1645 if (bus->glomerr++ < 3) {
1646 brcmf_sdio_rxfail(bus, true, true);
1649 brcmf_sdio_rxfail(bus, true, false);
1650 bus->sdcnt.rxglomfail++;
1651 brcmf_sdio_free_glom(bus);
1653 sdio_release_host(bus->sdiodev->func[1]);
1657 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1658 pfirst->data, min_t(int, pfirst->len, 48),
1661 rd_new.seq_num = rxseq;
1663 sdio_claim_host(bus->sdiodev->func[1]);
1664 errcode = brcmf_sdio_hdparse(bus, pfirst->data, &rd_new,
1665 BRCMF_SDIO_FT_SUPER);
1666 sdio_release_host(bus->sdiodev->func[1]);
1667 bus->cur_read.len = rd_new.len_nxtfrm << 4;
1669 /* Remove superframe header, remember offset */
1670 skb_pull(pfirst, rd_new.dat_offset);
1671 sfdoff = rd_new.dat_offset;
1674 /* Validate all the subframe headers */
1675 skb_queue_walk(&bus->glom, pnext) {
1676 /* leave when invalid subframe is found */
1680 rd_new.len = pnext->len;
1681 rd_new.seq_num = rxseq++;
1682 sdio_claim_host(bus->sdiodev->func[1]);
1683 errcode = brcmf_sdio_hdparse(bus, pnext->data, &rd_new,
1685 sdio_release_host(bus->sdiodev->func[1]);
1686 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1687 pnext->data, 32, "subframe:\n");
1693 /* Terminate frame on error, request
1695 sdio_claim_host(bus->sdiodev->func[1]);
1696 if (bus->glomerr++ < 3) {
1697 /* Restore superframe header space */
1698 skb_push(pfirst, sfdoff);
1699 brcmf_sdio_rxfail(bus, true, true);
1702 brcmf_sdio_rxfail(bus, true, false);
1703 bus->sdcnt.rxglomfail++;
1704 brcmf_sdio_free_glom(bus);
1706 sdio_release_host(bus->sdiodev->func[1]);
1707 bus->cur_read.len = 0;
1711 /* Basic SD framing looks ok - process each packet (header) */
1713 skb_queue_walk_safe(&bus->glom, pfirst, pnext) {
1714 dptr = (u8 *) (pfirst->data);
1715 sublen = get_unaligned_le16(dptr);
1716 doff = brcmf_sdio_getdatoffset(&dptr[SDPCM_HWHDR_LEN]);
1718 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(),
1720 "Rx Subframe Data:\n");
1722 __skb_trim(pfirst, sublen);
1723 skb_pull(pfirst, doff);
1725 if (pfirst->len == 0) {
1726 skb_unlink(pfirst, &bus->glom);
1727 brcmu_pkt_buf_free_skb(pfirst);
1731 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1733 min_t(int, pfirst->len, 32),
1734 "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n",
1735 bus->glom.qlen, pfirst, pfirst->data,
1736 pfirst->len, pfirst->next,
1738 skb_unlink(pfirst, &bus->glom);
1739 brcmf_rx_frame(bus->sdiodev->dev, pfirst);
1740 bus->sdcnt.rxglompkts++;
1743 bus->sdcnt.rxglomframes++;
1748 static int brcmf_sdio_dcmd_resp_wait(struct brcmf_sdio *bus, uint *condition,
1751 DECLARE_WAITQUEUE(wait, current);
1752 int timeout = msecs_to_jiffies(DCMD_RESP_TIMEOUT);
1754 /* Wait until control frame is available */
1755 add_wait_queue(&bus->dcmd_resp_wait, &wait);
1756 set_current_state(TASK_INTERRUPTIBLE);
1758 while (!(*condition) && (!signal_pending(current) && timeout))
1759 timeout = schedule_timeout(timeout);
1761 if (signal_pending(current))
1764 set_current_state(TASK_RUNNING);
1765 remove_wait_queue(&bus->dcmd_resp_wait, &wait);
1770 static int brcmf_sdio_dcmd_resp_wake(struct brcmf_sdio *bus)
1772 if (waitqueue_active(&bus->dcmd_resp_wait))
1773 wake_up_interruptible(&bus->dcmd_resp_wait);
1778 brcmf_sdio_read_control(struct brcmf_sdio *bus, u8 *hdr, uint len, uint doff)
1781 u8 *buf = NULL, *rbuf;
1784 brcmf_dbg(TRACE, "Enter\n");
1787 buf = vzalloc(bus->rxblen);
1792 pad = ((unsigned long)rbuf % bus->head_align);
1794 rbuf += (bus->head_align - pad);
1796 /* Copy the already-read portion over */
1797 memcpy(buf, hdr, BRCMF_FIRSTREAD);
1798 if (len <= BRCMF_FIRSTREAD)
1801 /* Raise rdlen to next SDIO block to avoid tail command */
1802 rdlen = len - BRCMF_FIRSTREAD;
1803 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
1804 pad = bus->blocksize - (rdlen % bus->blocksize);
1805 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
1806 ((len + pad) < bus->sdiodev->bus_if->maxctl))
1808 } else if (rdlen % bus->head_align) {
1809 rdlen += bus->head_align - (rdlen % bus->head_align);
1812 /* Drop if the read is too big or it exceeds our maximum */
1813 if ((rdlen + BRCMF_FIRSTREAD) > bus->sdiodev->bus_if->maxctl) {
1814 brcmf_err("%d-byte control read exceeds %d-byte buffer\n",
1815 rdlen, bus->sdiodev->bus_if->maxctl);
1816 brcmf_sdio_rxfail(bus, false, false);
1820 if ((len - doff) > bus->sdiodev->bus_if->maxctl) {
1821 brcmf_err("%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n",
1822 len, len - doff, bus->sdiodev->bus_if->maxctl);
1823 bus->sdcnt.rx_toolong++;
1824 brcmf_sdio_rxfail(bus, false, false);
1828 /* Read remain of frame body */
1829 sdret = brcmf_sdiod_recv_buf(bus->sdiodev, rbuf, rdlen);
1830 bus->sdcnt.f2rxdata++;
1832 /* Control frame failures need retransmission */
1834 brcmf_err("read %d control bytes failed: %d\n",
1836 bus->sdcnt.rxc_errors++;
1837 brcmf_sdio_rxfail(bus, true, true);
1840 memcpy(buf + BRCMF_FIRSTREAD, rbuf, rdlen);
1844 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(),
1845 buf, len, "RxCtrl:\n");
1847 /* Point to valid data and indicate its length */
1848 spin_lock_bh(&bus->rxctl_lock);
1850 brcmf_err("last control frame is being processed.\n");
1851 spin_unlock_bh(&bus->rxctl_lock);
1855 bus->rxctl = buf + doff;
1856 bus->rxctl_orig = buf;
1857 bus->rxlen = len - doff;
1858 spin_unlock_bh(&bus->rxctl_lock);
1861 /* Awake any waiters */
1862 brcmf_sdio_dcmd_resp_wake(bus);
1865 /* Pad read to blocksize for efficiency */
1866 static void brcmf_sdio_pad(struct brcmf_sdio *bus, u16 *pad, u16 *rdlen)
1868 if (bus->roundup && bus->blocksize && *rdlen > bus->blocksize) {
1869 *pad = bus->blocksize - (*rdlen % bus->blocksize);
1870 if (*pad <= bus->roundup && *pad < bus->blocksize &&
1871 *rdlen + *pad + BRCMF_FIRSTREAD < MAX_RX_DATASZ)
1873 } else if (*rdlen % bus->head_align) {
1874 *rdlen += bus->head_align - (*rdlen % bus->head_align);
1878 static uint brcmf_sdio_readframes(struct brcmf_sdio *bus, uint maxframes)
1880 struct sk_buff *pkt; /* Packet for event or data frames */
1881 u16 pad; /* Number of pad bytes to read */
1882 uint rxleft = 0; /* Remaining number of frames allowed */
1883 int ret; /* Return code from calls */
1884 uint rxcount = 0; /* Total frames read */
1885 struct brcmf_sdio_hdrinfo *rd = &bus->cur_read, rd_new;
1888 brcmf_dbg(TRACE, "Enter\n");
1890 /* Not finished unless we encounter no more frames indication */
1891 bus->rxpending = true;
1893 for (rd->seq_num = bus->rx_seq, rxleft = maxframes;
1894 !bus->rxskip && rxleft && bus->sdiodev->state == BRCMF_SDIOD_DATA;
1895 rd->seq_num++, rxleft--) {
1897 /* Handle glomming separately */
1898 if (bus->glomd || !skb_queue_empty(&bus->glom)) {
1900 brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n",
1901 bus->glomd, skb_peek(&bus->glom));
1902 cnt = brcmf_sdio_rxglom(bus, rd->seq_num);
1903 brcmf_dbg(GLOM, "rxglom returned %d\n", cnt);
1904 rd->seq_num += cnt - 1;
1905 rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
1909 rd->len_left = rd->len;
1910 /* read header first for unknow frame length */
1911 sdio_claim_host(bus->sdiodev->func[1]);
1913 ret = brcmf_sdiod_recv_buf(bus->sdiodev,
1914 bus->rxhdr, BRCMF_FIRSTREAD);
1915 bus->sdcnt.f2rxhdrs++;
1917 brcmf_err("RXHEADER FAILED: %d\n",
1919 bus->sdcnt.rx_hdrfail++;
1920 brcmf_sdio_rxfail(bus, true, true);
1921 sdio_release_host(bus->sdiodev->func[1]);
1925 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() || BRCMF_HDRS_ON(),
1926 bus->rxhdr, SDPCM_HDRLEN,
1929 if (brcmf_sdio_hdparse(bus, bus->rxhdr, rd,
1930 BRCMF_SDIO_FT_NORMAL)) {
1931 sdio_release_host(bus->sdiodev->func[1]);
1932 if (!bus->rxpending)
1938 if (rd->channel == SDPCM_CONTROL_CHANNEL) {
1939 brcmf_sdio_read_control(bus, bus->rxhdr,
1942 /* prepare the descriptor for the next read */
1943 rd->len = rd->len_nxtfrm << 4;
1945 /* treat all packet as event if we don't know */
1946 rd->channel = SDPCM_EVENT_CHANNEL;
1947 sdio_release_host(bus->sdiodev->func[1]);
1950 rd->len_left = rd->len > BRCMF_FIRSTREAD ?
1951 rd->len - BRCMF_FIRSTREAD : 0;
1952 head_read = BRCMF_FIRSTREAD;
1955 brcmf_sdio_pad(bus, &pad, &rd->len_left);
1957 pkt = brcmu_pkt_buf_get_skb(rd->len_left + head_read +
1960 /* Give up on data, request rtx of events */
1961 brcmf_err("brcmu_pkt_buf_get_skb failed\n");
1962 brcmf_sdio_rxfail(bus, false,
1963 RETRYCHAN(rd->channel));
1964 sdio_release_host(bus->sdiodev->func[1]);
1967 skb_pull(pkt, head_read);
1968 pkt_align(pkt, rd->len_left, bus->head_align);
1970 ret = brcmf_sdiod_recv_pkt(bus->sdiodev, pkt);
1971 bus->sdcnt.f2rxdata++;
1972 sdio_release_host(bus->sdiodev->func[1]);
1975 brcmf_err("read %d bytes from channel %d failed: %d\n",
1976 rd->len, rd->channel, ret);
1977 brcmu_pkt_buf_free_skb(pkt);
1978 sdio_claim_host(bus->sdiodev->func[1]);
1979 brcmf_sdio_rxfail(bus, true,
1980 RETRYCHAN(rd->channel));
1981 sdio_release_host(bus->sdiodev->func[1]);
1986 skb_push(pkt, head_read);
1987 memcpy(pkt->data, bus->rxhdr, head_read);
1990 memcpy(bus->rxhdr, pkt->data, SDPCM_HDRLEN);
1991 rd_new.seq_num = rd->seq_num;
1992 sdio_claim_host(bus->sdiodev->func[1]);
1993 if (brcmf_sdio_hdparse(bus, bus->rxhdr, &rd_new,
1994 BRCMF_SDIO_FT_NORMAL)) {
1996 brcmu_pkt_buf_free_skb(pkt);
1998 bus->sdcnt.rx_readahead_cnt++;
1999 if (rd->len != roundup(rd_new.len, 16)) {
2000 brcmf_err("frame length mismatch:read %d, should be %d\n",
2002 roundup(rd_new.len, 16) >> 4);
2004 brcmf_sdio_rxfail(bus, true, true);
2005 sdio_release_host(bus->sdiodev->func[1]);
2006 brcmu_pkt_buf_free_skb(pkt);
2009 sdio_release_host(bus->sdiodev->func[1]);
2010 rd->len_nxtfrm = rd_new.len_nxtfrm;
2011 rd->channel = rd_new.channel;
2012 rd->dat_offset = rd_new.dat_offset;
2014 brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() &&
2017 bus->rxhdr, SDPCM_HDRLEN,
2020 if (rd_new.channel == SDPCM_CONTROL_CHANNEL) {
2021 brcmf_err("readahead on control packet %d?\n",
2023 /* Force retry w/normal header read */
2025 sdio_claim_host(bus->sdiodev->func[1]);
2026 brcmf_sdio_rxfail(bus, false, true);
2027 sdio_release_host(bus->sdiodev->func[1]);
2028 brcmu_pkt_buf_free_skb(pkt);
2033 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(),
2034 pkt->data, rd->len, "Rx Data:\n");
2036 /* Save superframe descriptor and allocate packet frame */
2037 if (rd->channel == SDPCM_GLOM_CHANNEL) {
2038 if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_HWHDR_LEN])) {
2039 brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n",
2041 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
2044 __skb_trim(pkt, rd->len);
2045 skb_pull(pkt, SDPCM_HDRLEN);
2048 brcmf_err("%s: glom superframe w/o "
2049 "descriptor!\n", __func__);
2050 sdio_claim_host(bus->sdiodev->func[1]);
2051 brcmf_sdio_rxfail(bus, false, false);
2052 sdio_release_host(bus->sdiodev->func[1]);
2054 /* prepare the descriptor for the next read */
2055 rd->len = rd->len_nxtfrm << 4;
2057 /* treat all packet as event if we don't know */
2058 rd->channel = SDPCM_EVENT_CHANNEL;
2062 /* Fill in packet len and prio, deliver upward */
2063 __skb_trim(pkt, rd->len);
2064 skb_pull(pkt, rd->dat_offset);
2066 /* prepare the descriptor for the next read */
2067 rd->len = rd->len_nxtfrm << 4;
2069 /* treat all packet as event if we don't know */
2070 rd->channel = SDPCM_EVENT_CHANNEL;
2072 if (pkt->len == 0) {
2073 brcmu_pkt_buf_free_skb(pkt);
2077 brcmf_rx_frame(bus->sdiodev->dev, pkt);
2080 rxcount = maxframes - rxleft;
2081 /* Message if we hit the limit */
2083 brcmf_dbg(DATA, "hit rx limit of %d frames\n", maxframes);
2085 brcmf_dbg(DATA, "processed %d frames\n", rxcount);
2086 /* Back off rxseq if awaiting rtx, update rx_seq */
2089 bus->rx_seq = rd->seq_num;
2095 brcmf_sdio_wait_event_wakeup(struct brcmf_sdio *bus)
2097 if (waitqueue_active(&bus->ctrl_wait))
2098 wake_up_interruptible(&bus->ctrl_wait);
2102 static int brcmf_sdio_txpkt_hdalign(struct brcmf_sdio *bus, struct sk_buff *pkt)
2107 dat_buf = (u8 *)(pkt->data);
2109 /* Check head padding */
2110 head_pad = ((unsigned long)dat_buf % bus->head_align);
2112 if (skb_headroom(pkt) < head_pad) {
2113 bus->sdiodev->bus_if->tx_realloc++;
2115 if (skb_cow(pkt, head_pad))
2118 skb_push(pkt, head_pad);
2119 dat_buf = (u8 *)(pkt->data);
2120 memset(dat_buf, 0, head_pad + bus->tx_hdrlen);
2126 * struct brcmf_skbuff_cb reserves first two bytes in sk_buff::cb for
2129 /* flag marking a dummy skb added for DMA alignment requirement */
2130 #define ALIGN_SKB_FLAG 0x8000
2131 /* bit mask of data length chopped from the previous packet */
2132 #define ALIGN_SKB_CHOP_LEN_MASK 0x7fff
2134 static int brcmf_sdio_txpkt_prep_sg(struct brcmf_sdio *bus,
2135 struct sk_buff_head *pktq,
2136 struct sk_buff *pkt, u16 total_len)
2138 struct brcmf_sdio_dev *sdiodev;
2139 struct sk_buff *pkt_pad;
2140 u16 tail_pad, tail_chop, chain_pad;
2141 unsigned int blksize;
2145 sdiodev = bus->sdiodev;
2146 blksize = sdiodev->func[SDIO_FUNC_2]->cur_blksize;
2147 /* sg entry alignment should be a divisor of block size */
2148 WARN_ON(blksize % bus->sgentry_align);
2150 /* Check tail padding */
2151 lastfrm = skb_queue_is_last(pktq, pkt);
2153 tail_chop = pkt->len % bus->sgentry_align;
2155 tail_pad = bus->sgentry_align - tail_chop;
2156 chain_pad = (total_len + tail_pad) % blksize;
2157 if (lastfrm && chain_pad)
2158 tail_pad += blksize - chain_pad;
2159 if (skb_tailroom(pkt) < tail_pad && pkt->len > blksize) {
2160 pkt_pad = brcmu_pkt_buf_get_skb(tail_pad + tail_chop +
2162 if (pkt_pad == NULL)
2164 ret = brcmf_sdio_txpkt_hdalign(bus, pkt_pad);
2165 if (unlikely(ret < 0)) {
2169 memcpy(pkt_pad->data,
2170 pkt->data + pkt->len - tail_chop,
2172 *(u16 *)(pkt_pad->cb) = ALIGN_SKB_FLAG + tail_chop;
2173 skb_trim(pkt, pkt->len - tail_chop);
2174 skb_trim(pkt_pad, tail_pad + tail_chop);
2175 __skb_queue_after(pktq, pkt, pkt_pad);
2177 ntail = pkt->data_len + tail_pad -
2178 (pkt->end - pkt->tail);
2179 if (skb_cloned(pkt) || ntail > 0)
2180 if (pskb_expand_head(pkt, 0, ntail, GFP_ATOMIC))
2182 if (skb_linearize(pkt))
2184 __skb_put(pkt, tail_pad);
2191 * brcmf_sdio_txpkt_prep - packet preparation for transmit
2192 * @bus: brcmf_sdio structure pointer
2193 * @pktq: packet list pointer
2194 * @chan: virtual channel to transmit the packet
2196 * Processes to be applied to the packet
2197 * - Align data buffer pointer
2198 * - Align data buffer length
2200 * Return: negative value if there is error
2203 brcmf_sdio_txpkt_prep(struct brcmf_sdio *bus, struct sk_buff_head *pktq,
2206 u16 head_pad, total_len;
2207 struct sk_buff *pkt_next;
2210 struct brcmf_sdio_hdrinfo hd_info = {0};
2212 txseq = bus->tx_seq;
2214 skb_queue_walk(pktq, pkt_next) {
2215 /* alignment packet inserted in previous
2216 * loop cycle can be skipped as it is
2217 * already properly aligned and does not
2218 * need an sdpcm header.
2220 if (*(u16 *)(pkt_next->cb) & ALIGN_SKB_FLAG)
2223 /* align packet data pointer */
2224 ret = brcmf_sdio_txpkt_hdalign(bus, pkt_next);
2227 head_pad = (u16)ret;
2229 memset(pkt_next->data + bus->tx_hdrlen, 0, head_pad);
2231 total_len += pkt_next->len;
2233 hd_info.len = pkt_next->len;
2234 hd_info.lastfrm = skb_queue_is_last(pktq, pkt_next);
2235 if (bus->txglom && pktq->qlen > 1) {
2236 ret = brcmf_sdio_txpkt_prep_sg(bus, pktq,
2237 pkt_next, total_len);
2240 hd_info.tail_pad = (u16)ret;
2241 total_len += (u16)ret;
2244 hd_info.channel = chan;
2245 hd_info.dat_offset = head_pad + bus->tx_hdrlen;
2246 hd_info.seq_num = txseq++;
2248 /* Now fill the header */
2249 brcmf_sdio_hdpack(bus, pkt_next->data, &hd_info);
2251 if (BRCMF_BYTES_ON() &&
2252 ((BRCMF_CTL_ON() && chan == SDPCM_CONTROL_CHANNEL) ||
2253 (BRCMF_DATA_ON() && chan != SDPCM_CONTROL_CHANNEL)))
2254 brcmf_dbg_hex_dump(true, pkt_next->data, hd_info.len,
2256 else if (BRCMF_HDRS_ON())
2257 brcmf_dbg_hex_dump(true, pkt_next->data,
2258 head_pad + bus->tx_hdrlen,
2261 /* Hardware length tag of the first packet should be total
2262 * length of the chain (including padding)
2265 brcmf_sdio_update_hwhdr(pktq->next->data, total_len);
2270 * brcmf_sdio_txpkt_postp - packet post processing for transmit
2271 * @bus: brcmf_sdio structure pointer
2272 * @pktq: packet list pointer
2274 * Processes to be applied to the packet
2275 * - Remove head padding
2276 * - Remove tail padding
2279 brcmf_sdio_txpkt_postp(struct brcmf_sdio *bus, struct sk_buff_head *pktq)
2284 u16 dummy_flags, chop_len;
2285 struct sk_buff *pkt_next, *tmp, *pkt_prev;
2287 skb_queue_walk_safe(pktq, pkt_next, tmp) {
2288 dummy_flags = *(u16 *)(pkt_next->cb);
2289 if (dummy_flags & ALIGN_SKB_FLAG) {
2290 chop_len = dummy_flags & ALIGN_SKB_CHOP_LEN_MASK;
2292 pkt_prev = pkt_next->prev;
2293 skb_put(pkt_prev, chop_len);
2295 __skb_unlink(pkt_next, pktq);
2296 brcmu_pkt_buf_free_skb(pkt_next);
2298 hdr = pkt_next->data + bus->tx_hdrlen - SDPCM_SWHDR_LEN;
2299 dat_offset = le32_to_cpu(*(__le32 *)hdr);
2300 dat_offset = (dat_offset & SDPCM_DOFFSET_MASK) >>
2301 SDPCM_DOFFSET_SHIFT;
2302 skb_pull(pkt_next, dat_offset);
2304 tail_pad = le16_to_cpu(*(__le16 *)(hdr - 2));
2305 skb_trim(pkt_next, pkt_next->len - tail_pad);
2311 /* Writes a HW/SW header into the packet and sends it. */
2312 /* Assumes: (a) header space already there, (b) caller holds lock */
2313 static int brcmf_sdio_txpkt(struct brcmf_sdio *bus, struct sk_buff_head *pktq,
2317 struct sk_buff *pkt_next, *tmp;
2319 brcmf_dbg(TRACE, "Enter\n");
2321 ret = brcmf_sdio_txpkt_prep(bus, pktq, chan);
2325 sdio_claim_host(bus->sdiodev->func[1]);
2326 ret = brcmf_sdiod_send_pkt(bus->sdiodev, pktq);
2327 bus->sdcnt.f2txdata++;
2330 brcmf_sdio_txfail(bus);
2332 sdio_release_host(bus->sdiodev->func[1]);
2335 brcmf_sdio_txpkt_postp(bus, pktq);
2337 bus->tx_seq = (bus->tx_seq + pktq->qlen) % SDPCM_SEQ_WRAP;
2338 skb_queue_walk_safe(pktq, pkt_next, tmp) {
2339 __skb_unlink(pkt_next, pktq);
2340 brcmf_txcomplete(bus->sdiodev->dev, pkt_next, ret == 0);
2345 static uint brcmf_sdio_sendfromq(struct brcmf_sdio *bus, uint maxframes)
2347 struct sk_buff *pkt;
2348 struct sk_buff_head pktq;
2350 int ret = 0, prec_out, i;
2352 u8 tx_prec_map, pkt_num;
2354 brcmf_dbg(TRACE, "Enter\n");
2356 tx_prec_map = ~bus->flowcontrol;
2358 /* Send frames until the limit or some other event */
2359 for (cnt = 0; (cnt < maxframes) && data_ok(bus);) {
2362 pkt_num = min_t(u8, bus->tx_max - bus->tx_seq,
2363 bus->sdiodev->txglomsz);
2364 pkt_num = min_t(u32, pkt_num,
2365 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol));
2366 __skb_queue_head_init(&pktq);
2367 spin_lock_bh(&bus->txq_lock);
2368 for (i = 0; i < pkt_num; i++) {
2369 pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map,
2373 __skb_queue_tail(&pktq, pkt);
2375 spin_unlock_bh(&bus->txq_lock);
2379 ret = brcmf_sdio_txpkt(bus, &pktq, SDPCM_DATA_CHANNEL);
2383 /* In poll mode, need to check for other events */
2385 /* Check device status, signal pending interrupt */
2386 sdio_claim_host(bus->sdiodev->func[1]);
2387 ret = r_sdreg32(bus, &intstatus,
2388 offsetof(struct sdpcmd_regs,
2390 sdio_release_host(bus->sdiodev->func[1]);
2391 bus->sdcnt.f2txdata++;
2394 if (intstatus & bus->hostintmask)
2395 atomic_set(&bus->ipend, 1);
2399 /* Deflow-control stack if needed */
2400 if ((bus->sdiodev->state == BRCMF_SDIOD_DATA) &&
2401 bus->txoff && (pktq_len(&bus->txq) < TXLOW)) {
2403 brcmf_txflowblock(bus->sdiodev->dev, false);
2409 static int brcmf_sdio_tx_ctrlframe(struct brcmf_sdio *bus, u8 *frame, u16 len)
2414 struct brcmf_sdio_hdrinfo hd_info = {0};
2417 brcmf_dbg(TRACE, "Enter\n");
2419 /* Back the pointer to make room for bus header */
2420 frame -= bus->tx_hdrlen;
2421 len += bus->tx_hdrlen;
2423 /* Add alignment padding (optional for ctl frames) */
2424 doff = ((unsigned long)frame % bus->head_align);
2428 memset(frame + bus->tx_hdrlen, 0, doff);
2431 /* Round send length to next SDIO block */
2433 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
2434 pad = bus->blocksize - (len % bus->blocksize);
2435 if ((pad > bus->roundup) || (pad >= bus->blocksize))
2437 } else if (len % bus->head_align) {
2438 pad = bus->head_align - (len % bus->head_align);
2442 hd_info.len = len - pad;
2443 hd_info.channel = SDPCM_CONTROL_CHANNEL;
2444 hd_info.dat_offset = doff + bus->tx_hdrlen;
2445 hd_info.seq_num = bus->tx_seq;
2446 hd_info.lastfrm = true;
2447 hd_info.tail_pad = pad;
2448 brcmf_sdio_hdpack(bus, frame, &hd_info);
2451 brcmf_sdio_update_hwhdr(frame, len);
2453 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(),
2454 frame, len, "Tx Frame:\n");
2455 brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() && BRCMF_CTL_ON()) &&
2457 frame, min_t(u16, len, 16), "TxHdr:\n");
2460 ret = brcmf_sdiod_send_buf(bus->sdiodev, frame, len);
2463 brcmf_sdio_txfail(bus);
2465 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQ_WRAP;
2466 } while (ret < 0 && retries++ < TXRETRIES);
2471 static void brcmf_sdio_bus_stop(struct device *dev)
2473 u32 local_hostintmask;
2476 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2477 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2478 struct brcmf_sdio *bus = sdiodev->bus;
2480 brcmf_dbg(TRACE, "Enter\n");
2482 if (bus->watchdog_tsk) {
2483 send_sig(SIGTERM, bus->watchdog_tsk, 1);
2484 kthread_stop(bus->watchdog_tsk);
2485 bus->watchdog_tsk = NULL;
2488 if (sdiodev->state != BRCMF_SDIOD_NOMEDIUM) {
2489 sdio_claim_host(sdiodev->func[1]);
2491 /* Enable clock for device interrupts */
2492 brcmf_sdio_bus_sleep(bus, false, false);
2494 /* Disable and clear interrupts at the chip level also */
2495 w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, hostintmask));
2496 local_hostintmask = bus->hostintmask;
2497 bus->hostintmask = 0;
2499 /* Force backplane clocks to assure F2 interrupt propagates */
2500 saveclk = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
2503 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
2504 (saveclk | SBSDIO_FORCE_HT), &err);
2506 brcmf_err("Failed to force clock for F2: err %d\n",
2509 /* Turn off the bus (F2), free any pending packets */
2510 brcmf_dbg(INTR, "disable SDIO interrupts\n");
2511 sdio_disable_func(sdiodev->func[SDIO_FUNC_2]);
2513 /* Clear any pending interrupts now that F2 is disabled */
2514 w_sdreg32(bus, local_hostintmask,
2515 offsetof(struct sdpcmd_regs, intstatus));
2517 sdio_release_host(sdiodev->func[1]);
2519 /* Clear the data packet queues */
2520 brcmu_pktq_flush(&bus->txq, true, NULL, NULL);
2522 /* Clear any held glomming stuff */
2523 brcmu_pkt_buf_free_skb(bus->glomd);
2524 brcmf_sdio_free_glom(bus);
2526 /* Clear rx control and wake any waiters */
2527 spin_lock_bh(&bus->rxctl_lock);
2529 spin_unlock_bh(&bus->rxctl_lock);
2530 brcmf_sdio_dcmd_resp_wake(bus);
2532 /* Reset some F2 state stuff */
2533 bus->rxskip = false;
2534 bus->tx_seq = bus->rx_seq = 0;
2537 static inline void brcmf_sdio_clrintr(struct brcmf_sdio *bus)
2539 unsigned long flags;
2541 if (bus->sdiodev->oob_irq_requested) {
2542 spin_lock_irqsave(&bus->sdiodev->irq_en_lock, flags);
2543 if (!bus->sdiodev->irq_en && !atomic_read(&bus->ipend)) {
2544 enable_irq(bus->sdiodev->pdata->oob_irq_nr);
2545 bus->sdiodev->irq_en = true;
2547 spin_unlock_irqrestore(&bus->sdiodev->irq_en_lock, flags);
2551 static void atomic_orr(int val, atomic_t *v)
2555 old_val = atomic_read(v);
2556 while (atomic_cmpxchg(v, old_val, val | old_val) != old_val)
2557 old_val = atomic_read(v);
2560 static int brcmf_sdio_intr_rstatus(struct brcmf_sdio *bus)
2562 struct brcmf_core *buscore;
2567 buscore = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV);
2568 addr = buscore->base + offsetof(struct sdpcmd_regs, intstatus);
2570 val = brcmf_sdiod_regrl(bus->sdiodev, addr, &ret);
2571 bus->sdcnt.f1regdata++;
2575 val &= bus->hostintmask;
2576 atomic_set(&bus->fcstate, !!(val & I_HMB_FC_STATE));
2578 /* Clear interrupts */
2580 brcmf_sdiod_regwl(bus->sdiodev, addr, val, &ret);
2581 bus->sdcnt.f1regdata++;
2582 atomic_orr(val, &bus->intstatus);
2588 static void brcmf_sdio_dpc(struct brcmf_sdio *bus)
2591 unsigned long intstatus;
2592 uint txlimit = bus->txbound; /* Tx frames to send before resched */
2593 uint framecnt; /* Temporary counter of tx/rx frames */
2596 brcmf_dbg(TRACE, "Enter\n");
2598 sdio_claim_host(bus->sdiodev->func[1]);
2600 /* If waiting for HTAVAIL, check status */
2601 if (!bus->sr_enabled && bus->clkstate == CLK_PENDING) {
2602 u8 clkctl, devctl = 0;
2605 /* Check for inconsistent device control */
2606 devctl = brcmf_sdiod_regrb(bus->sdiodev,
2607 SBSDIO_DEVICE_CTL, &err);
2610 /* Read CSR, if clock on switch to AVAIL, else ignore */
2611 clkctl = brcmf_sdiod_regrb(bus->sdiodev,
2612 SBSDIO_FUNC1_CHIPCLKCSR, &err);
2614 brcmf_dbg(SDIO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n",
2617 if (SBSDIO_HTAV(clkctl)) {
2618 devctl = brcmf_sdiod_regrb(bus->sdiodev,
2619 SBSDIO_DEVICE_CTL, &err);
2620 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
2621 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
2623 bus->clkstate = CLK_AVAIL;
2627 /* Make sure backplane clock is on */
2628 brcmf_sdio_bus_sleep(bus, false, true);
2630 /* Pending interrupt indicates new device status */
2631 if (atomic_read(&bus->ipend) > 0) {
2632 atomic_set(&bus->ipend, 0);
2633 err = brcmf_sdio_intr_rstatus(bus);
2636 /* Start with leftover status bits */
2637 intstatus = atomic_xchg(&bus->intstatus, 0);
2639 /* Handle flow-control change: read new state in case our ack
2640 * crossed another change interrupt. If change still set, assume
2641 * FC ON for safety, let next loop through do the debounce.
2643 if (intstatus & I_HMB_FC_CHANGE) {
2644 intstatus &= ~I_HMB_FC_CHANGE;
2645 err = w_sdreg32(bus, I_HMB_FC_CHANGE,
2646 offsetof(struct sdpcmd_regs, intstatus));
2648 err = r_sdreg32(bus, &newstatus,
2649 offsetof(struct sdpcmd_regs, intstatus));
2650 bus->sdcnt.f1regdata += 2;
2651 atomic_set(&bus->fcstate,
2652 !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE)));
2653 intstatus |= (newstatus & bus->hostintmask);
2656 /* Handle host mailbox indication */
2657 if (intstatus & I_HMB_HOST_INT) {
2658 intstatus &= ~I_HMB_HOST_INT;
2659 intstatus |= brcmf_sdio_hostmail(bus);
2662 sdio_release_host(bus->sdiodev->func[1]);
2664 /* Generally don't ask for these, can get CRC errors... */
2665 if (intstatus & I_WR_OOSYNC) {
2666 brcmf_err("Dongle reports WR_OOSYNC\n");
2667 intstatus &= ~I_WR_OOSYNC;
2670 if (intstatus & I_RD_OOSYNC) {
2671 brcmf_err("Dongle reports RD_OOSYNC\n");
2672 intstatus &= ~I_RD_OOSYNC;
2675 if (intstatus & I_SBINT) {
2676 brcmf_err("Dongle reports SBINT\n");
2677 intstatus &= ~I_SBINT;
2680 /* Would be active due to wake-wlan in gSPI */
2681 if (intstatus & I_CHIPACTIVE) {
2682 brcmf_dbg(INFO, "Dongle reports CHIPACTIVE\n");
2683 intstatus &= ~I_CHIPACTIVE;
2686 /* Ignore frame indications if rxskip is set */
2688 intstatus &= ~I_HMB_FRAME_IND;
2690 /* On frame indication, read available frames */
2691 if ((intstatus & I_HMB_FRAME_IND) && (bus->clkstate == CLK_AVAIL)) {
2692 brcmf_sdio_readframes(bus, bus->rxbound);
2693 if (!bus->rxpending)
2694 intstatus &= ~I_HMB_FRAME_IND;
2697 /* Keep still-pending events for next scheduling */
2699 atomic_orr(intstatus, &bus->intstatus);
2701 brcmf_sdio_clrintr(bus);
2703 if (bus->ctrl_frame_stat && (bus->clkstate == CLK_AVAIL) &&
2705 sdio_claim_host(bus->sdiodev->func[1]);
2706 if (bus->ctrl_frame_stat) {
2707 err = brcmf_sdio_tx_ctrlframe(bus, bus->ctrl_frame_buf,
2708 bus->ctrl_frame_len);
2709 bus->ctrl_frame_err = err;
2710 bus->ctrl_frame_stat = false;
2712 sdio_release_host(bus->sdiodev->func[1]);
2713 brcmf_sdio_wait_event_wakeup(bus);
2715 /* Send queued frames (limit 1 if rx may still be pending) */
2716 if ((bus->clkstate == CLK_AVAIL) && !atomic_read(&bus->fcstate) &&
2717 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit &&
2719 framecnt = bus->rxpending ? min(txlimit, bus->txminmax) :
2721 brcmf_sdio_sendfromq(bus, framecnt);
2724 if ((bus->sdiodev->state != BRCMF_SDIOD_DATA) || (err != 0)) {
2725 brcmf_err("failed backplane access over SDIO, halting operation\n");
2726 atomic_set(&bus->intstatus, 0);
2727 if (bus->ctrl_frame_stat) {
2728 sdio_claim_host(bus->sdiodev->func[1]);
2729 if (bus->ctrl_frame_stat) {
2730 bus->ctrl_frame_err = -ENODEV;
2731 bus->ctrl_frame_stat = false;
2732 brcmf_sdio_wait_event_wakeup(bus);
2734 sdio_release_host(bus->sdiodev->func[1]);
2736 } else if (atomic_read(&bus->intstatus) ||
2737 atomic_read(&bus->ipend) > 0 ||
2738 (!atomic_read(&bus->fcstate) &&
2739 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) &&
2741 atomic_inc(&bus->dpc_tskcnt);
2745 static struct pktq *brcmf_sdio_bus_gettxq(struct device *dev)
2747 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2748 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2749 struct brcmf_sdio *bus = sdiodev->bus;
2754 static bool brcmf_sdio_prec_enq(struct pktq *q, struct sk_buff *pkt, int prec)
2757 int eprec = -1; /* precedence to evict from */
2759 /* Fast case, precedence queue is not full and we are also not
2760 * exceeding total queue length
2762 if (!pktq_pfull(q, prec) && !pktq_full(q)) {
2763 brcmu_pktq_penq(q, prec, pkt);
2767 /* Determine precedence from which to evict packet, if any */
2768 if (pktq_pfull(q, prec)) {
2770 } else if (pktq_full(q)) {
2771 p = brcmu_pktq_peek_tail(q, &eprec);
2776 /* Evict if needed */
2778 /* Detect queueing to unconfigured precedence */
2780 return false; /* refuse newer (incoming) packet */
2781 /* Evict packet according to discard policy */
2782 p = brcmu_pktq_pdeq_tail(q, eprec);
2784 brcmf_err("brcmu_pktq_pdeq_tail() failed\n");
2785 brcmu_pkt_buf_free_skb(p);
2789 p = brcmu_pktq_penq(q, prec, pkt);
2791 brcmf_err("brcmu_pktq_penq() failed\n");
2796 static int brcmf_sdio_bus_txdata(struct device *dev, struct sk_buff *pkt)
2800 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2801 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2802 struct brcmf_sdio *bus = sdiodev->bus;
2804 brcmf_dbg(TRACE, "Enter: pkt: data %p len %d\n", pkt->data, pkt->len);
2806 /* Add space for the header */
2807 skb_push(pkt, bus->tx_hdrlen);
2808 /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */
2810 prec = prio2prec((pkt->priority & PRIOMASK));
2812 /* Check for existing queue, current flow-control,
2813 pending event, or pending clock */
2814 brcmf_dbg(TRACE, "deferring pktq len %d\n", pktq_len(&bus->txq));
2815 bus->sdcnt.fcqueued++;
2817 /* Priority based enq */
2818 spin_lock_bh(&bus->txq_lock);
2819 /* reset bus_flags in packet cb */
2820 *(u16 *)(pkt->cb) = 0;
2821 if (!brcmf_sdio_prec_enq(&bus->txq, pkt, prec)) {
2822 skb_pull(pkt, bus->tx_hdrlen);
2823 brcmf_err("out of bus->txq !!!\n");
2829 if (pktq_len(&bus->txq) >= TXHI) {
2831 brcmf_txflowblock(dev, true);
2833 spin_unlock_bh(&bus->txq_lock);
2836 if (pktq_plen(&bus->txq, prec) > qcount[prec])
2837 qcount[prec] = pktq_plen(&bus->txq, prec);
2840 brcmf_sdio_trigger_dpc(bus);
2845 #define CONSOLE_LINE_MAX 192
2847 static int brcmf_sdio_readconsole(struct brcmf_sdio *bus)
2849 struct brcmf_console *c = &bus->console;
2850 u8 line[CONSOLE_LINE_MAX], ch;
2854 /* Don't do anything until FWREADY updates console address */
2855 if (bus->console_addr == 0)
2858 /* Read console log struct */
2859 addr = bus->console_addr + offsetof(struct rte_console, log_le);
2860 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&c->log_le,
2865 /* Allocate console buffer (one time only) */
2866 if (c->buf == NULL) {
2867 c->bufsize = le32_to_cpu(c->log_le.buf_size);
2868 c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
2873 idx = le32_to_cpu(c->log_le.idx);
2875 /* Protect against corrupt value */
2876 if (idx > c->bufsize)
2879 /* Skip reading the console buffer if the index pointer
2884 /* Read the console buffer */
2885 addr = le32_to_cpu(c->log_le.buf);
2886 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, c->buf, c->bufsize);
2890 while (c->last != idx) {
2891 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
2892 if (c->last == idx) {
2893 /* This would output a partial line.
2895 * the buffer pointer and output this
2896 * line next time around.
2901 c->last = c->bufsize - n;
2904 ch = c->buf[c->last];
2905 c->last = (c->last + 1) % c->bufsize;
2912 if (line[n - 1] == '\r')
2915 pr_debug("CONSOLE: %s\n", line);
2925 brcmf_sdio_bus_txctl(struct device *dev, unsigned char *msg, uint msglen)
2927 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2928 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2929 struct brcmf_sdio *bus = sdiodev->bus;
2932 brcmf_dbg(TRACE, "Enter\n");
2935 bus->ctrl_frame_buf = msg;
2936 bus->ctrl_frame_len = msglen;
2937 bus->ctrl_frame_stat = true;
2939 brcmf_sdio_trigger_dpc(bus);
2940 wait_event_interruptible_timeout(bus->ctrl_wait, !bus->ctrl_frame_stat,
2941 msecs_to_jiffies(CTL_DONE_TIMEOUT));
2943 if (bus->ctrl_frame_stat) {
2944 sdio_claim_host(bus->sdiodev->func[1]);
2945 if (bus->ctrl_frame_stat) {
2946 brcmf_dbg(SDIO, "ctrl_frame timeout\n");
2947 bus->ctrl_frame_stat = false;
2950 sdio_release_host(bus->sdiodev->func[1]);
2953 brcmf_dbg(SDIO, "ctrl_frame complete, err=%d\n",
2954 bus->ctrl_frame_err);
2955 ret = bus->ctrl_frame_err;
2959 bus->sdcnt.tx_ctlerrs++;
2961 bus->sdcnt.tx_ctlpkts++;
2967 static int brcmf_sdio_dump_console(struct seq_file *seq, struct brcmf_sdio *bus,
2968 struct sdpcm_shared *sh)
2970 u32 addr, console_ptr, console_size, console_index;
2971 char *conbuf = NULL;
2975 /* obtain console information from device memory */
2976 addr = sh->console_addr + offsetof(struct rte_console, log_le);
2977 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
2978 (u8 *)&sh_val, sizeof(u32));
2981 console_ptr = le32_to_cpu(sh_val);
2983 addr = sh->console_addr + offsetof(struct rte_console, log_le.buf_size);
2984 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
2985 (u8 *)&sh_val, sizeof(u32));
2988 console_size = le32_to_cpu(sh_val);
2990 addr = sh->console_addr + offsetof(struct rte_console, log_le.idx);
2991 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
2992 (u8 *)&sh_val, sizeof(u32));
2995 console_index = le32_to_cpu(sh_val);
2997 /* allocate buffer for console data */
2998 if (console_size <= CONSOLE_BUFFER_MAX)
2999 conbuf = vzalloc(console_size+1);
3004 /* obtain the console data from device */
3005 conbuf[console_size] = '\0';
3006 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, console_ptr, (u8 *)conbuf,
3011 rv = seq_write(seq, conbuf + console_index,
3012 console_size - console_index);
3016 if (console_index > 0)
3017 rv = seq_write(seq, conbuf, console_index - 1);
3024 static int brcmf_sdio_trap_info(struct seq_file *seq, struct brcmf_sdio *bus,
3025 struct sdpcm_shared *sh)
3028 struct brcmf_trap_info tr;
3030 if ((sh->flags & SDPCM_SHARED_TRAP) == 0) {
3031 brcmf_dbg(INFO, "no trap in firmware\n");
3035 error = brcmf_sdiod_ramrw(bus->sdiodev, false, sh->trap_addr, (u8 *)&tr,
3036 sizeof(struct brcmf_trap_info));
3041 "dongle trap info: type 0x%x @ epc 0x%08x\n"
3042 " cpsr 0x%08x spsr 0x%08x sp 0x%08x\n"
3043 " lr 0x%08x pc 0x%08x offset 0x%x\n"
3044 " r0 0x%08x r1 0x%08x r2 0x%08x r3 0x%08x\n"
3045 " r4 0x%08x r5 0x%08x r6 0x%08x r7 0x%08x\n",
3046 le32_to_cpu(tr.type), le32_to_cpu(tr.epc),
3047 le32_to_cpu(tr.cpsr), le32_to_cpu(tr.spsr),
3048 le32_to_cpu(tr.r13), le32_to_cpu(tr.r14),
3049 le32_to_cpu(tr.pc), sh->trap_addr,
3050 le32_to_cpu(tr.r0), le32_to_cpu(tr.r1),
3051 le32_to_cpu(tr.r2), le32_to_cpu(tr.r3),
3052 le32_to_cpu(tr.r4), le32_to_cpu(tr.r5),
3053 le32_to_cpu(tr.r6), le32_to_cpu(tr.r7));
3058 static int brcmf_sdio_assert_info(struct seq_file *seq, struct brcmf_sdio *bus,
3059 struct sdpcm_shared *sh)
3062 char file[80] = "?";
3063 char expr[80] = "<???>";
3065 if ((sh->flags & SDPCM_SHARED_ASSERT_BUILT) == 0) {
3066 brcmf_dbg(INFO, "firmware not built with -assert\n");
3068 } else if ((sh->flags & SDPCM_SHARED_ASSERT) == 0) {
3069 brcmf_dbg(INFO, "no assert in dongle\n");
3073 sdio_claim_host(bus->sdiodev->func[1]);
3074 if (sh->assert_file_addr != 0) {
3075 error = brcmf_sdiod_ramrw(bus->sdiodev, false,
3076 sh->assert_file_addr, (u8 *)file, 80);
3080 if (sh->assert_exp_addr != 0) {
3081 error = brcmf_sdiod_ramrw(bus->sdiodev, false,
3082 sh->assert_exp_addr, (u8 *)expr, 80);
3086 sdio_release_host(bus->sdiodev->func[1]);
3088 seq_printf(seq, "dongle assert: %s:%d: assert(%s)\n",
3089 file, sh->assert_line, expr);
3093 static int brcmf_sdio_checkdied(struct brcmf_sdio *bus)
3096 struct sdpcm_shared sh;
3098 error = brcmf_sdio_readshared(bus, &sh);
3103 if ((sh.flags & SDPCM_SHARED_ASSERT_BUILT) == 0)
3104 brcmf_dbg(INFO, "firmware not built with -assert\n");
3105 else if (sh.flags & SDPCM_SHARED_ASSERT)
3106 brcmf_err("assertion in dongle\n");
3108 if (sh.flags & SDPCM_SHARED_TRAP)
3109 brcmf_err("firmware trap in dongle\n");
3114 static int brcmf_sdio_died_dump(struct seq_file *seq, struct brcmf_sdio *bus)
3117 struct sdpcm_shared sh;
3119 error = brcmf_sdio_readshared(bus, &sh);
3123 error = brcmf_sdio_assert_info(seq, bus, &sh);
3127 error = brcmf_sdio_trap_info(seq, bus, &sh);
3131 error = brcmf_sdio_dump_console(seq, bus, &sh);
3137 static int brcmf_sdio_forensic_read(struct seq_file *seq, void *data)
3139 struct brcmf_bus *bus_if = dev_get_drvdata(seq->private);
3140 struct brcmf_sdio *bus = bus_if->bus_priv.sdio->bus;
3142 return brcmf_sdio_died_dump(seq, bus);
3145 static int brcmf_debugfs_sdio_count_read(struct seq_file *seq, void *data)
3147 struct brcmf_bus *bus_if = dev_get_drvdata(seq->private);
3148 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3149 struct brcmf_sdio_count *sdcnt = &sdiodev->bus->sdcnt;
3152 "intrcount: %u\nlastintrs: %u\n"
3153 "pollcnt: %u\nregfails: %u\n"
3154 "tx_sderrs: %u\nfcqueued: %u\n"
3155 "rxrtx: %u\nrx_toolong: %u\n"
3156 "rxc_errors: %u\nrx_hdrfail: %u\n"
3157 "rx_badhdr: %u\nrx_badseq: %u\n"
3158 "fc_rcvd: %u\nfc_xoff: %u\n"
3159 "fc_xon: %u\nrxglomfail: %u\n"
3160 "rxglomframes: %u\nrxglompkts: %u\n"
3161 "f2rxhdrs: %u\nf2rxdata: %u\n"
3162 "f2txdata: %u\nf1regdata: %u\n"
3163 "tickcnt: %u\ntx_ctlerrs: %lu\n"
3164 "tx_ctlpkts: %lu\nrx_ctlerrs: %lu\n"
3165 "rx_ctlpkts: %lu\nrx_readahead: %lu\n",
3166 sdcnt->intrcount, sdcnt->lastintrs,
3167 sdcnt->pollcnt, sdcnt->regfails,
3168 sdcnt->tx_sderrs, sdcnt->fcqueued,
3169 sdcnt->rxrtx, sdcnt->rx_toolong,
3170 sdcnt->rxc_errors, sdcnt->rx_hdrfail,
3171 sdcnt->rx_badhdr, sdcnt->rx_badseq,
3172 sdcnt->fc_rcvd, sdcnt->fc_xoff,
3173 sdcnt->fc_xon, sdcnt->rxglomfail,
3174 sdcnt->rxglomframes, sdcnt->rxglompkts,
3175 sdcnt->f2rxhdrs, sdcnt->f2rxdata,
3176 sdcnt->f2txdata, sdcnt->f1regdata,
3177 sdcnt->tickcnt, sdcnt->tx_ctlerrs,
3178 sdcnt->tx_ctlpkts, sdcnt->rx_ctlerrs,
3179 sdcnt->rx_ctlpkts, sdcnt->rx_readahead_cnt);
3184 static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus)
3186 struct brcmf_pub *drvr = bus->sdiodev->bus_if->drvr;
3187 struct dentry *dentry = brcmf_debugfs_get_devdir(drvr);
3189 if (IS_ERR_OR_NULL(dentry))
3192 brcmf_debugfs_add_entry(drvr, "forensics", brcmf_sdio_forensic_read);
3193 brcmf_debugfs_add_entry(drvr, "counters",
3194 brcmf_debugfs_sdio_count_read);
3195 debugfs_create_u32("console_interval", 0644, dentry,
3196 &bus->console_interval);
3199 static int brcmf_sdio_checkdied(struct brcmf_sdio *bus)
3204 static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus)
3210 brcmf_sdio_bus_rxctl(struct device *dev, unsigned char *msg, uint msglen)
3216 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3217 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3218 struct brcmf_sdio *bus = sdiodev->bus;
3220 brcmf_dbg(TRACE, "Enter\n");
3222 /* Wait until control frame is available */
3223 timeleft = brcmf_sdio_dcmd_resp_wait(bus, &bus->rxlen, &pending);
3225 spin_lock_bh(&bus->rxctl_lock);
3227 memcpy(msg, bus->rxctl, min(msglen, rxlen));
3229 buf = bus->rxctl_orig;
3230 bus->rxctl_orig = NULL;
3232 spin_unlock_bh(&bus->rxctl_lock);
3236 brcmf_dbg(CTL, "resumed on rxctl frame, got %d expected %d\n",
3238 } else if (timeleft == 0) {
3239 brcmf_err("resumed on timeout\n");
3240 brcmf_sdio_checkdied(bus);
3241 } else if (pending) {
3242 brcmf_dbg(CTL, "cancelled\n");
3243 return -ERESTARTSYS;
3245 brcmf_dbg(CTL, "resumed for unknown reason?\n");
3246 brcmf_sdio_checkdied(bus);
3250 bus->sdcnt.rx_ctlpkts++;
3252 bus->sdcnt.rx_ctlerrs++;
3254 return rxlen ? (int)rxlen : -ETIMEDOUT;
3259 brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr,
3260 u8 *ram_data, uint ram_sz)
3269 /* read back and verify */
3270 brcmf_dbg(INFO, "Compare RAM dl & ul at 0x%08x; size=%d\n", ram_addr,
3272 ram_cmp = kmalloc(MEMBLOCK, GFP_KERNEL);
3273 /* do not proceed while no memory but */
3279 while (offset < ram_sz) {
3280 len = ((offset + MEMBLOCK) < ram_sz) ? MEMBLOCK :
3282 err = brcmf_sdiod_ramrw(sdiodev, false, address, ram_cmp, len);
3284 brcmf_err("error %d on reading %d membytes at 0x%08x\n",
3288 } else if (memcmp(ram_cmp, &ram_data[offset], len)) {
3289 brcmf_err("Downloaded RAM image is corrupted, block offset is %d, len is %d\n",
3304 brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr,
3305 u8 *ram_data, uint ram_sz)
3311 static int brcmf_sdio_download_code_file(struct brcmf_sdio *bus,
3312 const struct firmware *fw)
3316 brcmf_dbg(TRACE, "Enter\n");
3318 err = brcmf_sdiod_ramrw(bus->sdiodev, true, bus->ci->rambase,
3319 (u8 *)fw->data, fw->size);
3321 brcmf_err("error %d on writing %d membytes at 0x%08x\n",
3322 err, (int)fw->size, bus->ci->rambase);
3323 else if (!brcmf_sdio_verifymemory(bus->sdiodev, bus->ci->rambase,
3324 (u8 *)fw->data, fw->size))
3330 static int brcmf_sdio_download_nvram(struct brcmf_sdio *bus,
3331 void *vars, u32 varsz)
3336 brcmf_dbg(TRACE, "Enter\n");
3338 address = bus->ci->ramsize - varsz + bus->ci->rambase;
3339 err = brcmf_sdiod_ramrw(bus->sdiodev, true, address, vars, varsz);
3341 brcmf_err("error %d on writing %d nvram bytes at 0x%08x\n",
3342 err, varsz, address);
3343 else if (!brcmf_sdio_verifymemory(bus->sdiodev, address, vars, varsz))
3349 static int brcmf_sdio_download_firmware(struct brcmf_sdio *bus,
3350 const struct firmware *fw,
3351 void *nvram, u32 nvlen)
3353 int bcmerror = -EFAULT;
3356 sdio_claim_host(bus->sdiodev->func[1]);
3357 brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
3359 rstvec = get_unaligned_le32(fw->data);
3360 brcmf_dbg(SDIO, "firmware rstvec: %x\n", rstvec);
3362 bcmerror = brcmf_sdio_download_code_file(bus, fw);
3363 release_firmware(fw);
3365 brcmf_err("dongle image file download failed\n");
3366 brcmf_fw_nvram_free(nvram);
3370 bcmerror = brcmf_sdio_download_nvram(bus, nvram, nvlen);
3371 brcmf_fw_nvram_free(nvram);
3373 brcmf_err("dongle nvram file download failed\n");
3377 /* Take arm out of reset */
3378 if (!brcmf_chip_set_active(bus->ci, rstvec)) {
3379 brcmf_err("error getting out of ARM core reset\n");
3383 /* Allow full data communication using DPC from now on. */
3384 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DATA);
3388 brcmf_sdio_clkctl(bus, CLK_SDONLY, false);
3389 sdio_release_host(bus->sdiodev->func[1]);
3393 static void brcmf_sdio_sr_init(struct brcmf_sdio *bus)
3398 brcmf_dbg(TRACE, "Enter\n");
3400 val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, &err);
3402 brcmf_err("error reading SBSDIO_FUNC1_WAKEUPCTRL\n");
3406 val |= 1 << SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT;
3407 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, val, &err);
3409 brcmf_err("error writing SBSDIO_FUNC1_WAKEUPCTRL\n");
3413 /* Add CMD14 Support */
3414 brcmf_sdiod_regwb(bus->sdiodev, SDIO_CCCR_BRCM_CARDCAP,
3415 (SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT |
3416 SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT),
3419 brcmf_err("error writing SDIO_CCCR_BRCM_CARDCAP\n");
3423 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
3424 SBSDIO_FORCE_HT, &err);
3426 brcmf_err("error writing SBSDIO_FUNC1_CHIPCLKCSR\n");
3431 bus->sr_enabled = true;
3432 brcmf_dbg(INFO, "SR enabled\n");
3435 /* enable KSO bit */
3436 static int brcmf_sdio_kso_init(struct brcmf_sdio *bus)
3441 brcmf_dbg(TRACE, "Enter\n");
3443 /* KSO bit added in SDIO core rev 12 */
3444 if (brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV)->rev < 12)
3447 val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, &err);
3449 brcmf_err("error reading SBSDIO_FUNC1_SLEEPCSR\n");
3453 if (!(val & SBSDIO_FUNC1_SLEEPCSR_KSO_MASK)) {
3454 val |= (SBSDIO_FUNC1_SLEEPCSR_KSO_EN <<
3455 SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT);
3456 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
3459 brcmf_err("error writing SBSDIO_FUNC1_SLEEPCSR\n");
3468 static int brcmf_sdio_bus_preinit(struct device *dev)
3470 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3471 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3472 struct brcmf_sdio *bus = sdiodev->bus;
3477 /* the commands below use the terms tx and rx from
3478 * a device perspective, ie. bus:txglom affects the
3479 * bus transfers from device to host.
3481 if (brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV)->rev < 12) {
3482 /* for sdio core rev < 12, disable txgloming */
3484 err = brcmf_iovar_data_set(dev, "bus:txglom", &value,
3487 /* otherwise, set txglomalign */
3490 value = sdiodev->pdata->sd_sgentry_align;
3491 /* SDIO ADMA requires at least 32 bit alignment */
3492 value = max_t(u32, value, 4);
3493 err = brcmf_iovar_data_set(dev, "bus:txglomalign", &value,
3500 bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN;
3501 if (sdiodev->sg_support) {
3502 bus->txglom = false;
3504 pad_size = bus->sdiodev->func[2]->cur_blksize << 1;
3505 err = brcmf_iovar_data_set(bus->sdiodev->dev, "bus:rxglom",
3506 &value, sizeof(u32));
3508 /* bus:rxglom is allowed to fail */
3512 bus->tx_hdrlen += SDPCM_HWEXT_LEN;
3515 brcmf_bus_add_txhdrlen(bus->sdiodev->dev, bus->tx_hdrlen);
3521 void brcmf_sdio_trigger_dpc(struct brcmf_sdio *bus)
3523 if (atomic_read(&bus->dpc_tskcnt) == 0) {
3524 atomic_inc(&bus->dpc_tskcnt);
3525 queue_work(bus->brcmf_wq, &bus->datawork);
3529 void brcmf_sdio_isr(struct brcmf_sdio *bus)
3531 brcmf_dbg(TRACE, "Enter\n");
3534 brcmf_err("bus is null pointer, exiting\n");
3538 if (bus->sdiodev->state != BRCMF_SDIOD_DATA) {
3539 brcmf_err("bus is down. we have nothing to do\n");
3542 /* Count the interrupt call */
3543 bus->sdcnt.intrcount++;
3545 atomic_set(&bus->ipend, 1);
3547 if (brcmf_sdio_intr_rstatus(bus)) {
3548 brcmf_err("failed backplane access\n");
3551 /* Disable additional interrupts (is this needed now)? */
3553 brcmf_err("isr w/o interrupt configured!\n");
3555 atomic_inc(&bus->dpc_tskcnt);
3556 queue_work(bus->brcmf_wq, &bus->datawork);
3559 static void brcmf_sdio_bus_watchdog(struct brcmf_sdio *bus)
3561 brcmf_dbg(TIMER, "Enter\n");
3563 /* Poll period: check device if appropriate. */
3564 if (!bus->sr_enabled &&
3565 bus->poll && (++bus->polltick >= bus->pollrate)) {
3568 /* Reset poll tick */
3571 /* Check device if no interrupts */
3573 (bus->sdcnt.intrcount == bus->sdcnt.lastintrs)) {
3575 if (atomic_read(&bus->dpc_tskcnt) == 0) {
3578 sdio_claim_host(bus->sdiodev->func[1]);
3579 devpend = brcmf_sdiod_regrb(bus->sdiodev,
3582 sdio_release_host(bus->sdiodev->func[1]);
3583 intstatus = devpend & (INTR_STATUS_FUNC1 |
3587 /* If there is something, make like the ISR and
3590 bus->sdcnt.pollcnt++;
3591 atomic_set(&bus->ipend, 1);
3593 atomic_inc(&bus->dpc_tskcnt);
3594 queue_work(bus->brcmf_wq, &bus->datawork);
3598 /* Update interrupt tracking */
3599 bus->sdcnt.lastintrs = bus->sdcnt.intrcount;
3602 /* Poll for console output periodically */
3603 if (bus->sdiodev->state == BRCMF_SDIOD_DATA &&
3604 bus->console_interval != 0) {
3605 bus->console.count += BRCMF_WD_POLL_MS;
3606 if (bus->console.count >= bus->console_interval) {
3607 bus->console.count -= bus->console_interval;
3608 sdio_claim_host(bus->sdiodev->func[1]);
3609 /* Make sure backplane clock is on */
3610 brcmf_sdio_bus_sleep(bus, false, false);
3611 if (brcmf_sdio_readconsole(bus) < 0)
3613 bus->console_interval = 0;
3614 sdio_release_host(bus->sdiodev->func[1]);
3619 /* On idle timeout clear activity flag and/or turn off clock */
3620 if ((atomic_read(&bus->dpc_tskcnt) == 0) &&
3621 (atomic_read(&bus->dpc_running) == 0) &&
3622 (bus->idletime > 0) && (bus->clkstate == CLK_AVAIL)) {
3624 if (bus->idlecount > bus->idletime) {
3625 brcmf_dbg(SDIO, "idle\n");
3626 sdio_claim_host(bus->sdiodev->func[1]);
3627 brcmf_sdio_wd_timer(bus, 0);
3629 brcmf_sdio_bus_sleep(bus, true, false);
3630 sdio_release_host(bus->sdiodev->func[1]);
3637 static void brcmf_sdio_dataworker(struct work_struct *work)
3639 struct brcmf_sdio *bus = container_of(work, struct brcmf_sdio,
3642 while (atomic_read(&bus->dpc_tskcnt)) {
3643 atomic_set(&bus->dpc_running, 1);
3644 atomic_set(&bus->dpc_tskcnt, 0);
3645 brcmf_sdio_dpc(bus);
3647 atomic_set(&bus->dpc_running, 0);
3649 if (brcmf_sdiod_freezing(bus->sdiodev)) {
3650 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DOWN);
3651 brcmf_sdiod_try_freeze(bus->sdiodev);
3652 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DATA);
3657 brcmf_sdio_drivestrengthinit(struct brcmf_sdio_dev *sdiodev,
3658 struct brcmf_chip *ci, u32 drivestrength)
3660 const struct sdiod_drive_str *str_tab = NULL;
3665 u32 drivestrength_sel = 0;
3669 if (!(ci->cc_caps & CC_CAP_PMU))
3672 switch (SDIOD_DRVSTR_KEY(ci->chip, ci->pmurev)) {
3673 case SDIOD_DRVSTR_KEY(BRCM_CC_4330_CHIP_ID, 12):
3674 str_tab = sdiod_drvstr_tab1_1v8;
3675 str_mask = 0x00003800;
3678 case SDIOD_DRVSTR_KEY(BRCM_CC_4334_CHIP_ID, 17):
3679 str_tab = sdiod_drvstr_tab6_1v8;
3680 str_mask = 0x00001800;
3683 case SDIOD_DRVSTR_KEY(BRCM_CC_43143_CHIP_ID, 17):
3684 /* note: 43143 does not support tristate */
3685 i = ARRAY_SIZE(sdiod_drvstr_tab2_3v3) - 1;
3686 if (drivestrength >= sdiod_drvstr_tab2_3v3[i].strength) {
3687 str_tab = sdiod_drvstr_tab2_3v3;
3688 str_mask = 0x00000007;
3691 brcmf_err("Invalid SDIO Drive strength for chip %s, strength=%d\n",
3692 ci->name, drivestrength);
3694 case SDIOD_DRVSTR_KEY(BRCM_CC_43362_CHIP_ID, 13):
3695 str_tab = sdiod_drive_strength_tab5_1v8;
3696 str_mask = 0x00003800;
3700 brcmf_err("No SDIO Drive strength init done for chip %s rev %d pmurev %d\n",
3701 ci->name, ci->chiprev, ci->pmurev);
3705 if (str_tab != NULL) {
3706 for (i = 0; str_tab[i].strength != 0; i++) {
3707 if (drivestrength >= str_tab[i].strength) {
3708 drivestrength_sel = str_tab[i].sel;
3712 base = brcmf_chip_get_chipcommon(ci)->base;
3713 addr = CORE_CC_REG(base, chipcontrol_addr);
3714 brcmf_sdiod_regwl(sdiodev, addr, 1, NULL);
3715 cc_data_temp = brcmf_sdiod_regrl(sdiodev, addr, NULL);
3716 cc_data_temp &= ~str_mask;
3717 drivestrength_sel <<= str_shift;
3718 cc_data_temp |= drivestrength_sel;
3719 brcmf_sdiod_regwl(sdiodev, addr, cc_data_temp, NULL);
3721 brcmf_dbg(INFO, "SDIO: %d mA (req=%d mA) drive strength selected, set to 0x%08x\n",
3722 str_tab[i].strength, drivestrength, cc_data_temp);
3726 static int brcmf_sdio_buscoreprep(void *ctx)
3728 struct brcmf_sdio_dev *sdiodev = ctx;
3732 /* Try forcing SDIO core to do ALPAvail request only */
3733 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;
3734 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
3736 brcmf_err("error writing for HT off\n");
3740 /* If register supported, wait for ALPAvail and then force ALP */
3741 /* This may take up to 15 milliseconds */
3742 clkval = brcmf_sdiod_regrb(sdiodev,
3743 SBSDIO_FUNC1_CHIPCLKCSR, NULL);
3745 if ((clkval & ~SBSDIO_AVBITS) != clkset) {
3746 brcmf_err("ChipClkCSR access: wrote 0x%02x read 0x%02x\n",
3751 SPINWAIT(((clkval = brcmf_sdiod_regrb(sdiodev,
3752 SBSDIO_FUNC1_CHIPCLKCSR, NULL)),
3753 !SBSDIO_ALPAV(clkval)),
3754 PMU_MAX_TRANSITION_DLY);
3755 if (!SBSDIO_ALPAV(clkval)) {
3756 brcmf_err("timeout on ALPAV wait, clkval 0x%02x\n",
3761 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP;
3762 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
3765 /* Also, disable the extra SDIO pull-ups */
3766 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_SDIOPULLUP, 0, NULL);
3771 static void brcmf_sdio_buscore_activate(void *ctx, struct brcmf_chip *chip,
3774 struct brcmf_sdio_dev *sdiodev = ctx;
3775 struct brcmf_core *core;
3778 /* clear all interrupts */
3779 core = brcmf_chip_get_core(chip, BCMA_CORE_SDIO_DEV);
3780 reg_addr = core->base + offsetof(struct sdpcmd_regs, intstatus);
3781 brcmf_sdiod_regwl(sdiodev, reg_addr, 0xFFFFFFFF, NULL);
3784 /* Write reset vector to address 0 */
3785 brcmf_sdiod_ramrw(sdiodev, true, 0, (void *)&rstvec,
3789 static u32 brcmf_sdio_buscore_read32(void *ctx, u32 addr)
3791 struct brcmf_sdio_dev *sdiodev = ctx;
3794 val = brcmf_sdiod_regrl(sdiodev, addr, NULL);
3795 if (sdiodev->func[0]->device == SDIO_DEVICE_ID_BROADCOM_4335_4339 &&
3796 addr == CORE_CC_REG(SI_ENUM_BASE, chipid)) {
3797 rev = (val & CID_REV_MASK) >> CID_REV_SHIFT;
3799 val &= ~CID_ID_MASK;
3800 val |= BRCM_CC_4339_CHIP_ID;
3806 static void brcmf_sdio_buscore_write32(void *ctx, u32 addr, u32 val)
3808 struct brcmf_sdio_dev *sdiodev = ctx;
3810 brcmf_sdiod_regwl(sdiodev, addr, val, NULL);
3813 static const struct brcmf_buscore_ops brcmf_sdio_buscore_ops = {
3814 .prepare = brcmf_sdio_buscoreprep,
3815 .activate = brcmf_sdio_buscore_activate,
3816 .read32 = brcmf_sdio_buscore_read32,
3817 .write32 = brcmf_sdio_buscore_write32,
3821 brcmf_sdio_probe_attach(struct brcmf_sdio *bus)
3829 sdio_claim_host(bus->sdiodev->func[1]);
3831 pr_debug("F1 signature read @0x18000000=0x%4x\n",
3832 brcmf_sdiod_regrl(bus->sdiodev, SI_ENUM_BASE, NULL));
3835 * Force PLL off until brcmf_chip_attach()
3836 * programs PLL control regs
3839 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
3840 BRCMF_INIT_CLKCTL1, &err);
3842 clkctl = brcmf_sdiod_regrb(bus->sdiodev,
3843 SBSDIO_FUNC1_CHIPCLKCSR, &err);
3845 if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) {
3846 brcmf_err("ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n",
3847 err, BRCMF_INIT_CLKCTL1, clkctl);
3851 bus->ci = brcmf_chip_attach(bus->sdiodev, &brcmf_sdio_buscore_ops);
3852 if (IS_ERR(bus->ci)) {
3853 brcmf_err("brcmf_chip_attach failed!\n");
3858 if (brcmf_sdio_kso_init(bus)) {
3859 brcmf_err("error enabling KSO\n");
3863 if ((bus->sdiodev->pdata) && (bus->sdiodev->pdata->drive_strength))
3864 drivestrength = bus->sdiodev->pdata->drive_strength;
3866 drivestrength = DEFAULT_SDIO_DRIVE_STRENGTH;
3867 brcmf_sdio_drivestrengthinit(bus->sdiodev, bus->ci, drivestrength);
3869 /* Set card control so an SDIO card reset does a WLAN backplane reset */
3870 reg_val = brcmf_sdiod_regrb(bus->sdiodev,
3871 SDIO_CCCR_BRCM_CARDCTRL, &err);
3875 reg_val |= SDIO_CCCR_BRCM_CARDCTRL_WLANRESET;
3877 brcmf_sdiod_regwb(bus->sdiodev,
3878 SDIO_CCCR_BRCM_CARDCTRL, reg_val, &err);
3882 /* set PMUControl so a backplane reset does PMU state reload */
3883 reg_addr = CORE_CC_REG(brcmf_chip_get_chipcommon(bus->ci)->base,
3885 reg_val = brcmf_sdiod_regrl(bus->sdiodev, reg_addr, &err);
3889 reg_val |= (BCMA_CC_PMU_CTL_RES_RELOAD << BCMA_CC_PMU_CTL_RES_SHIFT);
3891 brcmf_sdiod_regwl(bus->sdiodev, reg_addr, reg_val, &err);
3895 sdio_release_host(bus->sdiodev->func[1]);
3897 brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
3899 /* allocate header buffer */
3900 bus->hdrbuf = kzalloc(MAX_HDR_READ + bus->head_align, GFP_KERNEL);
3903 /* Locate an appropriately-aligned portion of hdrbuf */
3904 bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0],
3907 /* Set the poll and/or interrupt flags */
3916 sdio_release_host(bus->sdiodev->func[1]);
3921 brcmf_sdio_watchdog_thread(void *data)
3923 struct brcmf_sdio *bus = (struct brcmf_sdio *)data;
3926 allow_signal(SIGTERM);
3927 /* Run until signal received */
3928 brcmf_sdiod_freezer_count(bus->sdiodev);
3930 if (kthread_should_stop())
3932 brcmf_sdiod_freezer_uncount(bus->sdiodev);
3933 wait = wait_for_completion_interruptible(&bus->watchdog_wait);
3934 brcmf_sdiod_freezer_count(bus->sdiodev);
3935 brcmf_sdiod_try_freeze(bus->sdiodev);
3937 brcmf_sdio_bus_watchdog(bus);
3938 /* Count the tick for reference */
3939 bus->sdcnt.tickcnt++;
3940 reinit_completion(&bus->watchdog_wait);
3948 brcmf_sdio_watchdog(unsigned long data)
3950 struct brcmf_sdio *bus = (struct brcmf_sdio *)data;
3952 if (bus->watchdog_tsk) {
3953 complete(&bus->watchdog_wait);
3954 /* Reschedule the watchdog */
3955 if (bus->wd_timer_valid)
3956 mod_timer(&bus->timer,
3957 jiffies + msecs_to_jiffies(BRCMF_WD_POLL_MS));
3961 static struct brcmf_bus_ops brcmf_sdio_bus_ops = {
3962 .stop = brcmf_sdio_bus_stop,
3963 .preinit = brcmf_sdio_bus_preinit,
3964 .txdata = brcmf_sdio_bus_txdata,
3965 .txctl = brcmf_sdio_bus_txctl,
3966 .rxctl = brcmf_sdio_bus_rxctl,
3967 .gettxq = brcmf_sdio_bus_gettxq,
3968 .wowl_config = brcmf_sdio_wowl_config
3971 static void brcmf_sdio_firmware_callback(struct device *dev,
3972 const struct firmware *code,
3973 void *nvram, u32 nvram_len)
3975 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3976 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3977 struct brcmf_sdio *bus = sdiodev->bus;
3981 brcmf_dbg(TRACE, "Enter: dev=%s\n", dev_name(dev));
3986 /* try to download image and nvram to the dongle */
3987 bus->alp_only = true;
3988 err = brcmf_sdio_download_firmware(bus, code, nvram, nvram_len);
3991 bus->alp_only = false;
3993 /* Start the watchdog timer */
3994 bus->sdcnt.tickcnt = 0;
3995 brcmf_sdio_wd_timer(bus, BRCMF_WD_POLL_MS);
3997 sdio_claim_host(sdiodev->func[1]);
3999 /* Make sure backplane clock is on, needed to generate F2 interrupt */
4000 brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
4001 if (bus->clkstate != CLK_AVAIL)
4004 /* Force clocks on backplane to be sure F2 interrupt propagates */
4005 saveclk = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, &err);
4007 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
4008 (saveclk | SBSDIO_FORCE_HT), &err);
4011 brcmf_err("Failed to force clock for F2: err %d\n", err);
4015 /* Enable function 2 (frame transfers) */
4016 w_sdreg32(bus, SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT,
4017 offsetof(struct sdpcmd_regs, tosbmailboxdata));
4018 err = sdio_enable_func(sdiodev->func[SDIO_FUNC_2]);
4021 brcmf_dbg(INFO, "enable F2: err=%d\n", err);
4023 /* If F2 successfully enabled, set core and enable interrupts */
4025 /* Set up the interrupt mask and enable interrupts */
4026 bus->hostintmask = HOSTINTMASK;
4027 w_sdreg32(bus, bus->hostintmask,
4028 offsetof(struct sdpcmd_regs, hostintmask));
4030 brcmf_sdiod_regwb(sdiodev, SBSDIO_WATERMARK, 8, &err);
4032 /* Disable F2 again */
4033 sdio_disable_func(sdiodev->func[SDIO_FUNC_2]);
4037 if (brcmf_chip_sr_capable(bus->ci)) {
4038 brcmf_sdio_sr_init(bus);
4040 /* Restore previous clock setting */
4041 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
4046 err = brcmf_sdiod_intr_register(sdiodev);
4048 brcmf_err("intr register failed:%d\n", err);
4051 /* If we didn't come up, turn off backplane clock */
4053 brcmf_sdio_clkctl(bus, CLK_NONE, false);
4055 sdio_release_host(sdiodev->func[1]);
4057 err = brcmf_bus_start(dev);
4059 brcmf_err("dongle is not responding\n");
4065 sdio_release_host(sdiodev->func[1]);
4067 brcmf_dbg(TRACE, "failed: dev=%s, err=%d\n", dev_name(dev), err);
4068 device_release_driver(dev);
4071 struct brcmf_sdio *brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev)
4074 struct brcmf_sdio *bus;
4075 struct workqueue_struct *wq;
4077 brcmf_dbg(TRACE, "Enter\n");
4079 /* Allocate private bus interface state */
4080 bus = kzalloc(sizeof(struct brcmf_sdio), GFP_ATOMIC);
4084 bus->sdiodev = sdiodev;
4086 skb_queue_head_init(&bus->glom);
4087 bus->txbound = BRCMF_TXBOUND;
4088 bus->rxbound = BRCMF_RXBOUND;
4089 bus->txminmax = BRCMF_TXMINMAX;
4090 bus->tx_seq = SDPCM_SEQ_WRAP - 1;
4092 /* platform specific configuration:
4093 * alignments must be at least 4 bytes for ADMA
4095 bus->head_align = ALIGNMENT;
4096 bus->sgentry_align = ALIGNMENT;
4097 if (sdiodev->pdata) {
4098 if (sdiodev->pdata->sd_head_align > ALIGNMENT)
4099 bus->head_align = sdiodev->pdata->sd_head_align;
4100 if (sdiodev->pdata->sd_sgentry_align > ALIGNMENT)
4101 bus->sgentry_align = sdiodev->pdata->sd_sgentry_align;
4104 /* single-threaded workqueue */
4105 wq = alloc_ordered_workqueue("brcmf_wq/%s", WQ_MEM_RECLAIM,
4106 dev_name(&sdiodev->func[1]->dev));
4108 brcmf_err("insufficient memory to create txworkqueue\n");
4111 brcmf_sdiod_freezer_count(sdiodev);
4112 INIT_WORK(&bus->datawork, brcmf_sdio_dataworker);
4115 /* attempt to attach to the dongle */
4116 if (!(brcmf_sdio_probe_attach(bus))) {
4117 brcmf_err("brcmf_sdio_probe_attach failed\n");
4121 spin_lock_init(&bus->rxctl_lock);
4122 spin_lock_init(&bus->txq_lock);
4123 init_waitqueue_head(&bus->ctrl_wait);
4124 init_waitqueue_head(&bus->dcmd_resp_wait);
4126 /* Set up the watchdog timer */
4127 init_timer(&bus->timer);
4128 bus->timer.data = (unsigned long)bus;
4129 bus->timer.function = brcmf_sdio_watchdog;
4131 /* Initialize watchdog thread */
4132 init_completion(&bus->watchdog_wait);
4133 bus->watchdog_tsk = kthread_run(brcmf_sdio_watchdog_thread,
4134 bus, "brcmf_wdog/%s",
4135 dev_name(&sdiodev->func[1]->dev));
4136 if (IS_ERR(bus->watchdog_tsk)) {
4137 pr_warn("brcmf_watchdog thread failed to start\n");
4138 bus->watchdog_tsk = NULL;
4140 /* Initialize DPC thread */
4141 atomic_set(&bus->dpc_tskcnt, 0);
4142 atomic_set(&bus->dpc_running, 0);
4144 /* Assign bus interface call back */
4145 bus->sdiodev->bus_if->dev = bus->sdiodev->dev;
4146 bus->sdiodev->bus_if->ops = &brcmf_sdio_bus_ops;
4147 bus->sdiodev->bus_if->chip = bus->ci->chip;
4148 bus->sdiodev->bus_if->chiprev = bus->ci->chiprev;
4150 /* default sdio bus header length for tx packet */
4151 bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN;
4153 /* Attach to the common layer, reserve hdr space */
4154 ret = brcmf_attach(bus->sdiodev->dev);
4156 brcmf_err("brcmf_attach failed\n");
4160 /* Query the F2 block size, set roundup accordingly */
4161 bus->blocksize = bus->sdiodev->func[2]->cur_blksize;
4162 bus->roundup = min(max_roundup, bus->blocksize);
4164 /* Allocate buffers */
4165 if (bus->sdiodev->bus_if->maxctl) {
4166 bus->sdiodev->bus_if->maxctl += bus->roundup;
4168 roundup((bus->sdiodev->bus_if->maxctl + SDPCM_HDRLEN),
4169 ALIGNMENT) + bus->head_align;
4170 bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC);
4171 if (!(bus->rxbuf)) {
4172 brcmf_err("rxbuf allocation failed\n");
4177 sdio_claim_host(bus->sdiodev->func[1]);
4179 /* Disable F2 to clear any intermediate frame state on the dongle */
4180 sdio_disable_func(bus->sdiodev->func[SDIO_FUNC_2]);
4182 bus->rxflow = false;
4184 /* Done with backplane-dependent accesses, can drop clock... */
4185 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
4187 sdio_release_host(bus->sdiodev->func[1]);
4189 /* ...and initialize clock/power states */
4190 bus->clkstate = CLK_SDONLY;
4191 bus->idletime = BRCMF_IDLE_INTERVAL;
4192 bus->idleclock = BRCMF_IDLE_ACTIVE;
4195 bus->sr_enabled = false;
4197 brcmf_sdio_debugfs_create(bus);
4198 brcmf_dbg(INFO, "completed!!\n");
4200 ret = brcmf_sdio_get_fwnames(bus->ci, sdiodev);
4204 ret = brcmf_fw_get_firmwares(sdiodev->dev, BRCMF_FW_REQUEST_NVRAM,
4205 sdiodev->fw_name, sdiodev->nvram_name,
4206 brcmf_sdio_firmware_callback);
4208 brcmf_err("async firmware request failed: %d\n", ret);
4215 brcmf_sdio_remove(bus);
4219 /* Detach and free everything */
4220 void brcmf_sdio_remove(struct brcmf_sdio *bus)
4222 brcmf_dbg(TRACE, "Enter\n");
4225 /* De-register interrupt handler */
4226 brcmf_sdiod_intr_unregister(bus->sdiodev);
4228 brcmf_detach(bus->sdiodev->dev);
4230 cancel_work_sync(&bus->datawork);
4232 destroy_workqueue(bus->brcmf_wq);
4235 if (bus->sdiodev->state != BRCMF_SDIOD_NOMEDIUM) {
4236 sdio_claim_host(bus->sdiodev->func[1]);
4237 brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
4238 /* Leave the device in state where it is
4239 * 'passive'. This is done by resetting all
4243 brcmf_chip_set_passive(bus->ci);
4244 brcmf_sdio_clkctl(bus, CLK_NONE, false);
4245 sdio_release_host(bus->sdiodev->func[1]);
4247 brcmf_chip_detach(bus->ci);
4255 brcmf_dbg(TRACE, "Disconnected\n");
4258 void brcmf_sdio_wd_timer(struct brcmf_sdio *bus, uint wdtick)
4260 /* Totally stop the timer */
4261 if (!wdtick && bus->wd_timer_valid) {
4262 del_timer_sync(&bus->timer);
4263 bus->wd_timer_valid = false;
4264 bus->save_ms = wdtick;
4268 /* don't start the wd until fw is loaded */
4269 if (bus->sdiodev->state != BRCMF_SDIOD_DATA)
4273 if (bus->save_ms != BRCMF_WD_POLL_MS) {
4274 if (bus->wd_timer_valid)
4275 /* Stop timer and restart at new value */
4276 del_timer_sync(&bus->timer);
4278 /* Create timer again when watchdog period is
4279 dynamically changed or in the first instance
4281 bus->timer.expires =
4282 jiffies + msecs_to_jiffies(BRCMF_WD_POLL_MS);
4283 add_timer(&bus->timer);
4286 /* Re arm the timer, at last watchdog period */
4287 mod_timer(&bus->timer,
4288 jiffies + msecs_to_jiffies(BRCMF_WD_POLL_MS));
4291 bus->wd_timer_valid = true;
4292 bus->save_ms = wdtick;
4296 int brcmf_sdio_sleep(struct brcmf_sdio *bus, bool sleep)
4300 sdio_claim_host(bus->sdiodev->func[1]);
4301 ret = brcmf_sdio_bus_sleep(bus, sleep, false);
4302 sdio_release_host(bus->sdiodev->func[1]);
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