drivers/net/wireless/intel/iwlwifi/pcie/tx.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
   4  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
   5  * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
   6  *
   7  * Portions of this file are derived from the ipw3945 project, as well
   8  * as portions of the ieee80211 subsystem header files.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program; if not, write to the Free Software Foundation, Inc.,
  21  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  22  *
  23  * The full GNU General Public License is included in this distribution in the
  24  * file called LICENSE.
  25  *
  26  * Contact Information:
  27  *  Intel Linux Wireless <linuxwifi@intel.com>
  28  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  29  *
  30  *****************************************************************************/
  31 #include <linux/etherdevice.h>
  32 #include <linux/ieee80211.h>
  33 #include <linux/slab.h>
  34 #include <linux/sched.h>
  35 #include <linux/pm_runtime.h>
  36 #include <net/ip6_checksum.h>
  37 #include <net/tso.h>
  38
  39 #include "iwl-debug.h"
  40 #include "iwl-csr.h"
  41 #include "iwl-prph.h"
  42 #include "iwl-io.h"
  43 #include "iwl-scd.h"
  44 #include "iwl-op-mode.h"
  45 #include "internal.h"
  46 /* FIXME: need to abstract out TX command (once we know what it looks like) */
  47 #include "dvm/commands.h"
  48
  49 #define IWL_TX_CRC_SIZE 4
  50 #define IWL_TX_DELIMITER_SIZE 4
  51
  52 /*************** DMA-QUEUE-GENERAL-FUNCTIONS  *****
  53  * DMA services
  54  *
  55  * Theory of operation
  56  *
  57  * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
  58  * of buffer descriptors, each of which points to one or more data buffers for
  59  * the device to read from or fill.  Driver and device exchange status of each
  60  * queue via "read" and "write" pointers.  Driver keeps minimum of 2 empty
  61  * entries in each circular buffer, to protect against confusing empty and full
  62  * queue states.
  63  *
  64  * The device reads or writes the data in the queues via the device's several
  65  * DMA/FIFO channels.  Each queue is mapped to a single DMA channel.
  66  *
  67  * For Tx queue, there are low mark and high mark limits. If, after queuing
  68  * the packet for Tx, free space become < low mark, Tx queue stopped. When
  69  * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
  70  * Tx queue resumed.
  71  *
  72  ***************************************************/
  73
  74 int iwl_queue_space(const struct iwl_txq *q)
  75 {
  76         unsigned int max;
  77         unsigned int used;
  78
  79         /*
  80          * To avoid ambiguity between empty and completely full queues, there
  81          * should always be less than TFD_QUEUE_SIZE_MAX elements in the queue.
  82          * If q->n_window is smaller than TFD_QUEUE_SIZE_MAX, there is no need
  83          * to reserve any queue entries for this purpose.
  84          */
  85         if (q->n_window < TFD_QUEUE_SIZE_MAX)
  86                 max = q->n_window;
  87         else
  88                 max = TFD_QUEUE_SIZE_MAX - 1;
  89
  90         /*
  91          * TFD_QUEUE_SIZE_MAX is a power of 2, so the following is equivalent to
  92          * modulo by TFD_QUEUE_SIZE_MAX and is well defined.
  93          */
  94         used = (q->write_ptr - q->read_ptr) & (TFD_QUEUE_SIZE_MAX - 1);
  95
  96         if (WARN_ON(used > max))
  97                 return 0;
  98
  99         return max - used;
 100 }
 101
 102 /*
 103  * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
 104  */
 105 static int iwl_queue_init(struct iwl_txq *q, int slots_num)
 106 {
 107         q->n_window = slots_num;
 108
 109         /* slots_num must be power-of-two size, otherwise
 110          * get_cmd_index is broken. */
 111         if (WARN_ON(!is_power_of_2(slots_num)))
 112                 return -EINVAL;
 113
 114         q->low_mark = q->n_window / 4;
 115         if (q->low_mark < 4)
 116                 q->low_mark = 4;
 117
 118         q->high_mark = q->n_window / 8;
 119         if (q->high_mark < 2)
 120                 q->high_mark = 2;
 121
 122         q->write_ptr = 0;
 123         q->read_ptr = 0;
 124
 125         return 0;
 126 }
 127
 128 int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans,
 129                            struct iwl_dma_ptr *ptr, size_t size)
 130 {
 131         if (WARN_ON(ptr->addr))
 132                 return -EINVAL;
 133
 134         ptr->addr = dma_alloc_coherent(trans->dev, size,
 135                                        &ptr->dma, GFP_KERNEL);
 136         if (!ptr->addr)
 137                 return -ENOMEM;
 138         ptr->size = size;
 139         return 0;
 140 }
 141
 142 void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, struct iwl_dma_ptr *ptr)
 143 {
 144         if (unlikely(!ptr->addr))
 145                 return;
 146
 147         dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
 148         memset(ptr, 0, sizeof(*ptr));
 149 }
 150
 151 static void iwl_pcie_txq_stuck_timer(unsigned long data)
 152 {
 153         struct iwl_txq *txq = (void *)data;
 154         struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
 155         struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie);
 156
 157         spin_lock(&txq->lock);
 158         /* check if triggered erroneously */
 159         if (txq->read_ptr == txq->write_ptr) {
 160                 spin_unlock(&txq->lock);
 161                 return;
 162         }
 163         spin_unlock(&txq->lock);
 164
 165         iwl_trans_pcie_log_scd_error(trans, txq);
 166
 167         iwl_force_nmi(trans);
 168 }
 169
 170 /*
 171  * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
 172  */
 173 static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
 174                                              struct iwl_txq *txq, u16 byte_cnt,
 175                                              int num_tbs)
 176 {
 177         struct iwlagn_scd_bc_tbl *scd_bc_tbl;
 178         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 179         int write_ptr = txq->write_ptr;
 180         int txq_id = txq->id;
 181         u8 sec_ctl = 0;
 182         u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
 183         __le16 bc_ent;
 184         struct iwl_tx_cmd *tx_cmd =
 185                 (void *)txq->entries[txq->write_ptr].cmd->payload;
 186         u8 sta_id = tx_cmd->sta_id;
 187
 188         scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
 189
 190         sec_ctl = tx_cmd->sec_ctl;
 191
 192         switch (sec_ctl & TX_CMD_SEC_MSK) {
 193         case TX_CMD_SEC_CCM:
 194                 len += IEEE80211_CCMP_MIC_LEN;
 195                 break;
 196         case TX_CMD_SEC_TKIP:
 197                 len += IEEE80211_TKIP_ICV_LEN;
 198                 break;
 199         case TX_CMD_SEC_WEP:
 200                 len += IEEE80211_WEP_IV_LEN + IEEE80211_WEP_ICV_LEN;
 201                 break;
 202         }
 203         if (trans_pcie->bc_table_dword)
 204                 len = DIV_ROUND_UP(len, 4);
 205
 206         if (WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX))
 207                 return;
 208
 209         bc_ent = cpu_to_le16(len | (sta_id << 12));
 210
 211         scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
 212
 213         if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
 214                 scd_bc_tbl[txq_id].
 215                         tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
 216 }
 217
 218 static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans,
 219                                             struct iwl_txq *txq)
 220 {
 221         struct iwl_trans_pcie *trans_pcie =
 222                 IWL_TRANS_GET_PCIE_TRANS(trans);
 223         struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
 224         int txq_id = txq->id;
 225         int read_ptr = txq->read_ptr;
 226         u8 sta_id = 0;
 227         __le16 bc_ent;
 228         struct iwl_tx_cmd *tx_cmd =
 229                 (void *)txq->entries[read_ptr].cmd->payload;
 230
 231         WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
 232
 233         if (txq_id != trans_pcie->cmd_queue)
 234                 sta_id = tx_cmd->sta_id;
 235
 236         bc_ent = cpu_to_le16(1 | (sta_id << 12));
 237
 238         scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
 239
 240         if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
 241                 scd_bc_tbl[txq_id].
 242                         tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
 243 }
 244
 245 /*
 246  * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware
 247  */
 248 static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans,
 249                                     struct iwl_txq *txq)
 250 {
 251         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 252         u32 reg = 0;
 253         int txq_id = txq->id;
 254
 255         lockdep_assert_held(&txq->lock);
 256
 257         /*
 258          * explicitly wake up the NIC if:
 259          * 1. shadow registers aren't enabled
 260          * 2. NIC is woken up for CMD regardless of shadow outside this function
 261          * 3. there is a chance that the NIC is asleep
 262          */
 263         if (!trans->cfg->base_params->shadow_reg_enable &&
 264             txq_id != trans_pcie->cmd_queue &&
 265             test_bit(STATUS_TPOWER_PMI, &trans->status)) {
 266                 /*
 267                  * wake up nic if it's powered down ...
 268                  * uCode will wake up, and interrupt us again, so next
 269                  * time we'll skip this part.
 270                  */
 271                 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
 272
 273                 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
 274                         IWL_DEBUG_INFO(trans, "Tx queue %d requesting wakeup, GP1 = 0x%x\n",
 275                                        txq_id, reg);
 276                         iwl_set_bit(trans, CSR_GP_CNTRL,
 277                                     CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 278                         txq->need_update = true;
 279                         return;
 280                 }
 281         }
 282
 283         /*
 284          * if not in power-save mode, uCode will never sleep when we're
 285          * trying to tx (during RFKILL, we're not trying to tx).
 286          */
 287         IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id, txq->write_ptr);
 288         if (!txq->block)
 289                 iwl_write32(trans, HBUS_TARG_WRPTR,
 290                             txq->write_ptr | (txq_id << 8));
 291 }
 292
 293 void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans)
 294 {
 295         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 296         int i;
 297
 298         for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
 299                 struct iwl_txq *txq = trans_pcie->txq[i];
 300
 301                 spin_lock_bh(&txq->lock);
 302                 if (txq->need_update) {
 303                         iwl_pcie_txq_inc_wr_ptr(trans, txq);
 304                         txq->need_update = false;
 305                 }
 306                 spin_unlock_bh(&txq->lock);
 307         }
 308 }
 309
 310 static inline dma_addr_t iwl_pcie_tfd_tb_get_addr(struct iwl_trans *trans,
 311                                                   void *_tfd, u8 idx)
 312 {
 313
 314         if (trans->cfg->use_tfh) {
 315                 struct iwl_tfh_tfd *tfd = _tfd;
 316                 struct iwl_tfh_tb *tb = &tfd->tbs[idx];
 317
 318                 return (dma_addr_t)(le64_to_cpu(tb->addr));
 319         } else {
 320                 struct iwl_tfd *tfd = _tfd;
 321                 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 322                 dma_addr_t addr = get_unaligned_le32(&tb->lo);
 323                 dma_addr_t hi_len;
 324
 325                 if (sizeof(dma_addr_t) <= sizeof(u32))
 326                         return addr;
 327
 328                 hi_len = le16_to_cpu(tb->hi_n_len) & 0xF;
 329
 330                 /*
 331                  * shift by 16 twice to avoid warnings on 32-bit
 332                  * (where this code never runs anyway due to the
 333                  * if statement above)
 334                  */
 335                 return addr | ((hi_len << 16) << 16);
 336         }
 337 }
 338
 339 static inline void iwl_pcie_tfd_set_tb(struct iwl_trans *trans, void *tfd,
 340                                        u8 idx, dma_addr_t addr, u16 len)
 341 {
 342         struct iwl_tfd *tfd_fh = (void *)tfd;
 343         struct iwl_tfd_tb *tb = &tfd_fh->tbs[idx];
 344
 345         u16 hi_n_len = len << 4;
 346
 347         put_unaligned_le32(addr, &tb->lo);
 348         hi_n_len |= iwl_get_dma_hi_addr(addr);
 349
 350         tb->hi_n_len = cpu_to_le16(hi_n_len);
 351
 352         tfd_fh->num_tbs = idx + 1;
 353 }
 354
 355 static inline u8 iwl_pcie_tfd_get_num_tbs(struct iwl_trans *trans, void *_tfd)
 356 {
 357         if (trans->cfg->use_tfh) {
 358                 struct iwl_tfh_tfd *tfd = _tfd;
 359
 360                 return le16_to_cpu(tfd->num_tbs) & 0x1f;
 361         } else {
 362                 struct iwl_tfd *tfd = _tfd;
 363
 364                 return tfd->num_tbs & 0x1f;
 365         }
 366 }
 367
 368 static void iwl_pcie_tfd_unmap(struct iwl_trans *trans,
 369                                struct iwl_cmd_meta *meta,
 370                                struct iwl_txq *txq, int index)
 371 {
 372         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 373         int i, num_tbs;
 374         void *tfd = iwl_pcie_get_tfd(trans_pcie, txq, index);
 375
 376         /* Sanity check on number of chunks */
 377         num_tbs = iwl_pcie_tfd_get_num_tbs(trans, tfd);
 378
 379         if (num_tbs >= trans_pcie->max_tbs) {
 380                 IWL_ERR(trans, "Too many chunks: %i\n", num_tbs);
 381                 /* @todo issue fatal error, it is quite serious situation */
 382                 return;
 383         }
 384
 385         /* first TB is never freed - it's the bidirectional DMA data */
 386
 387         for (i = 1; i < num_tbs; i++) {
 388                 if (meta->tbs & BIT(i))
 389                         dma_unmap_page(trans->dev,
 390                                        iwl_pcie_tfd_tb_get_addr(trans, tfd, i),
 391                                        iwl_pcie_tfd_tb_get_len(trans, tfd, i),
 392                                        DMA_TO_DEVICE);
 393                 else
 394                         dma_unmap_single(trans->dev,
 395                                          iwl_pcie_tfd_tb_get_addr(trans, tfd,
 396                                                                   i),
 397                                          iwl_pcie_tfd_tb_get_len(trans, tfd,
 398                                                                  i),
 399                                          DMA_TO_DEVICE);
 400         }
 401
 402         if (trans->cfg->use_tfh) {
 403                 struct iwl_tfh_tfd *tfd_fh = (void *)tfd;
 404
 405                 tfd_fh->num_tbs = 0;
 406         } else {
 407                 struct iwl_tfd *tfd_fh = (void *)tfd;
 408
 409                 tfd_fh->num_tbs = 0;
 410         }
 411
 412 }
 413
 414 /*
 415  * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
 416  * @trans - transport private data
 417  * @txq - tx queue
 418  * @dma_dir - the direction of the DMA mapping
 419  *
 420  * Does NOT advance any TFD circular buffer read/write indexes
 421  * Does NOT free the TFD itself (which is within circular buffer)
 422  */
 423 void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq)
 424 {
 425         /* rd_ptr is bounded by TFD_QUEUE_SIZE_MAX and
 426          * idx is bounded by n_window
 427          */
 428         int rd_ptr = txq->read_ptr;
 429         int idx = get_cmd_index(txq, rd_ptr);
 430
 431         lockdep_assert_held(&txq->lock);
 432
 433         /* We have only q->n_window txq->entries, but we use
 434          * TFD_QUEUE_SIZE_MAX tfds
 435          */
 436         iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, txq, rd_ptr);
 437
 438         /* free SKB */
 439         if (txq->entries) {
 440                 struct sk_buff *skb;
 441
 442                 skb = txq->entries[idx].skb;
 443
 444                 /* Can be called from irqs-disabled context
 445                  * If skb is not NULL, it means that the whole queue is being
 446                  * freed and that the queue is not empty - free the skb
 447                  */
 448                 if (skb) {
 449                         iwl_op_mode_free_skb(trans->op_mode, skb);
 450                         txq->entries[idx].skb = NULL;
 451                 }
 452         }
 453 }
 454
 455 static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq,
 456                                   dma_addr_t addr, u16 len, bool reset)
 457 {
 458         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 459         void *tfd;
 460         u32 num_tbs;
 461
 462         tfd = txq->tfds + trans_pcie->tfd_size * txq->write_ptr;
 463
 464         if (reset)
 465                 memset(tfd, 0, trans_pcie->tfd_size);
 466
 467         num_tbs = iwl_pcie_tfd_get_num_tbs(trans, tfd);
 468
 469         /* Each TFD can point to a maximum max_tbs Tx buffers */
 470         if (num_tbs >= trans_pcie->max_tbs) {
 471                 IWL_ERR(trans, "Error can not send more than %d chunks\n",
 472                         trans_pcie->max_tbs);
 473                 return -EINVAL;
 474         }
 475
 476         if (WARN(addr & ~IWL_TX_DMA_MASK,
 477                  "Unaligned address = %llx\n", (unsigned long long)addr))
 478                 return -EINVAL;
 479
 480         iwl_pcie_tfd_set_tb(trans, tfd, num_tbs, addr, len);
 481
 482         return num_tbs;
 483 }
 484
 485 int iwl_pcie_txq_alloc(struct iwl_trans *trans, struct iwl_txq *txq,
 486                        int slots_num, bool cmd_queue)
 487 {
 488         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 489         size_t tfd_sz = trans_pcie->tfd_size * TFD_QUEUE_SIZE_MAX;
 490         size_t tb0_buf_sz;
 491         int i;
 492
 493         if (WARN_ON(txq->entries || txq->tfds))
 494                 return -EINVAL;
 495
 496         setup_timer(&txq->stuck_timer, iwl_pcie_txq_stuck_timer,
 497                     (unsigned long)txq);
 498         txq->trans_pcie = trans_pcie;
 499
 500         txq->n_window = slots_num;
 501
 502         txq->entries = kcalloc(slots_num,
 503                                sizeof(struct iwl_pcie_txq_entry),
 504                                GFP_KERNEL);
 505
 506         if (!txq->entries)
 507                 goto error;
 508
 509         if (cmd_queue)
 510                 for (i = 0; i < slots_num; i++) {
 511                         txq->entries[i].cmd =
 512                                 kmalloc(sizeof(struct iwl_device_cmd),
 513                                         GFP_KERNEL);
 514                         if (!txq->entries[i].cmd)
 515                                 goto error;
 516                 }
 517
 518         /* Circular buffer of transmit frame descriptors (TFDs),
 519          * shared with device */
 520         txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
 521                                        &txq->dma_addr, GFP_KERNEL);
 522         if (!txq->tfds)
 523                 goto error;
 524
 525         BUILD_BUG_ON(IWL_FIRST_TB_SIZE_ALIGN != sizeof(*txq->first_tb_bufs));
 526
 527         tb0_buf_sz = sizeof(*txq->first_tb_bufs) * slots_num;
 528
 529         txq->first_tb_bufs = dma_alloc_coherent(trans->dev, tb0_buf_sz,
 530                                               &txq->first_tb_dma,
 531                                               GFP_KERNEL);
 532         if (!txq->first_tb_bufs)
 533                 goto err_free_tfds;
 534
 535         return 0;
 536 err_free_tfds:
 537         dma_free_coherent(trans->dev, tfd_sz, txq->tfds, txq->dma_addr);
 538 error:
 539         if (txq->entries && cmd_queue)
 540                 for (i = 0; i < slots_num; i++)
 541                         kfree(txq->entries[i].cmd);
 542         kfree(txq->entries);
 543         txq->entries = NULL;
 544
 545         return -ENOMEM;
 546
 547 }
 548
 549 int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq,
 550                       int slots_num, bool cmd_queue)
 551 {
 552         int ret;
 553
 554         txq->need_update = false;
 555
 556         /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
 557          * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
 558         BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
 559
 560         /* Initialize queue's high/low-water marks, and head/tail indexes */
 561         ret = iwl_queue_init(txq, slots_num);
 562         if (ret)
 563                 return ret;
 564
 565         spin_lock_init(&txq->lock);
 566
 567         if (cmd_queue) {
 568                 static struct lock_class_key iwl_pcie_cmd_queue_lock_class;
 569
 570                 lockdep_set_class(&txq->lock, &iwl_pcie_cmd_queue_lock_class);
 571         }
 572
 573         __skb_queue_head_init(&txq->overflow_q);
 574
 575         return 0;
 576 }
 577
 578 static void iwl_pcie_free_tso_page(struct iwl_trans_pcie *trans_pcie,
 579                                    struct sk_buff *skb)
 580 {
 581         struct page **page_ptr;
 582
 583         page_ptr = (void *)((u8 *)skb->cb + trans_pcie->page_offs);
 584
 585         if (*page_ptr) {
 586                 __free_page(*page_ptr);
 587                 *page_ptr = NULL;
 588         }
 589 }
 590
 591 static void iwl_pcie_clear_cmd_in_flight(struct iwl_trans *trans)
 592 {
 593         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 594
 595         lockdep_assert_held(&trans_pcie->reg_lock);
 596
 597         if (trans_pcie->ref_cmd_in_flight) {
 598                 trans_pcie->ref_cmd_in_flight = false;
 599                 IWL_DEBUG_RPM(trans, "clear ref_cmd_in_flight - unref\n");
 600                 iwl_trans_unref(trans);
 601         }
 602
 603         if (!trans->cfg->base_params->apmg_wake_up_wa)
 604                 return;
 605         if (WARN_ON(!trans_pcie->cmd_hold_nic_awake))
 606                 return;
 607
 608         trans_pcie->cmd_hold_nic_awake = false;
 609         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 610                                    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 611 }
 612
 613 /*
 614  * iwl_pcie_txq_unmap -  Unmap any remaining DMA mappings and free skb's
 615  */
 616 static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id)
 617 {
 618         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 619         struct iwl_txq *txq = trans_pcie->txq[txq_id];
 620
 621         spin_lock_bh(&txq->lock);
 622         while (txq->write_ptr != txq->read_ptr) {
 623                 IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n",
 624                                    txq_id, txq->read_ptr);
 625
 626                 if (txq_id != trans_pcie->cmd_queue) {
 627                         struct sk_buff *skb = txq->entries[txq->read_ptr].skb;
 628
 629                         if (WARN_ON_ONCE(!skb))
 630                                 continue;
 631
 632                         iwl_pcie_free_tso_page(trans_pcie, skb);
 633                 }
 634                 iwl_pcie_txq_free_tfd(trans, txq);
 635                 txq->read_ptr = iwl_queue_inc_wrap(txq->read_ptr);
 636
 637                 if (txq->read_ptr == txq->write_ptr) {
 638                         unsigned long flags;
 639
 640                         spin_lock_irqsave(&trans_pcie->reg_lock, flags);
 641                         if (txq_id != trans_pcie->cmd_queue) {
 642                                 IWL_DEBUG_RPM(trans, "Q %d - last tx freed\n",
 643                                               txq->id);
 644                                 iwl_trans_unref(trans);
 645                         } else {
 646                                 iwl_pcie_clear_cmd_in_flight(trans);
 647                         }
 648                         spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
 649                 }
 650         }
 651
 652         while (!skb_queue_empty(&txq->overflow_q)) {
 653                 struct sk_buff *skb = __skb_dequeue(&txq->overflow_q);
 654
 655                 iwl_op_mode_free_skb(trans->op_mode, skb);
 656         }
 657
 658         spin_unlock_bh(&txq->lock);
 659
 660         /* just in case - this queue may have been stopped */
 661         iwl_wake_queue(trans, txq);
 662 }
 663
 664 /*
 665  * iwl_pcie_txq_free - Deallocate DMA queue.
 666  * @txq: Transmit queue to deallocate.
 667  *
 668  * Empty queue by removing and destroying all BD's.
 669  * Free all buffers.
 670  * 0-fill, but do not free "txq" descriptor structure.
 671  */
 672 static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id)
 673 {
 674         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 675         struct iwl_txq *txq = trans_pcie->txq[txq_id];
 676         struct device *dev = trans->dev;
 677         int i;
 678
 679         if (WARN_ON(!txq))
 680                 return;
 681
 682         iwl_pcie_txq_unmap(trans, txq_id);
 683
 684         /* De-alloc array of command/tx buffers */
 685         if (txq_id == trans_pcie->cmd_queue)
 686                 for (i = 0; i < txq->n_window; i++) {
 687                         kzfree(txq->entries[i].cmd);
 688                         kzfree(txq->entries[i].free_buf);
 689                 }
 690
 691         /* De-alloc circular buffer of TFDs */
 692         if (txq->tfds) {
 693                 dma_free_coherent(dev,
 694                                   trans_pcie->tfd_size * TFD_QUEUE_SIZE_MAX,
 695                                   txq->tfds, txq->dma_addr);
 696                 txq->dma_addr = 0;
 697                 txq->tfds = NULL;
 698
 699                 dma_free_coherent(dev,
 700                                   sizeof(*txq->first_tb_bufs) * txq->n_window,
 701                                   txq->first_tb_bufs, txq->first_tb_dma);
 702         }
 703
 704         kfree(txq->entries);
 705         txq->entries = NULL;
 706
 707         del_timer_sync(&txq->stuck_timer);
 708
 709         /* 0-fill queue descriptor structure */
 710         memset(txq, 0, sizeof(*txq));
 711 }
 712
 713 void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr)
 714 {
 715         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 716         int nq = trans->cfg->base_params->num_of_queues;
 717         int chan;
 718         u32 reg_val;
 719         int clear_dwords = (SCD_TRANS_TBL_OFFSET_QUEUE(nq) -
 720                                 SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32);
 721
 722         /* make sure all queue are not stopped/used */
 723         memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
 724         memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
 725
 726         trans_pcie->scd_base_addr =
 727                 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
 728
 729         WARN_ON(scd_base_addr != 0 &&
 730                 scd_base_addr != trans_pcie->scd_base_addr);
 731
 732         /* reset context data, TX status and translation data */
 733         iwl_trans_write_mem(trans, trans_pcie->scd_base_addr +
 734                                    SCD_CONTEXT_MEM_LOWER_BOUND,
 735                             NULL, clear_dwords);
 736
 737         iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
 738                        trans_pcie->scd_bc_tbls.dma >> 10);
 739
 740         /* The chain extension of the SCD doesn't work well. This feature is
 741          * enabled by default by the HW, so we need to disable it manually.
 742          */
 743         if (trans->cfg->base_params->scd_chain_ext_wa)
 744                 iwl_write_prph(trans, SCD_CHAINEXT_EN, 0);
 745
 746         iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue,
 747                                 trans_pcie->cmd_fifo,
 748                                 trans_pcie->cmd_q_wdg_timeout);
 749
 750         /* Activate all Tx DMA/FIFO channels */
 751         iwl_scd_activate_fifos(trans);
 752
 753         /* Enable DMA channel */
 754         for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++)
 755                 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
 756                                    FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
 757                                    FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
 758
 759         /* Update FH chicken bits */
 760         reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
 761         iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
 762                            reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
 763
 764         /* Enable L1-Active */
 765         if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
 766                 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
 767                                     APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 768 }
 769
 770 void iwl_trans_pcie_tx_reset(struct iwl_trans *trans)
 771 {
 772         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 773         int txq_id;
 774
 775         /*
 776          * we should never get here in gen2 trans mode return early to avoid
 777          * having invalid accesses
 778          */
 779         if (WARN_ON_ONCE(trans->cfg->gen2))
 780                 return;
 781
 782         for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
 783              txq_id++) {
 784                 struct iwl_txq *txq = trans_pcie->txq[txq_id];
 785                 if (trans->cfg->use_tfh)
 786                         iwl_write_direct64(trans,
 787                                            FH_MEM_CBBC_QUEUE(trans, txq_id),
 788                                            txq->dma_addr);
 789                 else
 790                         iwl_write_direct32(trans,
 791                                            FH_MEM_CBBC_QUEUE(trans, txq_id),
 792                                            txq->dma_addr >> 8);
 793                 iwl_pcie_txq_unmap(trans, txq_id);
 794                 txq->read_ptr = 0;
 795                 txq->write_ptr = 0;
 796         }
 797
 798         /* Tell NIC where to find the "keep warm" buffer */
 799         iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
 800                            trans_pcie->kw.dma >> 4);
 801
 802         /*
 803          * Send 0 as the scd_base_addr since the device may have be reset
 804          * while we were in WoWLAN in which case SCD_SRAM_BASE_ADDR will
 805          * contain garbage.
 806          */
 807         iwl_pcie_tx_start(trans, 0);
 808 }
 809
 810 static void iwl_pcie_tx_stop_fh(struct iwl_trans *trans)
 811 {
 812         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 813         unsigned long flags;
 814         int ch, ret;
 815         u32 mask = 0;
 816
 817         spin_lock(&trans_pcie->irq_lock);
 818
 819         if (!iwl_trans_grab_nic_access(trans, &flags))
 820                 goto out;
 821
 822         /* Stop each Tx DMA channel */
 823         for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
 824                 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
 825                 mask |= FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch);
 826         }
 827
 828         /* Wait for DMA channels to be idle */
 829         ret = iwl_poll_bit(trans, FH_TSSR_TX_STATUS_REG, mask, mask, 5000);
 830         if (ret < 0)
 831                 IWL_ERR(trans,
 832                         "Failing on timeout while stopping DMA channel %d [0x%08x]\n",
 833                         ch, iwl_read32(trans, FH_TSSR_TX_STATUS_REG));
 834
 835         iwl_trans_release_nic_access(trans, &flags);
 836
 837 out:
 838         spin_unlock(&trans_pcie->irq_lock);
 839 }
 840
 841 /*
 842  * iwl_pcie_tx_stop - Stop all Tx DMA channels
 843  */
 844 int iwl_pcie_tx_stop(struct iwl_trans *trans)
 845 {
 846         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 847         int txq_id;
 848
 849         /* Turn off all Tx DMA fifos */
 850         iwl_scd_deactivate_fifos(trans);
 851
 852         /* Turn off all Tx DMA channels */
 853         iwl_pcie_tx_stop_fh(trans);
 854
 855         /*
 856          * This function can be called before the op_mode disabled the
 857          * queues. This happens when we have an rfkill interrupt.
 858          * Since we stop Tx altogether - mark the queues as stopped.
 859          */
 860         memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
 861         memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
 862
 863         /* This can happen: start_hw, stop_device */
 864         if (!trans_pcie->txq_memory)
 865                 return 0;
 866
 867         /* Unmap DMA from host system and free skb's */
 868         for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
 869              txq_id++)
 870                 iwl_pcie_txq_unmap(trans, txq_id);
 871
 872         return 0;
 873 }
 874
 875 /*
 876  * iwl_trans_tx_free - Free TXQ Context
 877  *
 878  * Destroy all TX DMA queues and structures
 879  */
 880 void iwl_pcie_tx_free(struct iwl_trans *trans)
 881 {
 882         int txq_id;
 883         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 884
 885         memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
 886
 887         /* Tx queues */
 888         if (trans_pcie->txq_memory) {
 889                 for (txq_id = 0;
 890                      txq_id < trans->cfg->base_params->num_of_queues;
 891                      txq_id++) {
 892                         iwl_pcie_txq_free(trans, txq_id);
 893                         trans_pcie->txq[txq_id] = NULL;
 894                 }
 895         }
 896
 897         kfree(trans_pcie->txq_memory);
 898         trans_pcie->txq_memory = NULL;
 899
 900         iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw);
 901
 902         iwl_pcie_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
 903 }
 904
 905 /*
 906  * iwl_pcie_tx_alloc - allocate TX context
 907  * Allocate all Tx DMA structures and initialize them
 908  */
 909 static int iwl_pcie_tx_alloc(struct iwl_trans *trans)
 910 {
 911         int ret;
 912         int txq_id, slots_num;
 913         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 914
 915         u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues *
 916                         sizeof(struct iwlagn_scd_bc_tbl);
 917
 918         /*It is not allowed to alloc twice, so warn when this happens.
 919          * We cannot rely on the previous allocation, so free and fail */
 920         if (WARN_ON(trans_pcie->txq_memory)) {
 921                 ret = -EINVAL;
 922                 goto error;
 923         }
 924
 925         ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
 926                                    scd_bc_tbls_size);
 927         if (ret) {
 928                 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
 929                 goto error;
 930         }
 931
 932         /* Alloc keep-warm buffer */
 933         ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
 934         if (ret) {
 935                 IWL_ERR(trans, "Keep Warm allocation failed\n");
 936                 goto error;
 937         }
 938
 939         trans_pcie->txq_memory = kcalloc(trans->cfg->base_params->num_of_queues,
 940                                          sizeof(struct iwl_txq), GFP_KERNEL);
 941         if (!trans_pcie->txq_memory) {
 942                 IWL_ERR(trans, "Not enough memory for txq\n");
 943                 ret = -ENOMEM;
 944                 goto error;
 945         }
 946
 947         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
 948         for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
 949              txq_id++) {
 950                 bool cmd_queue = (txq_id == trans_pcie->cmd_queue);
 951
 952                 slots_num = cmd_queue ? TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 953                 trans_pcie->txq[txq_id] = &trans_pcie->txq_memory[txq_id];
 954                 ret = iwl_pcie_txq_alloc(trans, trans_pcie->txq[txq_id],
 955                                          slots_num, cmd_queue);
 956                 if (ret) {
 957                         IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
 958                         goto error;
 959                 }
 960                 trans_pcie->txq[txq_id]->id = txq_id;
 961         }
 962
 963         return 0;
 964
 965 error:
 966         iwl_pcie_tx_free(trans);
 967
 968         return ret;
 969 }
 970
 971 int iwl_pcie_tx_init(struct iwl_trans *trans)
 972 {
 973         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 974         int ret;
 975         int txq_id, slots_num;
 976         bool alloc = false;
 977
 978         if (!trans_pcie->txq_memory) {
 979                 ret = iwl_pcie_tx_alloc(trans);
 980                 if (ret)
 981                         goto error;
 982                 alloc = true;
 983         }
 984
 985         spin_lock(&trans_pcie->irq_lock);
 986
 987         /* Turn off all Tx DMA fifos */
 988         iwl_scd_deactivate_fifos(trans);
 989
 990         /* Tell NIC where to find the "keep warm" buffer */
 991         iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
 992                            trans_pcie->kw.dma >> 4);
 993
 994         spin_unlock(&trans_pcie->irq_lock);
 995
 996         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
 997         for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
 998              txq_id++) {
 999                 bool cmd_queue = (txq_id == trans_pcie->cmd_queue);
1000
1001                 slots_num = cmd_queue ? TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
1002                 ret = iwl_pcie_txq_init(trans, trans_pcie->txq[txq_id],
1003                                         slots_num, cmd_queue);
1004                 if (ret) {
1005                         IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
1006                         goto error;
1007                 }
1008
1009                 /*
1010                  * Tell nic where to find circular buffer of TFDs for a
1011                  * given Tx queue, and enable the DMA channel used for that
1012                  * queue.
1013                  * Circular buffer (TFD queue in DRAM) physical base address
1014                  */
1015                 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(trans, txq_id),
1016                                    trans_pcie->txq[txq_id]->dma_addr >> 8);
1017         }
1018
1019         iwl_set_bits_prph(trans, SCD_GP_CTRL, SCD_GP_CTRL_AUTO_ACTIVE_MODE);
1020         if (trans->cfg->base_params->num_of_queues > 20)
1021                 iwl_set_bits_prph(trans, SCD_GP_CTRL,
1022                                   SCD_GP_CTRL_ENABLE_31_QUEUES);
1023
1024         return 0;
1025 error:
1026         /*Upon error, free only if we allocated something */
1027         if (alloc)
1028                 iwl_pcie_tx_free(trans);
1029         return ret;
1030 }
1031
1032 static inline void iwl_pcie_txq_progress(struct iwl_txq *txq)
1033 {
1034         lockdep_assert_held(&txq->lock);
1035
1036         if (!txq->wd_timeout)
1037                 return;
1038
1039         /*
1040          * station is asleep and we send data - that must
1041          * be uAPSD or PS-Poll. Don't rearm the timer.
1042          */
1043         if (txq->frozen)
1044                 return;
1045
1046         /*
1047          * if empty delete timer, otherwise move timer forward
1048          * since we're making progress on this queue
1049          */
1050         if (txq->read_ptr == txq->write_ptr)
1051                 del_timer(&txq->stuck_timer);
1052         else
1053                 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
1054 }
1055
1056 /* Frees buffers until index _not_ inclusive */
1057 void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
1058                             struct sk_buff_head *skbs)
1059 {
1060         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1061         struct iwl_txq *txq = trans_pcie->txq[txq_id];
1062         int tfd_num = ssn & (TFD_QUEUE_SIZE_MAX - 1);
1063         int last_to_free;
1064
1065         /* This function is not meant to release cmd queue*/
1066         if (WARN_ON(txq_id == trans_pcie->cmd_queue))
1067                 return;
1068
1069         spin_lock_bh(&txq->lock);
1070
1071         if (!test_bit(txq_id, trans_pcie->queue_used)) {
1072                 IWL_DEBUG_TX_QUEUES(trans, "Q %d inactive - ignoring idx %d\n",
1073                                     txq_id, ssn);
1074                 goto out;
1075         }
1076
1077         if (txq->read_ptr == tfd_num)
1078                 goto out;
1079
1080         IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n",
1081                            txq_id, txq->read_ptr, tfd_num, ssn);
1082
1083         /*Since we free until index _not_ inclusive, the one before index is
1084          * the last we will free. This one must be used */
1085         last_to_free = iwl_queue_dec_wrap(tfd_num);
1086
1087         if (!iwl_queue_used(txq, last_to_free)) {
1088                 IWL_ERR(trans,
1089                         "%s: Read index for DMA queue txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n",
1090                         __func__, txq_id, last_to_free, TFD_QUEUE_SIZE_MAX,
1091                         txq->write_ptr, txq->read_ptr);
1092                 goto out;
1093         }
1094
1095         if (WARN_ON(!skb_queue_empty(skbs)))
1096                 goto out;
1097
1098         for (;
1099              txq->read_ptr != tfd_num;
1100              txq->read_ptr = iwl_queue_inc_wrap(txq->read_ptr)) {
1101                 struct sk_buff *skb = txq->entries[txq->read_ptr].skb;
1102
1103                 if (WARN_ON_ONCE(!skb))
1104                         continue;
1105
1106                 iwl_pcie_free_tso_page(trans_pcie, skb);
1107
1108                 __skb_queue_tail(skbs, skb);
1109
1110                 txq->entries[txq->read_ptr].skb = NULL;
1111
1112                 if (!trans->cfg->use_tfh)
1113                         iwl_pcie_txq_inval_byte_cnt_tbl(trans, txq);
1114
1115                 iwl_pcie_txq_free_tfd(trans, txq);
1116         }
1117
1118         iwl_pcie_txq_progress(txq);
1119
1120         if (iwl_queue_space(txq) > txq->low_mark &&
1121             test_bit(txq_id, trans_pcie->queue_stopped)) {
1122                 struct sk_buff_head overflow_skbs;
1123
1124                 __skb_queue_head_init(&overflow_skbs);
1125                 skb_queue_splice_init(&txq->overflow_q, &overflow_skbs);
1126
1127                 /*
1128                  * This is tricky: we are in reclaim path which is non
1129                  * re-entrant, so noone will try to take the access the
1130                  * txq data from that path. We stopped tx, so we can't
1131                  * have tx as well. Bottom line, we can unlock and re-lock
1132                  * later.
1133                  */
1134                 spin_unlock_bh(&txq->lock);
1135
1136                 while (!skb_queue_empty(&overflow_skbs)) {
1137                         struct sk_buff *skb = __skb_dequeue(&overflow_skbs);
1138                         struct iwl_device_cmd *dev_cmd_ptr;
1139
1140                         dev_cmd_ptr = *(void **)((u8 *)skb->cb +
1141                                                  trans_pcie->dev_cmd_offs);
1142
1143                         /*
1144                          * Note that we can very well be overflowing again.
1145                          * In that case, iwl_queue_space will be small again
1146                          * and we won't wake mac80211's queue.
1147                          */
1148                         iwl_trans_pcie_tx(trans, skb, dev_cmd_ptr, txq_id);
1149                 }
1150                 spin_lock_bh(&txq->lock);
1151
1152                 if (iwl_queue_space(txq) > txq->low_mark)
1153                         iwl_wake_queue(trans, txq);
1154         }
1155
1156         if (txq->read_ptr == txq->write_ptr) {
1157                 IWL_DEBUG_RPM(trans, "Q %d - last tx reclaimed\n", txq->id);
1158                 iwl_trans_unref(trans);
1159         }
1160
1161 out:
1162         spin_unlock_bh(&txq->lock);
1163 }
1164
1165 static int iwl_pcie_set_cmd_in_flight(struct iwl_trans *trans,
1166                                       const struct iwl_host_cmd *cmd)
1167 {
1168         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1169         int ret;
1170
1171         lockdep_assert_held(&trans_pcie->reg_lock);
1172
1173         if (!(cmd->flags & CMD_SEND_IN_IDLE) &&
1174             !trans_pcie->ref_cmd_in_flight) {
1175                 trans_pcie->ref_cmd_in_flight = true;
1176                 IWL_DEBUG_RPM(trans, "set ref_cmd_in_flight - ref\n");
1177                 iwl_trans_ref(trans);
1178         }
1179
1180         /*
1181          * wake up the NIC to make sure that the firmware will see the host
1182          * command - we will let the NIC sleep once all the host commands
1183          * returned. This needs to be done only on NICs that have
1184          * apmg_wake_up_wa set.
1185          */
1186         if (trans->cfg->base_params->apmg_wake_up_wa &&
1187             !trans_pcie->cmd_hold_nic_awake) {
1188                 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1189                                          CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1190
1191                 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1192                                    CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1193                                    (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1194                                     CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP),
1195                                    15000);
1196                 if (ret < 0) {
1197                         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1198                                         CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1199                         IWL_ERR(trans, "Failed to wake NIC for hcmd\n");
1200                         return -EIO;
1201                 }
1202                 trans_pcie->cmd_hold_nic_awake = true;
1203         }
1204
1205         return 0;
1206 }
1207
1208 /*
1209  * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd
1210  *
1211  * When FW advances 'R' index, all entries between old and new 'R' index
1212  * need to be reclaimed. As result, some free space forms.  If there is
1213  * enough free space (> low mark), wake the stack that feeds us.
1214  */
1215 static void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx)
1216 {
1217         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1218         struct iwl_txq *txq = trans_pcie->txq[txq_id];
1219         unsigned long flags;
1220         int nfreed = 0;
1221
1222         lockdep_assert_held(&txq->lock);
1223
1224         if ((idx >= TFD_QUEUE_SIZE_MAX) || (!iwl_queue_used(txq, idx))) {
1225                 IWL_ERR(trans,
1226                         "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n",
1227                         __func__, txq_id, idx, TFD_QUEUE_SIZE_MAX,
1228                         txq->write_ptr, txq->read_ptr);
1229                 return;
1230         }
1231
1232         for (idx = iwl_queue_inc_wrap(idx); txq->read_ptr != idx;
1233              txq->read_ptr = iwl_queue_inc_wrap(txq->read_ptr)) {
1234
1235                 if (nfreed++ > 0) {
1236                         IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n",
1237                                 idx, txq->write_ptr, txq->read_ptr);
1238                         iwl_force_nmi(trans);
1239                 }
1240         }
1241
1242         if (txq->read_ptr == txq->write_ptr) {
1243                 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1244                 iwl_pcie_clear_cmd_in_flight(trans);
1245                 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1246         }
1247
1248         iwl_pcie_txq_progress(txq);
1249 }
1250
1251 static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid,
1252                                  u16 txq_id)
1253 {
1254         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1255         u32 tbl_dw_addr;
1256         u32 tbl_dw;
1257         u16 scd_q2ratid;
1258
1259         scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
1260
1261         tbl_dw_addr = trans_pcie->scd_base_addr +
1262                         SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
1263
1264         tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr);
1265
1266         if (txq_id & 0x1)
1267                 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
1268         else
1269                 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
1270
1271         iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw);
1272
1273         return 0;
1274 }
1275
1276 /* Receiver address (actually, Rx station's index into station table),
1277  * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */
1278 #define BUILD_RAxTID(sta_id, tid)       (((sta_id) << 4) + (tid))
1279
1280 void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn,
1281                                const struct iwl_trans_txq_scd_cfg *cfg,
1282                                unsigned int wdg_timeout)
1283 {
1284         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1285         struct iwl_txq *txq = trans_pcie->txq[txq_id];
1286         int fifo = -1;
1287
1288         if (test_and_set_bit(txq_id, trans_pcie->queue_used))
1289                 WARN_ONCE(1, "queue %d already used - expect issues", txq_id);
1290
1291         txq->wd_timeout = msecs_to_jiffies(wdg_timeout);
1292
1293         if (cfg) {
1294                 fifo = cfg->fifo;
1295
1296                 /* Disable the scheduler prior configuring the cmd queue */
1297                 if (txq_id == trans_pcie->cmd_queue &&
1298                     trans_pcie->scd_set_active)
1299                         iwl_scd_enable_set_active(trans, 0);
1300
1301                 /* Stop this Tx queue before configuring it */
1302                 iwl_scd_txq_set_inactive(trans, txq_id);
1303
1304                 /* Set this queue as a chain-building queue unless it is CMD */
1305                 if (txq_id != trans_pcie->cmd_queue)
1306                         iwl_scd_txq_set_chain(trans, txq_id);
1307
1308                 if (cfg->aggregate) {
1309                         u16 ra_tid = BUILD_RAxTID(cfg->sta_id, cfg->tid);
1310
1311                         /* Map receiver-address / traffic-ID to this queue */
1312                         iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id);
1313
1314                         /* enable aggregations for the queue */
1315                         iwl_scd_txq_enable_agg(trans, txq_id);
1316                         txq->ampdu = true;
1317                 } else {
1318                         /*
1319                          * disable aggregations for the queue, this will also
1320                          * make the ra_tid mapping configuration irrelevant
1321                          * since it is now a non-AGG queue.
1322                          */
1323                         iwl_scd_txq_disable_agg(trans, txq_id);
1324
1325                         ssn = txq->read_ptr;
1326                 }
1327         }
1328
1329         /* Place first TFD at index corresponding to start sequence number.
1330          * Assumes that ssn_idx is valid (!= 0xFFF) */
1331         txq->read_ptr = (ssn & 0xff);
1332         txq->write_ptr = (ssn & 0xff);
1333         iwl_write_direct32(trans, HBUS_TARG_WRPTR,
1334                            (ssn & 0xff) | (txq_id << 8));
1335
1336         if (cfg) {
1337                 u8 frame_limit = cfg->frame_limit;
1338
1339                 iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn);
1340
1341                 /* Set up Tx window size and frame limit for this queue */
1342                 iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr +
1343                                 SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0);
1344                 iwl_trans_write_mem32(trans,
1345                         trans_pcie->scd_base_addr +
1346                         SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
1347                         ((frame_limit << SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1348                                         SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1349                         ((frame_limit << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1350                                         SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1351
1352                 /* Set up status area in SRAM, map to Tx DMA/FIFO, activate */
1353                 iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),
1354                                (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
1355                                (cfg->fifo << SCD_QUEUE_STTS_REG_POS_TXF) |
1356                                (1 << SCD_QUEUE_STTS_REG_POS_WSL) |
1357                                SCD_QUEUE_STTS_REG_MSK);
1358
1359                 /* enable the scheduler for this queue (only) */
1360                 if (txq_id == trans_pcie->cmd_queue &&
1361                     trans_pcie->scd_set_active)
1362                         iwl_scd_enable_set_active(trans, BIT(txq_id));
1363
1364                 IWL_DEBUG_TX_QUEUES(trans,
1365                                     "Activate queue %d on FIFO %d WrPtr: %d\n",
1366                                     txq_id, fifo, ssn & 0xff);
1367         } else {
1368                 IWL_DEBUG_TX_QUEUES(trans,
1369                                     "Activate queue %d WrPtr: %d\n",
1370                                     txq_id, ssn & 0xff);
1371         }
1372 }
1373
1374 void iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans *trans, u32 txq_id,
1375                                         bool shared_mode)
1376 {
1377         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1378         struct iwl_txq *txq = trans_pcie->txq[txq_id];
1379
1380         txq->ampdu = !shared_mode;
1381 }
1382
1383 void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id,
1384                                 bool configure_scd)
1385 {
1386         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1387         u32 stts_addr = trans_pcie->scd_base_addr +
1388                         SCD_TX_STTS_QUEUE_OFFSET(txq_id);
1389         static const u32 zero_val[4] = {};
1390
1391         trans_pcie->txq[txq_id]->frozen_expiry_remainder = 0;
1392         trans_pcie->txq[txq_id]->frozen = false;
1393
1394         /*
1395          * Upon HW Rfkill - we stop the device, and then stop the queues
1396          * in the op_mode. Just for the sake of the simplicity of the op_mode,
1397          * allow the op_mode to call txq_disable after it already called
1398          * stop_device.
1399          */
1400         if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) {
1401                 WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED, &trans->status),
1402                           "queue %d not used", txq_id);
1403                 return;
1404         }
1405
1406         if (configure_scd) {
1407                 iwl_scd_txq_set_inactive(trans, txq_id);
1408
1409                 iwl_trans_write_mem(trans, stts_addr, (void *)zero_val,
1410                                     ARRAY_SIZE(zero_val));
1411         }
1412
1413         iwl_pcie_txq_unmap(trans, txq_id);
1414         trans_pcie->txq[txq_id]->ampdu = false;
1415
1416         IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id);
1417 }
1418
1419 /*************** HOST COMMAND QUEUE FUNCTIONS   *****/
1420
1421 /*
1422  * iwl_pcie_enqueue_hcmd - enqueue a uCode command
1423  * @priv: device private data point
1424  * @cmd: a pointer to the ucode command structure
1425  *
1426  * The function returns < 0 values to indicate the operation
1427  * failed. On success, it returns the index (>= 0) of command in the
1428  * command queue.
1429  */
1430 static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
1431                                  struct iwl_host_cmd *cmd)
1432 {
1433         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1434         struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue];
1435         struct iwl_device_cmd *out_cmd;
1436         struct iwl_cmd_meta *out_meta;
1437         unsigned long flags;
1438         void *dup_buf = NULL;
1439         dma_addr_t phys_addr;
1440         int idx;
1441         u16 copy_size, cmd_size, tb0_size;
1442         bool had_nocopy = false;
1443         u8 group_id = iwl_cmd_groupid(cmd->id);
1444         int i, ret;
1445         u32 cmd_pos;
1446         const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD];
1447         u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD];
1448
1449         if (WARN(!trans->wide_cmd_header &&
1450                  group_id > IWL_ALWAYS_LONG_GROUP,
1451                  "unsupported wide command %#x\n", cmd->id))
1452                 return -EINVAL;
1453
1454         if (group_id != 0) {
1455                 copy_size = sizeof(struct iwl_cmd_header_wide);
1456                 cmd_size = sizeof(struct iwl_cmd_header_wide);
1457         } else {
1458                 copy_size = sizeof(struct iwl_cmd_header);
1459                 cmd_size = sizeof(struct iwl_cmd_header);
1460         }
1461
1462         /* need one for the header if the first is NOCOPY */
1463         BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD > IWL_NUM_OF_TBS - 1);
1464
1465         for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1466                 cmddata[i] = cmd->data[i];
1467                 cmdlen[i] = cmd->len[i];
1468
1469                 if (!cmd->len[i])
1470                         continue;
1471
1472                 /* need at least IWL_FIRST_TB_SIZE copied */
1473                 if (copy_size < IWL_FIRST_TB_SIZE) {
1474                         int copy = IWL_FIRST_TB_SIZE - copy_size;
1475
1476                         if (copy > cmdlen[i])
1477                                 copy = cmdlen[i];
1478                         cmdlen[i] -= copy;
1479                         cmddata[i] += copy;
1480                         copy_size += copy;
1481                 }
1482
1483                 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) {
1484                         had_nocopy = true;
1485                         if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) {
1486                                 idx = -EINVAL;
1487                                 goto free_dup_buf;
1488                         }
1489                 } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) {
1490                         /*
1491                          * This is also a chunk that isn't copied
1492                          * to the static buffer so set had_nocopy.
1493                          */
1494                         had_nocopy = true;
1495
1496                         /* only allowed once */
1497                         if (WARN_ON(dup_buf)) {
1498                                 idx = -EINVAL;
1499                                 goto free_dup_buf;
1500                         }
1501
1502                         dup_buf = kmemdup(cmddata[i], cmdlen[i],
1503                                           GFP_ATOMIC);
1504                         if (!dup_buf)
1505                                 return -ENOMEM;
1506                 } else {
1507                         /* NOCOPY must not be followed by normal! */
1508                         if (WARN_ON(had_nocopy)) {
1509                                 idx = -EINVAL;
1510                                 goto free_dup_buf;
1511                         }
1512                         copy_size += cmdlen[i];
1513                 }
1514                 cmd_size += cmd->len[i];
1515         }
1516
1517         /*
1518          * If any of the command structures end up being larger than
1519          * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
1520          * allocated into separate TFDs, then we will need to
1521          * increase the size of the buffers.
1522          */
1523         if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE,
1524                  "Command %s (%#x) is too large (%d bytes)\n",
1525                  iwl_get_cmd_string(trans, cmd->id),
1526                  cmd->id, copy_size)) {
1527                 idx = -EINVAL;
1528                 goto free_dup_buf;
1529         }
1530
1531         spin_lock_bh(&txq->lock);
1532
1533         if (iwl_queue_space(txq) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
1534                 spin_unlock_bh(&txq->lock);
1535
1536                 IWL_ERR(trans, "No space in command queue\n");
1537                 iwl_op_mode_cmd_queue_full(trans->op_mode);
1538                 idx = -ENOSPC;
1539                 goto free_dup_buf;
1540         }
1541
1542         idx = get_cmd_index(txq, txq->write_ptr);
1543         out_cmd = txq->entries[idx].cmd;
1544         out_meta = &txq->entries[idx].meta;
1545
1546         memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
1547         if (cmd->flags & CMD_WANT_SKB)
1548                 out_meta->source = cmd;
1549
1550         /* set up the header */
1551         if (group_id != 0) {
1552                 out_cmd->hdr_wide.cmd = iwl_cmd_opcode(cmd->id);
1553                 out_cmd->hdr_wide.group_id = group_id;
1554                 out_cmd->hdr_wide.version = iwl_cmd_version(cmd->id);
1555                 out_cmd->hdr_wide.length =
1556                         cpu_to_le16(cmd_size -
1557                                     sizeof(struct iwl_cmd_header_wide));
1558                 out_cmd->hdr_wide.reserved = 0;
1559                 out_cmd->hdr_wide.sequence =
1560                         cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
1561                                                  INDEX_TO_SEQ(txq->write_ptr));
1562
1563                 cmd_pos = sizeof(struct iwl_cmd_header_wide);
1564                 copy_size = sizeof(struct iwl_cmd_header_wide);
1565         } else {
1566                 out_cmd->hdr.cmd = iwl_cmd_opcode(cmd->id);
1567                 out_cmd->hdr.sequence =
1568                         cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
1569                                                  INDEX_TO_SEQ(txq->write_ptr));
1570                 out_cmd->hdr.group_id = 0;
1571
1572                 cmd_pos = sizeof(struct iwl_cmd_header);
1573                 copy_size = sizeof(struct iwl_cmd_header);
1574         }
1575
1576         /* and copy the data that needs to be copied */
1577         for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1578                 int copy;
1579
1580                 if (!cmd->len[i])
1581                         continue;
1582
1583                 /* copy everything if not nocopy/dup */
1584                 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1585                                            IWL_HCMD_DFL_DUP))) {
1586                         copy = cmd->len[i];
1587
1588                         memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1589                         cmd_pos += copy;
1590                         copy_size += copy;
1591                         continue;
1592                 }
1593
1594                 /*
1595                  * Otherwise we need at least IWL_FIRST_TB_SIZE copied
1596                  * in total (for bi-directional DMA), but copy up to what
1597                  * we can fit into the payload for debug dump purposes.
1598                  */
1599                 copy = min_t(int, TFD_MAX_PAYLOAD_SIZE - cmd_pos, cmd->len[i]);
1600
1601                 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1602                 cmd_pos += copy;
1603
1604                 /* However, treat copy_size the proper way, we need it below */
1605                 if (copy_size < IWL_FIRST_TB_SIZE) {
1606                         copy = IWL_FIRST_TB_SIZE - copy_size;
1607
1608                         if (copy > cmd->len[i])
1609                                 copy = cmd->len[i];
1610                         copy_size += copy;
1611                 }
1612         }
1613
1614         IWL_DEBUG_HC(trans,
1615                      "Sending command %s (%.2x.%.2x), seq: 0x%04X, %d bytes at %d[%d]:%d\n",
1616                      iwl_get_cmd_string(trans, cmd->id),
1617                      group_id, out_cmd->hdr.cmd,
1618                      le16_to_cpu(out_cmd->hdr.sequence),
1619                      cmd_size, txq->write_ptr, idx, trans_pcie->cmd_queue);
1620
1621         /* start the TFD with the minimum copy bytes */
1622         tb0_size = min_t(int, copy_size, IWL_FIRST_TB_SIZE);
1623         memcpy(&txq->first_tb_bufs[idx], &out_cmd->hdr, tb0_size);
1624         iwl_pcie_txq_build_tfd(trans, txq,
1625                                iwl_pcie_get_first_tb_dma(txq, idx),
1626                                tb0_size, true);
1627
1628         /* map first command fragment, if any remains */
1629         if (copy_size > tb0_size) {
1630                 phys_addr = dma_map_single(trans->dev,
1631                                            ((u8 *)&out_cmd->hdr) + tb0_size,
1632                                            copy_size - tb0_size,
1633                                            DMA_TO_DEVICE);
1634                 if (dma_mapping_error(trans->dev, phys_addr)) {
1635                         iwl_pcie_tfd_unmap(trans, out_meta, txq,
1636                                            txq->write_ptr);
1637                         idx = -ENOMEM;
1638                         goto out;
1639                 }
1640
1641                 iwl_pcie_txq_build_tfd(trans, txq, phys_addr,
1642                                        copy_size - tb0_size, false);
1643         }
1644
1645         /* map the remaining (adjusted) nocopy/dup fragments */
1646         for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1647                 const void *data = cmddata[i];
1648
1649                 if (!cmdlen[i])
1650                         continue;
1651                 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1652                                            IWL_HCMD_DFL_DUP)))
1653                         continue;
1654                 if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP)
1655                         data = dup_buf;
1656                 phys_addr = dma_map_single(trans->dev, (void *)data,
1657                                            cmdlen[i], DMA_TO_DEVICE);
1658                 if (dma_mapping_error(trans->dev, phys_addr)) {
1659                         iwl_pcie_tfd_unmap(trans, out_meta, txq,
1660                                            txq->write_ptr);
1661                         idx = -ENOMEM;
1662                         goto out;
1663                 }
1664
1665                 iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmdlen[i], false);
1666         }
1667
1668         BUILD_BUG_ON(IWL_TFH_NUM_TBS > sizeof(out_meta->tbs) * BITS_PER_BYTE);
1669         out_meta->flags = cmd->flags;
1670         if (WARN_ON_ONCE(txq->entries[idx].free_buf))
1671                 kzfree(txq->entries[idx].free_buf);
1672         txq->entries[idx].free_buf = dup_buf;
1673
1674         trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr_wide);
1675
1676         /* start timer if queue currently empty */
1677         if (txq->read_ptr == txq->write_ptr && txq->wd_timeout)
1678                 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
1679
1680         spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1681         ret = iwl_pcie_set_cmd_in_flight(trans, cmd);
1682         if (ret < 0) {
1683                 idx = ret;
1684                 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1685                 goto out;
1686         }
1687
1688         /* Increment and update queue's write index */
1689         txq->write_ptr = iwl_queue_inc_wrap(txq->write_ptr);
1690         iwl_pcie_txq_inc_wr_ptr(trans, txq);
1691
1692         spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1693
1694  out:
1695         spin_unlock_bh(&txq->lock);
1696  free_dup_buf:
1697         if (idx < 0)
1698                 kfree(dup_buf);
1699         return idx;
1700 }
1701
1702 /*
1703  * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them
1704  * @rxb: Rx buffer to reclaim
1705  */
1706 void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
1707                             struct iwl_rx_cmd_buffer *rxb)
1708 {
1709         struct iwl_rx_packet *pkt = rxb_addr(rxb);
1710         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1711         u8 group_id = iwl_cmd_groupid(pkt->hdr.group_id);
1712         u32 cmd_id;
1713         int txq_id = SEQ_TO_QUEUE(sequence);
1714         int index = SEQ_TO_INDEX(sequence);
1715         int cmd_index;
1716         struct iwl_device_cmd *cmd;
1717         struct iwl_cmd_meta *meta;
1718         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1719         struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue];
1720
1721         /* If a Tx command is being handled and it isn't in the actual
1722          * command queue then there a command routing bug has been introduced
1723          * in the queue management code. */
1724         if (WARN(txq_id != trans_pcie->cmd_queue,
1725                  "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
1726                  txq_id, trans_pcie->cmd_queue, sequence, txq->read_ptr,
1727                  txq->write_ptr)) {
1728                 iwl_print_hex_error(trans, pkt, 32);
1729                 return;
1730         }
1731
1732         spin_lock_bh(&txq->lock);
1733
1734         cmd_index = get_cmd_index(txq, index);
1735         cmd = txq->entries[cmd_index].cmd;
1736         meta = &txq->entries[cmd_index].meta;
1737         cmd_id = iwl_cmd_id(cmd->hdr.cmd, group_id, 0);
1738
1739         iwl_pcie_tfd_unmap(trans, meta, txq, index);
1740
1741         /* Input error checking is done when commands are added to queue. */
1742         if (meta->flags & CMD_WANT_SKB) {
1743                 struct page *p = rxb_steal_page(rxb);
1744
1745                 meta->source->resp_pkt = pkt;
1746                 meta->source->_rx_page_addr = (unsigned long)page_address(p);
1747                 meta->source->_rx_page_order = trans_pcie->rx_page_order;
1748         }
1749
1750         if (meta->flags & CMD_WANT_ASYNC_CALLBACK)
1751                 iwl_op_mode_async_cb(trans->op_mode, cmd);
1752
1753         iwl_pcie_cmdq_reclaim(trans, txq_id, index);
1754
1755         if (!(meta->flags & CMD_ASYNC)) {
1756                 if (!test_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status)) {
1757                         IWL_WARN(trans,
1758                                  "HCMD_ACTIVE already clear for command %s\n",
1759                                  iwl_get_cmd_string(trans, cmd_id));
1760                 }
1761                 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1762                 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
1763                                iwl_get_cmd_string(trans, cmd_id));
1764                 wake_up(&trans_pcie->wait_command_queue);
1765         }
1766
1767         if (meta->flags & CMD_MAKE_TRANS_IDLE) {
1768                 IWL_DEBUG_INFO(trans, "complete %s - mark trans as idle\n",
1769                                iwl_get_cmd_string(trans, cmd->hdr.cmd));
1770                 set_bit(STATUS_TRANS_IDLE, &trans->status);
1771                 wake_up(&trans_pcie->d0i3_waitq);
1772         }
1773
1774         if (meta->flags & CMD_WAKE_UP_TRANS) {
1775                 IWL_DEBUG_INFO(trans, "complete %s - clear trans idle flag\n",
1776                                iwl_get_cmd_string(trans, cmd->hdr.cmd));
1777                 clear_bit(STATUS_TRANS_IDLE, &trans->status);
1778                 wake_up(&trans_pcie->d0i3_waitq);
1779         }
1780
1781         meta->flags = 0;
1782
1783         spin_unlock_bh(&txq->lock);
1784 }
1785
1786 #define HOST_COMPLETE_TIMEOUT   (2 * HZ)
1787
1788 static int iwl_pcie_send_hcmd_async(struct iwl_trans *trans,
1789                                     struct iwl_host_cmd *cmd)
1790 {
1791         int ret;
1792
1793         /* An asynchronous command can not expect an SKB to be set. */
1794         if (WARN_ON(cmd->flags & CMD_WANT_SKB))
1795                 return -EINVAL;
1796
1797         ret = iwl_pcie_enqueue_hcmd(trans, cmd);
1798         if (ret < 0) {
1799                 IWL_ERR(trans,
1800                         "Error sending %s: enqueue_hcmd failed: %d\n",
1801                         iwl_get_cmd_string(trans, cmd->id), ret);
1802                 return ret;
1803         }
1804         return 0;
1805 }
1806
1807 static int iwl_pcie_send_hcmd_sync(struct iwl_trans *trans,
1808                                    struct iwl_host_cmd *cmd)
1809 {
1810         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1811         struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue];
1812         int cmd_idx;
1813         int ret;
1814
1815         IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n",
1816                        iwl_get_cmd_string(trans, cmd->id));
1817
1818         if (WARN(test_and_set_bit(STATUS_SYNC_HCMD_ACTIVE,
1819                                   &trans->status),
1820                  "Command %s: a command is already active!\n",
1821                  iwl_get_cmd_string(trans, cmd->id)))
1822                 return -EIO;
1823
1824         IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n",
1825                        iwl_get_cmd_string(trans, cmd->id));
1826
1827         if (pm_runtime_suspended(&trans_pcie->pci_dev->dev)) {
1828                 ret = wait_event_timeout(trans_pcie->d0i3_waitq,
1829                                  pm_runtime_active(&trans_pcie->pci_dev->dev),
1830                                  msecs_to_jiffies(IWL_TRANS_IDLE_TIMEOUT));
1831                 if (!ret) {
1832                         IWL_ERR(trans, "Timeout exiting D0i3 before hcmd\n");
1833                         return -ETIMEDOUT;
1834                 }
1835         }
1836
1837         cmd_idx = iwl_pcie_enqueue_hcmd(trans, cmd);
1838         if (cmd_idx < 0) {
1839                 ret = cmd_idx;
1840                 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1841                 IWL_ERR(trans,
1842                         "Error sending %s: enqueue_hcmd failed: %d\n",
1843                         iwl_get_cmd_string(trans, cmd->id), ret);
1844                 return ret;
1845         }
1846
1847         ret = wait_event_timeout(trans_pcie->wait_command_queue,
1848                                  !test_bit(STATUS_SYNC_HCMD_ACTIVE,
1849                                            &trans->status),
1850                                  HOST_COMPLETE_TIMEOUT);
1851         if (!ret) {
1852                 IWL_ERR(trans, "Error sending %s: time out after %dms.\n",
1853                         iwl_get_cmd_string(trans, cmd->id),
1854                         jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
1855
1856                 IWL_ERR(trans, "Current CMD queue read_ptr %d write_ptr %d\n",
1857                         txq->read_ptr, txq->write_ptr);
1858
1859                 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1860                 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
1861                                iwl_get_cmd_string(trans, cmd->id));
1862                 ret = -ETIMEDOUT;
1863
1864                 iwl_force_nmi(trans);
1865                 iwl_trans_fw_error(trans);
1866
1867                 goto cancel;
1868         }
1869
1870         if (test_bit(STATUS_FW_ERROR, &trans->status)) {
1871                 IWL_ERR(trans, "FW error in SYNC CMD %s\n",
1872                         iwl_get_cmd_string(trans, cmd->id));
1873                 dump_stack();
1874                 ret = -EIO;
1875                 goto cancel;
1876         }
1877
1878         if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
1879             test_bit(STATUS_RFKILL, &trans->status)) {
1880                 IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n");
1881                 ret = -ERFKILL;
1882                 goto cancel;
1883         }
1884
1885         if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) {
1886                 IWL_ERR(trans, "Error: Response NULL in '%s'\n",
1887                         iwl_get_cmd_string(trans, cmd->id));
1888                 ret = -EIO;
1889                 goto cancel;
1890         }
1891
1892         return 0;
1893
1894 cancel:
1895         if (cmd->flags & CMD_WANT_SKB) {
1896                 /*
1897                  * Cancel the CMD_WANT_SKB flag for the cmd in the
1898                  * TX cmd queue. Otherwise in case the cmd comes
1899                  * in later, it will possibly set an invalid
1900                  * address (cmd->meta.source).
1901                  */
1902                 txq->entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB;
1903         }
1904
1905         if (cmd->resp_pkt) {
1906                 iwl_free_resp(cmd);
1907                 cmd->resp_pkt = NULL;
1908         }
1909
1910         return ret;
1911 }
1912
1913 int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
1914 {
1915         if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
1916             test_bit(STATUS_RFKILL, &trans->status)) {
1917                 IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n",
1918                                   cmd->id);
1919                 return -ERFKILL;
1920         }
1921
1922         if (cmd->flags & CMD_ASYNC)
1923                 return iwl_pcie_send_hcmd_async(trans, cmd);
1924
1925         /* We still can fail on RFKILL that can be asserted while we wait */
1926         return iwl_pcie_send_hcmd_sync(trans, cmd);
1927 }
1928
1929 static int iwl_fill_data_tbs(struct iwl_trans *trans, struct sk_buff *skb,
1930                              struct iwl_txq *txq, u8 hdr_len,
1931                              struct iwl_cmd_meta *out_meta,
1932                              struct iwl_device_cmd *dev_cmd, u16 tb1_len)
1933 {
1934         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1935         u16 tb2_len;
1936         int i;
1937
1938         /*
1939          * Set up TFD's third entry to point directly to remainder
1940          * of skb's head, if any
1941          */
1942         tb2_len = skb_headlen(skb) - hdr_len;
1943
1944         if (tb2_len > 0) {
1945                 dma_addr_t tb2_phys = dma_map_single(trans->dev,
1946                                                      skb->data + hdr_len,
1947                                                      tb2_len, DMA_TO_DEVICE);
1948                 if (unlikely(dma_mapping_error(trans->dev, tb2_phys))) {
1949                         iwl_pcie_tfd_unmap(trans, out_meta, txq,
1950                                            txq->write_ptr);
1951                         return -EINVAL;
1952                 }
1953                 iwl_pcie_txq_build_tfd(trans, txq, tb2_phys, tb2_len, false);
1954         }
1955
1956         /* set up the remaining entries to point to the data */
1957         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1958                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1959                 dma_addr_t tb_phys;
1960                 int tb_idx;
1961
1962                 if (!skb_frag_size(frag))
1963                         continue;
1964
1965                 tb_phys = skb_frag_dma_map(trans->dev, frag, 0,
1966                                            skb_frag_size(frag), DMA_TO_DEVICE);
1967
1968                 if (unlikely(dma_mapping_error(trans->dev, tb_phys))) {
1969                         iwl_pcie_tfd_unmap(trans, out_meta, txq,
1970                                            txq->write_ptr);
1971                         return -EINVAL;
1972                 }
1973                 tb_idx = iwl_pcie_txq_build_tfd(trans, txq, tb_phys,
1974                                                 skb_frag_size(frag), false);
1975
1976                 out_meta->tbs |= BIT(tb_idx);
1977         }
1978
1979         trace_iwlwifi_dev_tx(trans->dev, skb,
1980                              iwl_pcie_get_tfd(trans_pcie, txq, txq->write_ptr),
1981                              trans_pcie->tfd_size,
1982                              &dev_cmd->hdr, IWL_FIRST_TB_SIZE + tb1_len,
1983                              skb->data + hdr_len, tb2_len);
1984         trace_iwlwifi_dev_tx_data(trans->dev, skb,
1985                                   hdr_len, skb->len - hdr_len);
1986         return 0;
1987 }
1988
1989 #ifdef CONFIG_INET
1990 struct iwl_tso_hdr_page *get_page_hdr(struct iwl_trans *trans, size_t len)
1991 {
1992         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1993         struct iwl_tso_hdr_page *p = this_cpu_ptr(trans_pcie->tso_hdr_page);
1994
1995         if (!p->page)
1996                 goto alloc;
1997
1998         /* enough room on this page */
1999         if (p->pos + len < (u8 *)page_address(p->page) + PAGE_SIZE)
2000                 return p;
2001
2002         /* We don't have enough room on this page, get a new one. */
2003         __free_page(p->page);
2004
2005 alloc:
2006         p->page = alloc_page(GFP_ATOMIC);
2007         if (!p->page)
2008                 return NULL;
2009         p->pos = page_address(p->page);
2010         return p;
2011 }
2012
2013 static void iwl_compute_pseudo_hdr_csum(void *iph, struct tcphdr *tcph,
2014                                         bool ipv6, unsigned int len)
2015 {
2016         if (ipv6) {
2017                 struct ipv6hdr *iphv6 = iph;
2018
2019                 tcph->check = ~csum_ipv6_magic(&iphv6->saddr, &iphv6->daddr,
2020                                                len + tcph->doff * 4,
2021                                                IPPROTO_TCP, 0);
2022         } else {
2023                 struct iphdr *iphv4 = iph;
2024
2025                 ip_send_check(iphv4);
2026                 tcph->check = ~csum_tcpudp_magic(iphv4->saddr, iphv4->daddr,
2027                                                  len + tcph->doff * 4,
2028                                                  IPPROTO_TCP, 0);
2029         }
2030 }
2031
2032 static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb,
2033                                    struct iwl_txq *txq, u8 hdr_len,
2034                                    struct iwl_cmd_meta *out_meta,
2035                                    struct iwl_device_cmd *dev_cmd, u16 tb1_len)
2036 {
2037         struct iwl_tx_cmd *tx_cmd = (void *)dev_cmd->payload;
2038         struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
2039         struct ieee80211_hdr *hdr = (void *)skb->data;
2040         unsigned int snap_ip_tcp_hdrlen, ip_hdrlen, total_len, hdr_room;
2041         unsigned int mss = skb_shinfo(skb)->gso_size;
2042         u16 length, iv_len, amsdu_pad;
2043         u8 *start_hdr;
2044         struct iwl_tso_hdr_page *hdr_page;
2045         struct page **page_ptr;
2046         int ret;
2047         struct tso_t tso;
2048
2049         /* if the packet is protected, then it must be CCMP or GCMP */
2050         BUILD_BUG_ON(IEEE80211_CCMP_HDR_LEN != IEEE80211_GCMP_HDR_LEN);
2051         iv_len = ieee80211_has_protected(hdr->frame_control) ?
2052                 IEEE80211_CCMP_HDR_LEN : 0;
2053
2054         trace_iwlwifi_dev_tx(trans->dev, skb,
2055                              iwl_pcie_get_tfd(trans_pcie, txq, txq->write_ptr),
2056                              trans_pcie->tfd_size,
2057                              &dev_cmd->hdr, IWL_FIRST_TB_SIZE + tb1_len,
2058                              NULL, 0);
2059
2060         ip_hdrlen = skb_transport_header(skb) - skb_network_header(skb);
2061         snap_ip_tcp_hdrlen = 8 + ip_hdrlen + tcp_hdrlen(skb);
2062         total_len = skb->len - snap_ip_tcp_hdrlen - hdr_len - iv_len;
2063         amsdu_pad = 0;
2064
2065         /* total amount of header we may need for this A-MSDU */
2066         hdr_room = DIV_ROUND_UP(total_len, mss) *
2067                 (3 + snap_ip_tcp_hdrlen + sizeof(struct ethhdr)) + iv_len;
2068
2069         /* Our device supports 9 segments at most, it will fit in 1 page */
2070         hdr_page = get_page_hdr(trans, hdr_room);
2071         if (!hdr_page)
2072                 return -ENOMEM;
2073
2074         get_page(hdr_page->page);
2075         start_hdr = hdr_page->pos;
2076         page_ptr = (void *)((u8 *)skb->cb + trans_pcie->page_offs);
2077         *page_ptr = hdr_page->page;
2078         memcpy(hdr_page->pos, skb->data + hdr_len, iv_len);
2079         hdr_page->pos += iv_len;
2080
2081         /*
2082          * Pull the ieee80211 header + IV to be able to use TSO core,
2083          * we will restore it for the tx_status flow.
2084          */
2085         skb_pull(skb, hdr_len + iv_len);
2086
2087         /*
2088          * Remove the length of all the headers that we don't actually
2089          * have in the MPDU by themselves, but that we duplicate into
2090          * all the different MSDUs inside the A-MSDU.
2091          */
2092         le16_add_cpu(&tx_cmd->len, -snap_ip_tcp_hdrlen);
2093
2094         tso_start(skb, &tso);
2095
2096         while (total_len) {
2097                 /* this is the data left for this subframe */
2098                 unsigned int data_left =
2099                         min_t(unsigned int, mss, total_len);
2100                 struct sk_buff *csum_skb = NULL;
2101                 unsigned int hdr_tb_len;
2102                 dma_addr_t hdr_tb_phys;
2103                 struct tcphdr *tcph;
2104                 u8 *iph, *subf_hdrs_start = hdr_page->pos;
2105
2106                 total_len -= data_left;
2107
2108                 memset(hdr_page->pos, 0, amsdu_pad);
2109                 hdr_page->pos += amsdu_pad;
2110                 amsdu_pad = (4 - (sizeof(struct ethhdr) + snap_ip_tcp_hdrlen +
2111                                   data_left)) & 0x3;
2112                 ether_addr_copy(hdr_page->pos, ieee80211_get_DA(hdr));
2113                 hdr_page->pos += ETH_ALEN;
2114                 ether_addr_copy(hdr_page->pos, ieee80211_get_SA(hdr));
2115                 hdr_page->pos += ETH_ALEN;
2116
2117                 length = snap_ip_tcp_hdrlen + data_left;
2118                 *((__be16 *)hdr_page->pos) = cpu_to_be16(length);
2119                 hdr_page->pos += sizeof(length);
2120
2121                 /*
2122                  * This will copy the SNAP as well which will be considered
2123                  * as MAC header.
2124                  */
2125                 tso_build_hdr(skb, hdr_page->pos, &tso, data_left, !total_len);
2126                 iph = hdr_page->pos + 8;
2127                 tcph = (void *)(iph + ip_hdrlen);
2128
2129                 /* For testing on current hardware only */
2130                 if (trans_pcie->sw_csum_tx) {
2131                         csum_skb = alloc_skb(data_left + tcp_hdrlen(skb),
2132                                              GFP_ATOMIC);
2133                         if (!csum_skb) {
2134                                 ret = -ENOMEM;
2135                                 goto out_unmap;
2136                         }
2137
2138                         iwl_compute_pseudo_hdr_csum(iph, tcph,
2139                                                     skb->protocol ==
2140                                                         htons(ETH_P_IPV6),
2141                                                     data_left);
2142
2143                         memcpy(skb_put(csum_skb, tcp_hdrlen(skb)),
2144                                tcph, tcp_hdrlen(skb));
2145                         skb_reset_transport_header(csum_skb);
2146                         csum_skb->csum_start =
2147                                 (unsigned char *)tcp_hdr(csum_skb) -
2148                                                  csum_skb->head;
2149                 }
2150
2151                 hdr_page->pos += snap_ip_tcp_hdrlen;
2152
2153                 hdr_tb_len = hdr_page->pos - start_hdr;
2154                 hdr_tb_phys = dma_map_single(trans->dev, start_hdr,
2155                                              hdr_tb_len, DMA_TO_DEVICE);
2156                 if (unlikely(dma_mapping_error(trans->dev, hdr_tb_phys))) {
2157                         dev_kfree_skb(csum_skb);
2158                         ret = -EINVAL;
2159                         goto out_unmap;
2160                 }
2161                 iwl_pcie_txq_build_tfd(trans, txq, hdr_tb_phys,
2162                                        hdr_tb_len, false);
2163                 trace_iwlwifi_dev_tx_tso_chunk(trans->dev, start_hdr,
2164                                                hdr_tb_len);
2165                 /* add this subframe's headers' length to the tx_cmd */
2166                 le16_add_cpu(&tx_cmd->len, hdr_page->pos - subf_hdrs_start);
2167
2168                 /* prepare the start_hdr for the next subframe */
2169                 start_hdr = hdr_page->pos;
2170
2171                 /* put the payload */
2172                 while (data_left) {
2173                         unsigned int size = min_t(unsigned int, tso.size,
2174                                                   data_left);
2175                         dma_addr_t tb_phys;
2176
2177                         if (trans_pcie->sw_csum_tx)
2178                                 memcpy(skb_put(csum_skb, size), tso.data, size);
2179
2180                         tb_phys = dma_map_single(trans->dev, tso.data,
2181                                                  size, DMA_TO_DEVICE);
2182                         if (unlikely(dma_mapping_error(trans->dev, tb_phys))) {
2183                                 dev_kfree_skb(csum_skb);
2184                                 ret = -EINVAL;
2185                                 goto out_unmap;
2186                         }
2187
2188                         iwl_pcie_txq_build_tfd(trans, txq, tb_phys,
2189                                                size, false);
2190                         trace_iwlwifi_dev_tx_tso_chunk(trans->dev, tso.data,
2191                                                        size);
2192
2193                         data_left -= size;
2194                         tso_build_data(skb, &tso, size);
2195                 }
2196
2197                 /* For testing on early hardware only */
2198                 if (trans_pcie->sw_csum_tx) {
2199                         __wsum csum;
2200
2201                         csum = skb_checksum(csum_skb,
2202                                             skb_checksum_start_offset(csum_skb),
2203                                             csum_skb->len -
2204                                             skb_checksum_start_offset(csum_skb),
2205                                             0);
2206                         dev_kfree_skb(csum_skb);
2207                         dma_sync_single_for_cpu(trans->dev, hdr_tb_phys,
2208                                                 hdr_tb_len, DMA_TO_DEVICE);
2209                         tcph->check = csum_fold(csum);
2210                         dma_sync_single_for_device(trans->dev, hdr_tb_phys,
2211                                                    hdr_tb_len, DMA_TO_DEVICE);
2212                 }
2213         }
2214
2215         /* re -add the WiFi header and IV */
2216         skb_push(skb, hdr_len + iv_len);
2217
2218         return 0;
2219
2220 out_unmap:
2221         iwl_pcie_tfd_unmap(trans, out_meta, txq, txq->write_ptr);
2222         return ret;
2223 }
2224 #else /* CONFIG_INET */
2225 static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb,
2226                                    struct iwl_txq *txq, u8 hdr_len,
2227                                    struct iwl_cmd_meta *out_meta,
2228                                    struct iwl_device_cmd *dev_cmd, u16 tb1_len)
2229 {
2230         /* No A-MSDU without CONFIG_INET */
2231         WARN_ON(1);
2232
2233         return -1;
2234 }
2235 #endif /* CONFIG_INET */
2236
2237 int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
2238                       struct iwl_device_cmd *dev_cmd, int txq_id)
2239 {
2240         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2241         struct ieee80211_hdr *hdr;
2242         struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload;
2243         struct iwl_cmd_meta *out_meta;
2244         struct iwl_txq *txq;
2245         dma_addr_t tb0_phys, tb1_phys, scratch_phys;
2246         void *tb1_addr;
2247         void *tfd;
2248         u16 len, tb1_len;
2249         bool wait_write_ptr;
2250         __le16 fc;
2251         u8 hdr_len;
2252         u16 wifi_seq;
2253         bool amsdu;
2254
2255         txq = trans_pcie->txq[txq_id];
2256
2257         if (WARN_ONCE(!test_bit(txq_id, trans_pcie->queue_used),
2258                       "TX on unused queue %d\n", txq_id))
2259                 return -EINVAL;
2260
2261         if (unlikely(trans_pcie->sw_csum_tx &&
2262                      skb->ip_summed == CHECKSUM_PARTIAL)) {
2263                 int offs = skb_checksum_start_offset(skb);
2264                 int csum_offs = offs + skb->csum_offset;
2265                 __wsum csum;
2266
2267                 if (skb_ensure_writable(skb, csum_offs + sizeof(__sum16)))
2268                         return -1;
2269
2270                 csum = skb_checksum(skb, offs, skb->len - offs, 0);
2271                 *(__sum16 *)(skb->data + csum_offs) = csum_fold(csum);
2272
2273                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2274         }
2275
2276         if (skb_is_nonlinear(skb) &&
2277             skb_shinfo(skb)->nr_frags > IWL_PCIE_MAX_FRAGS(trans_pcie) &&
2278             __skb_linearize(skb))
2279                 return -ENOMEM;
2280
2281         /* mac80211 always puts the full header into the SKB's head,
2282          * so there's no need to check if it's readable there
2283          */
2284         hdr = (struct ieee80211_hdr *)skb->data;
2285         fc = hdr->frame_control;
2286         hdr_len = ieee80211_hdrlen(fc);
2287
2288         spin_lock(&txq->lock);
2289
2290         if (iwl_queue_space(txq) < txq->high_mark) {
2291                 iwl_stop_queue(trans, txq);
2292
2293                 /* don't put the packet on the ring, if there is no room */
2294                 if (unlikely(iwl_queue_space(txq) < 3)) {
2295                         struct iwl_device_cmd **dev_cmd_ptr;
2296
2297                         dev_cmd_ptr = (void *)((u8 *)skb->cb +
2298                                                trans_pcie->dev_cmd_offs);
2299
2300                         *dev_cmd_ptr = dev_cmd;
2301                         __skb_queue_tail(&txq->overflow_q, skb);
2302
2303                         spin_unlock(&txq->lock);
2304                         return 0;
2305                 }
2306         }
2307
2308         /* In AGG mode, the index in the ring must correspond to the WiFi
2309          * sequence number. This is a HW requirements to help the SCD to parse
2310          * the BA.
2311          * Check here that the packets are in the right place on the ring.
2312          */
2313         wifi_seq = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
2314         WARN_ONCE(txq->ampdu &&
2315                   (wifi_seq & 0xff) != txq->write_ptr,
2316                   "Q: %d WiFi Seq %d tfdNum %d",
2317                   txq_id, wifi_seq, txq->write_ptr);
2318
2319         /* Set up driver data for this TFD */
2320         txq->entries[txq->write_ptr].skb = skb;
2321         txq->entries[txq->write_ptr].cmd = dev_cmd;
2322
2323         dev_cmd->hdr.sequence =
2324                 cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
2325                             INDEX_TO_SEQ(txq->write_ptr)));
2326
2327         tb0_phys = iwl_pcie_get_first_tb_dma(txq, txq->write_ptr);
2328         scratch_phys = tb0_phys + sizeof(struct iwl_cmd_header) +
2329                        offsetof(struct iwl_tx_cmd, scratch);
2330
2331         tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
2332         tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
2333
2334         /* Set up first empty entry in queue's array of Tx/cmd buffers */
2335         out_meta = &txq->entries[txq->write_ptr].meta;
2336         out_meta->flags = 0;
2337
2338         /*
2339          * The second TB (tb1) points to the remainder of the TX command
2340          * and the 802.11 header - dword aligned size
2341          * (This calculation modifies the TX command, so do it before the
2342          * setup of the first TB)
2343          */
2344         len = sizeof(struct iwl_tx_cmd) + sizeof(struct iwl_cmd_header) +
2345               hdr_len - IWL_FIRST_TB_SIZE;
2346         /* do not align A-MSDU to dword as the subframe header aligns it */
2347         amsdu = ieee80211_is_data_qos(fc) &&
2348                 (*ieee80211_get_qos_ctl(hdr) &
2349                  IEEE80211_QOS_CTL_A_MSDU_PRESENT);
2350         if (trans_pcie->sw_csum_tx || !amsdu) {
2351                 tb1_len = ALIGN(len, 4);
2352                 /* Tell NIC about any 2-byte padding after MAC header */
2353                 if (tb1_len != len)
2354                         tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
2355         } else {
2356                 tb1_len = len;
2357         }
2358
2359         /*
2360          * The first TB points to bi-directional DMA data, we'll
2361          * memcpy the data into it later.
2362          */
2363         iwl_pcie_txq_build_tfd(trans, txq, tb0_phys,
2364                                IWL_FIRST_TB_SIZE, true);
2365
2366         /* there must be data left over for TB1 or this code must be changed */
2367         BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_FIRST_TB_SIZE);
2368
2369         /* map the data for TB1 */
2370         tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_FIRST_TB_SIZE;
2371         tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE);
2372         if (unlikely(dma_mapping_error(trans->dev, tb1_phys)))
2373                 goto out_err;
2374         iwl_pcie_txq_build_tfd(trans, txq, tb1_phys, tb1_len, false);
2375
2376         if (amsdu) {
2377                 if (unlikely(iwl_fill_data_tbs_amsdu(trans, skb, txq, hdr_len,
2378                                                      out_meta, dev_cmd,
2379                                                      tb1_len)))
2380                         goto out_err;
2381         } else if (unlikely(iwl_fill_data_tbs(trans, skb, txq, hdr_len,
2382                                        out_meta, dev_cmd, tb1_len))) {
2383                 goto out_err;
2384         }
2385
2386         /* building the A-MSDU might have changed this data, so memcpy it now */
2387         memcpy(&txq->first_tb_bufs[txq->write_ptr], &dev_cmd->hdr,
2388                IWL_FIRST_TB_SIZE);
2389
2390         tfd = iwl_pcie_get_tfd(trans_pcie, txq, txq->write_ptr);
2391         /* Set up entry for this TFD in Tx byte-count array */
2392         iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len),
2393                                          iwl_pcie_tfd_get_num_tbs(trans, tfd));
2394
2395         wait_write_ptr = ieee80211_has_morefrags(fc);
2396
2397         /* start timer if queue currently empty */
2398         if (txq->read_ptr == txq->write_ptr) {
2399                 if (txq->wd_timeout) {
2400                         /*
2401                          * If the TXQ is active, then set the timer, if not,
2402                          * set the timer in remainder so that the timer will
2403                          * be armed with the right value when the station will
2404                          * wake up.
2405                          */
2406                         if (!txq->frozen)
2407                                 mod_timer(&txq->stuck_timer,
2408                                           jiffies + txq->wd_timeout);
2409                         else
2410                                 txq->frozen_expiry_remainder = txq->wd_timeout;
2411                 }
2412                 IWL_DEBUG_RPM(trans, "Q: %d first tx - take ref\n", txq->id);
2413                 iwl_trans_ref(trans);
2414         }
2415
2416         /* Tell device the write index *just past* this latest filled TFD */
2417         txq->write_ptr = iwl_queue_inc_wrap(txq->write_ptr);
2418         if (!wait_write_ptr)
2419                 iwl_pcie_txq_inc_wr_ptr(trans, txq);
2420
2421         /*
2422          * At this point the frame is "transmitted" successfully
2423          * and we will get a TX status notification eventually.
2424          */
2425         spin_unlock(&txq->lock);
2426         return 0;
2427 out_err:
2428         spin_unlock(&txq->lock);
2429         return -1;
2430 }