drivers/net/wireless/intel/iwlwifi/pcie/tx.c

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
   9  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  10  * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
  11  * Copyright(c) 2018 - 2019 Intel Corporation
  12  *
  13  * This program is free software; you can redistribute it and/or modify it
  14  * under the terms of version 2 of the GNU General Public License as
  15  * published by the Free Software Foundation.
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  17  * This program is distributed in the hope that it will be useful, but WITHOUT
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  20  * more details.
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  22  * The full GNU General Public License is included in this distribution in the
  23  * file called COPYING.
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  25  * Contact Information:
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  27  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  28  *
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  30  *
  31  * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
  32  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  33  * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
  34  * Copyright(c) 2018 - 2019 Intel Corporation
  35  * All rights reserved.
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  38  * modification, are permitted provided that the following conditions
  39  * are met:
  40  *
  41  *  * Redistributions of source code must retain the above copyright
  42  *    notice, this list of conditions and the following disclaimer.
  43  *  * Redistributions in binary form must reproduce the above copyright
  44  *    notice, this list of conditions and the following disclaimer in
  45  *    the documentation and/or other materials provided with the
  46  *    distribution.
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  48  *    contributors may be used to endorse or promote products derived
  49  *    from this software without specific prior written permission.
  50  *
  51  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  52  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  53  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  54  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  55  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  60  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  61  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  62  *
  63  *****************************************************************************/
  64 #include <linux/etherdevice.h>
  65 #include <linux/ieee80211.h>
  66 #include <linux/slab.h>
  67 #include <linux/sched.h>
  68 #include <net/ip6_checksum.h>
  69 #include <net/tso.h>
  70
  71 #include "iwl-debug.h"
  72 #include "iwl-csr.h"
  73 #include "iwl-prph.h"
  74 #include "iwl-io.h"
  75 #include "iwl-scd.h"
  76 #include "iwl-op-mode.h"
  77 #include "internal.h"
  78 #include "fw/api/tx.h"
  79
  80 #define IWL_TX_CRC_SIZE 4
  81 #define IWL_TX_DELIMITER_SIZE 4
  82
  83 /*************** DMA-QUEUE-GENERAL-FUNCTIONS  *****
  84  * DMA services
  85  *
  86  * Theory of operation
  87  *
  88  * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
  89  * of buffer descriptors, each of which points to one or more data buffers for
  90  * the device to read from or fill.  Driver and device exchange status of each
  91  * queue via "read" and "write" pointers.  Driver keeps minimum of 2 empty
  92  * entries in each circular buffer, to protect against confusing empty and full
  93  * queue states.
  94  *
  95  * The device reads or writes the data in the queues via the device's several
  96  * DMA/FIFO channels.  Each queue is mapped to a single DMA channel.
  97  *
  98  * For Tx queue, there are low mark and high mark limits. If, after queuing
  99  * the packet for Tx, free space become < low mark, Tx queue stopped. When
 100  * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
 101  * Tx queue resumed.
 102  *
 103  ***************************************************/
 104
 105 int iwl_queue_space(struct iwl_trans *trans, const struct iwl_txq *q)
 106 {
 107         unsigned int max;
 108         unsigned int used;
 109
 110         /*
 111          * To avoid ambiguity between empty and completely full queues, there
 112          * should always be less than max_tfd_queue_size elements in the queue.
 113          * If q->n_window is smaller than max_tfd_queue_size, there is no need
 114          * to reserve any queue entries for this purpose.
 115          */
 116         if (q->n_window < trans->trans_cfg->base_params->max_tfd_queue_size)
 117                 max = q->n_window;
 118         else
 119                 max = trans->trans_cfg->base_params->max_tfd_queue_size - 1;
 120
 121         /*
 122          * max_tfd_queue_size is a power of 2, so the following is equivalent to
 123          * modulo by max_tfd_queue_size and is well defined.
 124          */
 125         used = (q->write_ptr - q->read_ptr) &
 126                 (trans->trans_cfg->base_params->max_tfd_queue_size - 1);
 127
 128         if (WARN_ON(used > max))
 129                 return 0;
 130
 131         return max - used;
 132 }
 133
 134 /*
 135  * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
 136  */
 137 static int iwl_queue_init(struct iwl_txq *q, int slots_num)
 138 {
 139         q->n_window = slots_num;
 140
 141         /* slots_num must be power-of-two size, otherwise
 142          * iwl_pcie_get_cmd_index is broken. */
 143         if (WARN_ON(!is_power_of_2(slots_num)))
 144                 return -EINVAL;
 145
 146         q->low_mark = q->n_window / 4;
 147         if (q->low_mark < 4)
 148                 q->low_mark = 4;
 149
 150         q->high_mark = q->n_window / 8;
 151         if (q->high_mark < 2)
 152                 q->high_mark = 2;
 153
 154         q->write_ptr = 0;
 155         q->read_ptr = 0;
 156
 157         return 0;
 158 }
 159
 160 int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans,
 161                            struct iwl_dma_ptr *ptr, size_t size)
 162 {
 163         if (WARN_ON(ptr->addr))
 164                 return -EINVAL;
 165
 166         ptr->addr = dma_alloc_coherent(trans->dev, size,
 167                                        &ptr->dma, GFP_KERNEL);
 168         if (!ptr->addr)
 169                 return -ENOMEM;
 170         ptr->size = size;
 171         return 0;
 172 }
 173
 174 void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, struct iwl_dma_ptr *ptr)
 175 {
 176         if (unlikely(!ptr->addr))
 177                 return;
 178
 179         dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
 180         memset(ptr, 0, sizeof(*ptr));
 181 }
 182
 183 static void iwl_pcie_txq_stuck_timer(struct timer_list *t)
 184 {
 185         struct iwl_txq *txq = from_timer(txq, t, stuck_timer);
 186         struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
 187         struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie);
 188
 189         spin_lock(&txq->lock);
 190         /* check if triggered erroneously */
 191         if (txq->read_ptr == txq->write_ptr) {
 192                 spin_unlock(&txq->lock);
 193                 return;
 194         }
 195         spin_unlock(&txq->lock);
 196
 197         iwl_trans_pcie_log_scd_error(trans, txq);
 198
 199         iwl_force_nmi(trans);
 200 }
 201
 202 /*
 203  * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
 204  */
 205 static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
 206                                              struct iwl_txq *txq, u16 byte_cnt,
 207                                              int num_tbs)
 208 {
 209         struct iwlagn_scd_bc_tbl *scd_bc_tbl;
 210         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 211         int write_ptr = txq->write_ptr;
 212         int txq_id = txq->id;
 213         u8 sec_ctl = 0;
 214         u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
 215         __le16 bc_ent;
 216         struct iwl_tx_cmd *tx_cmd =
 217                 (void *)txq->entries[txq->write_ptr].cmd->payload;
 218         u8 sta_id = tx_cmd->sta_id;
 219
 220         scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
 221
 222         sec_ctl = tx_cmd->sec_ctl;
 223
 224         switch (sec_ctl & TX_CMD_SEC_MSK) {
 225         case TX_CMD_SEC_CCM:
 226                 len += IEEE80211_CCMP_MIC_LEN;
 227                 break;
 228         case TX_CMD_SEC_TKIP:
 229                 len += IEEE80211_TKIP_ICV_LEN;
 230                 break;
 231         case TX_CMD_SEC_WEP:
 232                 len += IEEE80211_WEP_IV_LEN + IEEE80211_WEP_ICV_LEN;
 233                 break;
 234         }
 235         if (trans_pcie->bc_table_dword)
 236                 len = DIV_ROUND_UP(len, 4);
 237
 238         if (WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX))
 239                 return;
 240
 241         bc_ent = cpu_to_le16(len | (sta_id << 12));
 242
 243         scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
 244
 245         if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
 246                 scd_bc_tbl[txq_id].
 247                         tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
 248 }
 249
 250 static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans,
 251                                             struct iwl_txq *txq)
 252 {
 253         struct iwl_trans_pcie *trans_pcie =
 254                 IWL_TRANS_GET_PCIE_TRANS(trans);
 255         struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
 256         int txq_id = txq->id;
 257         int read_ptr = txq->read_ptr;
 258         u8 sta_id = 0;
 259         __le16 bc_ent;
 260         struct iwl_tx_cmd *tx_cmd =
 261                 (void *)txq->entries[read_ptr].cmd->payload;
 262
 263         WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
 264
 265         if (txq_id != trans_pcie->cmd_queue)
 266                 sta_id = tx_cmd->sta_id;
 267
 268         bc_ent = cpu_to_le16(1 | (sta_id << 12));
 269
 270         scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
 271
 272         if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
 273                 scd_bc_tbl[txq_id].
 274                         tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
 275 }
 276
 277 /*
 278  * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware
 279  */
 280 static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans,
 281                                     struct iwl_txq *txq)
 282 {
 283         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 284         u32 reg = 0;
 285         int txq_id = txq->id;
 286
 287         lockdep_assert_held(&txq->lock);
 288
 289         /*
 290          * explicitly wake up the NIC if:
 291          * 1. shadow registers aren't enabled
 292          * 2. NIC is woken up for CMD regardless of shadow outside this function
 293          * 3. there is a chance that the NIC is asleep
 294          */
 295         if (!trans->trans_cfg->base_params->shadow_reg_enable &&
 296             txq_id != trans_pcie->cmd_queue &&
 297             test_bit(STATUS_TPOWER_PMI, &trans->status)) {
 298                 /*
 299                  * wake up nic if it's powered down ...
 300                  * uCode will wake up, and interrupt us again, so next
 301                  * time we'll skip this part.
 302                  */
 303                 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
 304
 305                 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
 306                         IWL_DEBUG_INFO(trans, "Tx queue %d requesting wakeup, GP1 = 0x%x\n",
 307                                        txq_id, reg);
 308                         iwl_set_bit(trans, CSR_GP_CNTRL,
 309                                     BIT(trans->trans_cfg->csr->flag_mac_access_req));
 310                         txq->need_update = true;
 311                         return;
 312                 }
 313         }
 314
 315         /*
 316          * if not in power-save mode, uCode will never sleep when we're
 317          * trying to tx (during RFKILL, we're not trying to tx).
 318          */
 319         IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id, txq->write_ptr);
 320         if (!txq->block)
 321                 iwl_write32(trans, HBUS_TARG_WRPTR,
 322                             txq->write_ptr | (txq_id << 8));
 323 }
 324
 325 void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans)
 326 {
 327         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 328         int i;
 329
 330         for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) {
 331                 struct iwl_txq *txq = trans_pcie->txq[i];
 332
 333                 if (!test_bit(i, trans_pcie->queue_used))
 334                         continue;
 335
 336                 spin_lock_bh(&txq->lock);
 337                 if (txq->need_update) {
 338                         iwl_pcie_txq_inc_wr_ptr(trans, txq);
 339                         txq->need_update = false;
 340                 }
 341                 spin_unlock_bh(&txq->lock);
 342         }
 343 }
 344
 345 static inline dma_addr_t iwl_pcie_tfd_tb_get_addr(struct iwl_trans *trans,
 346                                                   void *_tfd, u8 idx)
 347 {
 348
 349         if (trans->trans_cfg->use_tfh) {
 350                 struct iwl_tfh_tfd *tfd = _tfd;
 351                 struct iwl_tfh_tb *tb = &tfd->tbs[idx];
 352
 353                 return (dma_addr_t)(le64_to_cpu(tb->addr));
 354         } else {
 355                 struct iwl_tfd *tfd = _tfd;
 356                 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 357                 dma_addr_t addr = get_unaligned_le32(&tb->lo);
 358                 dma_addr_t hi_len;
 359
 360                 if (sizeof(dma_addr_t) <= sizeof(u32))
 361                         return addr;
 362
 363                 hi_len = le16_to_cpu(tb->hi_n_len) & 0xF;
 364
 365                 /*
 366                  * shift by 16 twice to avoid warnings on 32-bit
 367                  * (where this code never runs anyway due to the
 368                  * if statement above)
 369                  */
 370                 return addr | ((hi_len << 16) << 16);
 371         }
 372 }
 373
 374 static inline void iwl_pcie_tfd_set_tb(struct iwl_trans *trans, void *tfd,
 375                                        u8 idx, dma_addr_t addr, u16 len)
 376 {
 377         struct iwl_tfd *tfd_fh = (void *)tfd;
 378         struct iwl_tfd_tb *tb = &tfd_fh->tbs[idx];
 379
 380         u16 hi_n_len = len << 4;
 381
 382         put_unaligned_le32(addr, &tb->lo);
 383         hi_n_len |= iwl_get_dma_hi_addr(addr);
 384
 385         tb->hi_n_len = cpu_to_le16(hi_n_len);
 386
 387         tfd_fh->num_tbs = idx + 1;
 388 }
 389
 390 static inline u8 iwl_pcie_tfd_get_num_tbs(struct iwl_trans *trans, void *_tfd)
 391 {
 392         if (trans->trans_cfg->use_tfh) {
 393                 struct iwl_tfh_tfd *tfd = _tfd;
 394
 395                 return le16_to_cpu(tfd->num_tbs) & 0x1f;
 396         } else {
 397                 struct iwl_tfd *tfd = _tfd;
 398
 399                 return tfd->num_tbs & 0x1f;
 400         }
 401 }
 402
 403 static void iwl_pcie_tfd_unmap(struct iwl_trans *trans,
 404                                struct iwl_cmd_meta *meta,
 405                                struct iwl_txq *txq, int index)
 406 {
 407         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 408         int i, num_tbs;
 409         void *tfd = iwl_pcie_get_tfd(trans, txq, index);
 410
 411         /* Sanity check on number of chunks */
 412         num_tbs = iwl_pcie_tfd_get_num_tbs(trans, tfd);
 413
 414         if (num_tbs > trans_pcie->max_tbs) {
 415                 IWL_ERR(trans, "Too many chunks: %i\n", num_tbs);
 416                 /* @todo issue fatal error, it is quite serious situation */
 417                 return;
 418         }
 419
 420         /* first TB is never freed - it's the bidirectional DMA data */
 421
 422         for (i = 1; i < num_tbs; i++) {
 423                 if (meta->tbs & BIT(i))
 424                         dma_unmap_page(trans->dev,
 425                                        iwl_pcie_tfd_tb_get_addr(trans, tfd, i),
 426                                        iwl_pcie_tfd_tb_get_len(trans, tfd, i),
 427                                        DMA_TO_DEVICE);
 428                 else
 429                         dma_unmap_single(trans->dev,
 430                                          iwl_pcie_tfd_tb_get_addr(trans, tfd,
 431                                                                   i),
 432                                          iwl_pcie_tfd_tb_get_len(trans, tfd,
 433                                                                  i),
 434                                          DMA_TO_DEVICE);
 435         }
 436
 437         meta->tbs = 0;
 438
 439         if (trans->trans_cfg->use_tfh) {
 440                 struct iwl_tfh_tfd *tfd_fh = (void *)tfd;
 441
 442                 tfd_fh->num_tbs = 0;
 443         } else {
 444                 struct iwl_tfd *tfd_fh = (void *)tfd;
 445
 446                 tfd_fh->num_tbs = 0;
 447         }
 448
 449 }
 450
 451 /*
 452  * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
 453  * @trans - transport private data
 454  * @txq - tx queue
 455  * @dma_dir - the direction of the DMA mapping
 456  *
 457  * Does NOT advance any TFD circular buffer read/write indexes
 458  * Does NOT free the TFD itself (which is within circular buffer)
 459  */
 460 void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq)
 461 {
 462         /* rd_ptr is bounded by TFD_QUEUE_SIZE_MAX and
 463          * idx is bounded by n_window
 464          */
 465         int rd_ptr = txq->read_ptr;
 466         int idx = iwl_pcie_get_cmd_index(txq, rd_ptr);
 467
 468         lockdep_assert_held(&txq->lock);
 469
 470         /* We have only q->n_window txq->entries, but we use
 471          * TFD_QUEUE_SIZE_MAX tfds
 472          */
 473         iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, txq, rd_ptr);
 474
 475         /* free SKB */
 476         if (txq->entries) {
 477                 struct sk_buff *skb;
 478
 479                 skb = txq->entries[idx].skb;
 480
 481                 /* Can be called from irqs-disabled context
 482                  * If skb is not NULL, it means that the whole queue is being
 483                  * freed and that the queue is not empty - free the skb
 484                  */
 485                 if (skb) {
 486                         iwl_op_mode_free_skb(trans->op_mode, skb);
 487                         txq->entries[idx].skb = NULL;
 488                 }
 489         }
 490 }
 491
 492 static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq,
 493                                   dma_addr_t addr, u16 len, bool reset)
 494 {
 495         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 496         void *tfd;
 497         u32 num_tbs;
 498
 499         tfd = txq->tfds + trans_pcie->tfd_size * txq->write_ptr;
 500
 501         if (reset)
 502                 memset(tfd, 0, trans_pcie->tfd_size);
 503
 504         num_tbs = iwl_pcie_tfd_get_num_tbs(trans, tfd);
 505
 506         /* Each TFD can point to a maximum max_tbs Tx buffers */
 507         if (num_tbs >= trans_pcie->max_tbs) {
 508                 IWL_ERR(trans, "Error can not send more than %d chunks\n",
 509                         trans_pcie->max_tbs);
 510                 return -EINVAL;
 511         }
 512
 513         if (WARN(addr & ~IWL_TX_DMA_MASK,
 514                  "Unaligned address = %llx\n", (unsigned long long)addr))
 515                 return -EINVAL;
 516
 517         iwl_pcie_tfd_set_tb(trans, tfd, num_tbs, addr, len);
 518
 519         return num_tbs;
 520 }
 521
 522 int iwl_pcie_txq_alloc(struct iwl_trans *trans, struct iwl_txq *txq,
 523                        int slots_num, bool cmd_queue)
 524 {
 525         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 526         size_t tfd_sz = trans_pcie->tfd_size *
 527                 trans->trans_cfg->base_params->max_tfd_queue_size;
 528         size_t tb0_buf_sz;
 529         int i;
 530
 531         if (WARN_ON(txq->entries || txq->tfds))
 532                 return -EINVAL;
 533
 534         if (trans->trans_cfg->use_tfh)
 535                 tfd_sz = trans_pcie->tfd_size * slots_num;
 536
 537         timer_setup(&txq->stuck_timer, iwl_pcie_txq_stuck_timer, 0);
 538         txq->trans_pcie = trans_pcie;
 539
 540         txq->n_window = slots_num;
 541
 542         txq->entries = kcalloc(slots_num,
 543                                sizeof(struct iwl_pcie_txq_entry),
 544                                GFP_KERNEL);
 545
 546         if (!txq->entries)
 547                 goto error;
 548
 549         if (cmd_queue)
 550                 for (i = 0; i < slots_num; i++) {
 551                         txq->entries[i].cmd =
 552                                 kmalloc(sizeof(struct iwl_device_cmd),
 553                                         GFP_KERNEL);
 554                         if (!txq->entries[i].cmd)
 555                                 goto error;
 556                 }
 557
 558         /* Circular buffer of transmit frame descriptors (TFDs),
 559          * shared with device */
 560         txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
 561                                        &txq->dma_addr, GFP_KERNEL);
 562         if (!txq->tfds)
 563                 goto error;
 564
 565         BUILD_BUG_ON(IWL_FIRST_TB_SIZE_ALIGN != sizeof(*txq->first_tb_bufs));
 566
 567         tb0_buf_sz = sizeof(*txq->first_tb_bufs) * slots_num;
 568
 569         txq->first_tb_bufs = dma_alloc_coherent(trans->dev, tb0_buf_sz,
 570                                               &txq->first_tb_dma,
 571                                               GFP_KERNEL);
 572         if (!txq->first_tb_bufs)
 573                 goto err_free_tfds;
 574
 575         return 0;
 576 err_free_tfds:
 577         dma_free_coherent(trans->dev, tfd_sz, txq->tfds, txq->dma_addr);
 578 error:
 579         if (txq->entries && cmd_queue)
 580                 for (i = 0; i < slots_num; i++)
 581                         kfree(txq->entries[i].cmd);
 582         kfree(txq->entries);
 583         txq->entries = NULL;
 584
 585         return -ENOMEM;
 586
 587 }
 588
 589 int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq,
 590                       int slots_num, bool cmd_queue)
 591 {
 592         int ret;
 593         u32 tfd_queue_max_size =
 594                 trans->trans_cfg->base_params->max_tfd_queue_size;
 595
 596         txq->need_update = false;
 597
 598         /* max_tfd_queue_size must be power-of-two size, otherwise
 599          * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
 600         if (WARN_ONCE(tfd_queue_max_size & (tfd_queue_max_size - 1),
 601                       "Max tfd queue size must be a power of two, but is %d",
 602                       tfd_queue_max_size))
 603                 return -EINVAL;
 604
 605         /* Initialize queue's high/low-water marks, and head/tail indexes */
 606         ret = iwl_queue_init(txq, slots_num);
 607         if (ret)
 608                 return ret;
 609
 610         spin_lock_init(&txq->lock);
 611
 612         if (cmd_queue) {
 613                 static struct lock_class_key iwl_pcie_cmd_queue_lock_class;
 614
 615                 lockdep_set_class(&txq->lock, &iwl_pcie_cmd_queue_lock_class);
 616         }
 617
 618         __skb_queue_head_init(&txq->overflow_q);
 619
 620         return 0;
 621 }
 622
 623 void iwl_pcie_free_tso_page(struct iwl_trans_pcie *trans_pcie,
 624                             struct sk_buff *skb)
 625 {
 626         struct page **page_ptr;
 627
 628         page_ptr = (void *)((u8 *)skb->cb + trans_pcie->page_offs);
 629
 630         if (*page_ptr) {
 631                 __free_page(*page_ptr);
 632                 *page_ptr = NULL;
 633         }
 634 }
 635
 636 static void iwl_pcie_clear_cmd_in_flight(struct iwl_trans *trans)
 637 {
 638         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 639
 640         lockdep_assert_held(&trans_pcie->reg_lock);
 641
 642         if (!trans->trans_cfg->base_params->apmg_wake_up_wa)
 643                 return;
 644         if (WARN_ON(!trans_pcie->cmd_hold_nic_awake))
 645                 return;
 646
 647         trans_pcie->cmd_hold_nic_awake = false;
 648         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 649                                    BIT(trans->trans_cfg->csr->flag_mac_access_req));
 650 }
 651
 652 /*
 653  * iwl_pcie_txq_unmap -  Unmap any remaining DMA mappings and free skb's
 654  */
 655 static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id)
 656 {
 657         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 658         struct iwl_txq *txq = trans_pcie->txq[txq_id];
 659
 660         spin_lock_bh(&txq->lock);
 661         while (txq->write_ptr != txq->read_ptr) {
 662                 IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n",
 663                                    txq_id, txq->read_ptr);
 664
 665                 if (txq_id != trans_pcie->cmd_queue) {
 666                         struct sk_buff *skb = txq->entries[txq->read_ptr].skb;
 667
 668                         if (WARN_ON_ONCE(!skb))
 669                                 continue;
 670
 671                         iwl_pcie_free_tso_page(trans_pcie, skb);
 672                 }
 673                 iwl_pcie_txq_free_tfd(trans, txq);
 674                 txq->read_ptr = iwl_queue_inc_wrap(trans, txq->read_ptr);
 675
 676                 if (txq->read_ptr == txq->write_ptr) {
 677                         unsigned long flags;
 678
 679                         spin_lock_irqsave(&trans_pcie->reg_lock, flags);
 680                         if (txq_id == trans_pcie->cmd_queue)
 681                                 iwl_pcie_clear_cmd_in_flight(trans);
 682                         spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
 683                 }
 684         }
 685
 686         while (!skb_queue_empty(&txq->overflow_q)) {
 687                 struct sk_buff *skb = __skb_dequeue(&txq->overflow_q);
 688
 689                 iwl_op_mode_free_skb(trans->op_mode, skb);
 690         }
 691
 692         spin_unlock_bh(&txq->lock);
 693
 694         /* just in case - this queue may have been stopped */
 695         iwl_wake_queue(trans, txq);
 696 }
 697
 698 /*
 699  * iwl_pcie_txq_free - Deallocate DMA queue.
 700  * @txq: Transmit queue to deallocate.
 701  *
 702  * Empty queue by removing and destroying all BD's.
 703  * Free all buffers.
 704  * 0-fill, but do not free "txq" descriptor structure.
 705  */
 706 static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id)
 707 {
 708         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 709         struct iwl_txq *txq = trans_pcie->txq[txq_id];
 710         struct device *dev = trans->dev;
 711         int i;
 712
 713         if (WARN_ON(!txq))
 714                 return;
 715
 716         iwl_pcie_txq_unmap(trans, txq_id);
 717
 718         /* De-alloc array of command/tx buffers */
 719         if (txq_id == trans_pcie->cmd_queue)
 720                 for (i = 0; i < txq->n_window; i++) {
 721                         kzfree(txq->entries[i].cmd);
 722                         kzfree(txq->entries[i].free_buf);
 723                 }
 724
 725         /* De-alloc circular buffer of TFDs */
 726         if (txq->tfds) {
 727                 dma_free_coherent(dev,
 728                                   trans_pcie->tfd_size *
 729                                   trans->trans_cfg->base_params->max_tfd_queue_size,
 730                                   txq->tfds, txq->dma_addr);
 731                 txq->dma_addr = 0;
 732                 txq->tfds = NULL;
 733
 734                 dma_free_coherent(dev,
 735                                   sizeof(*txq->first_tb_bufs) * txq->n_window,
 736                                   txq->first_tb_bufs, txq->first_tb_dma);
 737         }
 738
 739         kfree(txq->entries);
 740         txq->entries = NULL;
 741
 742         del_timer_sync(&txq->stuck_timer);
 743
 744         /* 0-fill queue descriptor structure */
 745         memset(txq, 0, sizeof(*txq));
 746 }
 747
 748 void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr)
 749 {
 750         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 751         int nq = trans->trans_cfg->base_params->num_of_queues;
 752         int chan;
 753         u32 reg_val;
 754         int clear_dwords = (SCD_TRANS_TBL_OFFSET_QUEUE(nq) -
 755                                 SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32);
 756
 757         /* make sure all queue are not stopped/used */
 758         memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
 759         memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
 760
 761         trans_pcie->scd_base_addr =
 762                 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
 763
 764         WARN_ON(scd_base_addr != 0 &&
 765                 scd_base_addr != trans_pcie->scd_base_addr);
 766
 767         /* reset context data, TX status and translation data */
 768         iwl_trans_write_mem(trans, trans_pcie->scd_base_addr +
 769                                    SCD_CONTEXT_MEM_LOWER_BOUND,
 770                             NULL, clear_dwords);
 771
 772         iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
 773                        trans_pcie->scd_bc_tbls.dma >> 10);
 774
 775         /* The chain extension of the SCD doesn't work well. This feature is
 776          * enabled by default by the HW, so we need to disable it manually.
 777          */
 778         if (trans->trans_cfg->base_params->scd_chain_ext_wa)
 779                 iwl_write_prph(trans, SCD_CHAINEXT_EN, 0);
 780
 781         iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue,
 782                                 trans_pcie->cmd_fifo,
 783                                 trans_pcie->cmd_q_wdg_timeout);
 784
 785         /* Activate all Tx DMA/FIFO channels */
 786         iwl_scd_activate_fifos(trans);
 787
 788         /* Enable DMA channel */
 789         for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++)
 790                 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
 791                                    FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
 792                                    FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
 793
 794         /* Update FH chicken bits */
 795         reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
 796         iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
 797                            reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
 798
 799         /* Enable L1-Active */
 800         if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000)
 801                 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
 802                                     APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 803 }
 804
 805 void iwl_trans_pcie_tx_reset(struct iwl_trans *trans)
 806 {
 807         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 808         int txq_id;
 809
 810         /*
 811          * we should never get here in gen2 trans mode return early to avoid
 812          * having invalid accesses
 813          */
 814         if (WARN_ON_ONCE(trans->trans_cfg->gen2))
 815                 return;
 816
 817         for (txq_id = 0; txq_id < trans->trans_cfg->base_params->num_of_queues;
 818              txq_id++) {
 819                 struct iwl_txq *txq = trans_pcie->txq[txq_id];
 820                 if (trans->trans_cfg->use_tfh)
 821                         iwl_write_direct64(trans,
 822                                            FH_MEM_CBBC_QUEUE(trans, txq_id),
 823                                            txq->dma_addr);
 824                 else
 825                         iwl_write_direct32(trans,
 826                                            FH_MEM_CBBC_QUEUE(trans, txq_id),
 827                                            txq->dma_addr >> 8);
 828                 iwl_pcie_txq_unmap(trans, txq_id);
 829                 txq->read_ptr = 0;
 830                 txq->write_ptr = 0;
 831         }
 832
 833         /* Tell NIC where to find the "keep warm" buffer */
 834         iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
 835                            trans_pcie->kw.dma >> 4);
 836
 837         /*
 838          * Send 0 as the scd_base_addr since the device may have be reset
 839          * while we were in WoWLAN in which case SCD_SRAM_BASE_ADDR will
 840          * contain garbage.
 841          */
 842         iwl_pcie_tx_start(trans, 0);
 843 }
 844
 845 static void iwl_pcie_tx_stop_fh(struct iwl_trans *trans)
 846 {
 847         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 848         unsigned long flags;
 849         int ch, ret;
 850         u32 mask = 0;
 851
 852         spin_lock(&trans_pcie->irq_lock);
 853
 854         if (!iwl_trans_grab_nic_access(trans, &flags))
 855                 goto out;
 856
 857         /* Stop each Tx DMA channel */
 858         for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
 859                 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
 860                 mask |= FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch);
 861         }
 862
 863         /* Wait for DMA channels to be idle */
 864         ret = iwl_poll_bit(trans, FH_TSSR_TX_STATUS_REG, mask, mask, 5000);
 865         if (ret < 0)
 866                 IWL_ERR(trans,
 867                         "Failing on timeout while stopping DMA channel %d [0x%08x]\n",
 868                         ch, iwl_read32(trans, FH_TSSR_TX_STATUS_REG));
 869
 870         iwl_trans_release_nic_access(trans, &flags);
 871
 872 out:
 873         spin_unlock(&trans_pcie->irq_lock);
 874 }
 875
 876 /*
 877  * iwl_pcie_tx_stop - Stop all Tx DMA channels
 878  */
 879 int iwl_pcie_tx_stop(struct iwl_trans *trans)
 880 {
 881         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 882         int txq_id;
 883
 884         /* Turn off all Tx DMA fifos */
 885         iwl_scd_deactivate_fifos(trans);
 886
 887         /* Turn off all Tx DMA channels */
 888         iwl_pcie_tx_stop_fh(trans);
 889
 890         /*
 891          * This function can be called before the op_mode disabled the
 892          * queues. This happens when we have an rfkill interrupt.
 893          * Since we stop Tx altogether - mark the queues as stopped.
 894          */
 895         memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
 896         memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
 897
 898         /* This can happen: start_hw, stop_device */
 899         if (!trans_pcie->txq_memory)
 900                 return 0;
 901
 902         /* Unmap DMA from host system and free skb's */
 903         for (txq_id = 0; txq_id < trans->trans_cfg->base_params->num_of_queues;
 904              txq_id++)
 905                 iwl_pcie_txq_unmap(trans, txq_id);
 906
 907         return 0;
 908 }
 909
 910 /*
 911  * iwl_trans_tx_free - Free TXQ Context
 912  *
 913  * Destroy all TX DMA queues and structures
 914  */
 915 void iwl_pcie_tx_free(struct iwl_trans *trans)
 916 {
 917         int txq_id;
 918         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 919
 920         memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
 921
 922         /* Tx queues */
 923         if (trans_pcie->txq_memory) {
 924                 for (txq_id = 0;
 925                      txq_id < trans->trans_cfg->base_params->num_of_queues;
 926                      txq_id++) {
 927                         iwl_pcie_txq_free(trans, txq_id);
 928                         trans_pcie->txq[txq_id] = NULL;
 929                 }
 930         }
 931
 932         kfree(trans_pcie->txq_memory);
 933         trans_pcie->txq_memory = NULL;
 934
 935         iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw);
 936
 937         iwl_pcie_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
 938 }
 939
 940 /*
 941  * iwl_pcie_tx_alloc - allocate TX context
 942  * Allocate all Tx DMA structures and initialize them
 943  */
 944 static int iwl_pcie_tx_alloc(struct iwl_trans *trans)
 945 {
 946         int ret;
 947         int txq_id, slots_num;
 948         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 949         u16 bc_tbls_size = trans->trans_cfg->base_params->num_of_queues;
 950
 951         bc_tbls_size *= (trans->trans_cfg->device_family >=
 952                          IWL_DEVICE_FAMILY_AX210) ?
 953                 sizeof(struct iwl_gen3_bc_tbl) :
 954                 sizeof(struct iwlagn_scd_bc_tbl);
 955
 956         /*It is not allowed to alloc twice, so warn when this happens.
 957          * We cannot rely on the previous allocation, so free and fail */
 958         if (WARN_ON(trans_pcie->txq_memory)) {
 959                 ret = -EINVAL;
 960                 goto error;
 961         }
 962
 963         ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
 964                                      bc_tbls_size);
 965         if (ret) {
 966                 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
 967                 goto error;
 968         }
 969
 970         /* Alloc keep-warm buffer */
 971         ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
 972         if (ret) {
 973                 IWL_ERR(trans, "Keep Warm allocation failed\n");
 974                 goto error;
 975         }
 976
 977         trans_pcie->txq_memory =
 978                 kcalloc(trans->trans_cfg->base_params->num_of_queues,
 979                         sizeof(struct iwl_txq), GFP_KERNEL);
 980         if (!trans_pcie->txq_memory) {
 981                 IWL_ERR(trans, "Not enough memory for txq\n");
 982                 ret = -ENOMEM;
 983                 goto error;
 984         }
 985
 986         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
 987         for (txq_id = 0; txq_id < trans->trans_cfg->base_params->num_of_queues;
 988              txq_id++) {
 989                 bool cmd_queue = (txq_id == trans_pcie->cmd_queue);
 990
 991                 if (cmd_queue)
 992                         slots_num = max_t(u32, IWL_CMD_QUEUE_SIZE,
 993                                           trans->cfg->min_txq_size);
 994                 else
 995                         slots_num = max_t(u32, IWL_DEFAULT_QUEUE_SIZE,
 996                                           trans->cfg->min_256_ba_txq_size);
 997                 trans_pcie->txq[txq_id] = &trans_pcie->txq_memory[txq_id];
 998                 ret = iwl_pcie_txq_alloc(trans, trans_pcie->txq[txq_id],
 999                                          slots_num, cmd_queue);
1000                 if (ret) {
1001                         IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
1002                         goto error;
1003                 }
1004                 trans_pcie->txq[txq_id]->id = txq_id;
1005         }
1006
1007         return 0;
1008
1009 error:
1010         iwl_pcie_tx_free(trans);
1011
1012         return ret;
1013 }
1014
1015 int iwl_pcie_tx_init(struct iwl_trans *trans)
1016 {
1017         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1018         int ret;
1019         int txq_id, slots_num;
1020         bool alloc = false;
1021
1022         if (!trans_pcie->txq_memory) {
1023                 ret = iwl_pcie_tx_alloc(trans);
1024                 if (ret)
1025                         goto error;
1026                 alloc = true;
1027         }
1028
1029         spin_lock(&trans_pcie->irq_lock);
1030
1031         /* Turn off all Tx DMA fifos */
1032         iwl_scd_deactivate_fifos(trans);
1033
1034         /* Tell NIC where to find the "keep warm" buffer */
1035         iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
1036                            trans_pcie->kw.dma >> 4);
1037
1038         spin_unlock(&trans_pcie->irq_lock);
1039
1040         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
1041         for (txq_id = 0; txq_id < trans->trans_cfg->base_params->num_of_queues;
1042              txq_id++) {
1043                 bool cmd_queue = (txq_id == trans_pcie->cmd_queue);
1044
1045                 if (cmd_queue)
1046                         slots_num = max_t(u32, IWL_CMD_QUEUE_SIZE,
1047                                           trans->cfg->min_txq_size);
1048                 else
1049                         slots_num = max_t(u32, IWL_DEFAULT_QUEUE_SIZE,
1050                                           trans->cfg->min_256_ba_txq_size);
1051                 ret = iwl_pcie_txq_init(trans, trans_pcie->txq[txq_id],
1052                                         slots_num, cmd_queue);
1053                 if (ret) {
1054                         IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
1055                         goto error;
1056                 }
1057
1058                 /*
1059                  * Tell nic where to find circular buffer of TFDs for a
1060                  * given Tx queue, and enable the DMA channel used for that
1061                  * queue.
1062                  * Circular buffer (TFD queue in DRAM) physical base address
1063                  */
1064                 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(trans, txq_id),
1065                                    trans_pcie->txq[txq_id]->dma_addr >> 8);
1066         }
1067
1068         iwl_set_bits_prph(trans, SCD_GP_CTRL, SCD_GP_CTRL_AUTO_ACTIVE_MODE);
1069         if (trans->trans_cfg->base_params->num_of_queues > 20)
1070                 iwl_set_bits_prph(trans, SCD_GP_CTRL,
1071                                   SCD_GP_CTRL_ENABLE_31_QUEUES);
1072
1073         return 0;
1074 error:
1075         /*Upon error, free only if we allocated something */
1076         if (alloc)
1077                 iwl_pcie_tx_free(trans);
1078         return ret;
1079 }
1080
1081 static inline void iwl_pcie_txq_progress(struct iwl_txq *txq)
1082 {
1083         lockdep_assert_held(&txq->lock);
1084
1085         if (!txq->wd_timeout)
1086                 return;
1087
1088         /*
1089          * station is asleep and we send data - that must
1090          * be uAPSD or PS-Poll. Don't rearm the timer.
1091          */
1092         if (txq->frozen)
1093                 return;
1094
1095         /*
1096          * if empty delete timer, otherwise move timer forward
1097          * since we're making progress on this queue
1098          */
1099         if (txq->read_ptr == txq->write_ptr)
1100                 del_timer(&txq->stuck_timer);
1101         else
1102                 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
1103 }
1104
1105 /* Frees buffers until index _not_ inclusive */
1106 void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
1107                             struct sk_buff_head *skbs)
1108 {
1109         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1110         struct iwl_txq *txq = trans_pcie->txq[txq_id];
1111         int tfd_num = iwl_pcie_get_cmd_index(txq, ssn);
1112         int read_ptr = iwl_pcie_get_cmd_index(txq, txq->read_ptr);
1113         int last_to_free;
1114
1115         /* This function is not meant to release cmd queue*/
1116         if (WARN_ON(txq_id == trans_pcie->cmd_queue))
1117                 return;
1118
1119         spin_lock_bh(&txq->lock);
1120
1121         if (!test_bit(txq_id, trans_pcie->queue_used)) {
1122                 IWL_DEBUG_TX_QUEUES(trans, "Q %d inactive - ignoring idx %d\n",
1123                                     txq_id, ssn);
1124                 goto out;
1125         }
1126
1127         if (read_ptr == tfd_num)
1128                 goto out;
1129
1130         IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n",
1131                            txq_id, txq->read_ptr, tfd_num, ssn);
1132
1133         /*Since we free until index _not_ inclusive, the one before index is
1134          * the last we will free. This one must be used */
1135         last_to_free = iwl_queue_dec_wrap(trans, tfd_num);
1136
1137         if (!iwl_queue_used(txq, last_to_free)) {
1138                 IWL_ERR(trans,
1139                         "%s: Read index for txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n",
1140                         __func__, txq_id, last_to_free,
1141                         trans->trans_cfg->base_params->max_tfd_queue_size,
1142                         txq->write_ptr, txq->read_ptr);
1143                 goto out;
1144         }
1145
1146         if (WARN_ON(!skb_queue_empty(skbs)))
1147                 goto out;
1148
1149         for (;
1150              read_ptr != tfd_num;
1151              txq->read_ptr = iwl_queue_inc_wrap(trans, txq->read_ptr),
1152              read_ptr = iwl_pcie_get_cmd_index(txq, txq->read_ptr)) {
1153                 struct sk_buff *skb = txq->entries[read_ptr].skb;
1154
1155                 if (WARN_ON_ONCE(!skb))
1156                         continue;
1157
1158                 iwl_pcie_free_tso_page(trans_pcie, skb);
1159
1160                 __skb_queue_tail(skbs, skb);
1161
1162                 txq->entries[read_ptr].skb = NULL;
1163
1164                 if (!trans->trans_cfg->use_tfh)
1165                         iwl_pcie_txq_inval_byte_cnt_tbl(trans, txq);
1166
1167                 iwl_pcie_txq_free_tfd(trans, txq);
1168         }
1169
1170         iwl_pcie_txq_progress(txq);
1171
1172         if (iwl_queue_space(trans, txq) > txq->low_mark &&
1173             test_bit(txq_id, trans_pcie->queue_stopped)) {
1174                 struct sk_buff_head overflow_skbs;
1175
1176                 __skb_queue_head_init(&overflow_skbs);
1177                 skb_queue_splice_init(&txq->overflow_q, &overflow_skbs);
1178
1179                 /*
1180                  * We are going to transmit from the overflow queue.
1181                  * Remember this state so that wait_for_txq_empty will know we
1182                  * are adding more packets to the TFD queue. It cannot rely on
1183                  * the state of &txq->overflow_q, as we just emptied it, but
1184                  * haven't TXed the content yet.
1185                  */
1186                 txq->overflow_tx = true;
1187
1188                 /*
1189                  * This is tricky: we are in reclaim path which is non
1190                  * re-entrant, so noone will try to take the access the
1191                  * txq data from that path. We stopped tx, so we can't
1192                  * have tx as well. Bottom line, we can unlock and re-lock
1193                  * later.
1194                  */
1195                 spin_unlock_bh(&txq->lock);
1196
1197                 while (!skb_queue_empty(&overflow_skbs)) {
1198                         struct sk_buff *skb = __skb_dequeue(&overflow_skbs);
1199                         struct iwl_device_cmd *dev_cmd_ptr;
1200
1201                         dev_cmd_ptr = *(void **)((u8 *)skb->cb +
1202                                                  trans_pcie->dev_cmd_offs);
1203
1204                         /*
1205                          * Note that we can very well be overflowing again.
1206                          * In that case, iwl_queue_space will be small again
1207                          * and we won't wake mac80211's queue.
1208                          */
1209                         iwl_trans_tx(trans, skb, dev_cmd_ptr, txq_id);
1210                 }
1211
1212                 if (iwl_queue_space(trans, txq) > txq->low_mark)
1213                         iwl_wake_queue(trans, txq);
1214
1215                 spin_lock_bh(&txq->lock);
1216                 txq->overflow_tx = false;
1217         }
1218
1219 out:
1220         spin_unlock_bh(&txq->lock);
1221 }
1222
1223 /* Set wr_ptr of specific device and txq  */
1224 void iwl_trans_pcie_set_q_ptrs(struct iwl_trans *trans, int txq_id, int ptr)
1225 {
1226         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1227         struct iwl_txq *txq = trans_pcie->txq[txq_id];
1228
1229         spin_lock_bh(&txq->lock);
1230
1231         txq->write_ptr = ptr;
1232         txq->read_ptr = txq->write_ptr;
1233
1234         spin_unlock_bh(&txq->lock);
1235 }
1236
1237 static int iwl_pcie_set_cmd_in_flight(struct iwl_trans *trans,
1238                                       const struct iwl_host_cmd *cmd)
1239 {
1240         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1241         int ret;
1242
1243         lockdep_assert_held(&trans_pcie->reg_lock);
1244
1245         /* Make sure the NIC is still alive in the bus */
1246         if (test_bit(STATUS_TRANS_DEAD, &trans->status))
1247                 return -ENODEV;
1248
1249         /*
1250          * wake up the NIC to make sure that the firmware will see the host
1251          * command - we will let the NIC sleep once all the host commands
1252          * returned. This needs to be done only on NICs that have
1253          * apmg_wake_up_wa set.
1254          */
1255         if (trans->trans_cfg->base_params->apmg_wake_up_wa &&
1256             !trans_pcie->cmd_hold_nic_awake) {
1257                 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1258                                          BIT(trans->trans_cfg->csr->flag_mac_access_req));
1259
1260                 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1261                                    BIT(trans->trans_cfg->csr->flag_val_mac_access_en),
1262                                    (BIT(trans->trans_cfg->csr->flag_mac_clock_ready) |
1263                                     CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP),
1264                                    15000);
1265                 if (ret < 0) {
1266                         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1267                                         BIT(trans->trans_cfg->csr->flag_mac_access_req));
1268                         IWL_ERR(trans, "Failed to wake NIC for hcmd\n");
1269                         return -EIO;
1270                 }
1271                 trans_pcie->cmd_hold_nic_awake = true;
1272         }
1273
1274         return 0;
1275 }
1276
1277 /*
1278  * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd
1279  *
1280  * When FW advances 'R' index, all entries between old and new 'R' index
1281  * need to be reclaimed. As result, some free space forms.  If there is
1282  * enough free space (> low mark), wake the stack that feeds us.
1283  */
1284 void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx)
1285 {
1286         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1287         struct iwl_txq *txq = trans_pcie->txq[txq_id];
1288         unsigned long flags;
1289         int nfreed = 0;
1290         u16 r;
1291
1292         lockdep_assert_held(&txq->lock);
1293
1294         idx = iwl_pcie_get_cmd_index(txq, idx);
1295         r = iwl_pcie_get_cmd_index(txq, txq->read_ptr);
1296
1297         if (idx >= trans->trans_cfg->base_params->max_tfd_queue_size ||
1298             (!iwl_queue_used(txq, idx))) {
1299                 WARN_ONCE(test_bit(txq_id, trans_pcie->queue_used),
1300                           "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n",
1301                           __func__, txq_id, idx,
1302                           trans->trans_cfg->base_params->max_tfd_queue_size,
1303                           txq->write_ptr, txq->read_ptr);
1304                 return;
1305         }
1306
1307         for (idx = iwl_queue_inc_wrap(trans, idx); r != idx;
1308              r = iwl_queue_inc_wrap(trans, r)) {
1309                 txq->read_ptr = iwl_queue_inc_wrap(trans, txq->read_ptr);
1310
1311                 if (nfreed++ > 0) {
1312                         IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n",
1313                                 idx, txq->write_ptr, r);
1314                         iwl_force_nmi(trans);
1315                 }
1316         }
1317
1318         if (txq->read_ptr == txq->write_ptr) {
1319                 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1320                 iwl_pcie_clear_cmd_in_flight(trans);
1321                 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1322         }
1323
1324         iwl_pcie_txq_progress(txq);
1325 }
1326
1327 static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid,
1328                                  u16 txq_id)
1329 {
1330         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1331         u32 tbl_dw_addr;
1332         u32 tbl_dw;
1333         u16 scd_q2ratid;
1334
1335         scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
1336
1337         tbl_dw_addr = trans_pcie->scd_base_addr +
1338                         SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
1339
1340         tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr);
1341
1342         if (txq_id & 0x1)
1343                 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
1344         else
1345                 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
1346
1347         iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw);
1348
1349         return 0;
1350 }
1351
1352 /* Receiver address (actually, Rx station's index into station table),
1353  * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */
1354 #define BUILD_RAxTID(sta_id, tid)       (((sta_id) << 4) + (tid))
1355
1356 bool iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn,
1357                                const struct iwl_trans_txq_scd_cfg *cfg,
1358                                unsigned int wdg_timeout)
1359 {
1360         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1361         struct iwl_txq *txq = trans_pcie->txq[txq_id];
1362         int fifo = -1;
1363         bool scd_bug = false;
1364
1365         if (test_and_set_bit(txq_id, trans_pcie->queue_used))
1366                 WARN_ONCE(1, "queue %d already used - expect issues", txq_id);
1367
1368         txq->wd_timeout = msecs_to_jiffies(wdg_timeout);
1369
1370         if (cfg) {
1371                 fifo = cfg->fifo;
1372
1373                 /* Disable the scheduler prior configuring the cmd queue */
1374                 if (txq_id == trans_pcie->cmd_queue &&
1375                     trans_pcie->scd_set_active)
1376                         iwl_scd_enable_set_active(trans, 0);
1377
1378                 /* Stop this Tx queue before configuring it */
1379                 iwl_scd_txq_set_inactive(trans, txq_id);
1380
1381                 /* Set this queue as a chain-building queue unless it is CMD */
1382                 if (txq_id != trans_pcie->cmd_queue)
1383                         iwl_scd_txq_set_chain(trans, txq_id);
1384
1385                 if (cfg->aggregate) {
1386                         u16 ra_tid = BUILD_RAxTID(cfg->sta_id, cfg->tid);
1387
1388                         /* Map receiver-address / traffic-ID to this queue */
1389                         iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id);
1390
1391                         /* enable aggregations for the queue */
1392                         iwl_scd_txq_enable_agg(trans, txq_id);
1393                         txq->ampdu = true;
1394                 } else {
1395                         /*
1396                          * disable aggregations for the queue, this will also
1397                          * make the ra_tid mapping configuration irrelevant
1398                          * since it is now a non-AGG queue.
1399                          */
1400                         iwl_scd_txq_disable_agg(trans, txq_id);
1401
1402                         ssn = txq->read_ptr;
1403                 }
1404         } else {
1405                 /*
1406                  * If we need to move the SCD write pointer by steps of
1407                  * 0x40, 0x80 or 0xc0, it gets stuck. Avoids this and let
1408                  * the op_mode know by returning true later.
1409                  * Do this only in case cfg is NULL since this trick can
1410                  * be done only if we have DQA enabled which is true for mvm
1411                  * only. And mvm never sets a cfg pointer.
1412                  * This is really ugly, but this is the easiest way out for
1413                  * this sad hardware issue.
1414                  * This bug has been fixed on devices 9000 and up.
1415                  */
1416                 scd_bug = !trans->trans_cfg->mq_rx_supported &&
1417                         !((ssn - txq->write_ptr) & 0x3f) &&
1418                         (ssn != txq->write_ptr);
1419                 if (scd_bug)
1420                         ssn++;
1421         }
1422
1423         /* Place first TFD at index corresponding to start sequence number.
1424          * Assumes that ssn_idx is valid (!= 0xFFF) */
1425         txq->read_ptr = (ssn & 0xff);
1426         txq->write_ptr = (ssn & 0xff);
1427         iwl_write_direct32(trans, HBUS_TARG_WRPTR,
1428                            (ssn & 0xff) | (txq_id << 8));
1429
1430         if (cfg) {
1431                 u8 frame_limit = cfg->frame_limit;
1432
1433                 iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn);
1434
1435                 /* Set up Tx window size and frame limit for this queue */
1436                 iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr +
1437                                 SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0);
1438                 iwl_trans_write_mem32(trans,
1439                         trans_pcie->scd_base_addr +
1440                         SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
1441                         SCD_QUEUE_CTX_REG2_VAL(WIN_SIZE, frame_limit) |
1442                         SCD_QUEUE_CTX_REG2_VAL(FRAME_LIMIT, frame_limit));
1443
1444                 /* Set up status area in SRAM, map to Tx DMA/FIFO, activate */
1445                 iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),
1446                                (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
1447                                (cfg->fifo << SCD_QUEUE_STTS_REG_POS_TXF) |
1448                                (1 << SCD_QUEUE_STTS_REG_POS_WSL) |
1449                                SCD_QUEUE_STTS_REG_MSK);
1450
1451                 /* enable the scheduler for this queue (only) */
1452                 if (txq_id == trans_pcie->cmd_queue &&
1453                     trans_pcie->scd_set_active)
1454                         iwl_scd_enable_set_active(trans, BIT(txq_id));
1455
1456                 IWL_DEBUG_TX_QUEUES(trans,
1457                                     "Activate queue %d on FIFO %d WrPtr: %d\n",
1458                                     txq_id, fifo, ssn & 0xff);
1459         } else {
1460                 IWL_DEBUG_TX_QUEUES(trans,
1461                                     "Activate queue %d WrPtr: %d\n",
1462                                     txq_id, ssn & 0xff);
1463         }
1464
1465         return scd_bug;
1466 }
1467
1468 void iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans *trans, u32 txq_id,
1469                                         bool shared_mode)
1470 {
1471         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1472         struct iwl_txq *txq = trans_pcie->txq[txq_id];
1473
1474         txq->ampdu = !shared_mode;
1475 }
1476
1477 void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id,
1478                                 bool configure_scd)
1479 {
1480         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1481         u32 stts_addr = trans_pcie->scd_base_addr +
1482                         SCD_TX_STTS_QUEUE_OFFSET(txq_id);
1483         static const u32 zero_val[4] = {};
1484
1485         trans_pcie->txq[txq_id]->frozen_expiry_remainder = 0;
1486         trans_pcie->txq[txq_id]->frozen = false;
1487
1488         /*
1489          * Upon HW Rfkill - we stop the device, and then stop the queues
1490          * in the op_mode. Just for the sake of the simplicity of the op_mode,
1491          * allow the op_mode to call txq_disable after it already called
1492          * stop_device.
1493          */
1494         if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) {
1495                 WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED, &trans->status),
1496                           "queue %d not used", txq_id);
1497                 return;
1498         }
1499
1500         if (configure_scd) {
1501                 iwl_scd_txq_set_inactive(trans, txq_id);
1502
1503                 iwl_trans_write_mem(trans, stts_addr, (void *)zero_val,
1504                                     ARRAY_SIZE(zero_val));
1505         }
1506
1507         iwl_pcie_txq_unmap(trans, txq_id);
1508         trans_pcie->txq[txq_id]->ampdu = false;
1509
1510         IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id);
1511 }
1512
1513 /*************** HOST COMMAND QUEUE FUNCTIONS   *****/
1514
1515 /*
1516  * iwl_pcie_enqueue_hcmd - enqueue a uCode command
1517  * @priv: device private data point
1518  * @cmd: a pointer to the ucode command structure
1519  *
1520  * The function returns < 0 values to indicate the operation
1521  * failed. On success, it returns the index (>= 0) of command in the
1522  * command queue.
1523  */
1524 static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
1525                                  struct iwl_host_cmd *cmd)
1526 {
1527         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1528         struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue];
1529         struct iwl_device_cmd *out_cmd;
1530         struct iwl_cmd_meta *out_meta;
1531         unsigned long flags;
1532         void *dup_buf = NULL;
1533         dma_addr_t phys_addr;
1534         int idx;
1535         u16 copy_size, cmd_size, tb0_size;
1536         bool had_nocopy = false;
1537         u8 group_id = iwl_cmd_groupid(cmd->id);
1538         int i, ret;
1539         u32 cmd_pos;
1540         const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD];
1541         u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD];
1542
1543         if (WARN(!trans->wide_cmd_header &&
1544                  group_id > IWL_ALWAYS_LONG_GROUP,
1545                  "unsupported wide command %#x\n", cmd->id))
1546                 return -EINVAL;
1547
1548         if (group_id != 0) {
1549                 copy_size = sizeof(struct iwl_cmd_header_wide);
1550                 cmd_size = sizeof(struct iwl_cmd_header_wide);
1551         } else {
1552                 copy_size = sizeof(struct iwl_cmd_header);
1553                 cmd_size = sizeof(struct iwl_cmd_header);
1554         }
1555
1556         /* need one for the header if the first is NOCOPY */
1557         BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD > IWL_NUM_OF_TBS - 1);
1558
1559         for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1560                 cmddata[i] = cmd->data[i];
1561                 cmdlen[i] = cmd->len[i];
1562
1563                 if (!cmd->len[i])
1564                         continue;
1565
1566                 /* need at least IWL_FIRST_TB_SIZE copied */
1567                 if (copy_size < IWL_FIRST_TB_SIZE) {
1568                         int copy = IWL_FIRST_TB_SIZE - copy_size;
1569
1570                         if (copy > cmdlen[i])
1571                                 copy = cmdlen[i];
1572                         cmdlen[i] -= copy;
1573                         cmddata[i] += copy;
1574                         copy_size += copy;
1575                 }
1576
1577                 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) {
1578                         had_nocopy = true;
1579                         if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) {
1580                                 idx = -EINVAL;
1581                                 goto free_dup_buf;
1582                         }
1583                 } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) {
1584                         /*
1585                          * This is also a chunk that isn't copied
1586                          * to the static buffer so set had_nocopy.
1587                          */
1588                         had_nocopy = true;
1589
1590                         /* only allowed once */
1591                         if (WARN_ON(dup_buf)) {
1592                                 idx = -EINVAL;
1593                                 goto free_dup_buf;
1594                         }
1595
1596                         dup_buf = kmemdup(cmddata[i], cmdlen[i],
1597                                           GFP_ATOMIC);
1598                         if (!dup_buf)
1599                                 return -ENOMEM;
1600                 } else {
1601                         /* NOCOPY must not be followed by normal! */
1602                         if (WARN_ON(had_nocopy)) {
1603                                 idx = -EINVAL;
1604                                 goto free_dup_buf;
1605                         }
1606                         copy_size += cmdlen[i];
1607                 }
1608                 cmd_size += cmd->len[i];
1609         }
1610
1611         /*
1612          * If any of the command structures end up being larger than
1613          * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
1614          * allocated into separate TFDs, then we will need to
1615          * increase the size of the buffers.
1616          */
1617         if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE,
1618                  "Command %s (%#x) is too large (%d bytes)\n",
1619                  iwl_get_cmd_string(trans, cmd->id),
1620                  cmd->id, copy_size)) {
1621                 idx = -EINVAL;
1622                 goto free_dup_buf;
1623         }
1624
1625         spin_lock_bh(&txq->lock);
1626
1627         if (iwl_queue_space(trans, txq) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
1628                 spin_unlock_bh(&txq->lock);
1629
1630                 IWL_ERR(trans, "No space in command queue\n");
1631                 iwl_op_mode_cmd_queue_full(trans->op_mode);
1632                 idx = -ENOSPC;
1633                 goto free_dup_buf;
1634         }
1635
1636         idx = iwl_pcie_get_cmd_index(txq, txq->write_ptr);
1637         out_cmd = txq->entries[idx].cmd;
1638         out_meta = &txq->entries[idx].meta;
1639
1640         memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
1641         if (cmd->flags & CMD_WANT_SKB)
1642                 out_meta->source = cmd;
1643
1644         /* set up the header */
1645         if (group_id != 0) {
1646                 out_cmd->hdr_wide.cmd = iwl_cmd_opcode(cmd->id);
1647                 out_cmd->hdr_wide.group_id = group_id;
1648                 out_cmd->hdr_wide.version = iwl_cmd_version(cmd->id);
1649                 out_cmd->hdr_wide.length =
1650                         cpu_to_le16(cmd_size -
1651                                     sizeof(struct iwl_cmd_header_wide));
1652                 out_cmd->hdr_wide.reserved = 0;
1653                 out_cmd->hdr_wide.sequence =
1654                         cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
1655                                                  INDEX_TO_SEQ(txq->write_ptr));
1656
1657                 cmd_pos = sizeof(struct iwl_cmd_header_wide);
1658                 copy_size = sizeof(struct iwl_cmd_header_wide);
1659         } else {
1660                 out_cmd->hdr.cmd = iwl_cmd_opcode(cmd->id);
1661                 out_cmd->hdr.sequence =
1662                         cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
1663                                                  INDEX_TO_SEQ(txq->write_ptr));
1664                 out_cmd->hdr.group_id = 0;
1665
1666                 cmd_pos = sizeof(struct iwl_cmd_header);
1667                 copy_size = sizeof(struct iwl_cmd_header);
1668         }
1669
1670         /* and copy the data that needs to be copied */
1671         for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1672                 int copy;
1673
1674                 if (!cmd->len[i])
1675                         continue;
1676
1677                 /* copy everything if not nocopy/dup */
1678                 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1679                                            IWL_HCMD_DFL_DUP))) {
1680                         copy = cmd->len[i];
1681
1682                         memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1683                         cmd_pos += copy;
1684                         copy_size += copy;
1685                         continue;
1686                 }
1687
1688                 /*
1689                  * Otherwise we need at least IWL_FIRST_TB_SIZE copied
1690                  * in total (for bi-directional DMA), but copy up to what
1691                  * we can fit into the payload for debug dump purposes.
1692                  */
1693                 copy = min_t(int, TFD_MAX_PAYLOAD_SIZE - cmd_pos, cmd->len[i]);
1694
1695                 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1696                 cmd_pos += copy;
1697
1698                 /* However, treat copy_size the proper way, we need it below */
1699                 if (copy_size < IWL_FIRST_TB_SIZE) {
1700                         copy = IWL_FIRST_TB_SIZE - copy_size;
1701
1702                         if (copy > cmd->len[i])
1703                                 copy = cmd->len[i];
1704                         copy_size += copy;
1705                 }
1706         }
1707
1708         IWL_DEBUG_HC(trans,
1709                      "Sending command %s (%.2x.%.2x), seq: 0x%04X, %d bytes at %d[%d]:%d\n",
1710                      iwl_get_cmd_string(trans, cmd->id),
1711                      group_id, out_cmd->hdr.cmd,
1712                      le16_to_cpu(out_cmd->hdr.sequence),
1713                      cmd_size, txq->write_ptr, idx, trans_pcie->cmd_queue);
1714
1715         /* start the TFD with the minimum copy bytes */
1716         tb0_size = min_t(int, copy_size, IWL_FIRST_TB_SIZE);
1717         memcpy(&txq->first_tb_bufs[idx], &out_cmd->hdr, tb0_size);
1718         iwl_pcie_txq_build_tfd(trans, txq,
1719                                iwl_pcie_get_first_tb_dma(txq, idx),
1720                                tb0_size, true);
1721
1722         /* map first command fragment, if any remains */
1723         if (copy_size > tb0_size) {
1724                 phys_addr = dma_map_single(trans->dev,
1725                                            ((u8 *)&out_cmd->hdr) + tb0_size,
1726                                            copy_size - tb0_size,
1727                                            DMA_TO_DEVICE);
1728                 if (dma_mapping_error(trans->dev, phys_addr)) {
1729                         iwl_pcie_tfd_unmap(trans, out_meta, txq,
1730                                            txq->write_ptr);
1731                         idx = -ENOMEM;
1732                         goto out;
1733                 }
1734
1735                 iwl_pcie_txq_build_tfd(trans, txq, phys_addr,
1736                                        copy_size - tb0_size, false);
1737         }
1738
1739         /* map the remaining (adjusted) nocopy/dup fragments */
1740         for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1741                 const void *data = cmddata[i];
1742
1743                 if (!cmdlen[i])
1744                         continue;
1745                 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1746                                            IWL_HCMD_DFL_DUP)))
1747                         continue;
1748                 if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP)
1749                         data = dup_buf;
1750                 phys_addr = dma_map_single(trans->dev, (void *)data,
1751                                            cmdlen[i], DMA_TO_DEVICE);
1752                 if (dma_mapping_error(trans->dev, phys_addr)) {
1753                         iwl_pcie_tfd_unmap(trans, out_meta, txq,
1754                                            txq->write_ptr);
1755                         idx = -ENOMEM;
1756                         goto out;
1757                 }
1758
1759                 iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmdlen[i], false);
1760         }
1761
1762         BUILD_BUG_ON(IWL_TFH_NUM_TBS > sizeof(out_meta->tbs) * BITS_PER_BYTE);
1763         out_meta->flags = cmd->flags;
1764         if (WARN_ON_ONCE(txq->entries[idx].free_buf))
1765                 kzfree(txq->entries[idx].free_buf);
1766         txq->entries[idx].free_buf = dup_buf;
1767
1768         trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr_wide);
1769
1770         /* start timer if queue currently empty */
1771         if (txq->read_ptr == txq->write_ptr && txq->wd_timeout)
1772                 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
1773
1774         spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1775         ret = iwl_pcie_set_cmd_in_flight(trans, cmd);
1776         if (ret < 0) {
1777                 idx = ret;
1778                 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1779                 goto out;
1780         }
1781
1782         /* Increment and update queue's write index */
1783         txq->write_ptr = iwl_queue_inc_wrap(trans, txq->write_ptr);
1784         iwl_pcie_txq_inc_wr_ptr(trans, txq);
1785
1786         spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1787
1788  out:
1789         spin_unlock_bh(&txq->lock);
1790  free_dup_buf:
1791         if (idx < 0)
1792                 kfree(dup_buf);
1793         return idx;
1794 }
1795
1796 /*
1797  * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them
1798  * @rxb: Rx buffer to reclaim
1799  */
1800 void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
1801                             struct iwl_rx_cmd_buffer *rxb)
1802 {
1803         struct iwl_rx_packet *pkt = rxb_addr(rxb);
1804         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1805         u8 group_id;
1806         u32 cmd_id;
1807         int txq_id = SEQ_TO_QUEUE(sequence);
1808         int index = SEQ_TO_INDEX(sequence);
1809         int cmd_index;
1810         struct iwl_device_cmd *cmd;
1811         struct iwl_cmd_meta *meta;
1812         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1813         struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue];
1814
1815         /* If a Tx command is being handled and it isn't in the actual
1816          * command queue then there a command routing bug has been introduced
1817          * in the queue management code. */
1818         if (WARN(txq_id != trans_pcie->cmd_queue,
1819                  "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
1820                  txq_id, trans_pcie->cmd_queue, sequence, txq->read_ptr,
1821                  txq->write_ptr)) {
1822                 iwl_print_hex_error(trans, pkt, 32);
1823                 return;
1824         }
1825
1826         spin_lock_bh(&txq->lock);
1827
1828         cmd_index = iwl_pcie_get_cmd_index(txq, index);
1829         cmd = txq->entries[cmd_index].cmd;
1830         meta = &txq->entries[cmd_index].meta;
1831         group_id = cmd->hdr.group_id;
1832         cmd_id = iwl_cmd_id(cmd->hdr.cmd, group_id, 0);
1833
1834         iwl_pcie_tfd_unmap(trans, meta, txq, index);
1835
1836         /* Input error checking is done when commands are added to queue. */
1837         if (meta->flags & CMD_WANT_SKB) {
1838                 struct page *p = rxb_steal_page(rxb);
1839
1840                 meta->source->resp_pkt = pkt;
1841                 meta->source->_rx_page_addr = (unsigned long)page_address(p);
1842                 meta->source->_rx_page_order = trans_pcie->rx_page_order;
1843         }
1844
1845         if (meta->flags & CMD_WANT_ASYNC_CALLBACK)
1846                 iwl_op_mode_async_cb(trans->op_mode, cmd);
1847
1848         iwl_pcie_cmdq_reclaim(trans, txq_id, index);
1849
1850         if (!(meta->flags & CMD_ASYNC)) {
1851                 if (!test_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status)) {
1852                         IWL_WARN(trans,
1853                                  "HCMD_ACTIVE already clear for command %s\n",
1854                                  iwl_get_cmd_string(trans, cmd_id));
1855                 }
1856                 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1857                 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
1858                                iwl_get_cmd_string(trans, cmd_id));
1859                 wake_up(&trans_pcie->wait_command_queue);
1860         }
1861
1862         meta->flags = 0;
1863
1864         spin_unlock_bh(&txq->lock);
1865 }
1866
1867 #define HOST_COMPLETE_TIMEOUT   (2 * HZ)
1868
1869 static int iwl_pcie_send_hcmd_async(struct iwl_trans *trans,
1870                                     struct iwl_host_cmd *cmd)
1871 {
1872         int ret;
1873
1874         /* An asynchronous command can not expect an SKB to be set. */
1875         if (WARN_ON(cmd->flags & CMD_WANT_SKB))
1876                 return -EINVAL;
1877
1878         ret = iwl_pcie_enqueue_hcmd(trans, cmd);
1879         if (ret < 0) {
1880                 IWL_ERR(trans,
1881                         "Error sending %s: enqueue_hcmd failed: %d\n",
1882                         iwl_get_cmd_string(trans, cmd->id), ret);
1883                 return ret;
1884         }
1885         return 0;
1886 }
1887
1888 static int iwl_pcie_send_hcmd_sync(struct iwl_trans *trans,
1889                                    struct iwl_host_cmd *cmd)
1890 {
1891         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1892         struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue];
1893         int cmd_idx;
1894         int ret;
1895
1896         IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n",
1897                        iwl_get_cmd_string(trans, cmd->id));
1898
1899         if (WARN(test_and_set_bit(STATUS_SYNC_HCMD_ACTIVE,
1900                                   &trans->status),
1901                  "Command %s: a command is already active!\n",
1902                  iwl_get_cmd_string(trans, cmd->id)))
1903                 return -EIO;
1904
1905         IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n",
1906                        iwl_get_cmd_string(trans, cmd->id));
1907
1908         cmd_idx = iwl_pcie_enqueue_hcmd(trans, cmd);
1909         if (cmd_idx < 0) {
1910                 ret = cmd_idx;
1911                 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1912                 IWL_ERR(trans,
1913                         "Error sending %s: enqueue_hcmd failed: %d\n",
1914                         iwl_get_cmd_string(trans, cmd->id), ret);
1915                 return ret;
1916         }
1917
1918         ret = wait_event_timeout(trans_pcie->wait_command_queue,
1919                                  !test_bit(STATUS_SYNC_HCMD_ACTIVE,
1920                                            &trans->status),
1921                                  HOST_COMPLETE_TIMEOUT);
1922         if (!ret) {
1923                 IWL_ERR(trans, "Error sending %s: time out after %dms.\n",
1924                         iwl_get_cmd_string(trans, cmd->id),
1925                         jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
1926
1927                 IWL_ERR(trans, "Current CMD queue read_ptr %d write_ptr %d\n",
1928                         txq->read_ptr, txq->write_ptr);
1929
1930                 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1931                 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
1932                                iwl_get_cmd_string(trans, cmd->id));
1933                 ret = -ETIMEDOUT;
1934
1935                 iwl_trans_pcie_sync_nmi(trans);
1936                 goto cancel;
1937         }
1938
1939         if (test_bit(STATUS_FW_ERROR, &trans->status)) {
1940                 iwl_trans_pcie_dump_regs(trans);
1941                 IWL_ERR(trans, "FW error in SYNC CMD %s\n",
1942                         iwl_get_cmd_string(trans, cmd->id));
1943                 dump_stack();
1944                 ret = -EIO;
1945                 goto cancel;
1946         }
1947
1948         if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
1949             test_bit(STATUS_RFKILL_OPMODE, &trans->status)) {
1950                 IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n");
1951                 ret = -ERFKILL;
1952                 goto cancel;
1953         }
1954
1955         if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) {
1956                 IWL_ERR(trans, "Error: Response NULL in '%s'\n",
1957                         iwl_get_cmd_string(trans, cmd->id));
1958                 ret = -EIO;
1959                 goto cancel;
1960         }
1961
1962         return 0;
1963
1964 cancel:
1965         if (cmd->flags & CMD_WANT_SKB) {
1966                 /*
1967                  * Cancel the CMD_WANT_SKB flag for the cmd in the
1968                  * TX cmd queue. Otherwise in case the cmd comes
1969                  * in later, it will possibly set an invalid
1970                  * address (cmd->meta.source).
1971                  */
1972                 txq->entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB;
1973         }
1974
1975         if (cmd->resp_pkt) {
1976                 iwl_free_resp(cmd);
1977                 cmd->resp_pkt = NULL;
1978         }
1979
1980         return ret;
1981 }
1982
1983 int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
1984 {
1985         /* Make sure the NIC is still alive in the bus */
1986         if (test_bit(STATUS_TRANS_DEAD, &trans->status))
1987                 return -ENODEV;
1988
1989         if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
1990             test_bit(STATUS_RFKILL_OPMODE, &trans->status)) {
1991                 IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n",
1992                                   cmd->id);
1993                 return -ERFKILL;
1994         }
1995
1996         if (cmd->flags & CMD_ASYNC)
1997                 return iwl_pcie_send_hcmd_async(trans, cmd);
1998
1999         /* We still can fail on RFKILL that can be asserted while we wait */
2000         return iwl_pcie_send_hcmd_sync(trans, cmd);
2001 }
2002
2003 static int iwl_fill_data_tbs(struct iwl_trans *trans, struct sk_buff *skb,
2004                              struct iwl_txq *txq, u8 hdr_len,
2005                              struct iwl_cmd_meta *out_meta)
2006 {
2007         u16 head_tb_len;
2008         int i;
2009
2010         /*
2011          * Set up TFD's third entry to point directly to remainder
2012          * of skb's head, if any
2013          */
2014         head_tb_len = skb_headlen(skb) - hdr_len;
2015
2016         if (head_tb_len > 0) {
2017                 dma_addr_t tb_phys = dma_map_single(trans->dev,
2018                                                     skb->data + hdr_len,
2019                                                     head_tb_len, DMA_TO_DEVICE);
2020                 if (unlikely(dma_mapping_error(trans->dev, tb_phys)))
2021                         return -EINVAL;
2022                 trace_iwlwifi_dev_tx_tb(trans->dev, skb, skb->data + hdr_len,
2023                                         tb_phys, head_tb_len);
2024                 iwl_pcie_txq_build_tfd(trans, txq, tb_phys, head_tb_len, false);
2025         }
2026
2027         /* set up the remaining entries to point to the data */
2028         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2029                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2030                 dma_addr_t tb_phys;
2031                 int tb_idx;
2032
2033                 if (!skb_frag_size(frag))
2034                         continue;
2035
2036                 tb_phys = skb_frag_dma_map(trans->dev, frag, 0,
2037                                            skb_frag_size(frag), DMA_TO_DEVICE);
2038
2039                 if (unlikely(dma_mapping_error(trans->dev, tb_phys)))
2040                         return -EINVAL;
2041                 trace_iwlwifi_dev_tx_tb(trans->dev, skb, skb_frag_address(frag),
2042                                         tb_phys, skb_frag_size(frag));
2043                 tb_idx = iwl_pcie_txq_build_tfd(trans, txq, tb_phys,
2044                                                 skb_frag_size(frag), false);
2045                 if (tb_idx < 0)
2046                         return tb_idx;
2047
2048                 out_meta->tbs |= BIT(tb_idx);
2049         }
2050
2051         return 0;
2052 }
2053
2054 #ifdef CONFIG_INET
2055 struct iwl_tso_hdr_page *get_page_hdr(struct iwl_trans *trans, size_t len)
2056 {
2057         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2058         struct iwl_tso_hdr_page *p = this_cpu_ptr(trans_pcie->tso_hdr_page);
2059
2060         if (!p->page)
2061                 goto alloc;
2062
2063         /* enough room on this page */
2064         if (p->pos + len < (u8 *)page_address(p->page) + PAGE_SIZE)
2065                 return p;
2066
2067         /* We don't have enough room on this page, get a new one. */
2068         __free_page(p->page);
2069
2070 alloc:
2071         p->page = alloc_page(GFP_ATOMIC);
2072         if (!p->page)
2073                 return NULL;
2074         p->pos = page_address(p->page);
2075         return p;
2076 }
2077
2078 static void iwl_compute_pseudo_hdr_csum(void *iph, struct tcphdr *tcph,
2079                                         bool ipv6, unsigned int len)
2080 {
2081         if (ipv6) {
2082                 struct ipv6hdr *iphv6 = iph;
2083
2084                 tcph->check = ~csum_ipv6_magic(&iphv6->saddr, &iphv6->daddr,
2085                                                len + tcph->doff * 4,
2086                                                IPPROTO_TCP, 0);
2087         } else {
2088                 struct iphdr *iphv4 = iph;
2089
2090                 ip_send_check(iphv4);
2091                 tcph->check = ~csum_tcpudp_magic(iphv4->saddr, iphv4->daddr,
2092                                                  len + tcph->doff * 4,
2093                                                  IPPROTO_TCP, 0);
2094         }
2095 }
2096
2097 static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb,
2098                                    struct iwl_txq *txq, u8 hdr_len,
2099                                    struct iwl_cmd_meta *out_meta,
2100                                    struct iwl_device_cmd *dev_cmd, u16 tb1_len)
2101 {
2102         struct iwl_tx_cmd *tx_cmd = (void *)dev_cmd->payload;
2103         struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
2104         struct ieee80211_hdr *hdr = (void *)skb->data;
2105         unsigned int snap_ip_tcp_hdrlen, ip_hdrlen, total_len, hdr_room;
2106         unsigned int mss = skb_shinfo(skb)->gso_size;
2107         u16 length, iv_len, amsdu_pad;
2108         u8 *start_hdr;
2109         struct iwl_tso_hdr_page *hdr_page;
2110         struct page **page_ptr;
2111         struct tso_t tso;
2112
2113         /* if the packet is protected, then it must be CCMP or GCMP */
2114         BUILD_BUG_ON(IEEE80211_CCMP_HDR_LEN != IEEE80211_GCMP_HDR_LEN);
2115         iv_len = ieee80211_has_protected(hdr->frame_control) ?
2116                 IEEE80211_CCMP_HDR_LEN : 0;
2117
2118         trace_iwlwifi_dev_tx(trans->dev, skb,
2119                              iwl_pcie_get_tfd(trans, txq, txq->write_ptr),
2120                              trans_pcie->tfd_size,
2121                              &dev_cmd->hdr, IWL_FIRST_TB_SIZE + tb1_len, 0);
2122
2123         ip_hdrlen = skb_transport_header(skb) - skb_network_header(skb);
2124         snap_ip_tcp_hdrlen = 8 + ip_hdrlen + tcp_hdrlen(skb);
2125         total_len = skb->len - snap_ip_tcp_hdrlen - hdr_len - iv_len;
2126         amsdu_pad = 0;
2127
2128         /* total amount of header we may need for this A-MSDU */
2129         hdr_room = DIV_ROUND_UP(total_len, mss) *
2130                 (3 + snap_ip_tcp_hdrlen + sizeof(struct ethhdr)) + iv_len;
2131
2132         /* Our device supports 9 segments at most, it will fit in 1 page */
2133         hdr_page = get_page_hdr(trans, hdr_room);
2134         if (!hdr_page)
2135                 return -ENOMEM;
2136
2137         get_page(hdr_page->page);
2138         start_hdr = hdr_page->pos;
2139         page_ptr = (void *)((u8 *)skb->cb + trans_pcie->page_offs);
2140         *page_ptr = hdr_page->page;
2141         memcpy(hdr_page->pos, skb->data + hdr_len, iv_len);
2142         hdr_page->pos += iv_len;
2143
2144         /*
2145          * Pull the ieee80211 header + IV to be able to use TSO core,
2146          * we will restore it for the tx_status flow.
2147          */
2148         skb_pull(skb, hdr_len + iv_len);
2149
2150         /*
2151          * Remove the length of all the headers that we don't actually
2152          * have in the MPDU by themselves, but that we duplicate into
2153          * all the different MSDUs inside the A-MSDU.
2154          */
2155         le16_add_cpu(&tx_cmd->len, -snap_ip_tcp_hdrlen);
2156
2157         tso_start(skb, &tso);
2158
2159         while (total_len) {
2160                 /* this is the data left for this subframe */
2161                 unsigned int data_left =
2162                         min_t(unsigned int, mss, total_len);
2163                 struct sk_buff *csum_skb = NULL;
2164                 unsigned int hdr_tb_len;
2165                 dma_addr_t hdr_tb_phys;
2166                 struct tcphdr *tcph;
2167                 u8 *iph, *subf_hdrs_start = hdr_page->pos;
2168
2169                 total_len -= data_left;
2170
2171                 memset(hdr_page->pos, 0, amsdu_pad);
2172                 hdr_page->pos += amsdu_pad;
2173                 amsdu_pad = (4 - (sizeof(struct ethhdr) + snap_ip_tcp_hdrlen +
2174                                   data_left)) & 0x3;
2175                 ether_addr_copy(hdr_page->pos, ieee80211_get_DA(hdr));
2176                 hdr_page->pos += ETH_ALEN;
2177                 ether_addr_copy(hdr_page->pos, ieee80211_get_SA(hdr));
2178                 hdr_page->pos += ETH_ALEN;
2179
2180                 length = snap_ip_tcp_hdrlen + data_left;
2181                 *((__be16 *)hdr_page->pos) = cpu_to_be16(length);
2182                 hdr_page->pos += sizeof(length);
2183
2184                 /*
2185                  * This will copy the SNAP as well which will be considered
2186                  * as MAC header.
2187                  */
2188                 tso_build_hdr(skb, hdr_page->pos, &tso, data_left, !total_len);
2189                 iph = hdr_page->pos + 8;
2190                 tcph = (void *)(iph + ip_hdrlen);
2191
2192                 /* For testing on current hardware only */
2193                 if (trans_pcie->sw_csum_tx) {
2194                         csum_skb = alloc_skb(data_left + tcp_hdrlen(skb),
2195                                              GFP_ATOMIC);
2196                         if (!csum_skb)
2197                                 return -ENOMEM;
2198
2199                         iwl_compute_pseudo_hdr_csum(iph, tcph,
2200                                                     skb->protocol ==
2201                                                         htons(ETH_P_IPV6),
2202                                                     data_left);
2203
2204                         skb_put_data(csum_skb, tcph, tcp_hdrlen(skb));
2205                         skb_reset_transport_header(csum_skb);
2206                         csum_skb->csum_start =
2207                                 (unsigned char *)tcp_hdr(csum_skb) -
2208                                                  csum_skb->head;
2209                 }
2210
2211                 hdr_page->pos += snap_ip_tcp_hdrlen;
2212
2213                 hdr_tb_len = hdr_page->pos - start_hdr;
2214                 hdr_tb_phys = dma_map_single(trans->dev, start_hdr,
2215                                              hdr_tb_len, DMA_TO_DEVICE);
2216                 if (unlikely(dma_mapping_error(trans->dev, hdr_tb_phys))) {
2217                         dev_kfree_skb(csum_skb);
2218                         return -EINVAL;
2219                 }
2220                 iwl_pcie_txq_build_tfd(trans, txq, hdr_tb_phys,
2221                                        hdr_tb_len, false);
2222                 trace_iwlwifi_dev_tx_tb(trans->dev, skb, start_hdr,
2223                                         hdr_tb_phys, hdr_tb_len);
2224                 /* add this subframe's headers' length to the tx_cmd */
2225                 le16_add_cpu(&tx_cmd->len, hdr_page->pos - subf_hdrs_start);
2226
2227                 /* prepare the start_hdr for the next subframe */
2228                 start_hdr = hdr_page->pos;
2229
2230                 /* put the payload */
2231                 while (data_left) {
2232                         unsigned int size = min_t(unsigned int, tso.size,
2233                                                   data_left);
2234                         dma_addr_t tb_phys;
2235
2236                         if (trans_pcie->sw_csum_tx)
2237                                 skb_put_data(csum_skb, tso.data, size);
2238
2239                         tb_phys = dma_map_single(trans->dev, tso.data,
2240                                                  size, DMA_TO_DEVICE);
2241                         if (unlikely(dma_mapping_error(trans->dev, tb_phys))) {
2242                                 dev_kfree_skb(csum_skb);
2243                                 return -EINVAL;
2244                         }
2245
2246                         iwl_pcie_txq_build_tfd(trans, txq, tb_phys,
2247                                                size, false);
2248                         trace_iwlwifi_dev_tx_tb(trans->dev, skb, tso.data,
2249                                                 tb_phys, size);
2250
2251                         data_left -= size;
2252                         tso_build_data(skb, &tso, size);
2253                 }
2254
2255                 /* For testing on early hardware only */
2256                 if (trans_pcie->sw_csum_tx) {
2257                         __wsum csum;
2258
2259                         csum = skb_checksum(csum_skb,
2260                                             skb_checksum_start_offset(csum_skb),
2261                                             csum_skb->len -
2262                                             skb_checksum_start_offset(csum_skb),
2263                                             0);
2264                         dev_kfree_skb(csum_skb);
2265                         dma_sync_single_for_cpu(trans->dev, hdr_tb_phys,
2266                                                 hdr_tb_len, DMA_TO_DEVICE);
2267                         tcph->check = csum_fold(csum);
2268                         dma_sync_single_for_device(trans->dev, hdr_tb_phys,
2269                                                    hdr_tb_len, DMA_TO_DEVICE);
2270                 }
2271         }
2272
2273         /* re -add the WiFi header and IV */
2274         skb_push(skb, hdr_len + iv_len);
2275
2276         return 0;
2277 }
2278 #else /* CONFIG_INET */
2279 static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb,
2280                                    struct iwl_txq *txq, u8 hdr_len,
2281                                    struct iwl_cmd_meta *out_meta,
2282                                    struct iwl_device_cmd *dev_cmd, u16 tb1_len)
2283 {
2284         /* No A-MSDU without CONFIG_INET */
2285         WARN_ON(1);
2286
2287         return -1;
2288 }
2289 #endif /* CONFIG_INET */
2290
2291 int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
2292                       struct iwl_device_cmd *dev_cmd, int txq_id)
2293 {
2294         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2295         struct ieee80211_hdr *hdr;
2296         struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload;
2297         struct iwl_cmd_meta *out_meta;
2298         struct iwl_txq *txq;
2299         dma_addr_t tb0_phys, tb1_phys, scratch_phys;
2300         void *tb1_addr;
2301         void *tfd;
2302         u16 len, tb1_len;
2303         bool wait_write_ptr;
2304         __le16 fc;
2305         u8 hdr_len;
2306         u16 wifi_seq;
2307         bool amsdu;
2308
2309         txq = trans_pcie->txq[txq_id];
2310
2311         if (WARN_ONCE(!test_bit(txq_id, trans_pcie->queue_used),
2312                       "TX on unused queue %d\n", txq_id))
2313                 return -EINVAL;
2314
2315         if (unlikely(trans_pcie->sw_csum_tx &&
2316                      skb->ip_summed == CHECKSUM_PARTIAL)) {
2317                 int offs = skb_checksum_start_offset(skb);
2318                 int csum_offs = offs + skb->csum_offset;
2319                 __wsum csum;
2320
2321                 if (skb_ensure_writable(skb, csum_offs + sizeof(__sum16)))
2322                         return -1;
2323
2324                 csum = skb_checksum(skb, offs, skb->len - offs, 0);
2325                 *(__sum16 *)(skb->data + csum_offs) = csum_fold(csum);
2326
2327                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2328         }
2329
2330         if (skb_is_nonlinear(skb) &&
2331             skb_shinfo(skb)->nr_frags > IWL_PCIE_MAX_FRAGS(trans_pcie) &&
2332             __skb_linearize(skb))
2333                 return -ENOMEM;
2334
2335         /* mac80211 always puts the full header into the SKB's head,
2336          * so there's no need to check if it's readable there
2337          */
2338         hdr = (struct ieee80211_hdr *)skb->data;
2339         fc = hdr->frame_control;
2340         hdr_len = ieee80211_hdrlen(fc);
2341
2342         spin_lock(&txq->lock);
2343
2344         if (iwl_queue_space(trans, txq) < txq->high_mark) {
2345                 iwl_stop_queue(trans, txq);
2346
2347                 /* don't put the packet on the ring, if there is no room */
2348                 if (unlikely(iwl_queue_space(trans, txq) < 3)) {
2349                         struct iwl_device_cmd **dev_cmd_ptr;
2350
2351                         dev_cmd_ptr = (void *)((u8 *)skb->cb +
2352                                                trans_pcie->dev_cmd_offs);
2353
2354                         *dev_cmd_ptr = dev_cmd;
2355                         __skb_queue_tail(&txq->overflow_q, skb);
2356
2357                         spin_unlock(&txq->lock);
2358                         return 0;
2359                 }
2360         }
2361
2362         /* In AGG mode, the index in the ring must correspond to the WiFi
2363          * sequence number. This is a HW requirements to help the SCD to parse
2364          * the BA.
2365          * Check here that the packets are in the right place on the ring.
2366          */
2367         wifi_seq = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
2368         WARN_ONCE(txq->ampdu &&
2369                   (wifi_seq & 0xff) != txq->write_ptr,
2370                   "Q: %d WiFi Seq %d tfdNum %d",
2371                   txq_id, wifi_seq, txq->write_ptr);
2372
2373         /* Set up driver data for this TFD */
2374         txq->entries[txq->write_ptr].skb = skb;
2375         txq->entries[txq->write_ptr].cmd = dev_cmd;
2376
2377         dev_cmd->hdr.sequence =
2378                 cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
2379                             INDEX_TO_SEQ(txq->write_ptr)));
2380
2381         tb0_phys = iwl_pcie_get_first_tb_dma(txq, txq->write_ptr);
2382         scratch_phys = tb0_phys + sizeof(struct iwl_cmd_header) +
2383                        offsetof(struct iwl_tx_cmd, scratch);
2384
2385         tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
2386         tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
2387
2388         /* Set up first empty entry in queue's array of Tx/cmd buffers */
2389         out_meta = &txq->entries[txq->write_ptr].meta;
2390         out_meta->flags = 0;
2391
2392         /*
2393          * The second TB (tb1) points to the remainder of the TX command
2394          * and the 802.11 header - dword aligned size
2395          * (This calculation modifies the TX command, so do it before the
2396          * setup of the first TB)
2397          */
2398         len = sizeof(struct iwl_tx_cmd) + sizeof(struct iwl_cmd_header) +
2399               hdr_len - IWL_FIRST_TB_SIZE;
2400         /* do not align A-MSDU to dword as the subframe header aligns it */
2401         amsdu = ieee80211_is_data_qos(fc) &&
2402                 (*ieee80211_get_qos_ctl(hdr) &
2403                  IEEE80211_QOS_CTL_A_MSDU_PRESENT);
2404         if (trans_pcie->sw_csum_tx || !amsdu) {
2405                 tb1_len = ALIGN(len, 4);
2406                 /* Tell NIC about any 2-byte padding after MAC header */
2407                 if (tb1_len != len)
2408                         tx_cmd->tx_flags |= cpu_to_le32(TX_CMD_FLG_MH_PAD);
2409         } else {
2410                 tb1_len = len;
2411         }
2412
2413         /*
2414          * The first TB points to bi-directional DMA data, we'll
2415          * memcpy the data into it later.
2416          */
2417         iwl_pcie_txq_build_tfd(trans, txq, tb0_phys,
2418                                IWL_FIRST_TB_SIZE, true);
2419
2420         /* there must be data left over for TB1 or this code must be changed */
2421         BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_FIRST_TB_SIZE);
2422
2423         /* map the data for TB1 */
2424         tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_FIRST_TB_SIZE;
2425         tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE);
2426         if (unlikely(dma_mapping_error(trans->dev, tb1_phys)))
2427                 goto out_err;
2428         iwl_pcie_txq_build_tfd(trans, txq, tb1_phys, tb1_len, false);
2429
2430         trace_iwlwifi_dev_tx(trans->dev, skb,
2431                              iwl_pcie_get_tfd(trans, txq,
2432                                               txq->write_ptr),
2433                              trans_pcie->tfd_size,
2434                              &dev_cmd->hdr, IWL_FIRST_TB_SIZE + tb1_len,
2435                              hdr_len);
2436
2437         /*
2438          * If gso_size wasn't set, don't give the frame "amsdu treatment"
2439          * (adding subframes, etc.).
2440          * This can happen in some testing flows when the amsdu was already
2441          * pre-built, and we just need to send the resulting skb.
2442          */
2443         if (amsdu && skb_shinfo(skb)->gso_size) {
2444                 if (unlikely(iwl_fill_data_tbs_amsdu(trans, skb, txq, hdr_len,
2445                                                      out_meta, dev_cmd,
2446                                                      tb1_len)))
2447                         goto out_err;
2448         } else {
2449                 struct sk_buff *frag;
2450
2451                 if (unlikely(iwl_fill_data_tbs(trans, skb, txq, hdr_len,
2452                                                out_meta)))
2453                         goto out_err;
2454
2455                 skb_walk_frags(skb, frag) {
2456                         if (unlikely(iwl_fill_data_tbs(trans, frag, txq, 0,
2457                                                        out_meta)))
2458                                 goto out_err;
2459                 }
2460         }
2461
2462         /* building the A-MSDU might have changed this data, so memcpy it now */
2463         memcpy(&txq->first_tb_bufs[txq->write_ptr], dev_cmd, IWL_FIRST_TB_SIZE);
2464
2465         tfd = iwl_pcie_get_tfd(trans, txq, txq->write_ptr);
2466         /* Set up entry for this TFD in Tx byte-count array */
2467         iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len),
2468                                          iwl_pcie_tfd_get_num_tbs(trans, tfd));
2469
2470         wait_write_ptr = ieee80211_has_morefrags(fc);
2471
2472         /* start timer if queue currently empty */
2473         if (txq->read_ptr == txq->write_ptr && txq->wd_timeout) {
2474                 /*
2475                  * If the TXQ is active, then set the timer, if not,
2476                  * set the timer in remainder so that the timer will
2477                  * be armed with the right value when the station will
2478                  * wake up.
2479                  */
2480                 if (!txq->frozen)
2481                         mod_timer(&txq->stuck_timer,
2482                                   jiffies + txq->wd_timeout);
2483                 else
2484                         txq->frozen_expiry_remainder = txq->wd_timeout;
2485         }
2486
2487         /* Tell device the write index *just past* this latest filled TFD */
2488         txq->write_ptr = iwl_queue_inc_wrap(trans, txq->write_ptr);
2489         if (!wait_write_ptr)
2490                 iwl_pcie_txq_inc_wr_ptr(trans, txq);
2491
2492         /*
2493          * At this point the frame is "transmitted" successfully
2494          * and we will get a TX status notification eventually.
2495          */
2496         spin_unlock(&txq->lock);
2497         return 0;
2498 out_err:
2499         iwl_pcie_tfd_unmap(trans, out_meta, txq, txq->write_ptr);
2500         spin_unlock(&txq->lock);
2501         return -1;
2502 }