1 /******************************************************************************
5 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
29 #include <linux/etherdevice.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/init.h>
33 #include <linux/sched.h>
38 #include "iwl-helpers.h"
39 #include "iwl-agn-hw.h"
43 static inline u32 iwlagn_get_scd_ssn(struct iwlagn_tx_resp *tx_resp)
45 return le32_to_cpup((__le32 *)&tx_resp->status +
46 tx_resp->frame_count) & MAX_SN;
49 static void iwlagn_count_tx_err_status(struct iwl_priv *priv, u16 status)
51 status &= TX_STATUS_MSK;
54 case TX_STATUS_POSTPONE_DELAY:
55 priv->_agn.reply_tx_stats.pp_delay++;
57 case TX_STATUS_POSTPONE_FEW_BYTES:
58 priv->_agn.reply_tx_stats.pp_few_bytes++;
60 case TX_STATUS_POSTPONE_BT_PRIO:
61 priv->_agn.reply_tx_stats.pp_bt_prio++;
63 case TX_STATUS_POSTPONE_QUIET_PERIOD:
64 priv->_agn.reply_tx_stats.pp_quiet_period++;
66 case TX_STATUS_POSTPONE_CALC_TTAK:
67 priv->_agn.reply_tx_stats.pp_calc_ttak++;
69 case TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY:
70 priv->_agn.reply_tx_stats.int_crossed_retry++;
72 case TX_STATUS_FAIL_SHORT_LIMIT:
73 priv->_agn.reply_tx_stats.short_limit++;
75 case TX_STATUS_FAIL_LONG_LIMIT:
76 priv->_agn.reply_tx_stats.long_limit++;
78 case TX_STATUS_FAIL_FIFO_UNDERRUN:
79 priv->_agn.reply_tx_stats.fifo_underrun++;
81 case TX_STATUS_FAIL_DRAIN_FLOW:
82 priv->_agn.reply_tx_stats.drain_flow++;
84 case TX_STATUS_FAIL_RFKILL_FLUSH:
85 priv->_agn.reply_tx_stats.rfkill_flush++;
87 case TX_STATUS_FAIL_LIFE_EXPIRE:
88 priv->_agn.reply_tx_stats.life_expire++;
90 case TX_STATUS_FAIL_DEST_PS:
91 priv->_agn.reply_tx_stats.dest_ps++;
93 case TX_STATUS_FAIL_HOST_ABORTED:
94 priv->_agn.reply_tx_stats.host_abort++;
96 case TX_STATUS_FAIL_BT_RETRY:
97 priv->_agn.reply_tx_stats.bt_retry++;
99 case TX_STATUS_FAIL_STA_INVALID:
100 priv->_agn.reply_tx_stats.sta_invalid++;
102 case TX_STATUS_FAIL_FRAG_DROPPED:
103 priv->_agn.reply_tx_stats.frag_drop++;
105 case TX_STATUS_FAIL_TID_DISABLE:
106 priv->_agn.reply_tx_stats.tid_disable++;
108 case TX_STATUS_FAIL_FIFO_FLUSHED:
109 priv->_agn.reply_tx_stats.fifo_flush++;
111 case TX_STATUS_FAIL_INSUFFICIENT_CF_POLL:
112 priv->_agn.reply_tx_stats.insuff_cf_poll++;
114 case TX_STATUS_FAIL_PASSIVE_NO_RX:
115 priv->_agn.reply_tx_stats.fail_hw_drop++;
117 case TX_STATUS_FAIL_NO_BEACON_ON_RADAR:
118 priv->_agn.reply_tx_stats.sta_color_mismatch++;
121 priv->_agn.reply_tx_stats.unknown++;
126 static void iwlagn_count_agg_tx_err_status(struct iwl_priv *priv, u16 status)
128 status &= AGG_TX_STATUS_MSK;
131 case AGG_TX_STATE_UNDERRUN_MSK:
132 priv->_agn.reply_agg_tx_stats.underrun++;
134 case AGG_TX_STATE_BT_PRIO_MSK:
135 priv->_agn.reply_agg_tx_stats.bt_prio++;
137 case AGG_TX_STATE_FEW_BYTES_MSK:
138 priv->_agn.reply_agg_tx_stats.few_bytes++;
140 case AGG_TX_STATE_ABORT_MSK:
141 priv->_agn.reply_agg_tx_stats.abort++;
143 case AGG_TX_STATE_LAST_SENT_TTL_MSK:
144 priv->_agn.reply_agg_tx_stats.last_sent_ttl++;
146 case AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK:
147 priv->_agn.reply_agg_tx_stats.last_sent_try++;
149 case AGG_TX_STATE_LAST_SENT_BT_KILL_MSK:
150 priv->_agn.reply_agg_tx_stats.last_sent_bt_kill++;
152 case AGG_TX_STATE_SCD_QUERY_MSK:
153 priv->_agn.reply_agg_tx_stats.scd_query++;
155 case AGG_TX_STATE_TEST_BAD_CRC32_MSK:
156 priv->_agn.reply_agg_tx_stats.bad_crc32++;
158 case AGG_TX_STATE_RESPONSE_MSK:
159 priv->_agn.reply_agg_tx_stats.response++;
161 case AGG_TX_STATE_DUMP_TX_MSK:
162 priv->_agn.reply_agg_tx_stats.dump_tx++;
164 case AGG_TX_STATE_DELAY_TX_MSK:
165 priv->_agn.reply_agg_tx_stats.delay_tx++;
168 priv->_agn.reply_agg_tx_stats.unknown++;
173 static void iwlagn_set_tx_status(struct iwl_priv *priv,
174 struct ieee80211_tx_info *info,
175 struct iwl_rxon_context *ctx,
176 struct iwlagn_tx_resp *tx_resp,
177 int txq_id, bool is_agg)
179 u16 status = le16_to_cpu(tx_resp->status.status);
181 info->status.rates[0].count = tx_resp->failure_frame + 1;
183 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
184 info->flags |= iwl_tx_status_to_mac80211(status);
185 iwlagn_hwrate_to_tx_control(priv, le32_to_cpu(tx_resp->rate_n_flags),
187 if (!iwl_is_tx_success(status))
188 iwlagn_count_tx_err_status(priv, status);
190 if (status == TX_STATUS_FAIL_PASSIVE_NO_RX &&
191 iwl_is_associated_ctx(ctx) && ctx->vif &&
192 ctx->vif->type == NL80211_IFTYPE_STATION) {
193 ctx->last_tx_rejected = true;
194 iwl_stop_queue(priv, &priv->txq[txq_id]);
197 IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags "
200 iwl_get_tx_fail_reason(status), status,
201 le32_to_cpu(tx_resp->rate_n_flags),
202 tx_resp->failure_frame);
205 #ifdef CONFIG_IWLWIFI_DEBUG
206 #define AGG_TX_STATE_FAIL(x) case AGG_TX_STATE_ ## x: return #x
208 const char *iwl_get_agg_tx_fail_reason(u16 status)
210 status &= AGG_TX_STATUS_MSK;
212 case AGG_TX_STATE_TRANSMITTED:
214 AGG_TX_STATE_FAIL(UNDERRUN_MSK);
215 AGG_TX_STATE_FAIL(BT_PRIO_MSK);
216 AGG_TX_STATE_FAIL(FEW_BYTES_MSK);
217 AGG_TX_STATE_FAIL(ABORT_MSK);
218 AGG_TX_STATE_FAIL(LAST_SENT_TTL_MSK);
219 AGG_TX_STATE_FAIL(LAST_SENT_TRY_CNT_MSK);
220 AGG_TX_STATE_FAIL(LAST_SENT_BT_KILL_MSK);
221 AGG_TX_STATE_FAIL(SCD_QUERY_MSK);
222 AGG_TX_STATE_FAIL(TEST_BAD_CRC32_MSK);
223 AGG_TX_STATE_FAIL(RESPONSE_MSK);
224 AGG_TX_STATE_FAIL(DUMP_TX_MSK);
225 AGG_TX_STATE_FAIL(DELAY_TX_MSK);
230 #endif /* CONFIG_IWLWIFI_DEBUG */
232 static int iwlagn_tx_status_reply_tx(struct iwl_priv *priv,
233 struct iwl_ht_agg *agg,
234 struct iwlagn_tx_resp *tx_resp,
235 int txq_id, u16 start_idx)
238 struct agg_tx_status *frame_status = &tx_resp->status;
239 struct ieee80211_hdr *hdr = NULL;
243 if (agg->wait_for_ba)
244 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
246 agg->frame_count = tx_resp->frame_count;
247 agg->start_idx = start_idx;
248 agg->rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
251 /* # frames attempted by Tx command */
252 if (agg->frame_count == 1) {
253 struct iwl_tx_info *txb;
255 /* Only one frame was attempted; no block-ack will arrive */
258 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
259 agg->frame_count, agg->start_idx, idx);
260 txb = &priv->txq[txq_id].txb[idx];
261 iwlagn_set_tx_status(priv, IEEE80211_SKB_CB(txb->skb),
262 txb->ctx, tx_resp, txq_id, true);
263 agg->wait_for_ba = 0;
265 /* Two or more frames were attempted; expect block-ack */
269 * Start is the lowest frame sent. It may not be the first
270 * frame in the batch; we figure this out dynamically during
271 * the following loop.
273 int start = agg->start_idx;
275 /* Construct bit-map of pending frames within Tx window */
276 for (i = 0; i < agg->frame_count; i++) {
278 status = le16_to_cpu(frame_status[i].status);
279 seq = le16_to_cpu(frame_status[i].sequence);
280 idx = SEQ_TO_INDEX(seq);
281 txq_id = SEQ_TO_QUEUE(seq);
283 if (status & AGG_TX_STATUS_MSK)
284 iwlagn_count_agg_tx_err_status(priv, status);
286 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
287 AGG_TX_STATE_ABORT_MSK))
290 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
291 agg->frame_count, txq_id, idx);
292 IWL_DEBUG_TX_REPLY(priv, "status %s (0x%08x), "
293 "try-count (0x%08x)\n",
294 iwl_get_agg_tx_fail_reason(status),
295 status & AGG_TX_STATUS_MSK,
296 status & AGG_TX_TRY_MSK);
298 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
301 "BUG_ON idx doesn't point to valid skb"
302 " idx=%d, txq_id=%d\n", idx, txq_id);
306 sc = le16_to_cpu(hdr->seq_ctrl);
307 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
309 "BUG_ON idx doesn't match seq control"
310 " idx=%d, seq_idx=%d, seq=%d\n",
316 IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
317 i, idx, SEQ_TO_SN(sc));
320 * sh -> how many frames ahead of the starting frame is
323 * Note that all frames sent in the batch must be in a
324 * 64-frame window, so this number should be in [0,63].
325 * If outside of this window, then we've found a new
326 * "first" frame in the batch and need to change start.
331 * If >= 64, out of window. start must be at the front
332 * of the circular buffer, idx must be near the end of
333 * the buffer, and idx is the new "first" frame. Shift
334 * the indices around.
337 /* Shift bitmap by start - idx, wrapped */
338 sh = 0x100 - idx + start;
339 bitmap = bitmap << sh;
340 /* Now idx is the new start so sh = 0 */
344 * If <= -64 then wraps the 256-pkt circular buffer
345 * (e.g., start = 255 and idx = 0, sh should be 1)
347 } else if (sh <= -64) {
348 sh = 0x100 - start + idx;
350 * If < 0 but > -64, out of window. idx is before start
351 * but not wrapped. Shift the indices around.
354 /* Shift by how far start is ahead of idx */
356 bitmap = bitmap << sh;
357 /* Now idx is the new start so sh = 0 */
361 /* Sequence number start + sh was sent in this batch */
362 bitmap |= 1ULL << sh;
363 IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
364 start, (unsigned long long)bitmap);
368 * Store the bitmap and possibly the new start, if we wrapped
371 agg->bitmap = bitmap;
372 agg->start_idx = start;
373 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
374 agg->frame_count, agg->start_idx,
375 (unsigned long long)agg->bitmap);
378 agg->wait_for_ba = 1;
383 void iwl_check_abort_status(struct iwl_priv *priv,
384 u8 frame_count, u32 status)
386 if (frame_count == 1 && status == TX_STATUS_FAIL_RFKILL_FLUSH) {
387 IWL_ERR(priv, "Tx flush command to flush out all frames\n");
388 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
389 queue_work(priv->workqueue, &priv->tx_flush);
393 static void iwlagn_rx_reply_tx(struct iwl_priv *priv,
394 struct iwl_rx_mem_buffer *rxb)
396 struct iwl_rx_packet *pkt = rxb_addr(rxb);
397 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
398 int txq_id = SEQ_TO_QUEUE(sequence);
399 int index = SEQ_TO_INDEX(sequence);
400 struct iwl_tx_queue *txq = &priv->txq[txq_id];
401 struct ieee80211_tx_info *info;
402 struct iwlagn_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
403 struct iwl_tx_info *txb;
404 u32 status = le16_to_cpu(tx_resp->status.status);
410 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
411 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
412 "is out of range [0-%d] %d %d\n", txq_id,
413 index, txq->q.n_bd, txq->q.write_ptr,
418 txq->time_stamp = jiffies;
419 txb = &txq->txb[txq->q.read_ptr];
420 info = IEEE80211_SKB_CB(txb->skb);
421 memset(&info->status, 0, sizeof(info->status));
423 tid = (tx_resp->ra_tid & IWLAGN_TX_RES_TID_MSK) >>
424 IWLAGN_TX_RES_TID_POS;
425 sta_id = (tx_resp->ra_tid & IWLAGN_TX_RES_RA_MSK) >>
426 IWLAGN_TX_RES_RA_POS;
428 spin_lock_irqsave(&priv->sta_lock, flags);
429 if (txq->sched_retry) {
430 const u32 scd_ssn = iwlagn_get_scd_ssn(tx_resp);
431 struct iwl_ht_agg *agg;
433 agg = &priv->stations[sta_id].tid[tid].agg;
435 * If the BT kill count is non-zero, we'll get this
436 * notification again.
438 if (tx_resp->bt_kill_count && tx_resp->frame_count == 1 &&
439 priv->cfg->bt_params &&
440 priv->cfg->bt_params->advanced_bt_coexist) {
441 IWL_WARN(priv, "receive reply tx with bt_kill\n");
443 iwlagn_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
445 /* check if BAR is needed */
446 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
447 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
449 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
450 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
451 IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim "
452 "scd_ssn=%d idx=%d txq=%d swq=%d\n",
453 scd_ssn , index, txq_id, txq->swq_id);
455 freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
456 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
458 if (priv->mac80211_registered &&
459 (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
460 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA))
461 iwl_wake_queue(priv, txq);
464 iwlagn_set_tx_status(priv, info, txb->ctx, tx_resp,
466 freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
467 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
469 if (priv->mac80211_registered &&
470 iwl_queue_space(&txq->q) > txq->q.low_mark &&
471 status != TX_STATUS_FAIL_PASSIVE_NO_RX)
472 iwl_wake_queue(priv, txq);
475 iwlagn_txq_check_empty(priv, sta_id, tid, txq_id);
477 iwl_check_abort_status(priv, tx_resp->frame_count, status);
478 spin_unlock_irqrestore(&priv->sta_lock, flags);
481 void iwlagn_rx_handler_setup(struct iwl_priv *priv)
483 /* init calibration handlers */
484 priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
485 iwlagn_rx_calib_result;
486 priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
487 iwlagn_rx_calib_complete;
488 priv->rx_handlers[REPLY_TX] = iwlagn_rx_reply_tx;
490 /* set up notification wait support */
491 spin_lock_init(&priv->_agn.notif_wait_lock);
492 INIT_LIST_HEAD(&priv->_agn.notif_waits);
493 init_waitqueue_head(&priv->_agn.notif_waitq);
496 void iwlagn_setup_deferred_work(struct iwl_priv *priv)
499 * nothing need to be done here anymore
500 * still keep for future use if needed
504 int iwlagn_hw_valid_rtc_data_addr(u32 addr)
506 return (addr >= IWLAGN_RTC_DATA_LOWER_BOUND) &&
507 (addr < IWLAGN_RTC_DATA_UPPER_BOUND);
510 int iwlagn_send_tx_power(struct iwl_priv *priv)
512 struct iwlagn_tx_power_dbm_cmd tx_power_cmd;
515 if (WARN_ONCE(test_bit(STATUS_SCAN_HW, &priv->status),
516 "TX Power requested while scanning!\n"))
519 /* half dBm need to multiply */
520 tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
522 if (priv->tx_power_lmt_in_half_dbm &&
523 priv->tx_power_lmt_in_half_dbm < tx_power_cmd.global_lmt) {
525 * For the newer devices which using enhanced/extend tx power
526 * table in EEPROM, the format is in half dBm. driver need to
527 * convert to dBm format before report to mac80211.
528 * By doing so, there is a possibility of 1/2 dBm resolution
529 * lost. driver will perform "round-up" operation before
530 * reporting, but it will cause 1/2 dBm tx power over the
531 * regulatory limit. Perform the checking here, if the
532 * "tx_power_user_lmt" is higher than EEPROM value (in
533 * half-dBm format), lower the tx power based on EEPROM
535 tx_power_cmd.global_lmt = priv->tx_power_lmt_in_half_dbm;
537 tx_power_cmd.flags = IWLAGN_TX_POWER_NO_CLOSED;
538 tx_power_cmd.srv_chan_lmt = IWLAGN_TX_POWER_AUTO;
540 if (IWL_UCODE_API(priv->ucode_ver) == 1)
541 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1;
543 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD;
545 return iwl_send_cmd_pdu(priv, tx_ant_cfg_cmd, sizeof(tx_power_cmd),
549 void iwlagn_temperature(struct iwl_priv *priv)
551 /* store temperature from correct statistics (in Celsius) */
552 priv->temperature = le32_to_cpu(priv->statistics.common.temperature);
553 iwl_tt_handler(priv);
556 u16 iwlagn_eeprom_calib_version(struct iwl_priv *priv)
558 struct iwl_eeprom_calib_hdr {
564 hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
573 static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
577 if ((address & INDIRECT_ADDRESS) == 0)
580 switch (address & INDIRECT_TYPE_MSK) {
582 offset = iwl_eeprom_query16(priv, EEPROM_LINK_HOST);
584 case INDIRECT_GENERAL:
585 offset = iwl_eeprom_query16(priv, EEPROM_LINK_GENERAL);
587 case INDIRECT_REGULATORY:
588 offset = iwl_eeprom_query16(priv, EEPROM_LINK_REGULATORY);
590 case INDIRECT_TXP_LIMIT:
591 offset = iwl_eeprom_query16(priv, EEPROM_LINK_TXP_LIMIT);
593 case INDIRECT_TXP_LIMIT_SIZE:
594 offset = iwl_eeprom_query16(priv, EEPROM_LINK_TXP_LIMIT_SIZE);
596 case INDIRECT_CALIBRATION:
597 offset = iwl_eeprom_query16(priv, EEPROM_LINK_CALIBRATION);
599 case INDIRECT_PROCESS_ADJST:
600 offset = iwl_eeprom_query16(priv, EEPROM_LINK_PROCESS_ADJST);
602 case INDIRECT_OTHERS:
603 offset = iwl_eeprom_query16(priv, EEPROM_LINK_OTHERS);
606 IWL_ERR(priv, "illegal indirect type: 0x%X\n",
607 address & INDIRECT_TYPE_MSK);
611 /* translate the offset from words to byte */
612 return (address & ADDRESS_MSK) + (offset << 1);
615 const u8 *iwlagn_eeprom_query_addr(const struct iwl_priv *priv,
618 u32 address = eeprom_indirect_address(priv, offset);
619 BUG_ON(address >= priv->cfg->base_params->eeprom_size);
620 return &priv->eeprom[address];
623 struct iwl_mod_params iwlagn_mod_params = {
627 /* the rest are 0 by default */
630 void iwlagn_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
634 spin_lock_irqsave(&rxq->lock, flags);
635 INIT_LIST_HEAD(&rxq->rx_free);
636 INIT_LIST_HEAD(&rxq->rx_used);
637 /* Fill the rx_used queue with _all_ of the Rx buffers */
638 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
639 /* In the reset function, these buffers may have been allocated
640 * to an SKB, so we need to unmap and free potential storage */
641 if (rxq->pool[i].page != NULL) {
642 pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
643 PAGE_SIZE << priv->hw_params.rx_page_order,
645 __iwl_free_pages(priv, rxq->pool[i].page);
646 rxq->pool[i].page = NULL;
648 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
651 for (i = 0; i < RX_QUEUE_SIZE; i++)
652 rxq->queue[i] = NULL;
654 /* Set us so that we have processed and used all buffers, but have
655 * not restocked the Rx queue with fresh buffers */
656 rxq->read = rxq->write = 0;
657 rxq->write_actual = 0;
659 spin_unlock_irqrestore(&rxq->lock, flags);
662 int iwlagn_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
665 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
666 u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT for all devices? */
668 rb_timeout = RX_RB_TIMEOUT;
670 if (priv->cfg->mod_params->amsdu_size_8K)
671 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
673 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
676 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
678 /* Reset driver's Rx queue write index */
679 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
681 /* Tell device where to find RBD circular buffer in DRAM */
682 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
683 (u32)(rxq->bd_dma >> 8));
685 /* Tell device where in DRAM to update its Rx status */
686 iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
687 rxq->rb_stts_dma >> 4);
690 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
691 * the credit mechanism in 5000 HW RX FIFO
692 * Direct rx interrupts to hosts
693 * Rx buffer size 4 or 8k
697 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
698 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
699 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
700 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
701 FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
703 (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
704 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
706 /* Set interrupt coalescing timer to default (2048 usecs) */
707 iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
712 static void iwlagn_set_pwr_vmain(struct iwl_priv *priv)
715 * (for documentation purposes)
716 * to set power to V_AUX, do:
718 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
719 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
720 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
721 ~APMG_PS_CTRL_MSK_PWR_SRC);
724 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
725 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
726 ~APMG_PS_CTRL_MSK_PWR_SRC);
729 int iwlagn_hw_nic_init(struct iwl_priv *priv)
732 struct iwl_rx_queue *rxq = &priv->rxq;
736 spin_lock_irqsave(&priv->lock, flags);
737 priv->cfg->ops->lib->apm_ops.init(priv);
739 /* Set interrupt coalescing calibration timer to default (512 usecs) */
740 iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
742 spin_unlock_irqrestore(&priv->lock, flags);
744 iwlagn_set_pwr_vmain(priv);
746 priv->cfg->ops->lib->apm_ops.config(priv);
748 /* Allocate the RX queue, or reset if it is already allocated */
750 ret = iwl_rx_queue_alloc(priv);
752 IWL_ERR(priv, "Unable to initialize Rx queue\n");
756 iwlagn_rx_queue_reset(priv, rxq);
758 iwlagn_rx_replenish(priv);
760 iwlagn_rx_init(priv, rxq);
762 spin_lock_irqsave(&priv->lock, flags);
764 rxq->need_update = 1;
765 iwl_rx_queue_update_write_ptr(priv, rxq);
767 spin_unlock_irqrestore(&priv->lock, flags);
769 /* Allocate or reset and init all Tx and Command queues */
771 ret = iwlagn_txq_ctx_alloc(priv);
775 iwlagn_txq_ctx_reset(priv);
777 if (priv->cfg->base_params->shadow_reg_enable) {
778 /* enable shadow regs in HW */
779 iwl_set_bit(priv, CSR_MAC_SHADOW_REG_CTRL,
783 set_bit(STATUS_INIT, &priv->status);
789 * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
791 static inline __le32 iwlagn_dma_addr2rbd_ptr(struct iwl_priv *priv,
794 return cpu_to_le32((u32)(dma_addr >> 8));
798 * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool
800 * If there are slots in the RX queue that need to be restocked,
801 * and we have free pre-allocated buffers, fill the ranks as much
802 * as we can, pulling from rx_free.
804 * This moves the 'write' index forward to catch up with 'processed', and
805 * also updates the memory address in the firmware to reference the new
808 void iwlagn_rx_queue_restock(struct iwl_priv *priv)
810 struct iwl_rx_queue *rxq = &priv->rxq;
811 struct list_head *element;
812 struct iwl_rx_mem_buffer *rxb;
815 spin_lock_irqsave(&rxq->lock, flags);
816 while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
817 /* The overwritten rxb must be a used one */
818 rxb = rxq->queue[rxq->write];
819 BUG_ON(rxb && rxb->page);
821 /* Get next free Rx buffer, remove from free list */
822 element = rxq->rx_free.next;
823 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
826 /* Point to Rx buffer via next RBD in circular buffer */
827 rxq->bd[rxq->write] = iwlagn_dma_addr2rbd_ptr(priv,
829 rxq->queue[rxq->write] = rxb;
830 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
833 spin_unlock_irqrestore(&rxq->lock, flags);
834 /* If the pre-allocated buffer pool is dropping low, schedule to
836 if (rxq->free_count <= RX_LOW_WATERMARK)
837 queue_work(priv->workqueue, &priv->rx_replenish);
840 /* If we've added more space for the firmware to place data, tell it.
841 * Increment device's write pointer in multiples of 8. */
842 if (rxq->write_actual != (rxq->write & ~0x7)) {
843 spin_lock_irqsave(&rxq->lock, flags);
844 rxq->need_update = 1;
845 spin_unlock_irqrestore(&rxq->lock, flags);
846 iwl_rx_queue_update_write_ptr(priv, rxq);
851 * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free
853 * When moving to rx_free an SKB is allocated for the slot.
855 * Also restock the Rx queue via iwl_rx_queue_restock.
856 * This is called as a scheduled work item (except for during initialization)
858 void iwlagn_rx_allocate(struct iwl_priv *priv, gfp_t priority)
860 struct iwl_rx_queue *rxq = &priv->rxq;
861 struct list_head *element;
862 struct iwl_rx_mem_buffer *rxb;
865 gfp_t gfp_mask = priority;
868 spin_lock_irqsave(&rxq->lock, flags);
869 if (list_empty(&rxq->rx_used)) {
870 spin_unlock_irqrestore(&rxq->lock, flags);
873 spin_unlock_irqrestore(&rxq->lock, flags);
875 if (rxq->free_count > RX_LOW_WATERMARK)
876 gfp_mask |= __GFP_NOWARN;
878 if (priv->hw_params.rx_page_order > 0)
879 gfp_mask |= __GFP_COMP;
881 /* Alloc a new receive buffer */
882 page = alloc_pages(gfp_mask, priv->hw_params.rx_page_order);
885 IWL_DEBUG_INFO(priv, "alloc_pages failed, "
887 priv->hw_params.rx_page_order);
889 if ((rxq->free_count <= RX_LOW_WATERMARK) &&
891 IWL_CRIT(priv, "Failed to alloc_pages with %s. Only %u free buffers remaining.\n",
892 priority == GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL",
894 /* We don't reschedule replenish work here -- we will
895 * call the restock method and if it still needs
896 * more buffers it will schedule replenish */
900 spin_lock_irqsave(&rxq->lock, flags);
902 if (list_empty(&rxq->rx_used)) {
903 spin_unlock_irqrestore(&rxq->lock, flags);
904 __free_pages(page, priv->hw_params.rx_page_order);
907 element = rxq->rx_used.next;
908 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
911 spin_unlock_irqrestore(&rxq->lock, flags);
915 /* Get physical address of the RB */
916 rxb->page_dma = pci_map_page(priv->pci_dev, page, 0,
917 PAGE_SIZE << priv->hw_params.rx_page_order,
919 /* dma address must be no more than 36 bits */
920 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
921 /* and also 256 byte aligned! */
922 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
924 spin_lock_irqsave(&rxq->lock, flags);
926 list_add_tail(&rxb->list, &rxq->rx_free);
929 spin_unlock_irqrestore(&rxq->lock, flags);
933 void iwlagn_rx_replenish(struct iwl_priv *priv)
937 iwlagn_rx_allocate(priv, GFP_KERNEL);
939 spin_lock_irqsave(&priv->lock, flags);
940 iwlagn_rx_queue_restock(priv);
941 spin_unlock_irqrestore(&priv->lock, flags);
944 void iwlagn_rx_replenish_now(struct iwl_priv *priv)
946 iwlagn_rx_allocate(priv, GFP_ATOMIC);
948 iwlagn_rx_queue_restock(priv);
951 /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
952 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
953 * This free routine walks the list of POOL entries and if SKB is set to
954 * non NULL it is unmapped and freed
956 void iwlagn_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
959 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
960 if (rxq->pool[i].page != NULL) {
961 pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
962 PAGE_SIZE << priv->hw_params.rx_page_order,
964 __iwl_free_pages(priv, rxq->pool[i].page);
965 rxq->pool[i].page = NULL;
969 dma_free_coherent(&priv->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
971 dma_free_coherent(&priv->pci_dev->dev, sizeof(struct iwl_rb_status),
972 rxq->rb_stts, rxq->rb_stts_dma);
977 int iwlagn_rxq_stop(struct iwl_priv *priv)
981 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
982 iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
983 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
988 int iwlagn_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band)
993 /* HT rate format: mac80211 wants an MCS number, which is just LSB */
994 if (rate_n_flags & RATE_MCS_HT_MSK) {
995 idx = (rate_n_flags & 0xff);
997 /* Legacy rate format, search for match in table */
999 if (band == IEEE80211_BAND_5GHZ)
1000 band_offset = IWL_FIRST_OFDM_RATE;
1001 for (idx = band_offset; idx < IWL_RATE_COUNT_LEGACY; idx++)
1002 if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
1003 return idx - band_offset;
1009 static int iwl_get_single_channel_for_scan(struct iwl_priv *priv,
1010 struct ieee80211_vif *vif,
1011 enum ieee80211_band band,
1012 struct iwl_scan_channel *scan_ch)
1014 const struct ieee80211_supported_band *sband;
1015 u16 passive_dwell = 0;
1016 u16 active_dwell = 0;
1020 sband = iwl_get_hw_mode(priv, band);
1022 IWL_ERR(priv, "invalid band\n");
1026 active_dwell = iwl_get_active_dwell_time(priv, band, 0);
1027 passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
1029 if (passive_dwell <= active_dwell)
1030 passive_dwell = active_dwell + 1;
1032 channel = iwl_get_single_channel_number(priv, band);
1034 scan_ch->channel = cpu_to_le16(channel);
1035 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
1036 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1037 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1038 /* Set txpower levels to defaults */
1039 scan_ch->dsp_atten = 110;
1040 if (band == IEEE80211_BAND_5GHZ)
1041 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
1043 scan_ch->tx_gain = ((1 << 5) | (5 << 3));
1046 IWL_ERR(priv, "no valid channel found\n");
1050 static int iwl_get_channels_for_scan(struct iwl_priv *priv,
1051 struct ieee80211_vif *vif,
1052 enum ieee80211_band band,
1053 u8 is_active, u8 n_probes,
1054 struct iwl_scan_channel *scan_ch)
1056 struct ieee80211_channel *chan;
1057 const struct ieee80211_supported_band *sband;
1058 const struct iwl_channel_info *ch_info;
1059 u16 passive_dwell = 0;
1060 u16 active_dwell = 0;
1064 sband = iwl_get_hw_mode(priv, band);
1068 active_dwell = iwl_get_active_dwell_time(priv, band, n_probes);
1069 passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
1071 if (passive_dwell <= active_dwell)
1072 passive_dwell = active_dwell + 1;
1074 for (i = 0, added = 0; i < priv->scan_request->n_channels; i++) {
1075 chan = priv->scan_request->channels[i];
1077 if (chan->band != band)
1080 channel = chan->hw_value;
1081 scan_ch->channel = cpu_to_le16(channel);
1083 ch_info = iwl_get_channel_info(priv, band, channel);
1084 if (!is_channel_valid(ch_info)) {
1085 IWL_DEBUG_SCAN(priv, "Channel %d is INVALID for this band.\n",
1090 if (!is_active || is_channel_passive(ch_info) ||
1091 (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN))
1092 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
1094 scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
1097 scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
1099 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1100 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1102 /* Set txpower levels to defaults */
1103 scan_ch->dsp_atten = 110;
1105 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
1107 * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3;
1109 if (band == IEEE80211_BAND_5GHZ)
1110 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
1112 scan_ch->tx_gain = ((1 << 5) | (5 << 3));
1114 IWL_DEBUG_SCAN(priv, "Scanning ch=%d prob=0x%X [%s %d]\n",
1115 channel, le32_to_cpu(scan_ch->type),
1116 (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
1117 "ACTIVE" : "PASSIVE",
1118 (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
1119 active_dwell : passive_dwell);
1125 IWL_DEBUG_SCAN(priv, "total channels to scan %d\n", added);
1129 static int iwl_fill_offch_tx(struct iwl_priv *priv, void *data, size_t maxlen)
1131 struct sk_buff *skb = priv->_agn.offchan_tx_skb;
1133 if (skb->len < maxlen)
1136 memcpy(data, skb->data, maxlen);
1141 int iwlagn_request_scan(struct iwl_priv *priv, struct ieee80211_vif *vif)
1143 struct iwl_host_cmd cmd = {
1144 .id = REPLY_SCAN_CMD,
1145 .len = sizeof(struct iwl_scan_cmd),
1146 .flags = CMD_SIZE_HUGE,
1148 struct iwl_scan_cmd *scan;
1149 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
1153 enum ieee80211_band band;
1155 u8 rx_ant = priv->hw_params.valid_rx_ant;
1157 bool is_active = false;
1160 u8 scan_tx_antennas = priv->hw_params.valid_tx_ant;
1163 lockdep_assert_held(&priv->mutex);
1166 ctx = iwl_rxon_ctx_from_vif(vif);
1168 if (!priv->scan_cmd) {
1169 priv->scan_cmd = kmalloc(sizeof(struct iwl_scan_cmd) +
1170 IWL_MAX_SCAN_SIZE, GFP_KERNEL);
1171 if (!priv->scan_cmd) {
1172 IWL_DEBUG_SCAN(priv,
1173 "fail to allocate memory for scan\n");
1177 scan = priv->scan_cmd;
1178 memset(scan, 0, sizeof(struct iwl_scan_cmd) + IWL_MAX_SCAN_SIZE);
1180 scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
1181 scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
1183 if (priv->scan_type != IWL_SCAN_OFFCH_TX &&
1184 iwl_is_any_associated(priv)) {
1187 u32 suspend_time = 100;
1188 u32 scan_suspend_time = 100;
1190 IWL_DEBUG_INFO(priv, "Scanning while associated...\n");
1191 switch (priv->scan_type) {
1192 case IWL_SCAN_OFFCH_TX:
1195 case IWL_SCAN_RADIO_RESET:
1198 case IWL_SCAN_NORMAL:
1199 interval = vif->bss_conf.beacon_int;
1203 scan->suspend_time = 0;
1204 scan->max_out_time = cpu_to_le32(200 * 1024);
1206 interval = suspend_time;
1208 extra = (suspend_time / interval) << 22;
1209 scan_suspend_time = (extra |
1210 ((suspend_time % interval) * 1024));
1211 scan->suspend_time = cpu_to_le32(scan_suspend_time);
1212 IWL_DEBUG_SCAN(priv, "suspend_time 0x%X beacon interval %d\n",
1213 scan_suspend_time, interval);
1214 } else if (priv->scan_type == IWL_SCAN_OFFCH_TX) {
1215 scan->suspend_time = 0;
1216 scan->max_out_time =
1217 cpu_to_le32(1024 * priv->_agn.offchan_tx_timeout);
1220 switch (priv->scan_type) {
1221 case IWL_SCAN_RADIO_RESET:
1222 IWL_DEBUG_SCAN(priv, "Start internal passive scan.\n");
1224 case IWL_SCAN_NORMAL:
1225 if (priv->scan_request->n_ssids) {
1227 IWL_DEBUG_SCAN(priv, "Kicking off active scan\n");
1228 for (i = 0; i < priv->scan_request->n_ssids; i++) {
1229 /* always does wildcard anyway */
1230 if (!priv->scan_request->ssids[i].ssid_len)
1232 scan->direct_scan[p].id = WLAN_EID_SSID;
1233 scan->direct_scan[p].len =
1234 priv->scan_request->ssids[i].ssid_len;
1235 memcpy(scan->direct_scan[p].ssid,
1236 priv->scan_request->ssids[i].ssid,
1237 priv->scan_request->ssids[i].ssid_len);
1243 IWL_DEBUG_SCAN(priv, "Start passive scan.\n");
1245 case IWL_SCAN_OFFCH_TX:
1246 IWL_DEBUG_SCAN(priv, "Start offchannel TX scan.\n");
1250 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
1251 scan->tx_cmd.sta_id = ctx->bcast_sta_id;
1252 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
1254 switch (priv->scan_band) {
1255 case IEEE80211_BAND_2GHZ:
1256 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
1257 chan_mod = le32_to_cpu(
1258 priv->contexts[IWL_RXON_CTX_BSS].active.flags &
1259 RXON_FLG_CHANNEL_MODE_MSK)
1260 >> RXON_FLG_CHANNEL_MODE_POS;
1261 if (chan_mod == CHANNEL_MODE_PURE_40) {
1262 rate = IWL_RATE_6M_PLCP;
1264 rate = IWL_RATE_1M_PLCP;
1265 rate_flags = RATE_MCS_CCK_MSK;
1268 * Internal scans are passive, so we can indiscriminately set
1269 * the BT ignore flag on 2.4 GHz since it applies to TX only.
1271 if (priv->cfg->bt_params &&
1272 priv->cfg->bt_params->advanced_bt_coexist)
1273 scan->tx_cmd.tx_flags |= TX_CMD_FLG_IGNORE_BT;
1275 case IEEE80211_BAND_5GHZ:
1276 rate = IWL_RATE_6M_PLCP;
1279 IWL_WARN(priv, "Invalid scan band\n");
1284 * If active scanning is requested but a certain channel is
1285 * marked passive, we can do active scanning if we detect
1288 * There is an issue with some firmware versions that triggers
1289 * a sysassert on a "good CRC threshold" of zero (== disabled),
1290 * on a radar channel even though this means that we should NOT
1293 * The "good CRC threshold" is the number of frames that we
1294 * need to receive during our dwell time on a channel before
1295 * sending out probes -- setting this to a huge value will
1296 * mean we never reach it, but at the same time work around
1297 * the aforementioned issue. Thus use IWL_GOOD_CRC_TH_NEVER
1298 * here instead of IWL_GOOD_CRC_TH_DISABLED.
1300 scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH_DEFAULT :
1301 IWL_GOOD_CRC_TH_NEVER;
1303 band = priv->scan_band;
1305 if (priv->cfg->scan_rx_antennas[band])
1306 rx_ant = priv->cfg->scan_rx_antennas[band];
1308 if (band == IEEE80211_BAND_2GHZ &&
1309 priv->cfg->bt_params &&
1310 priv->cfg->bt_params->advanced_bt_coexist) {
1311 /* transmit 2.4 GHz probes only on first antenna */
1312 scan_tx_antennas = first_antenna(scan_tx_antennas);
1315 priv->scan_tx_ant[band] = iwl_toggle_tx_ant(priv, priv->scan_tx_ant[band],
1317 rate_flags |= iwl_ant_idx_to_flags(priv->scan_tx_ant[band]);
1318 scan->tx_cmd.rate_n_flags = iwl_hw_set_rate_n_flags(rate, rate_flags);
1320 /* In power save mode use one chain, otherwise use all chains */
1321 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
1322 /* rx_ant has been set to all valid chains previously */
1323 active_chains = rx_ant &
1324 ((u8)(priv->chain_noise_data.active_chains));
1326 active_chains = rx_ant;
1328 IWL_DEBUG_SCAN(priv, "chain_noise_data.active_chains: %u\n",
1329 priv->chain_noise_data.active_chains);
1331 rx_ant = first_antenna(active_chains);
1333 if (priv->cfg->bt_params &&
1334 priv->cfg->bt_params->advanced_bt_coexist &&
1335 priv->bt_full_concurrent) {
1336 /* operated as 1x1 in full concurrency mode */
1337 rx_ant = first_antenna(rx_ant);
1340 /* MIMO is not used here, but value is required */
1341 rx_chain |= priv->hw_params.valid_rx_ant << RXON_RX_CHAIN_VALID_POS;
1342 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
1343 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_SEL_POS;
1344 rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
1345 scan->rx_chain = cpu_to_le16(rx_chain);
1346 switch (priv->scan_type) {
1347 case IWL_SCAN_NORMAL:
1348 cmd_len = iwl_fill_probe_req(priv,
1349 (struct ieee80211_mgmt *)scan->data,
1351 priv->scan_request->ie,
1352 priv->scan_request->ie_len,
1353 IWL_MAX_SCAN_SIZE - sizeof(*scan));
1355 case IWL_SCAN_RADIO_RESET:
1356 /* use bcast addr, will not be transmitted but must be valid */
1357 cmd_len = iwl_fill_probe_req(priv,
1358 (struct ieee80211_mgmt *)scan->data,
1359 iwl_bcast_addr, NULL, 0,
1360 IWL_MAX_SCAN_SIZE - sizeof(*scan));
1362 case IWL_SCAN_OFFCH_TX:
1363 cmd_len = iwl_fill_offch_tx(priv, scan->data,
1366 - sizeof(struct iwl_scan_channel));
1367 scan->scan_flags |= IWL_SCAN_FLAGS_ACTION_FRAME_TX;
1372 scan->tx_cmd.len = cpu_to_le16(cmd_len);
1374 scan->filter_flags |= (RXON_FILTER_ACCEPT_GRP_MSK |
1375 RXON_FILTER_BCON_AWARE_MSK);
1377 switch (priv->scan_type) {
1378 case IWL_SCAN_RADIO_RESET:
1379 scan->channel_count =
1380 iwl_get_single_channel_for_scan(priv, vif, band,
1381 (void *)&scan->data[cmd_len]);
1383 case IWL_SCAN_NORMAL:
1384 scan->channel_count =
1385 iwl_get_channels_for_scan(priv, vif, band,
1386 is_active, n_probes,
1387 (void *)&scan->data[cmd_len]);
1389 case IWL_SCAN_OFFCH_TX: {
1390 struct iwl_scan_channel *scan_ch;
1392 scan->channel_count = 1;
1394 scan_ch = (void *)&scan->data[cmd_len];
1395 scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
1397 cpu_to_le16(priv->_agn.offchan_tx_chan->hw_value);
1398 scan_ch->active_dwell =
1399 cpu_to_le16(priv->_agn.offchan_tx_timeout);
1400 scan_ch->passive_dwell = 0;
1402 /* Set txpower levels to defaults */
1403 scan_ch->dsp_atten = 110;
1405 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
1407 * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3;
1409 if (priv->_agn.offchan_tx_chan->band == IEEE80211_BAND_5GHZ)
1410 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
1412 scan_ch->tx_gain = ((1 << 5) | (5 << 3));
1417 if (scan->channel_count == 0) {
1418 IWL_DEBUG_SCAN(priv, "channel count %d\n", scan->channel_count);
1422 cmd.len += le16_to_cpu(scan->tx_cmd.len) +
1423 scan->channel_count * sizeof(struct iwl_scan_channel);
1425 scan->len = cpu_to_le16(cmd.len);
1427 /* set scan bit here for PAN params */
1428 set_bit(STATUS_SCAN_HW, &priv->status);
1430 if (priv->cfg->ops->hcmd->set_pan_params) {
1431 ret = priv->cfg->ops->hcmd->set_pan_params(priv);
1436 ret = iwl_send_cmd_sync(priv, &cmd);
1438 clear_bit(STATUS_SCAN_HW, &priv->status);
1439 if (priv->cfg->ops->hcmd->set_pan_params)
1440 priv->cfg->ops->hcmd->set_pan_params(priv);
1446 int iwlagn_manage_ibss_station(struct iwl_priv *priv,
1447 struct ieee80211_vif *vif, bool add)
1449 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
1452 return iwlagn_add_bssid_station(priv, vif_priv->ctx,
1453 vif->bss_conf.bssid,
1454 &vif_priv->ibss_bssid_sta_id);
1455 return iwl_remove_station(priv, vif_priv->ibss_bssid_sta_id,
1456 vif->bss_conf.bssid);
1459 void iwl_free_tfds_in_queue(struct iwl_priv *priv,
1460 int sta_id, int tid, int freed)
1462 lockdep_assert_held(&priv->sta_lock);
1464 if (priv->stations[sta_id].tid[tid].tfds_in_queue >= freed)
1465 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1467 IWL_DEBUG_TX(priv, "free more than tfds_in_queue (%u:%d)\n",
1468 priv->stations[sta_id].tid[tid].tfds_in_queue,
1470 priv->stations[sta_id].tid[tid].tfds_in_queue = 0;
1474 #define IWL_FLUSH_WAIT_MS 2000
1476 int iwlagn_wait_tx_queue_empty(struct iwl_priv *priv)
1478 struct iwl_tx_queue *txq;
1479 struct iwl_queue *q;
1481 unsigned long now = jiffies;
1484 /* waiting for all the tx frames complete might take a while */
1485 for (cnt = 0; cnt < priv->hw_params.max_txq_num; cnt++) {
1486 if (cnt == priv->cmd_queue)
1488 txq = &priv->txq[cnt];
1490 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1491 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1494 if (q->read_ptr != q->write_ptr) {
1495 IWL_ERR(priv, "fail to flush all tx fifo queues\n");
1503 #define IWL_TX_QUEUE_MSK 0xfffff
1506 * iwlagn_txfifo_flush: send REPLY_TXFIFO_FLUSH command to uCode
1509 * 1. acquire mutex before calling
1510 * 2. make sure rf is on and not in exit state
1512 int iwlagn_txfifo_flush(struct iwl_priv *priv, u16 flush_control)
1514 struct iwl_txfifo_flush_cmd flush_cmd;
1515 struct iwl_host_cmd cmd = {
1516 .id = REPLY_TXFIFO_FLUSH,
1517 .len = sizeof(struct iwl_txfifo_flush_cmd),
1524 memset(&flush_cmd, 0, sizeof(flush_cmd));
1525 flush_cmd.fifo_control = IWL_TX_FIFO_VO_MSK | IWL_TX_FIFO_VI_MSK |
1526 IWL_TX_FIFO_BE_MSK | IWL_TX_FIFO_BK_MSK;
1527 if (priv->cfg->sku & IWL_SKU_N)
1528 flush_cmd.fifo_control |= IWL_AGG_TX_QUEUE_MSK;
1530 IWL_DEBUG_INFO(priv, "fifo queue control: 0X%x\n",
1531 flush_cmd.fifo_control);
1532 flush_cmd.flush_control = cpu_to_le16(flush_control);
1534 return iwl_send_cmd(priv, &cmd);
1537 void iwlagn_dev_txfifo_flush(struct iwl_priv *priv, u16 flush_control)
1539 mutex_lock(&priv->mutex);
1540 ieee80211_stop_queues(priv->hw);
1541 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
1542 IWL_ERR(priv, "flush request fail\n");
1545 IWL_DEBUG_INFO(priv, "wait transmit/flush all frames\n");
1546 iwlagn_wait_tx_queue_empty(priv);
1548 ieee80211_wake_queues(priv->hw);
1549 mutex_unlock(&priv->mutex);
1556 * Macros to access the lookup table.
1558 * The lookup table has 7 inputs: bt3_prio, bt3_txrx, bt_rf_act, wifi_req,
1559 * wifi_prio, wifi_txrx and wifi_sh_ant_req.
1561 * It has three outputs: WLAN_ACTIVE, WLAN_KILL and ANT_SWITCH
1563 * The format is that "registers" 8 through 11 contain the WLAN_ACTIVE bits
1564 * one after another in 32-bit registers, and "registers" 0 through 7 contain
1565 * the WLAN_KILL and ANT_SWITCH bits interleaved (in that order).
1567 * These macros encode that format.
1569 #define LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, wifi_req, wifi_prio, \
1570 wifi_txrx, wifi_sh_ant_req) \
1571 (bt3_prio | (bt3_txrx << 1) | (bt_rf_act << 2) | (wifi_req << 3) | \
1572 (wifi_prio << 4) | (wifi_txrx << 5) | (wifi_sh_ant_req << 6))
1574 #define LUT_PTA_WLAN_ACTIVE_OP(lut, op, val) \
1575 lut[8 + ((val) >> 5)] op (cpu_to_le32(BIT((val) & 0x1f)))
1576 #define LUT_TEST_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1577 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1578 (!!(LUT_PTA_WLAN_ACTIVE_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, \
1579 bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1581 #define LUT_SET_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1582 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1583 LUT_PTA_WLAN_ACTIVE_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, \
1584 bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1586 #define LUT_CLEAR_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, \
1587 wifi_req, wifi_prio, wifi_txrx, \
1589 LUT_PTA_WLAN_ACTIVE_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, \
1590 bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1593 #define LUT_WLAN_KILL_OP(lut, op, val) \
1594 lut[(val) >> 4] op (cpu_to_le32(BIT(((val) << 1) & 0x1e)))
1595 #define LUT_TEST_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1596 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1597 (!!(LUT_WLAN_KILL_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1598 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))))
1599 #define LUT_SET_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1600 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1601 LUT_WLAN_KILL_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1602 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1603 #define LUT_CLEAR_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1604 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1605 LUT_WLAN_KILL_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1606 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1608 #define LUT_ANT_SWITCH_OP(lut, op, val) \
1609 lut[(val) >> 4] op (cpu_to_le32(BIT((((val) << 1) & 0x1e) + 1)))
1610 #define LUT_TEST_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1611 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1612 (!!(LUT_ANT_SWITCH_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1613 wifi_req, wifi_prio, wifi_txrx, \
1615 #define LUT_SET_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1616 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1617 LUT_ANT_SWITCH_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1618 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1619 #define LUT_CLEAR_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1620 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1621 LUT_ANT_SWITCH_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1622 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1624 static const __le32 iwlagn_def_3w_lookup[12] = {
1625 cpu_to_le32(0xaaaaaaaa),
1626 cpu_to_le32(0xaaaaaaaa),
1627 cpu_to_le32(0xaeaaaaaa),
1628 cpu_to_le32(0xaaaaaaaa),
1629 cpu_to_le32(0xcc00ff28),
1630 cpu_to_le32(0x0000aaaa),
1631 cpu_to_le32(0xcc00aaaa),
1632 cpu_to_le32(0x0000aaaa),
1633 cpu_to_le32(0xc0004000),
1634 cpu_to_le32(0x00004000),
1635 cpu_to_le32(0xf0005000),
1636 cpu_to_le32(0xf0005000),
1639 static const __le32 iwlagn_concurrent_lookup[12] = {
1640 cpu_to_le32(0xaaaaaaaa),
1641 cpu_to_le32(0xaaaaaaaa),
1642 cpu_to_le32(0xaaaaaaaa),
1643 cpu_to_le32(0xaaaaaaaa),
1644 cpu_to_le32(0xaaaaaaaa),
1645 cpu_to_le32(0xaaaaaaaa),
1646 cpu_to_le32(0xaaaaaaaa),
1647 cpu_to_le32(0xaaaaaaaa),
1648 cpu_to_le32(0x00000000),
1649 cpu_to_le32(0x00000000),
1650 cpu_to_le32(0x00000000),
1651 cpu_to_le32(0x00000000),
1654 void iwlagn_send_advance_bt_config(struct iwl_priv *priv)
1656 struct iwl_basic_bt_cmd basic = {
1657 .max_kill = IWLAGN_BT_MAX_KILL_DEFAULT,
1658 .bt3_timer_t7_value = IWLAGN_BT3_T7_DEFAULT,
1659 .bt3_prio_sample_time = IWLAGN_BT3_PRIO_SAMPLE_DEFAULT,
1660 .bt3_timer_t2_value = IWLAGN_BT3_T2_DEFAULT,
1662 struct iwl6000_bt_cmd bt_cmd_6000;
1663 struct iwl2000_bt_cmd bt_cmd_2000;
1666 BUILD_BUG_ON(sizeof(iwlagn_def_3w_lookup) !=
1667 sizeof(basic.bt3_lookup_table));
1669 if (priv->cfg->bt_params) {
1670 if (priv->cfg->bt_params->bt_session_2) {
1671 bt_cmd_2000.prio_boost = cpu_to_le32(
1672 priv->cfg->bt_params->bt_prio_boost);
1673 bt_cmd_2000.tx_prio_boost = 0;
1674 bt_cmd_2000.rx_prio_boost = 0;
1676 bt_cmd_6000.prio_boost =
1677 priv->cfg->bt_params->bt_prio_boost;
1678 bt_cmd_6000.tx_prio_boost = 0;
1679 bt_cmd_6000.rx_prio_boost = 0;
1682 IWL_ERR(priv, "failed to construct BT Coex Config\n");
1686 basic.kill_ack_mask = priv->kill_ack_mask;
1687 basic.kill_cts_mask = priv->kill_cts_mask;
1688 basic.valid = priv->bt_valid;
1691 * Configure BT coex mode to "no coexistence" when the
1692 * user disabled BT coexistence, we have no interface
1693 * (might be in monitor mode), or the interface is in
1694 * IBSS mode (no proper uCode support for coex then).
1696 if (!bt_coex_active || priv->iw_mode == NL80211_IFTYPE_ADHOC) {
1697 basic.flags = IWLAGN_BT_FLAG_COEX_MODE_DISABLED;
1699 basic.flags = IWLAGN_BT_FLAG_COEX_MODE_3W <<
1700 IWLAGN_BT_FLAG_COEX_MODE_SHIFT;
1701 if (priv->cfg->bt_params &&
1702 priv->cfg->bt_params->bt_sco_disable)
1703 basic.flags |= IWLAGN_BT_FLAG_SYNC_2_BT_DISABLE;
1705 if (priv->bt_ch_announce)
1706 basic.flags |= IWLAGN_BT_FLAG_CHANNEL_INHIBITION;
1707 IWL_DEBUG_INFO(priv, "BT coex flag: 0X%x\n", basic.flags);
1709 priv->bt_enable_flag = basic.flags;
1710 if (priv->bt_full_concurrent)
1711 memcpy(basic.bt3_lookup_table, iwlagn_concurrent_lookup,
1712 sizeof(iwlagn_concurrent_lookup));
1714 memcpy(basic.bt3_lookup_table, iwlagn_def_3w_lookup,
1715 sizeof(iwlagn_def_3w_lookup));
1717 IWL_DEBUG_INFO(priv, "BT coex %s in %s mode\n",
1718 basic.flags ? "active" : "disabled",
1719 priv->bt_full_concurrent ?
1720 "full concurrency" : "3-wire");
1722 if (priv->cfg->bt_params->bt_session_2) {
1723 memcpy(&bt_cmd_2000.basic, &basic,
1725 ret = iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG,
1726 sizeof(bt_cmd_2000), &bt_cmd_2000);
1728 memcpy(&bt_cmd_6000.basic, &basic,
1730 ret = iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG,
1731 sizeof(bt_cmd_6000), &bt_cmd_6000);
1734 IWL_ERR(priv, "failed to send BT Coex Config\n");
1738 static void iwlagn_bt_traffic_change_work(struct work_struct *work)
1740 struct iwl_priv *priv =
1741 container_of(work, struct iwl_priv, bt_traffic_change_work);
1742 struct iwl_rxon_context *ctx;
1743 int smps_request = -1;
1745 if (priv->bt_enable_flag == IWLAGN_BT_FLAG_COEX_MODE_DISABLED) {
1746 /* bt coex disabled */
1751 * Note: bt_traffic_load can be overridden by scan complete and
1752 * coex profile notifications. Ignore that since only bad consequence
1753 * can be not matching debug print with actual state.
1755 IWL_DEBUG_INFO(priv, "BT traffic load changes: %d\n",
1756 priv->bt_traffic_load);
1758 switch (priv->bt_traffic_load) {
1759 case IWL_BT_COEX_TRAFFIC_LOAD_NONE:
1760 if (priv->bt_status)
1761 smps_request = IEEE80211_SMPS_DYNAMIC;
1763 smps_request = IEEE80211_SMPS_AUTOMATIC;
1765 case IWL_BT_COEX_TRAFFIC_LOAD_LOW:
1766 smps_request = IEEE80211_SMPS_DYNAMIC;
1768 case IWL_BT_COEX_TRAFFIC_LOAD_HIGH:
1769 case IWL_BT_COEX_TRAFFIC_LOAD_CONTINUOUS:
1770 smps_request = IEEE80211_SMPS_STATIC;
1773 IWL_ERR(priv, "Invalid BT traffic load: %d\n",
1774 priv->bt_traffic_load);
1778 mutex_lock(&priv->mutex);
1781 * We can not send command to firmware while scanning. When the scan
1782 * complete we will schedule this work again. We do check with mutex
1783 * locked to prevent new scan request to arrive. We do not check
1784 * STATUS_SCANNING to avoid race when queue_work two times from
1785 * different notifications, but quit and not perform any work at all.
1787 if (test_bit(STATUS_SCAN_HW, &priv->status))
1790 if (priv->cfg->ops->lib->update_chain_flags)
1791 priv->cfg->ops->lib->update_chain_flags(priv);
1793 if (smps_request != -1) {
1794 for_each_context(priv, ctx) {
1795 if (ctx->vif && ctx->vif->type == NL80211_IFTYPE_STATION)
1796 ieee80211_request_smps(ctx->vif, smps_request);
1800 mutex_unlock(&priv->mutex);
1803 static void iwlagn_print_uartmsg(struct iwl_priv *priv,
1804 struct iwl_bt_uart_msg *uart_msg)
1806 IWL_DEBUG_NOTIF(priv, "Message Type = 0x%X, SSN = 0x%X, "
1807 "Update Req = 0x%X",
1808 (BT_UART_MSG_FRAME1MSGTYPE_MSK & uart_msg->frame1) >>
1809 BT_UART_MSG_FRAME1MSGTYPE_POS,
1810 (BT_UART_MSG_FRAME1SSN_MSK & uart_msg->frame1) >>
1811 BT_UART_MSG_FRAME1SSN_POS,
1812 (BT_UART_MSG_FRAME1UPDATEREQ_MSK & uart_msg->frame1) >>
1813 BT_UART_MSG_FRAME1UPDATEREQ_POS);
1815 IWL_DEBUG_NOTIF(priv, "Open connections = 0x%X, Traffic load = 0x%X, "
1816 "Chl_SeqN = 0x%X, In band = 0x%X",
1817 (BT_UART_MSG_FRAME2OPENCONNECTIONS_MSK & uart_msg->frame2) >>
1818 BT_UART_MSG_FRAME2OPENCONNECTIONS_POS,
1819 (BT_UART_MSG_FRAME2TRAFFICLOAD_MSK & uart_msg->frame2) >>
1820 BT_UART_MSG_FRAME2TRAFFICLOAD_POS,
1821 (BT_UART_MSG_FRAME2CHLSEQN_MSK & uart_msg->frame2) >>
1822 BT_UART_MSG_FRAME2CHLSEQN_POS,
1823 (BT_UART_MSG_FRAME2INBAND_MSK & uart_msg->frame2) >>
1824 BT_UART_MSG_FRAME2INBAND_POS);
1826 IWL_DEBUG_NOTIF(priv, "SCO/eSCO = 0x%X, Sniff = 0x%X, A2DP = 0x%X, "
1827 "ACL = 0x%X, Master = 0x%X, OBEX = 0x%X",
1828 (BT_UART_MSG_FRAME3SCOESCO_MSK & uart_msg->frame3) >>
1829 BT_UART_MSG_FRAME3SCOESCO_POS,
1830 (BT_UART_MSG_FRAME3SNIFF_MSK & uart_msg->frame3) >>
1831 BT_UART_MSG_FRAME3SNIFF_POS,
1832 (BT_UART_MSG_FRAME3A2DP_MSK & uart_msg->frame3) >>
1833 BT_UART_MSG_FRAME3A2DP_POS,
1834 (BT_UART_MSG_FRAME3ACL_MSK & uart_msg->frame3) >>
1835 BT_UART_MSG_FRAME3ACL_POS,
1836 (BT_UART_MSG_FRAME3MASTER_MSK & uart_msg->frame3) >>
1837 BT_UART_MSG_FRAME3MASTER_POS,
1838 (BT_UART_MSG_FRAME3OBEX_MSK & uart_msg->frame3) >>
1839 BT_UART_MSG_FRAME3OBEX_POS);
1841 IWL_DEBUG_NOTIF(priv, "Idle duration = 0x%X",
1842 (BT_UART_MSG_FRAME4IDLEDURATION_MSK & uart_msg->frame4) >>
1843 BT_UART_MSG_FRAME4IDLEDURATION_POS);
1845 IWL_DEBUG_NOTIF(priv, "Tx Activity = 0x%X, Rx Activity = 0x%X, "
1846 "eSCO Retransmissions = 0x%X",
1847 (BT_UART_MSG_FRAME5TXACTIVITY_MSK & uart_msg->frame5) >>
1848 BT_UART_MSG_FRAME5TXACTIVITY_POS,
1849 (BT_UART_MSG_FRAME5RXACTIVITY_MSK & uart_msg->frame5) >>
1850 BT_UART_MSG_FRAME5RXACTIVITY_POS,
1851 (BT_UART_MSG_FRAME5ESCORETRANSMIT_MSK & uart_msg->frame5) >>
1852 BT_UART_MSG_FRAME5ESCORETRANSMIT_POS);
1854 IWL_DEBUG_NOTIF(priv, "Sniff Interval = 0x%X, Discoverable = 0x%X",
1855 (BT_UART_MSG_FRAME6SNIFFINTERVAL_MSK & uart_msg->frame6) >>
1856 BT_UART_MSG_FRAME6SNIFFINTERVAL_POS,
1857 (BT_UART_MSG_FRAME6DISCOVERABLE_MSK & uart_msg->frame6) >>
1858 BT_UART_MSG_FRAME6DISCOVERABLE_POS);
1860 IWL_DEBUG_NOTIF(priv, "Sniff Activity = 0x%X, Page = "
1861 "0x%X, Inquiry = 0x%X, Connectable = 0x%X",
1862 (BT_UART_MSG_FRAME7SNIFFACTIVITY_MSK & uart_msg->frame7) >>
1863 BT_UART_MSG_FRAME7SNIFFACTIVITY_POS,
1864 (BT_UART_MSG_FRAME7PAGE_MSK & uart_msg->frame7) >>
1865 BT_UART_MSG_FRAME7PAGE_POS,
1866 (BT_UART_MSG_FRAME7INQUIRY_MSK & uart_msg->frame7) >>
1867 BT_UART_MSG_FRAME7INQUIRY_POS,
1868 (BT_UART_MSG_FRAME7CONNECTABLE_MSK & uart_msg->frame7) >>
1869 BT_UART_MSG_FRAME7CONNECTABLE_POS);
1872 static void iwlagn_set_kill_msk(struct iwl_priv *priv,
1873 struct iwl_bt_uart_msg *uart_msg)
1876 static const __le32 bt_kill_ack_msg[2] = {
1877 IWLAGN_BT_KILL_ACK_MASK_DEFAULT,
1878 IWLAGN_BT_KILL_ACK_CTS_MASK_SCO };
1879 static const __le32 bt_kill_cts_msg[2] = {
1880 IWLAGN_BT_KILL_CTS_MASK_DEFAULT,
1881 IWLAGN_BT_KILL_ACK_CTS_MASK_SCO };
1883 kill_msk = (BT_UART_MSG_FRAME3SCOESCO_MSK & uart_msg->frame3)
1885 if (priv->kill_ack_mask != bt_kill_ack_msg[kill_msk] ||
1886 priv->kill_cts_mask != bt_kill_cts_msg[kill_msk]) {
1887 priv->bt_valid |= IWLAGN_BT_VALID_KILL_ACK_MASK;
1888 priv->kill_ack_mask = bt_kill_ack_msg[kill_msk];
1889 priv->bt_valid |= IWLAGN_BT_VALID_KILL_CTS_MASK;
1890 priv->kill_cts_mask = bt_kill_cts_msg[kill_msk];
1892 /* schedule to send runtime bt_config */
1893 queue_work(priv->workqueue, &priv->bt_runtime_config);
1897 void iwlagn_bt_coex_profile_notif(struct iwl_priv *priv,
1898 struct iwl_rx_mem_buffer *rxb)
1900 unsigned long flags;
1901 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1902 struct iwl_bt_coex_profile_notif *coex = &pkt->u.bt_coex_profile_notif;
1903 struct iwl_bt_uart_msg *uart_msg = &coex->last_bt_uart_msg;
1905 if (priv->bt_enable_flag == IWLAGN_BT_FLAG_COEX_MODE_DISABLED) {
1906 /* bt coex disabled */
1910 IWL_DEBUG_NOTIF(priv, "BT Coex notification:\n");
1911 IWL_DEBUG_NOTIF(priv, " status: %d\n", coex->bt_status);
1912 IWL_DEBUG_NOTIF(priv, " traffic load: %d\n", coex->bt_traffic_load);
1913 IWL_DEBUG_NOTIF(priv, " CI compliance: %d\n",
1914 coex->bt_ci_compliance);
1915 iwlagn_print_uartmsg(priv, uart_msg);
1917 priv->last_bt_traffic_load = priv->bt_traffic_load;
1918 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
1919 if (priv->bt_status != coex->bt_status ||
1920 priv->last_bt_traffic_load != coex->bt_traffic_load) {
1921 if (coex->bt_status) {
1923 if (!priv->bt_ch_announce)
1924 priv->bt_traffic_load =
1925 IWL_BT_COEX_TRAFFIC_LOAD_HIGH;
1927 priv->bt_traffic_load =
1928 coex->bt_traffic_load;
1931 priv->bt_traffic_load =
1932 IWL_BT_COEX_TRAFFIC_LOAD_NONE;
1934 priv->bt_status = coex->bt_status;
1935 queue_work(priv->workqueue,
1936 &priv->bt_traffic_change_work);
1940 iwlagn_set_kill_msk(priv, uart_msg);
1942 /* FIXME: based on notification, adjust the prio_boost */
1944 spin_lock_irqsave(&priv->lock, flags);
1945 priv->bt_ci_compliance = coex->bt_ci_compliance;
1946 spin_unlock_irqrestore(&priv->lock, flags);
1949 void iwlagn_bt_rx_handler_setup(struct iwl_priv *priv)
1951 iwlagn_rx_handler_setup(priv);
1952 priv->rx_handlers[REPLY_BT_COEX_PROFILE_NOTIF] =
1953 iwlagn_bt_coex_profile_notif;
1956 void iwlagn_bt_setup_deferred_work(struct iwl_priv *priv)
1958 iwlagn_setup_deferred_work(priv);
1960 INIT_WORK(&priv->bt_traffic_change_work,
1961 iwlagn_bt_traffic_change_work);
1964 void iwlagn_bt_cancel_deferred_work(struct iwl_priv *priv)
1966 cancel_work_sync(&priv->bt_traffic_change_work);
1969 static bool is_single_rx_stream(struct iwl_priv *priv)
1971 return priv->current_ht_config.smps == IEEE80211_SMPS_STATIC ||
1972 priv->current_ht_config.single_chain_sufficient;
1975 #define IWL_NUM_RX_CHAINS_MULTIPLE 3
1976 #define IWL_NUM_RX_CHAINS_SINGLE 2
1977 #define IWL_NUM_IDLE_CHAINS_DUAL 2
1978 #define IWL_NUM_IDLE_CHAINS_SINGLE 1
1981 * Determine how many receiver/antenna chains to use.
1983 * More provides better reception via diversity. Fewer saves power
1984 * at the expense of throughput, but only when not in powersave to
1987 * MIMO (dual stream) requires at least 2, but works better with 3.
1988 * This does not determine *which* chains to use, just how many.
1990 static int iwl_get_active_rx_chain_count(struct iwl_priv *priv)
1992 if (priv->cfg->bt_params &&
1993 priv->cfg->bt_params->advanced_bt_coexist &&
1994 (priv->bt_full_concurrent ||
1995 priv->bt_traffic_load >= IWL_BT_COEX_TRAFFIC_LOAD_HIGH)) {
1997 * only use chain 'A' in bt high traffic load or
1998 * full concurrency mode
2000 return IWL_NUM_RX_CHAINS_SINGLE;
2002 /* # of Rx chains to use when expecting MIMO. */
2003 if (is_single_rx_stream(priv))
2004 return IWL_NUM_RX_CHAINS_SINGLE;
2006 return IWL_NUM_RX_CHAINS_MULTIPLE;
2010 * When we are in power saving mode, unless device support spatial
2011 * multiplexing power save, use the active count for rx chain count.
2013 static int iwl_get_idle_rx_chain_count(struct iwl_priv *priv, int active_cnt)
2015 /* # Rx chains when idling, depending on SMPS mode */
2016 switch (priv->current_ht_config.smps) {
2017 case IEEE80211_SMPS_STATIC:
2018 case IEEE80211_SMPS_DYNAMIC:
2019 return IWL_NUM_IDLE_CHAINS_SINGLE;
2020 case IEEE80211_SMPS_OFF:
2023 WARN(1, "invalid SMPS mode %d",
2024 priv->current_ht_config.smps);
2029 /* up to 4 chains */
2030 static u8 iwl_count_chain_bitmap(u32 chain_bitmap)
2033 res = (chain_bitmap & BIT(0)) >> 0;
2034 res += (chain_bitmap & BIT(1)) >> 1;
2035 res += (chain_bitmap & BIT(2)) >> 2;
2036 res += (chain_bitmap & BIT(3)) >> 3;
2041 * iwlagn_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
2043 * Selects how many and which Rx receivers/antennas/chains to use.
2044 * This should not be used for scan command ... it puts data in wrong place.
2046 void iwlagn_set_rxon_chain(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
2048 bool is_single = is_single_rx_stream(priv);
2049 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
2050 u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
2054 /* Tell uCode which antennas are actually connected.
2055 * Before first association, we assume all antennas are connected.
2056 * Just after first association, iwl_chain_noise_calibration()
2057 * checks which antennas actually *are* connected. */
2058 if (priv->chain_noise_data.active_chains)
2059 active_chains = priv->chain_noise_data.active_chains;
2061 active_chains = priv->hw_params.valid_rx_ant;
2063 if (priv->cfg->bt_params &&
2064 priv->cfg->bt_params->advanced_bt_coexist &&
2065 (priv->bt_full_concurrent ||
2066 priv->bt_traffic_load >= IWL_BT_COEX_TRAFFIC_LOAD_HIGH)) {
2068 * only use chain 'A' in bt high traffic load or
2069 * full concurrency mode
2071 active_chains = first_antenna(active_chains);
2074 rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
2076 /* How many receivers should we use? */
2077 active_rx_cnt = iwl_get_active_rx_chain_count(priv);
2078 idle_rx_cnt = iwl_get_idle_rx_chain_count(priv, active_rx_cnt);
2081 /* correct rx chain count according hw settings
2082 * and chain noise calibration
2084 valid_rx_cnt = iwl_count_chain_bitmap(active_chains);
2085 if (valid_rx_cnt < active_rx_cnt)
2086 active_rx_cnt = valid_rx_cnt;
2088 if (valid_rx_cnt < idle_rx_cnt)
2089 idle_rx_cnt = valid_rx_cnt;
2091 rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
2092 rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
2094 ctx->staging.rx_chain = cpu_to_le16(rx_chain);
2096 if (!is_single && (active_rx_cnt >= IWL_NUM_RX_CHAINS_SINGLE) && is_cam)
2097 ctx->staging.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
2099 ctx->staging.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
2101 IWL_DEBUG_ASSOC(priv, "rx_chain=0x%X active=%d idle=%d\n",
2102 ctx->staging.rx_chain,
2103 active_rx_cnt, idle_rx_cnt);
2105 WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
2106 active_rx_cnt < idle_rx_cnt);
2109 u8 iwl_toggle_tx_ant(struct iwl_priv *priv, u8 ant, u8 valid)
2114 if (priv->band == IEEE80211_BAND_2GHZ &&
2115 priv->bt_traffic_load >= IWL_BT_COEX_TRAFFIC_LOAD_HIGH)
2118 for (i = 0; i < RATE_ANT_NUM - 1; i++) {
2119 ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0;
2120 if (valid & BIT(ind))
2126 static const char *get_csr_string(int cmd)
2129 IWL_CMD(CSR_HW_IF_CONFIG_REG);
2130 IWL_CMD(CSR_INT_COALESCING);
2132 IWL_CMD(CSR_INT_MASK);
2133 IWL_CMD(CSR_FH_INT_STATUS);
2134 IWL_CMD(CSR_GPIO_IN);
2136 IWL_CMD(CSR_GP_CNTRL);
2137 IWL_CMD(CSR_HW_REV);
2138 IWL_CMD(CSR_EEPROM_REG);
2139 IWL_CMD(CSR_EEPROM_GP);
2140 IWL_CMD(CSR_OTP_GP_REG);
2141 IWL_CMD(CSR_GIO_REG);
2142 IWL_CMD(CSR_GP_UCODE_REG);
2143 IWL_CMD(CSR_GP_DRIVER_REG);
2144 IWL_CMD(CSR_UCODE_DRV_GP1);
2145 IWL_CMD(CSR_UCODE_DRV_GP2);
2146 IWL_CMD(CSR_LED_REG);
2147 IWL_CMD(CSR_DRAM_INT_TBL_REG);
2148 IWL_CMD(CSR_GIO_CHICKEN_BITS);
2149 IWL_CMD(CSR_ANA_PLL_CFG);
2150 IWL_CMD(CSR_HW_REV_WA_REG);
2151 IWL_CMD(CSR_DBG_HPET_MEM_REG);
2157 void iwl_dump_csr(struct iwl_priv *priv)
2160 static const u32 csr_tbl[] = {
2161 CSR_HW_IF_CONFIG_REG,
2179 CSR_DRAM_INT_TBL_REG,
2180 CSR_GIO_CHICKEN_BITS,
2183 CSR_DBG_HPET_MEM_REG
2185 IWL_ERR(priv, "CSR values:\n");
2186 IWL_ERR(priv, "(2nd byte of CSR_INT_COALESCING is "
2187 "CSR_INT_PERIODIC_REG)\n");
2188 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
2189 IWL_ERR(priv, " %25s: 0X%08x\n",
2190 get_csr_string(csr_tbl[i]),
2191 iwl_read32(priv, csr_tbl[i]));
2195 static const char *get_fh_string(int cmd)
2198 IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
2199 IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
2200 IWL_CMD(FH_RSCSR_CHNL0_WPTR);
2201 IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
2202 IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
2203 IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
2204 IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
2205 IWL_CMD(FH_TSSR_TX_STATUS_REG);
2206 IWL_CMD(FH_TSSR_TX_ERROR_REG);
2212 int iwl_dump_fh(struct iwl_priv *priv, char **buf, bool display)
2215 #ifdef CONFIG_IWLWIFI_DEBUG
2219 static const u32 fh_tbl[] = {
2220 FH_RSCSR_CHNL0_STTS_WPTR_REG,
2221 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
2222 FH_RSCSR_CHNL0_WPTR,
2223 FH_MEM_RCSR_CHNL0_CONFIG_REG,
2224 FH_MEM_RSSR_SHARED_CTRL_REG,
2225 FH_MEM_RSSR_RX_STATUS_REG,
2226 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
2227 FH_TSSR_TX_STATUS_REG,
2228 FH_TSSR_TX_ERROR_REG
2230 #ifdef CONFIG_IWLWIFI_DEBUG
2232 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
2233 *buf = kmalloc(bufsz, GFP_KERNEL);
2236 pos += scnprintf(*buf + pos, bufsz - pos,
2237 "FH register values:\n");
2238 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
2239 pos += scnprintf(*buf + pos, bufsz - pos,
2241 get_fh_string(fh_tbl[i]),
2242 iwl_read_direct32(priv, fh_tbl[i]));
2247 IWL_ERR(priv, "FH register values:\n");
2248 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
2249 IWL_ERR(priv, " %34s: 0X%08x\n",
2250 get_fh_string(fh_tbl[i]),
2251 iwl_read_direct32(priv, fh_tbl[i]));
2256 /* notification wait support */
2257 void iwlagn_init_notification_wait(struct iwl_priv *priv,
2258 struct iwl_notification_wait *wait_entry,
2260 void (*fn)(struct iwl_priv *priv,
2261 struct iwl_rx_packet *pkt,
2265 wait_entry->fn = fn;
2266 wait_entry->fn_data = fn_data;
2267 wait_entry->cmd = cmd;
2268 wait_entry->triggered = false;
2270 spin_lock_bh(&priv->_agn.notif_wait_lock);
2271 list_add(&wait_entry->list, &priv->_agn.notif_waits);
2272 spin_unlock_bh(&priv->_agn.notif_wait_lock);
2275 signed long iwlagn_wait_notification(struct iwl_priv *priv,
2276 struct iwl_notification_wait *wait_entry,
2277 unsigned long timeout)
2281 ret = wait_event_timeout(priv->_agn.notif_waitq,
2282 wait_entry->triggered,
2285 spin_lock_bh(&priv->_agn.notif_wait_lock);
2286 list_del(&wait_entry->list);
2287 spin_unlock_bh(&priv->_agn.notif_wait_lock);
2292 void iwlagn_remove_notification(struct iwl_priv *priv,
2293 struct iwl_notification_wait *wait_entry)
2295 spin_lock_bh(&priv->_agn.notif_wait_lock);
2296 list_del(&wait_entry->list);
2297 spin_unlock_bh(&priv->_agn.notif_wait_lock);
2300 int iwlagn_start_device(struct iwl_priv *priv)
2304 iwl_prepare_card_hw(priv);
2305 if (!priv->hw_ready) {
2306 IWL_WARN(priv, "Exit HW not ready\n");
2310 /* If platform's RF_KILL switch is NOT set to KILL */
2311 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2312 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2314 set_bit(STATUS_RF_KILL_HW, &priv->status);
2316 if (iwl_is_rfkill(priv)) {
2317 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
2318 iwl_enable_interrupts(priv);
2322 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2324 ret = iwlagn_hw_nic_init(priv);
2326 IWL_ERR(priv, "Unable to init nic\n");
2330 /* make sure rfkill handshake bits are cleared */
2331 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2332 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2333 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2335 /* clear (again), then enable host interrupts */
2336 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2337 iwl_enable_interrupts(priv);
2339 /* really make sure rfkill handshake bits are cleared */
2340 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2341 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2346 void iwlagn_stop_device(struct iwl_priv *priv)
2348 unsigned long flags;
2350 /* stop and reset the on-board processor */
2351 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
2353 /* tell the device to stop sending interrupts */
2354 spin_lock_irqsave(&priv->lock, flags);
2355 iwl_disable_interrupts(priv);
2356 spin_unlock_irqrestore(&priv->lock, flags);
2357 iwl_synchronize_irq(priv);
2359 /* device going down, Stop using ICT table */
2360 iwl_disable_ict(priv);
2362 iwlagn_txq_ctx_stop(priv);
2363 iwlagn_rxq_stop(priv);
2365 /* Power-down device's busmaster DMA clocks */
2366 iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
2369 /* Make sure (redundant) we've released our request to stay awake */
2370 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2372 /* Stop the device, and put it in low power state */