2 * (c) Copyright 2002-2010, Ralink Technology, Inc.
3 * Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org>
4 * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl>
5 * Copyright (C) 2018 Stanislaw Gruszka <stf_xl@wp.pl>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2
9 * as published by the Free Software Foundation
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
22 static void mt76x0_vht_cap_mask(struct ieee80211_supported_band *sband)
24 struct ieee80211_sta_vht_cap *vht_cap = &sband->vht_cap;
28 vht_cap->cap &= ~IEEE80211_VHT_CAP_RXLDPC;
29 for (i = 0; i < 8; i++) {
31 mcs_map |= (IEEE80211_VHT_MCS_SUPPORT_0_7 << (i * 2));
34 (IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2));
36 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(mcs_map);
37 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(mcs_map);
41 mt76x0_set_wlan_state(struct mt76x02_dev *dev, u32 val, bool enable)
43 u32 mask = MT_CMB_CTRL_XTAL_RDY | MT_CMB_CTRL_PLL_LD;
45 /* Note: we don't turn off WLAN_CLK because that makes the device
46 * not respond properly on the probe path.
47 * In case anyone (PSM?) wants to use this function we can
48 * bring the clock stuff back and fixup the probe path.
52 val |= (MT_WLAN_FUN_CTRL_WLAN_EN |
53 MT_WLAN_FUN_CTRL_WLAN_CLK_EN);
55 val &= ~(MT_WLAN_FUN_CTRL_WLAN_EN);
57 mt76_wr(dev, MT_WLAN_FUN_CTRL, val);
60 /* Note: vendor driver tries to disable/enable wlan here and retry
61 * but the code which does it is so buggy it must have never
62 * triggered, so don't bother.
64 if (enable && !mt76_poll(dev, MT_CMB_CTRL, mask, mask, 2000))
65 dev_err(dev->mt76.dev, "PLL and XTAL check failed\n");
68 void mt76x0_chip_onoff(struct mt76x02_dev *dev, bool enable, bool reset)
72 val = mt76_rr(dev, MT_WLAN_FUN_CTRL);
75 val |= MT_WLAN_FUN_CTRL_GPIO_OUT_EN;
76 val &= ~MT_WLAN_FUN_CTRL_FRC_WL_ANT_SEL;
78 if (val & MT_WLAN_FUN_CTRL_WLAN_EN) {
79 val |= (MT_WLAN_FUN_CTRL_WLAN_RESET |
80 MT_WLAN_FUN_CTRL_WLAN_RESET_RF);
81 mt76_wr(dev, MT_WLAN_FUN_CTRL, val);
84 val &= ~(MT_WLAN_FUN_CTRL_WLAN_RESET |
85 MT_WLAN_FUN_CTRL_WLAN_RESET_RF);
89 mt76_wr(dev, MT_WLAN_FUN_CTRL, val);
92 mt76x0_set_wlan_state(dev, val, enable);
94 EXPORT_SYMBOL_GPL(mt76x0_chip_onoff);
96 static void mt76x0_reset_csr_bbp(struct mt76x02_dev *dev)
98 mt76_wr(dev, MT_MAC_SYS_CTRL,
99 MT_MAC_SYS_CTRL_RESET_CSR |
100 MT_MAC_SYS_CTRL_RESET_BBP);
102 mt76_clear(dev, MT_MAC_SYS_CTRL,
103 MT_MAC_SYS_CTRL_RESET_CSR |
104 MT_MAC_SYS_CTRL_RESET_BBP);
107 #define RANDOM_WRITE(dev, tab) \
108 mt76_wr_rp(dev, MT_MCU_MEMMAP_WLAN, \
109 tab, ARRAY_SIZE(tab))
111 static int mt76x0_init_bbp(struct mt76x02_dev *dev)
115 ret = mt76x0_phy_wait_bbp_ready(dev);
119 RANDOM_WRITE(dev, mt76x0_bbp_init_tab);
121 for (i = 0; i < ARRAY_SIZE(mt76x0_bbp_switch_tab); i++) {
122 const struct mt76x0_bbp_switch_item *item = &mt76x0_bbp_switch_tab[i];
123 const struct mt76_reg_pair *pair = &item->reg_pair;
125 if (((RF_G_BAND | RF_BW_20) & item->bw_band) == (RF_G_BAND | RF_BW_20))
126 mt76_wr(dev, pair->reg, pair->value);
129 RANDOM_WRITE(dev, mt76x0_dcoc_tab);
134 static void mt76x0_init_mac_registers(struct mt76x02_dev *dev)
136 RANDOM_WRITE(dev, common_mac_reg_table);
138 /* Enable PBF and MAC clock SYS_CTRL[11:10] = 0x3 */
139 RANDOM_WRITE(dev, mt76x0_mac_reg_table);
141 /* Release BBP and MAC reset MAC_SYS_CTRL[1:0] = 0x0 */
142 mt76_clear(dev, MT_MAC_SYS_CTRL, 0x3);
144 /* Set 0x141C[15:12]=0xF */
145 mt76_set(dev, MT_EXT_CCA_CFG, 0xf000);
147 mt76_clear(dev, MT_FCE_L2_STUFF, MT_FCE_L2_STUFF_WR_MPDU_LEN_EN);
150 * tx_ring 9 is for mgmt frame
151 * tx_ring 8 is for in-band command frame.
152 * WMM_RG0_TXQMA: this register setting is for FCE to
153 * define the rule of tx_ring 9
154 * WMM_RG1_TXQMA: this register setting is for FCE to
155 * define the rule of tx_ring 8
157 mt76_rmw(dev, MT_WMM_CTRL, 0x3ff, 0x201);
160 static void mt76x0_reset_counters(struct mt76x02_dev *dev)
162 mt76_rr(dev, MT_RX_STAT_0);
163 mt76_rr(dev, MT_RX_STAT_1);
164 mt76_rr(dev, MT_RX_STAT_2);
165 mt76_rr(dev, MT_TX_STA_0);
166 mt76_rr(dev, MT_TX_STA_1);
167 mt76_rr(dev, MT_TX_STA_2);
170 int mt76x0_mac_start(struct mt76x02_dev *dev)
172 mt76_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX);
174 if (!mt76x02_wait_for_wpdma(&dev->mt76, 200000))
177 mt76_wr(dev, MT_RX_FILTR_CFG, dev->mt76.rxfilter);
178 mt76_wr(dev, MT_MAC_SYS_CTRL,
179 MT_MAC_SYS_CTRL_ENABLE_TX | MT_MAC_SYS_CTRL_ENABLE_RX);
181 return !mt76x02_wait_for_wpdma(&dev->mt76, 50) ? -ETIMEDOUT : 0;
183 EXPORT_SYMBOL_GPL(mt76x0_mac_start);
185 void mt76x0_mac_stop(struct mt76x02_dev *dev)
189 /* Page count on TxQ */
190 while (i-- && ((mt76_rr(dev, 0x0438) & 0xffffffff) ||
191 (mt76_rr(dev, 0x0a30) & 0x000000ff) ||
192 (mt76_rr(dev, 0x0a34) & 0x00ff00ff)))
195 if (!mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_TX, 0, 1000))
196 dev_warn(dev->mt76.dev, "Warning: MAC TX did not stop!\n");
198 mt76_clear(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_RX |
199 MT_MAC_SYS_CTRL_ENABLE_TX);
201 /* Page count on RxQ */
202 for (i = 0; i < 200; i++) {
203 if (!(mt76_rr(dev, MT_RXQ_STA) & 0x00ff0000) &&
204 !mt76_rr(dev, 0x0a30) &&
205 !mt76_rr(dev, 0x0a34)) {
213 if (!mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_RX, 0, 1000))
214 dev_warn(dev->mt76.dev, "Warning: MAC RX did not stop!\n");
216 EXPORT_SYMBOL_GPL(mt76x0_mac_stop);
218 int mt76x0_init_hardware(struct mt76x02_dev *dev)
222 if (!mt76x02_wait_for_wpdma(&dev->mt76, 1000))
225 /* Wait for ASIC ready after FW load. */
226 if (!mt76x02_wait_for_mac(&dev->mt76))
229 mt76x0_reset_csr_bbp(dev);
230 ret = mt76x02_mcu_function_select(dev, Q_SELECT, 1, false);
234 mt76x0_init_mac_registers(dev);
236 if (!mt76x02_wait_for_txrx_idle(&dev->mt76))
239 ret = mt76x0_init_bbp(dev);
243 dev->mt76.rxfilter = mt76_rr(dev, MT_RX_FILTR_CFG);
245 for (i = 0; i < 16; i++)
246 for (k = 0; k < 4; k++)
247 mt76x02_mac_shared_key_setup(dev, i, k, NULL);
249 for (i = 0; i < 256; i++)
250 mt76x02_mac_wcid_setup(dev, i, 0, NULL);
252 mt76x0_reset_counters(dev);
254 ret = mt76x0_eeprom_init(dev);
258 mt76x0_phy_init(dev);
259 mt76x02_init_beacon_config(dev);
263 EXPORT_SYMBOL_GPL(mt76x0_init_hardware);
266 mt76x0_alloc_device(struct device *pdev,
267 const struct mt76_driver_ops *drv_ops,
268 const struct ieee80211_ops *ops)
270 struct mt76x02_dev *dev;
271 struct mt76_dev *mdev;
273 mdev = mt76_alloc_device(sizeof(*dev), ops);
280 dev = container_of(mdev, struct mt76x02_dev, mt76);
281 mutex_init(&dev->phy_mutex);
285 EXPORT_SYMBOL_GPL(mt76x0_alloc_device);
287 int mt76x0_register_device(struct mt76x02_dev *dev)
291 mt76x02_init_device(dev);
292 ret = mt76_register_device(&dev->mt76, true, mt76x02_rates,
293 ARRAY_SIZE(mt76x02_rates));
297 /* overwrite unsupported features */
298 if (dev->mt76.cap.has_5ghz)
299 mt76x0_vht_cap_mask(&dev->mt76.sband_5g.sband);
301 mt76x02_init_debugfs(dev);
305 EXPORT_SYMBOL_GPL(mt76x0_register_device);