2 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/delay.h>
23 mt76x2_mac_pbf_init(struct mt76x02_dev *dev)
27 val = MT_PBF_SYS_CTRL_MCU_RESET |
28 MT_PBF_SYS_CTRL_DMA_RESET |
29 MT_PBF_SYS_CTRL_MAC_RESET |
30 MT_PBF_SYS_CTRL_PBF_RESET |
31 MT_PBF_SYS_CTRL_ASY_RESET;
33 mt76_set(dev, MT_PBF_SYS_CTRL, val);
34 mt76_clear(dev, MT_PBF_SYS_CTRL, val);
36 mt76_wr(dev, MT_PBF_TX_MAX_PCNT, 0xefef3f1f);
37 mt76_wr(dev, MT_PBF_RX_MAX_PCNT, 0xfebf);
41 mt76x2_fixup_xtal(struct mt76x02_dev *dev)
46 eep_val = mt76x02_eeprom_get(dev, MT_EE_XTAL_TRIM_2);
48 offset = eep_val & 0x7f;
49 if ((eep_val & 0xff) == 0xff)
51 else if (eep_val & 0x80)
55 if (eep_val == 0x00 || eep_val == 0xff) {
56 eep_val = mt76x02_eeprom_get(dev, MT_EE_XTAL_TRIM_1);
59 if (eep_val == 0x00 || eep_val == 0xff)
64 mt76_rmw_field(dev, MT_XO_CTRL5, MT_XO_CTRL5_C2_VAL, eep_val + offset);
65 mt76_set(dev, MT_XO_CTRL6, MT_XO_CTRL6_C2_CTRL);
67 eep_val = mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_2);
68 switch (FIELD_GET(MT_EE_NIC_CONF_2_XTAL_OPTION, eep_val)) {
70 mt76_wr(dev, MT_XO_CTRL7, 0x5c1fee80);
73 mt76_wr(dev, MT_XO_CTRL7, 0x5c1feed0);
80 static int mt76x2_mac_reset(struct mt76x02_dev *dev, bool hard)
82 const u8 *macaddr = dev->mt76.macaddr;
86 if (!mt76x02_wait_for_mac(&dev->mt76))
89 val = mt76_rr(dev, MT_WPDMA_GLO_CFG);
91 val &= ~(MT_WPDMA_GLO_CFG_TX_DMA_EN |
92 MT_WPDMA_GLO_CFG_TX_DMA_BUSY |
93 MT_WPDMA_GLO_CFG_RX_DMA_EN |
94 MT_WPDMA_GLO_CFG_RX_DMA_BUSY |
95 MT_WPDMA_GLO_CFG_DMA_BURST_SIZE);
96 val |= FIELD_PREP(MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 3);
98 mt76_wr(dev, MT_WPDMA_GLO_CFG, val);
100 mt76x2_mac_pbf_init(dev);
101 mt76_write_mac_initvals(dev);
102 mt76x2_fixup_xtal(dev);
104 mt76_clear(dev, MT_MAC_SYS_CTRL,
105 MT_MAC_SYS_CTRL_RESET_CSR |
106 MT_MAC_SYS_CTRL_RESET_BBP);
109 mt76_clear(dev, MT_COEXCFG0, MT_COEXCFG0_COEX_EN);
111 mt76_set(dev, MT_EXT_CCA_CFG, 0x0000f000);
112 mt76_clear(dev, MT_TX_ALC_CFG_4, BIT(31));
114 mt76_wr(dev, MT_RF_BYPASS_0, 0x06000000);
115 mt76_wr(dev, MT_RF_SETTING_0, 0x08800000);
116 usleep_range(5000, 10000);
117 mt76_wr(dev, MT_RF_BYPASS_0, 0x00000000);
119 mt76_wr(dev, MT_MCU_CLOCK_CTL, 0x1401);
120 mt76_clear(dev, MT_FCE_L2_STUFF, MT_FCE_L2_STUFF_WR_MPDU_LEN_EN);
122 mt76_wr(dev, MT_MAC_ADDR_DW0, get_unaligned_le32(macaddr));
123 mt76_wr(dev, MT_MAC_ADDR_DW1, get_unaligned_le16(macaddr + 4));
125 mt76x02_init_beacon_config(dev);
129 for (i = 0; i < 256 / 32; i++)
130 mt76_wr(dev, MT_WCID_DROP_BASE + i * 4, 0);
132 for (i = 0; i < 256; i++)
133 mt76x02_mac_wcid_setup(dev, i, 0, NULL);
135 for (i = 0; i < MT_MAX_VIFS; i++)
136 mt76x02_mac_wcid_setup(dev, MT_VIF_WCID(i), i, NULL);
138 for (i = 0; i < 16; i++)
139 for (k = 0; k < 4; k++)
140 mt76x02_mac_shared_key_setup(dev, i, k, NULL);
142 for (i = 0; i < 16; i++)
143 mt76_rr(dev, MT_TX_STAT_FIFO);
145 mt76_wr(dev, MT_CH_TIME_CFG,
146 MT_CH_TIME_CFG_TIMER_EN |
147 MT_CH_TIME_CFG_TX_AS_BUSY |
148 MT_CH_TIME_CFG_RX_AS_BUSY |
149 MT_CH_TIME_CFG_NAV_AS_BUSY |
150 MT_CH_TIME_CFG_EIFS_AS_BUSY |
151 FIELD_PREP(MT_CH_TIME_CFG_CH_TIMER_CLR, 1));
153 mt76x02_set_tx_ackto(dev);
158 int mt76x2_mac_start(struct mt76x02_dev *dev)
162 for (i = 0; i < 16; i++)
163 mt76_rr(dev, MT_TX_AGG_CNT(i));
165 for (i = 0; i < 16; i++)
166 mt76_rr(dev, MT_TX_STAT_FIFO);
168 memset(dev->aggr_stats, 0, sizeof(dev->aggr_stats));
169 mt76x02_mac_start(dev);
174 void mt76x2_mac_resume(struct mt76x02_dev *dev)
176 mt76_wr(dev, MT_MAC_SYS_CTRL,
177 MT_MAC_SYS_CTRL_ENABLE_TX |
178 MT_MAC_SYS_CTRL_ENABLE_RX);
182 mt76x2_power_on_rf_patch(struct mt76x02_dev *dev)
184 mt76_set(dev, 0x10130, BIT(0) | BIT(16));
187 mt76_clear(dev, 0x1001c, 0xff);
188 mt76_set(dev, 0x1001c, 0x30);
190 mt76_wr(dev, 0x10014, 0x484f);
193 mt76_set(dev, 0x10130, BIT(17));
196 mt76_clear(dev, 0x10130, BIT(16));
199 mt76_set(dev, 0x1014c, BIT(19) | BIT(20));
203 mt76x2_power_on_rf(struct mt76x02_dev *dev, int unit)
205 int shift = unit ? 8 : 0;
208 mt76_set(dev, 0x10130, BIT(0) << shift);
211 /* Enable RFDIG LDO/AFE/ABB/ADDA */
212 mt76_set(dev, 0x10130, (BIT(1) | BIT(3) | BIT(4) | BIT(5)) << shift);
215 /* Switch RFDIG power to internal LDO */
216 mt76_clear(dev, 0x10130, BIT(2) << shift);
219 mt76x2_power_on_rf_patch(dev);
221 mt76_set(dev, 0x530, 0xf);
225 mt76x2_power_on(struct mt76x02_dev *dev)
229 /* Turn on WL MTCMOS */
230 mt76_set(dev, MT_WLAN_MTC_CTRL, MT_WLAN_MTC_CTRL_MTCMOS_PWR_UP);
232 val = MT_WLAN_MTC_CTRL_STATE_UP |
233 MT_WLAN_MTC_CTRL_PWR_ACK |
234 MT_WLAN_MTC_CTRL_PWR_ACK_S;
236 mt76_poll(dev, MT_WLAN_MTC_CTRL, val, val, 1000);
238 mt76_clear(dev, MT_WLAN_MTC_CTRL, 0x7f << 16);
241 mt76_clear(dev, MT_WLAN_MTC_CTRL, 0xf << 24);
244 mt76_set(dev, MT_WLAN_MTC_CTRL, 0xf << 24);
245 mt76_clear(dev, MT_WLAN_MTC_CTRL, 0xfff);
247 /* Turn on AD/DA power down */
248 mt76_clear(dev, 0x11204, BIT(3));
250 /* WLAN function enable */
251 mt76_set(dev, 0x10080, BIT(0));
253 /* Release BBP software reset */
254 mt76_clear(dev, 0x10064, BIT(18));
256 mt76x2_power_on_rf(dev, 0);
257 mt76x2_power_on_rf(dev, 1);
260 int mt76x2_init_hardware(struct mt76x02_dev *dev)
264 mt76x02_dma_disable(dev);
265 mt76x2_reset_wlan(dev, true);
266 mt76x2_power_on(dev);
268 ret = mt76x2_eeprom_init(dev);
272 ret = mt76x2_mac_reset(dev, true);
276 dev->mt76.rxfilter = mt76_rr(dev, MT_RX_FILTR_CFG);
278 ret = mt76x02_dma_init(dev);
282 set_bit(MT76_STATE_INITIALIZED, &dev->mt76.state);
283 ret = mt76x2_mac_start(dev);
287 ret = mt76x2_mcu_init(dev);
291 mt76x2_mac_stop(dev, false);
296 void mt76x2_stop_hardware(struct mt76x02_dev *dev)
298 cancel_delayed_work_sync(&dev->cal_work);
299 cancel_delayed_work_sync(&dev->mac_work);
300 mt76x02_mcu_set_radio_state(dev, false, true);
301 mt76x2_mac_stop(dev, false);
304 void mt76x2_cleanup(struct mt76x02_dev *dev)
306 tasklet_disable(&dev->dfs_pd.dfs_tasklet);
307 tasklet_disable(&dev->pre_tbtt_tasklet);
308 mt76x2_stop_hardware(dev);
309 mt76x02_dma_cleanup(dev);
310 mt76x02_mcu_cleanup(dev);
313 struct mt76x02_dev *mt76x2_alloc_device(struct device *pdev)
315 static const struct mt76_driver_ops drv_ops = {
316 .txwi_size = sizeof(struct mt76x02_txwi),
317 .update_survey = mt76x02_update_channel,
318 .tx_prepare_skb = mt76x02_tx_prepare_skb,
319 .tx_complete_skb = mt76x02_tx_complete_skb,
320 .rx_skb = mt76x02_queue_rx_skb,
321 .rx_poll_complete = mt76x02_rx_poll_complete,
322 .sta_ps = mt76x02_sta_ps,
324 struct mt76x02_dev *dev;
325 struct mt76_dev *mdev;
327 mdev = mt76_alloc_device(sizeof(*dev), &mt76x2_ops);
331 dev = container_of(mdev, struct mt76x02_dev, mt76);
333 mdev->drv = &drv_ops;
338 static void mt76x2_led_set_config(struct mt76_dev *mt76, u8 delay_on,
341 struct mt76x02_dev *dev = container_of(mt76, struct mt76x02_dev,
345 val = MT_LED_STATUS_DURATION(0xff) |
346 MT_LED_STATUS_OFF(delay_off) |
347 MT_LED_STATUS_ON(delay_on);
349 mt76_wr(dev, MT_LED_S0(mt76->led_pin), val);
350 mt76_wr(dev, MT_LED_S1(mt76->led_pin), val);
352 val = MT_LED_CTRL_REPLAY(mt76->led_pin) |
353 MT_LED_CTRL_KICK(mt76->led_pin);
355 val |= MT_LED_CTRL_POLARITY(mt76->led_pin);
356 mt76_wr(dev, MT_LED_CTRL, val);
359 static int mt76x2_led_set_blink(struct led_classdev *led_cdev,
360 unsigned long *delay_on,
361 unsigned long *delay_off)
363 struct mt76_dev *mt76 = container_of(led_cdev, struct mt76_dev,
365 u8 delta_on, delta_off;
367 delta_off = max_t(u8, *delay_off / 10, 1);
368 delta_on = max_t(u8, *delay_on / 10, 1);
370 mt76x2_led_set_config(mt76, delta_on, delta_off);
374 static void mt76x2_led_set_brightness(struct led_classdev *led_cdev,
375 enum led_brightness brightness)
377 struct mt76_dev *mt76 = container_of(led_cdev, struct mt76_dev,
381 mt76x2_led_set_config(mt76, 0, 0xff);
383 mt76x2_led_set_config(mt76, 0xff, 0);
386 int mt76x2_register_device(struct mt76x02_dev *dev)
388 struct ieee80211_hw *hw = mt76_hw(dev);
389 struct wiphy *wiphy = hw->wiphy;
392 INIT_DELAYED_WORK(&dev->cal_work, mt76x2_phy_calibrate);
394 mt76x02_init_device(dev);
396 ret = mt76x2_init_hardware(dev);
400 for (i = 0; i < ARRAY_SIZE(dev->macaddr_list); i++) {
401 u8 *addr = dev->macaddr_list[i].addr;
403 memcpy(addr, dev->mt76.macaddr, ETH_ALEN);
409 addr[0] ^= ((i - 1) << 2);
411 wiphy->addresses = dev->macaddr_list;
412 wiphy->n_addresses = ARRAY_SIZE(dev->macaddr_list);
414 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_VHT_IBSS);
416 /* init led callbacks */
417 dev->mt76.led_cdev.brightness_set = mt76x2_led_set_brightness;
418 dev->mt76.led_cdev.blink_set = mt76x2_led_set_blink;
420 ret = mt76_register_device(&dev->mt76, true, mt76x02_rates,
421 ARRAY_SIZE(mt76x02_rates));
425 mt76x02_init_debugfs(dev);
426 mt76x2_init_txpower(dev, &dev->mt76.sband_2g.sband);
427 mt76x2_init_txpower(dev, &dev->mt76.sband_5g.sband);
432 mt76x2_stop_hardware(dev);