2 * drivers/net/wireless/mwl8k.c
3 * Driver for Marvell TOPDOG 802.11 Wireless cards
5 * Copyright (C) 2008-2009 Marvell Semiconductor Inc.
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/sched.h>
16 #include <linux/spinlock.h>
17 #include <linux/list.h>
18 #include <linux/pci.h>
19 #include <linux/delay.h>
20 #include <linux/completion.h>
21 #include <linux/etherdevice.h>
22 #include <net/mac80211.h>
23 #include <linux/moduleparam.h>
24 #include <linux/firmware.h>
25 #include <linux/workqueue.h>
27 #define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
28 #define MWL8K_NAME KBUILD_MODNAME
29 #define MWL8K_VERSION "0.10"
31 /* Register definitions */
32 #define MWL8K_HIU_GEN_PTR 0x00000c10
33 #define MWL8K_MODE_STA 0x0000005a
34 #define MWL8K_MODE_AP 0x000000a5
35 #define MWL8K_HIU_INT_CODE 0x00000c14
36 #define MWL8K_FWSTA_READY 0xf0f1f2f4
37 #define MWL8K_FWAP_READY 0xf1f2f4a5
38 #define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
39 #define MWL8K_HIU_SCRATCH 0x00000c40
41 /* Host->device communications */
42 #define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
43 #define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
44 #define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
45 #define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
46 #define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
47 #define MWL8K_H2A_INT_DUMMY (1 << 20)
48 #define MWL8K_H2A_INT_RESET (1 << 15)
49 #define MWL8K_H2A_INT_DOORBELL (1 << 1)
50 #define MWL8K_H2A_INT_PPA_READY (1 << 0)
52 /* Device->host communications */
53 #define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
54 #define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
55 #define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
56 #define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
57 #define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
58 #define MWL8K_A2H_INT_DUMMY (1 << 20)
59 #define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
60 #define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
61 #define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
62 #define MWL8K_A2H_INT_RADIO_ON (1 << 6)
63 #define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
64 #define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
65 #define MWL8K_A2H_INT_OPC_DONE (1 << 2)
66 #define MWL8K_A2H_INT_RX_READY (1 << 1)
67 #define MWL8K_A2H_INT_TX_DONE (1 << 0)
69 #define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
70 MWL8K_A2H_INT_CHNL_SWITCHED | \
71 MWL8K_A2H_INT_QUEUE_EMPTY | \
72 MWL8K_A2H_INT_RADAR_DETECT | \
73 MWL8K_A2H_INT_RADIO_ON | \
74 MWL8K_A2H_INT_RADIO_OFF | \
75 MWL8K_A2H_INT_MAC_EVENT | \
76 MWL8K_A2H_INT_OPC_DONE | \
77 MWL8K_A2H_INT_RX_READY | \
78 MWL8K_A2H_INT_TX_DONE)
80 #define MWL8K_RX_QUEUES 1
81 #define MWL8K_TX_QUEUES 4
83 struct mwl8k_device_info {
89 struct mwl8k_rx_queue {
92 /* hw receives here */
95 /* refill descs here */
98 struct mwl8k_rx_desc *rxd;
102 DECLARE_PCI_UNMAP_ADDR(dma)
106 struct mwl8k_tx_queue {
107 /* hw transmits here */
110 /* sw appends here */
113 struct ieee80211_tx_queue_stats stats;
114 struct mwl8k_tx_desc *txd;
116 struct sk_buff **skb;
119 /* Pointers to the firmware data and meta information about it. */
120 struct mwl8k_firmware {
121 /* Boot helper code */
122 struct firmware *helper;
125 struct firmware *ucode;
131 struct ieee80211_hw *hw;
133 struct pci_dev *pdev;
135 struct mwl8k_device_info *device_info;
138 /* firmware files and meta data */
139 struct mwl8k_firmware fw;
141 /* firmware access */
142 struct mutex fw_mutex;
143 struct task_struct *fw_mutex_owner;
145 struct completion *hostcmd_wait;
147 /* lock held over TX and TX reap */
150 /* TX quiesce completion, protected by fw_mutex and tx_lock */
151 struct completion *tx_wait;
153 struct ieee80211_vif *vif;
155 struct ieee80211_channel *current_channel;
157 /* power management status cookie from firmware */
159 dma_addr_t cookie_dma;
166 * Running count of TX packets in flight, to avoid
167 * iterating over the transmit rings each time.
171 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
172 struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES];
175 struct ieee80211_supported_band band;
176 struct ieee80211_channel channels[14];
177 struct ieee80211_rate rates[13];
180 bool radio_short_preamble;
181 bool sniffer_enabled;
184 /* XXX need to convert this to handle multiple interfaces */
186 u8 capture_bssid[ETH_ALEN];
187 struct sk_buff *beacon_skb;
190 * This FJ worker has to be global as it is scheduled from the
191 * RX handler. At this point we don't know which interface it
192 * belongs to until the list of bssids waiting to complete join
195 struct work_struct finalize_join_worker;
197 /* Tasklet to reclaim TX descriptors and buffers after tx */
198 struct tasklet_struct tx_reclaim_task;
201 /* Per interface specific private data */
203 /* backpointer to parent config block */
204 struct mwl8k_priv *priv;
206 /* BSS config of AP or IBSS from mac80211*/
207 struct ieee80211_bss_conf bss_info;
209 /* BSSID of AP or IBSS */
211 u8 mac_addr[ETH_ALEN];
214 * Subset of supported legacy rates.
215 * Intersection of AP and STA supported rates.
217 struct ieee80211_rate legacy_rates[13];
219 /* number of supported legacy rates */
222 /* Index into station database.Returned by update_sta_db call */
225 /* Non AMPDU sequence number assigned by driver */
229 #define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
231 static const struct ieee80211_channel mwl8k_channels[] = {
232 { .center_freq = 2412, .hw_value = 1, },
233 { .center_freq = 2417, .hw_value = 2, },
234 { .center_freq = 2422, .hw_value = 3, },
235 { .center_freq = 2427, .hw_value = 4, },
236 { .center_freq = 2432, .hw_value = 5, },
237 { .center_freq = 2437, .hw_value = 6, },
238 { .center_freq = 2442, .hw_value = 7, },
239 { .center_freq = 2447, .hw_value = 8, },
240 { .center_freq = 2452, .hw_value = 9, },
241 { .center_freq = 2457, .hw_value = 10, },
242 { .center_freq = 2462, .hw_value = 11, },
245 static const struct ieee80211_rate mwl8k_rates[] = {
246 { .bitrate = 10, .hw_value = 2, },
247 { .bitrate = 20, .hw_value = 4, },
248 { .bitrate = 55, .hw_value = 11, },
249 { .bitrate = 110, .hw_value = 22, },
250 { .bitrate = 220, .hw_value = 44, },
251 { .bitrate = 60, .hw_value = 12, },
252 { .bitrate = 90, .hw_value = 18, },
253 { .bitrate = 120, .hw_value = 24, },
254 { .bitrate = 180, .hw_value = 36, },
255 { .bitrate = 240, .hw_value = 48, },
256 { .bitrate = 360, .hw_value = 72, },
257 { .bitrate = 480, .hw_value = 96, },
258 { .bitrate = 540, .hw_value = 108, },
261 /* Set or get info from Firmware */
262 #define MWL8K_CMD_SET 0x0001
263 #define MWL8K_CMD_GET 0x0000
265 /* Firmware command codes */
266 #define MWL8K_CMD_CODE_DNLD 0x0001
267 #define MWL8K_CMD_GET_HW_SPEC 0x0003
268 #define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
269 #define MWL8K_CMD_GET_STAT 0x0014
270 #define MWL8K_CMD_RADIO_CONTROL 0x001c
271 #define MWL8K_CMD_RF_TX_POWER 0x001e
272 #define MWL8K_CMD_SET_PRE_SCAN 0x0107
273 #define MWL8K_CMD_SET_POST_SCAN 0x0108
274 #define MWL8K_CMD_SET_RF_CHANNEL 0x010a
275 #define MWL8K_CMD_SET_AID 0x010d
276 #define MWL8K_CMD_SET_RATE 0x0110
277 #define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
278 #define MWL8K_CMD_RTS_THRESHOLD 0x0113
279 #define MWL8K_CMD_SET_SLOT 0x0114
280 #define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
281 #define MWL8K_CMD_SET_WMM_MODE 0x0123
282 #define MWL8K_CMD_MIMO_CONFIG 0x0125
283 #define MWL8K_CMD_USE_FIXED_RATE 0x0126
284 #define MWL8K_CMD_ENABLE_SNIFFER 0x0150
285 #define MWL8K_CMD_SET_MAC_ADDR 0x0202
286 #define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
287 #define MWL8K_CMD_UPDATE_STADB 0x1123
289 static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize)
291 #define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
292 snprintf(buf, bufsize, "%s", #x);\
295 switch (cmd & ~0x8000) {
296 MWL8K_CMDNAME(CODE_DNLD);
297 MWL8K_CMDNAME(GET_HW_SPEC);
298 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
299 MWL8K_CMDNAME(GET_STAT);
300 MWL8K_CMDNAME(RADIO_CONTROL);
301 MWL8K_CMDNAME(RF_TX_POWER);
302 MWL8K_CMDNAME(SET_PRE_SCAN);
303 MWL8K_CMDNAME(SET_POST_SCAN);
304 MWL8K_CMDNAME(SET_RF_CHANNEL);
305 MWL8K_CMDNAME(SET_AID);
306 MWL8K_CMDNAME(SET_RATE);
307 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
308 MWL8K_CMDNAME(RTS_THRESHOLD);
309 MWL8K_CMDNAME(SET_SLOT);
310 MWL8K_CMDNAME(SET_EDCA_PARAMS);
311 MWL8K_CMDNAME(SET_WMM_MODE);
312 MWL8K_CMDNAME(MIMO_CONFIG);
313 MWL8K_CMDNAME(USE_FIXED_RATE);
314 MWL8K_CMDNAME(ENABLE_SNIFFER);
315 MWL8K_CMDNAME(SET_MAC_ADDR);
316 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
317 MWL8K_CMDNAME(UPDATE_STADB);
319 snprintf(buf, bufsize, "0x%x", cmd);
326 /* Hardware and firmware reset */
327 static void mwl8k_hw_reset(struct mwl8k_priv *priv)
329 iowrite32(MWL8K_H2A_INT_RESET,
330 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
331 iowrite32(MWL8K_H2A_INT_RESET,
332 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
336 /* Release fw image */
337 static void mwl8k_release_fw(struct firmware **fw)
341 release_firmware(*fw);
345 static void mwl8k_release_firmware(struct mwl8k_priv *priv)
347 mwl8k_release_fw(&priv->fw.ucode);
348 mwl8k_release_fw(&priv->fw.helper);
351 /* Request fw image */
352 static int mwl8k_request_fw(struct mwl8k_priv *priv,
353 const char *fname, struct firmware **fw)
355 /* release current image */
357 mwl8k_release_fw(fw);
359 return request_firmware((const struct firmware **)fw,
360 fname, &priv->pdev->dev);
363 static int mwl8k_request_firmware(struct mwl8k_priv *priv)
365 struct mwl8k_device_info *di = priv->device_info;
368 if (di->helper_image != NULL) {
369 rc = mwl8k_request_fw(priv, di->helper_image, &priv->fw.helper);
371 printk(KERN_ERR "%s: Error requesting helper "
372 "firmware file %s\n", pci_name(priv->pdev),
378 rc = mwl8k_request_fw(priv, di->fw_image, &priv->fw.ucode);
380 printk(KERN_ERR "%s: Error requesting firmware file %s\n",
381 pci_name(priv->pdev), di->fw_image);
382 mwl8k_release_fw(&priv->fw.helper);
389 struct mwl8k_cmd_pkt {
395 } __attribute__((packed));
401 mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
403 void __iomem *regs = priv->regs;
407 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
408 if (pci_dma_mapping_error(priv->pdev, dma_addr))
411 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
412 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
413 iowrite32(MWL8K_H2A_INT_DOORBELL,
414 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
415 iowrite32(MWL8K_H2A_INT_DUMMY,
416 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
422 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
423 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
424 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
432 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
434 return loops ? 0 : -ETIMEDOUT;
437 static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
438 const u8 *data, size_t length)
440 struct mwl8k_cmd_pkt *cmd;
444 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
448 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
454 int block_size = length > 256 ? 256 : length;
456 memcpy(cmd->payload, data + done, block_size);
457 cmd->length = cpu_to_le16(block_size);
459 rc = mwl8k_send_fw_load_cmd(priv, cmd,
460 sizeof(*cmd) + block_size);
465 length -= block_size;
470 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
478 static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
479 const u8 *data, size_t length)
481 unsigned char *buffer;
482 int may_continue, rc = 0;
483 u32 done, prev_block_size;
485 buffer = kmalloc(1024, GFP_KERNEL);
492 while (may_continue > 0) {
495 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
496 if (block_size & 1) {
500 done += prev_block_size;
501 length -= prev_block_size;
504 if (block_size > 1024 || block_size > length) {
514 if (block_size == 0) {
521 prev_block_size = block_size;
522 memcpy(buffer, data + done, block_size);
524 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
529 if (!rc && length != 0)
537 static int mwl8k_load_firmware(struct ieee80211_hw *hw)
539 struct mwl8k_priv *priv = hw->priv;
540 struct firmware *fw = priv->fw.ucode;
541 struct mwl8k_device_info *di = priv->device_info;
545 if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) {
546 struct firmware *helper = priv->fw.helper;
548 if (helper == NULL) {
549 printk(KERN_ERR "%s: helper image needed but none "
550 "given\n", pci_name(priv->pdev));
554 rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
556 printk(KERN_ERR "%s: unable to load firmware "
557 "helper image\n", pci_name(priv->pdev));
562 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
564 rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
568 printk(KERN_ERR "%s: unable to load firmware image\n",
569 pci_name(priv->pdev));
573 if (di->modes & BIT(NL80211_IFTYPE_AP))
574 iowrite32(MWL8K_MODE_AP, priv->regs + MWL8K_HIU_GEN_PTR);
576 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
583 ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE);
584 if (ready_code == MWL8K_FWAP_READY) {
587 } else if (ready_code == MWL8K_FWSTA_READY) {
596 return loops ? 0 : -ETIMEDOUT;
601 * Defines shared between transmission and reception.
603 /* HT control fields for firmware */
608 } __attribute__((packed));
610 /* Firmware Station database operations */
611 #define MWL8K_STA_DB_ADD_ENTRY 0
612 #define MWL8K_STA_DB_MODIFY_ENTRY 1
613 #define MWL8K_STA_DB_DEL_ENTRY 2
614 #define MWL8K_STA_DB_FLUSH 3
616 /* Peer Entry flags - used to define the type of the peer node */
617 #define MWL8K_PEER_TYPE_ACCESSPOINT 2
619 #define MWL8K_IEEE_LEGACY_DATA_RATES 13
620 #define MWL8K_MCS_BITMAP_SIZE 16
622 struct peer_capability_info {
623 /* Peer type - AP vs. STA. */
626 /* Basic 802.11 capabilities from assoc resp. */
629 /* Set if peer supports 802.11n high throughput (HT). */
632 /* Valid if HT is supported. */
634 __u8 extended_ht_caps;
635 struct ewc_ht_info ewc_info;
637 /* Legacy rate table. Intersection of our rates and peer rates. */
638 __u8 legacy_rates[MWL8K_IEEE_LEGACY_DATA_RATES];
640 /* HT rate table. Intersection of our rates and peer rates. */
641 __u8 ht_rates[MWL8K_MCS_BITMAP_SIZE];
644 /* If set, interoperability mode, no proprietary extensions. */
648 __le16 amsdu_enabled;
649 } __attribute__((packed));
651 /* Inline functions to manipulate QoS field in data descriptor. */
652 static inline u16 mwl8k_qos_setbit_eosp(u16 qos)
654 u16 val_mask = 1 << 4;
656 /* End of Service Period Bit 4 */
657 return qos | val_mask;
660 static inline u16 mwl8k_qos_setbit_ack(u16 qos, u8 ack_policy)
664 u16 qos_mask = ~(val_mask << shift);
666 /* Ack Policy Bit 5-6 */
667 return (qos & qos_mask) | ((ack_policy & val_mask) << shift);
670 static inline u16 mwl8k_qos_setbit_amsdu(u16 qos)
672 u16 val_mask = 1 << 7;
674 /* AMSDU present Bit 7 */
675 return qos | val_mask;
678 static inline u16 mwl8k_qos_setbit_qlen(u16 qos, u8 len)
682 u16 qos_mask = ~(val_mask << shift);
684 /* Queue Length Bits 8-15 */
685 return (qos & qos_mask) | ((len & val_mask) << shift);
688 /* DMA header used by firmware and hardware. */
689 struct mwl8k_dma_data {
691 struct ieee80211_hdr wh;
692 } __attribute__((packed));
694 /* Routines to add/remove DMA header from skb. */
695 static inline void mwl8k_remove_dma_header(struct sk_buff *skb)
697 struct mwl8k_dma_data *tr = (struct mwl8k_dma_data *)skb->data;
698 void *dst, *src = &tr->wh;
699 int hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
700 u16 space = sizeof(struct mwl8k_dma_data) - hdrlen;
702 dst = (void *)tr + space;
704 memmove(dst, src, hdrlen);
705 skb_pull(skb, space);
709 static inline void mwl8k_add_dma_header(struct sk_buff *skb)
711 struct ieee80211_hdr *wh;
713 struct mwl8k_dma_data *tr;
715 wh = (struct ieee80211_hdr *)skb->data;
716 hdrlen = ieee80211_hdrlen(wh->frame_control);
720 * Copy up/down the 802.11 header; the firmware requires
721 * we present a 2-byte payload length followed by a
722 * 4-address header (w/o QoS), followed (optionally) by
723 * any WEP/ExtIV header (but only filled in for CCMP).
725 if (hdrlen != sizeof(struct mwl8k_dma_data))
726 skb_push(skb, sizeof(struct mwl8k_dma_data) - hdrlen);
728 tr = (struct mwl8k_dma_data *)skb->data;
730 memmove(&tr->wh, wh, hdrlen);
733 memset(tr->wh.addr4, 0, ETH_ALEN);
736 * Firmware length is the length of the fully formed "802.11
737 * payload". That is, everything except for the 802.11 header.
738 * This includes all crypto material including the MIC.
740 tr->fwlen = cpu_to_le16(pktlen - hdrlen);
747 #define MWL8K_RX_CTRL_OWNED_BY_HOST 0x02
749 struct mwl8k_rx_desc {
753 __le32 pkt_phys_addr;
754 __le32 next_rxd_phys_addr;
764 } __attribute__((packed));
766 #define MWL8K_RX_DESCS 256
767 #define MWL8K_RX_MAXSZ 3800
769 #define RATE_INFO_SHORTPRE 0x8000
770 #define RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3)
771 #define RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f)
772 #define RATE_INFO_40MHZ 0x0004
773 #define RATE_INFO_SHORTGI 0x0002
774 #define RATE_INFO_MCS_FORMAT 0x0001
776 static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
778 struct mwl8k_priv *priv = hw->priv;
779 struct mwl8k_rx_queue *rxq = priv->rxq + index;
787 size = MWL8K_RX_DESCS * sizeof(struct mwl8k_rx_desc);
789 rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma);
790 if (rxq->rxd == NULL) {
791 printk(KERN_ERR "%s: failed to alloc RX descriptors\n",
792 wiphy_name(hw->wiphy));
795 memset(rxq->rxd, 0, size);
797 rxq->buf = kmalloc(MWL8K_RX_DESCS * sizeof(*rxq->buf), GFP_KERNEL);
798 if (rxq->buf == NULL) {
799 printk(KERN_ERR "%s: failed to alloc RX skbuff list\n",
800 wiphy_name(hw->wiphy));
801 pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma);
804 memset(rxq->buf, 0, MWL8K_RX_DESCS * sizeof(*rxq->buf));
806 for (i = 0; i < MWL8K_RX_DESCS; i++) {
807 struct mwl8k_rx_desc *rx_desc;
810 rx_desc = rxq->rxd + i;
811 nexti = (i + 1) % MWL8K_RX_DESCS;
813 rx_desc->next_rxd_phys_addr =
814 cpu_to_le32(rxq->rxd_dma + nexti * sizeof(*rx_desc));
815 rx_desc->rx_ctrl = MWL8K_RX_CTRL_OWNED_BY_HOST;
821 static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
823 struct mwl8k_priv *priv = hw->priv;
824 struct mwl8k_rx_queue *rxq = priv->rxq + index;
828 while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) {
833 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
840 rxq->tail = (rx + 1) % MWL8K_RX_DESCS;
842 addr = pci_map_single(priv->pdev, skb->data,
843 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE);
845 rxq->rxd[rx].pkt_len = cpu_to_le16(MWL8K_RX_MAXSZ);
846 rxq->rxd[rx].pkt_phys_addr = cpu_to_le32(addr);
847 rxq->buf[rx].skb = skb;
848 pci_unmap_addr_set(&rxq->buf[rx], dma, addr);
850 rxq->rxd[rx].rx_ctrl = 0;
858 /* Must be called only when the card's reception is completely halted */
859 static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
861 struct mwl8k_priv *priv = hw->priv;
862 struct mwl8k_rx_queue *rxq = priv->rxq + index;
865 for (i = 0; i < MWL8K_RX_DESCS; i++) {
866 if (rxq->buf[i].skb != NULL) {
867 pci_unmap_single(priv->pdev,
868 pci_unmap_addr(&rxq->buf[i], dma),
869 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
870 pci_unmap_addr_set(&rxq->buf[i], dma, 0);
872 kfree_skb(rxq->buf[i].skb);
873 rxq->buf[i].skb = NULL;
880 pci_free_consistent(priv->pdev,
881 MWL8K_RX_DESCS * sizeof(struct mwl8k_rx_desc),
882 rxq->rxd, rxq->rxd_dma);
888 * Scan a list of BSSIDs to process for finalize join.
889 * Allows for extension to process multiple BSSIDs.
892 mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
894 return priv->capture_beacon &&
895 ieee80211_is_beacon(wh->frame_control) &&
896 !compare_ether_addr(wh->addr3, priv->capture_bssid);
899 static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
902 struct mwl8k_priv *priv = hw->priv;
904 priv->capture_beacon = false;
905 memset(priv->capture_bssid, 0, ETH_ALEN);
908 * Use GFP_ATOMIC as rxq_process is called from
909 * the primary interrupt handler, memory allocation call
912 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
913 if (priv->beacon_skb != NULL)
914 ieee80211_queue_work(hw, &priv->finalize_join_worker);
917 static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
919 struct mwl8k_priv *priv = hw->priv;
920 struct mwl8k_rx_queue *rxq = priv->rxq + index;
924 while (rxq->rxd_count && limit--) {
925 struct mwl8k_rx_desc *rx_desc;
927 struct ieee80211_rx_status status;
928 struct ieee80211_hdr *wh;
931 rx_desc = rxq->rxd + rxq->head;
932 if (!(rx_desc->rx_ctrl & MWL8K_RX_CTRL_OWNED_BY_HOST))
936 skb = rxq->buf[rxq->head].skb;
939 rxq->buf[rxq->head].skb = NULL;
941 pci_unmap_single(priv->pdev,
942 pci_unmap_addr(&rxq->buf[rxq->head], dma),
943 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
944 pci_unmap_addr_set(&rxq->buf[rxq->head], dma, 0);
946 rxq->head = (rxq->head + 1) % MWL8K_RX_DESCS;
949 skb_put(skb, le16_to_cpu(rx_desc->pkt_len));
950 mwl8k_remove_dma_header(skb);
952 wh = (struct ieee80211_hdr *)skb->data;
955 * Check for a pending join operation. Save a
956 * copy of the beacon and schedule a tasklet to
957 * send a FINALIZE_JOIN command to the firmware.
959 if (mwl8k_capture_bssid(priv, wh))
960 mwl8k_save_beacon(hw, skb);
962 rate_info = le16_to_cpu(rx_desc->rate_info);
964 memset(&status, 0, sizeof(status));
966 status.signal = -rx_desc->rssi;
967 status.noise = -rx_desc->noise_level;
968 status.qual = rx_desc->link_quality;
969 status.antenna = RATE_INFO_ANTSELECT(rate_info);
970 status.rate_idx = RATE_INFO_RATEID(rate_info);
972 if (rate_info & RATE_INFO_SHORTPRE)
973 status.flag |= RX_FLAG_SHORTPRE;
974 if (rate_info & RATE_INFO_40MHZ)
975 status.flag |= RX_FLAG_40MHZ;
976 if (rate_info & RATE_INFO_SHORTGI)
977 status.flag |= RX_FLAG_SHORT_GI;
978 if (rate_info & RATE_INFO_MCS_FORMAT)
979 status.flag |= RX_FLAG_HT;
980 status.band = IEEE80211_BAND_2GHZ;
981 status.freq = ieee80211_channel_to_frequency(rx_desc->channel);
982 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
983 ieee80211_rx_irqsafe(hw, skb);
993 * Packet transmission.
996 /* Transmit packet ACK policy */
997 #define MWL8K_TXD_ACK_POLICY_NORMAL 0
998 #define MWL8K_TXD_ACK_POLICY_BLOCKACK 3
1000 #define MWL8K_TXD_STATUS_OK 0x00000001
1001 #define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
1002 #define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
1003 #define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
1004 #define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
1006 struct mwl8k_tx_desc {
1011 __le32 pkt_phys_addr;
1013 __u8 dest_MAC_addr[ETH_ALEN];
1014 __le32 next_txd_phys_addr;
1019 } __attribute__((packed));
1021 #define MWL8K_TX_DESCS 128
1023 static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1025 struct mwl8k_priv *priv = hw->priv;
1026 struct mwl8k_tx_queue *txq = priv->txq + index;
1030 memset(&txq->stats, 0, sizeof(struct ieee80211_tx_queue_stats));
1031 txq->stats.limit = MWL8K_TX_DESCS;
1035 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1037 txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma);
1038 if (txq->txd == NULL) {
1039 printk(KERN_ERR "%s: failed to alloc TX descriptors\n",
1040 wiphy_name(hw->wiphy));
1043 memset(txq->txd, 0, size);
1045 txq->skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->skb), GFP_KERNEL);
1046 if (txq->skb == NULL) {
1047 printk(KERN_ERR "%s: failed to alloc TX skbuff list\n",
1048 wiphy_name(hw->wiphy));
1049 pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma);
1052 memset(txq->skb, 0, MWL8K_TX_DESCS * sizeof(*txq->skb));
1054 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1055 struct mwl8k_tx_desc *tx_desc;
1058 tx_desc = txq->txd + i;
1059 nexti = (i + 1) % MWL8K_TX_DESCS;
1061 tx_desc->status = 0;
1062 tx_desc->next_txd_phys_addr =
1063 cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc));
1069 static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1071 iowrite32(MWL8K_H2A_INT_PPA_READY,
1072 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1073 iowrite32(MWL8K_H2A_INT_DUMMY,
1074 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1075 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1078 struct mwl8k_txq_info {
1087 static int mwl8k_scan_tx_ring(struct mwl8k_priv *priv,
1088 struct mwl8k_txq_info *txinfo)
1090 int count, desc, status;
1091 struct mwl8k_tx_queue *txq;
1092 struct mwl8k_tx_desc *tx_desc;
1095 memset(txinfo, 0, MWL8K_TX_QUEUES * sizeof(struct mwl8k_txq_info));
1097 for (count = 0; count < MWL8K_TX_QUEUES; count++) {
1098 txq = priv->txq + count;
1099 txinfo[count].len = txq->stats.len;
1100 txinfo[count].head = txq->head;
1101 txinfo[count].tail = txq->tail;
1102 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
1103 tx_desc = txq->txd + desc;
1104 status = le32_to_cpu(tx_desc->status);
1106 if (status & MWL8K_TXD_STATUS_FW_OWNED)
1107 txinfo[count].fw_owned++;
1109 txinfo[count].drv_owned++;
1111 if (tx_desc->pkt_len == 0)
1112 txinfo[count].unused++;
1120 * Must be called with priv->fw_mutex held and tx queues stopped.
1122 static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
1124 struct mwl8k_priv *priv = hw->priv;
1125 DECLARE_COMPLETION_ONSTACK(tx_wait);
1127 unsigned long timeout;
1131 spin_lock_bh(&priv->tx_lock);
1132 count = priv->pending_tx_pkts;
1134 priv->tx_wait = &tx_wait;
1135 spin_unlock_bh(&priv->tx_lock);
1138 struct mwl8k_txq_info txinfo[MWL8K_TX_QUEUES];
1142 timeout = wait_for_completion_timeout(&tx_wait,
1143 msecs_to_jiffies(5000));
1147 spin_lock_bh(&priv->tx_lock);
1148 priv->tx_wait = NULL;
1149 newcount = priv->pending_tx_pkts;
1150 mwl8k_scan_tx_ring(priv, txinfo);
1151 spin_unlock_bh(&priv->tx_lock);
1153 printk(KERN_ERR "%s(%u) TIMEDOUT:5000ms Pend:%u-->%u\n",
1154 __func__, __LINE__, count, newcount);
1156 for (index = 0; index < MWL8K_TX_QUEUES; index++)
1157 printk(KERN_ERR "TXQ:%u L:%u H:%u T:%u FW:%u "
1163 txinfo[index].fw_owned,
1164 txinfo[index].drv_owned,
1165 txinfo[index].unused);
1173 #define MWL8K_TXD_SUCCESS(status) \
1174 ((status) & (MWL8K_TXD_STATUS_OK | \
1175 MWL8K_TXD_STATUS_OK_RETRY | \
1176 MWL8K_TXD_STATUS_OK_MORE_RETRY))
1178 static void mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int force)
1180 struct mwl8k_priv *priv = hw->priv;
1181 struct mwl8k_tx_queue *txq = priv->txq + index;
1184 while (txq->stats.len > 0) {
1186 struct mwl8k_tx_desc *tx_desc;
1189 struct sk_buff *skb;
1190 struct ieee80211_tx_info *info;
1194 tx_desc = txq->txd + tx;
1196 status = le32_to_cpu(tx_desc->status);
1198 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1202 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1205 txq->head = (tx + 1) % MWL8K_TX_DESCS;
1206 BUG_ON(txq->stats.len == 0);
1208 priv->pending_tx_pkts--;
1210 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
1211 size = le16_to_cpu(tx_desc->pkt_len);
1213 txq->skb[tx] = NULL;
1215 BUG_ON(skb == NULL);
1216 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1218 mwl8k_remove_dma_header(skb);
1220 /* Mark descriptor as unused */
1221 tx_desc->pkt_phys_addr = 0;
1222 tx_desc->pkt_len = 0;
1224 info = IEEE80211_SKB_CB(skb);
1225 ieee80211_tx_info_clear_status(info);
1226 if (MWL8K_TXD_SUCCESS(status))
1227 info->flags |= IEEE80211_TX_STAT_ACK;
1229 ieee80211_tx_status_irqsafe(hw, skb);
1234 if (wake && priv->radio_on && !mutex_is_locked(&priv->fw_mutex))
1235 ieee80211_wake_queue(hw, index);
1238 /* must be called only when the card's transmit is completely halted */
1239 static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1241 struct mwl8k_priv *priv = hw->priv;
1242 struct mwl8k_tx_queue *txq = priv->txq + index;
1244 mwl8k_txq_reclaim(hw, index, 1);
1249 pci_free_consistent(priv->pdev,
1250 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
1251 txq->txd, txq->txd_dma);
1256 mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1258 struct mwl8k_priv *priv = hw->priv;
1259 struct ieee80211_tx_info *tx_info;
1260 struct mwl8k_vif *mwl8k_vif;
1261 struct ieee80211_hdr *wh;
1262 struct mwl8k_tx_queue *txq;
1263 struct mwl8k_tx_desc *tx;
1269 wh = (struct ieee80211_hdr *)skb->data;
1270 if (ieee80211_is_data_qos(wh->frame_control))
1271 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1275 mwl8k_add_dma_header(skb);
1276 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
1278 tx_info = IEEE80211_SKB_CB(skb);
1279 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
1281 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1282 u16 seqno = mwl8k_vif->seqno;
1284 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1285 wh->seq_ctrl |= cpu_to_le16(seqno << 4);
1286 mwl8k_vif->seqno = seqno++ % 4096;
1289 /* Setup firmware control bit fields for each frame type. */
1292 if (ieee80211_is_mgmt(wh->frame_control) ||
1293 ieee80211_is_ctl(wh->frame_control)) {
1295 qos = mwl8k_qos_setbit_eosp(qos);
1296 /* Set Queue size to unspecified */
1297 qos = mwl8k_qos_setbit_qlen(qos, 0xff);
1298 } else if (ieee80211_is_data(wh->frame_control)) {
1300 if (is_multicast_ether_addr(wh->addr1))
1301 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
1303 /* Send pkt in an aggregate if AMPDU frame. */
1304 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
1305 qos = mwl8k_qos_setbit_ack(qos,
1306 MWL8K_TXD_ACK_POLICY_BLOCKACK);
1308 qos = mwl8k_qos_setbit_ack(qos,
1309 MWL8K_TXD_ACK_POLICY_NORMAL);
1311 if (qos & IEEE80211_QOS_CONTROL_A_MSDU_PRESENT)
1312 qos = mwl8k_qos_setbit_amsdu(qos);
1315 dma = pci_map_single(priv->pdev, skb->data,
1316 skb->len, PCI_DMA_TODEVICE);
1318 if (pci_dma_mapping_error(priv->pdev, dma)) {
1319 printk(KERN_DEBUG "%s: failed to dma map skb, "
1320 "dropping TX frame.\n", wiphy_name(hw->wiphy));
1322 return NETDEV_TX_OK;
1325 spin_lock_bh(&priv->tx_lock);
1327 txq = priv->txq + index;
1329 BUG_ON(txq->skb[txq->tail] != NULL);
1330 txq->skb[txq->tail] = skb;
1332 tx = txq->txd + txq->tail;
1333 tx->data_rate = txdatarate;
1334 tx->tx_priority = index;
1335 tx->qos_control = cpu_to_le16(qos);
1336 tx->pkt_phys_addr = cpu_to_le32(dma);
1337 tx->pkt_len = cpu_to_le16(skb->len);
1339 tx->peer_id = mwl8k_vif->peer_id;
1341 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
1345 priv->pending_tx_pkts++;
1348 if (txq->tail == MWL8K_TX_DESCS)
1351 if (txq->head == txq->tail)
1352 ieee80211_stop_queue(hw, index);
1354 mwl8k_tx_start(priv);
1356 spin_unlock_bh(&priv->tx_lock);
1358 return NETDEV_TX_OK;
1365 * We have the following requirements for issuing firmware commands:
1366 * - Some commands require that the packet transmit path is idle when
1367 * the command is issued. (For simplicity, we'll just quiesce the
1368 * transmit path for every command.)
1369 * - There are certain sequences of commands that need to be issued to
1370 * the hardware sequentially, with no other intervening commands.
1372 * This leads to an implementation of a "firmware lock" as a mutex that
1373 * can be taken recursively, and which is taken by both the low-level
1374 * command submission function (mwl8k_post_cmd) as well as any users of
1375 * that function that require issuing of an atomic sequence of commands,
1376 * and quiesces the transmit path whenever it's taken.
1378 static int mwl8k_fw_lock(struct ieee80211_hw *hw)
1380 struct mwl8k_priv *priv = hw->priv;
1382 if (priv->fw_mutex_owner != current) {
1385 mutex_lock(&priv->fw_mutex);
1386 ieee80211_stop_queues(hw);
1388 rc = mwl8k_tx_wait_empty(hw);
1390 ieee80211_wake_queues(hw);
1391 mutex_unlock(&priv->fw_mutex);
1396 priv->fw_mutex_owner = current;
1399 priv->fw_mutex_depth++;
1404 static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
1406 struct mwl8k_priv *priv = hw->priv;
1408 if (!--priv->fw_mutex_depth) {
1409 ieee80211_wake_queues(hw);
1410 priv->fw_mutex_owner = NULL;
1411 mutex_unlock(&priv->fw_mutex);
1417 * Command processing.
1420 /* Timeout firmware commands after 2000ms */
1421 #define MWL8K_CMD_TIMEOUT_MS 2000
1423 static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
1425 DECLARE_COMPLETION_ONSTACK(cmd_wait);
1426 struct mwl8k_priv *priv = hw->priv;
1427 void __iomem *regs = priv->regs;
1428 dma_addr_t dma_addr;
1429 unsigned int dma_size;
1431 unsigned long timeout = 0;
1434 cmd->result = 0xffff;
1435 dma_size = le16_to_cpu(cmd->length);
1436 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
1437 PCI_DMA_BIDIRECTIONAL);
1438 if (pci_dma_mapping_error(priv->pdev, dma_addr))
1441 rc = mwl8k_fw_lock(hw);
1443 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1444 PCI_DMA_BIDIRECTIONAL);
1448 priv->hostcmd_wait = &cmd_wait;
1449 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
1450 iowrite32(MWL8K_H2A_INT_DOORBELL,
1451 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1452 iowrite32(MWL8K_H2A_INT_DUMMY,
1453 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1455 timeout = wait_for_completion_timeout(&cmd_wait,
1456 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
1458 priv->hostcmd_wait = NULL;
1460 mwl8k_fw_unlock(hw);
1462 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1463 PCI_DMA_BIDIRECTIONAL);
1466 printk(KERN_ERR "%s: Command %s timeout after %u ms\n",
1467 wiphy_name(hw->wiphy),
1468 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1469 MWL8K_CMD_TIMEOUT_MS);
1472 rc = cmd->result ? -EINVAL : 0;
1474 printk(KERN_ERR "%s: Command %s error 0x%x\n",
1475 wiphy_name(hw->wiphy),
1476 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1477 le16_to_cpu(cmd->result));
1486 struct mwl8k_cmd_get_hw_spec {
1487 struct mwl8k_cmd_pkt header;
1489 __u8 host_interface;
1491 __u8 perm_addr[ETH_ALEN];
1496 __u8 mcs_bitmap[16];
1497 __le32 rx_queue_ptr;
1498 __le32 num_tx_queues;
1499 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1501 __le32 num_tx_desc_per_queue;
1503 } __attribute__((packed));
1505 static int mwl8k_cmd_get_hw_spec(struct ieee80211_hw *hw)
1507 struct mwl8k_priv *priv = hw->priv;
1508 struct mwl8k_cmd_get_hw_spec *cmd;
1512 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1516 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1517 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1519 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1520 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1521 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
1522 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
1523 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1524 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
1525 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1526 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
1528 rc = mwl8k_post_cmd(hw, &cmd->header);
1531 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1532 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
1533 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
1534 priv->hw_rev = cmd->hw_rev;
1542 * CMD_MAC_MULTICAST_ADR.
1544 struct mwl8k_cmd_mac_multicast_adr {
1545 struct mwl8k_cmd_pkt header;
1548 __u8 addr[0][ETH_ALEN];
1551 #define MWL8K_ENABLE_RX_DIRECTED 0x0001
1552 #define MWL8K_ENABLE_RX_MULTICAST 0x0002
1553 #define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
1554 #define MWL8K_ENABLE_RX_BROADCAST 0x0008
1556 static struct mwl8k_cmd_pkt *
1557 __mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti,
1558 int mc_count, struct dev_addr_list *mclist)
1560 struct mwl8k_priv *priv = hw->priv;
1561 struct mwl8k_cmd_mac_multicast_adr *cmd;
1564 if (allmulti || mc_count > priv->num_mcaddrs) {
1569 size = sizeof(*cmd) + mc_count * ETH_ALEN;
1571 cmd = kzalloc(size, GFP_ATOMIC);
1575 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
1576 cmd->header.length = cpu_to_le16(size);
1577 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
1578 MWL8K_ENABLE_RX_BROADCAST);
1581 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
1582 } else if (mc_count) {
1585 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
1586 cmd->numaddr = cpu_to_le16(mc_count);
1587 for (i = 0; i < mc_count && mclist; i++) {
1588 if (mclist->da_addrlen != ETH_ALEN) {
1592 memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN);
1593 mclist = mclist->next;
1597 return &cmd->header;
1601 * CMD_802_11_GET_STAT.
1603 struct mwl8k_cmd_802_11_get_stat {
1604 struct mwl8k_cmd_pkt header;
1606 } __attribute__((packed));
1608 #define MWL8K_STAT_ACK_FAILURE 9
1609 #define MWL8K_STAT_RTS_FAILURE 12
1610 #define MWL8K_STAT_FCS_ERROR 24
1611 #define MWL8K_STAT_RTS_SUCCESS 11
1613 static int mwl8k_cmd_802_11_get_stat(struct ieee80211_hw *hw,
1614 struct ieee80211_low_level_stats *stats)
1616 struct mwl8k_cmd_802_11_get_stat *cmd;
1619 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1623 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
1624 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1626 rc = mwl8k_post_cmd(hw, &cmd->header);
1628 stats->dot11ACKFailureCount =
1629 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
1630 stats->dot11RTSFailureCount =
1631 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
1632 stats->dot11FCSErrorCount =
1633 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
1634 stats->dot11RTSSuccessCount =
1635 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
1643 * CMD_802_11_RADIO_CONTROL.
1645 struct mwl8k_cmd_802_11_radio_control {
1646 struct mwl8k_cmd_pkt header;
1650 } __attribute__((packed));
1653 mwl8k_cmd_802_11_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
1655 struct mwl8k_priv *priv = hw->priv;
1656 struct mwl8k_cmd_802_11_radio_control *cmd;
1659 if (enable == priv->radio_on && !force)
1662 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1666 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
1667 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1668 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1669 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
1670 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
1672 rc = mwl8k_post_cmd(hw, &cmd->header);
1676 priv->radio_on = enable;
1681 static int mwl8k_cmd_802_11_radio_disable(struct ieee80211_hw *hw)
1683 return mwl8k_cmd_802_11_radio_control(hw, 0, 0);
1686 static int mwl8k_cmd_802_11_radio_enable(struct ieee80211_hw *hw)
1688 return mwl8k_cmd_802_11_radio_control(hw, 1, 0);
1692 mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
1694 struct mwl8k_priv *priv;
1696 if (hw == NULL || hw->priv == NULL)
1700 priv->radio_short_preamble = short_preamble;
1702 return mwl8k_cmd_802_11_radio_control(hw, 1, 1);
1706 * CMD_802_11_RF_TX_POWER.
1708 #define MWL8K_TX_POWER_LEVEL_TOTAL 8
1710 struct mwl8k_cmd_802_11_rf_tx_power {
1711 struct mwl8k_cmd_pkt header;
1713 __le16 support_level;
1714 __le16 current_level;
1716 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
1717 } __attribute__((packed));
1719 static int mwl8k_cmd_802_11_rf_tx_power(struct ieee80211_hw *hw, int dBm)
1721 struct mwl8k_cmd_802_11_rf_tx_power *cmd;
1724 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1728 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
1729 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1730 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1731 cmd->support_level = cpu_to_le16(dBm);
1733 rc = mwl8k_post_cmd(hw, &cmd->header);
1742 struct mwl8k_cmd_set_pre_scan {
1743 struct mwl8k_cmd_pkt header;
1744 } __attribute__((packed));
1746 static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
1748 struct mwl8k_cmd_set_pre_scan *cmd;
1751 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1755 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
1756 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1758 rc = mwl8k_post_cmd(hw, &cmd->header);
1765 * CMD_SET_POST_SCAN.
1767 struct mwl8k_cmd_set_post_scan {
1768 struct mwl8k_cmd_pkt header;
1770 __u8 bssid[ETH_ALEN];
1771 } __attribute__((packed));
1774 mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, __u8 *mac)
1776 struct mwl8k_cmd_set_post_scan *cmd;
1779 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1783 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
1784 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1786 memcpy(cmd->bssid, mac, ETH_ALEN);
1788 rc = mwl8k_post_cmd(hw, &cmd->header);
1795 * CMD_SET_RF_CHANNEL.
1797 struct mwl8k_cmd_set_rf_channel {
1798 struct mwl8k_cmd_pkt header;
1800 __u8 current_channel;
1801 __le32 channel_flags;
1802 } __attribute__((packed));
1804 static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
1805 struct ieee80211_channel *channel)
1807 struct mwl8k_cmd_set_rf_channel *cmd;
1810 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1814 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
1815 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1816 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1817 cmd->current_channel = channel->hw_value;
1818 if (channel->band == IEEE80211_BAND_2GHZ)
1819 cmd->channel_flags = cpu_to_le32(0x00000081);
1821 cmd->channel_flags = cpu_to_le32(0x00000000);
1823 rc = mwl8k_post_cmd(hw, &cmd->header);
1832 struct mwl8k_cmd_set_slot {
1833 struct mwl8k_cmd_pkt header;
1836 } __attribute__((packed));
1838 static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
1840 struct mwl8k_cmd_set_slot *cmd;
1843 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1847 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
1848 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1849 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1850 cmd->short_slot = short_slot_time;
1852 rc = mwl8k_post_cmd(hw, &cmd->header);
1861 struct mwl8k_cmd_mimo_config {
1862 struct mwl8k_cmd_pkt header;
1864 __u8 rx_antenna_map;
1865 __u8 tx_antenna_map;
1866 } __attribute__((packed));
1868 static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
1870 struct mwl8k_cmd_mimo_config *cmd;
1873 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1877 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
1878 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1879 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
1880 cmd->rx_antenna_map = rx;
1881 cmd->tx_antenna_map = tx;
1883 rc = mwl8k_post_cmd(hw, &cmd->header);
1890 * CMD_ENABLE_SNIFFER.
1892 struct mwl8k_cmd_enable_sniffer {
1893 struct mwl8k_cmd_pkt header;
1895 } __attribute__((packed));
1897 static int mwl8k_enable_sniffer(struct ieee80211_hw *hw, bool enable)
1899 struct mwl8k_cmd_enable_sniffer *cmd;
1902 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1906 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
1907 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1908 cmd->action = cpu_to_le32(!!enable);
1910 rc = mwl8k_post_cmd(hw, &cmd->header);
1919 struct mwl8k_cmd_set_mac_addr {
1920 struct mwl8k_cmd_pkt header;
1921 __u8 mac_addr[ETH_ALEN];
1922 } __attribute__((packed));
1924 static int mwl8k_set_mac_addr(struct ieee80211_hw *hw, u8 *mac)
1926 struct mwl8k_cmd_set_mac_addr *cmd;
1929 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1933 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR);
1934 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1935 memcpy(cmd->mac_addr, mac, ETH_ALEN);
1937 rc = mwl8k_post_cmd(hw, &cmd->header);
1945 * CMD_SET_RATEADAPT_MODE.
1947 struct mwl8k_cmd_set_rate_adapt_mode {
1948 struct mwl8k_cmd_pkt header;
1951 } __attribute__((packed));
1953 static int mwl8k_cmd_setrateadaptmode(struct ieee80211_hw *hw, __u16 mode)
1955 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
1958 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1962 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
1963 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1964 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1965 cmd->mode = cpu_to_le16(mode);
1967 rc = mwl8k_post_cmd(hw, &cmd->header);
1976 struct mwl8k_cmd_set_wmm {
1977 struct mwl8k_cmd_pkt header;
1979 } __attribute__((packed));
1981 static int mwl8k_set_wmm(struct ieee80211_hw *hw, bool enable)
1983 struct mwl8k_priv *priv = hw->priv;
1984 struct mwl8k_cmd_set_wmm *cmd;
1987 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1991 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
1992 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1993 cmd->action = cpu_to_le16(!!enable);
1995 rc = mwl8k_post_cmd(hw, &cmd->header);
1999 priv->wmm_enabled = enable;
2005 * CMD_SET_RTS_THRESHOLD.
2007 struct mwl8k_cmd_rts_threshold {
2008 struct mwl8k_cmd_pkt header;
2011 } __attribute__((packed));
2013 static int mwl8k_rts_threshold(struct ieee80211_hw *hw,
2014 u16 action, u16 threshold)
2016 struct mwl8k_cmd_rts_threshold *cmd;
2019 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2023 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
2024 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2025 cmd->action = cpu_to_le16(action);
2026 cmd->threshold = cpu_to_le16(threshold);
2028 rc = mwl8k_post_cmd(hw, &cmd->header);
2035 * CMD_SET_EDCA_PARAMS.
2037 struct mwl8k_cmd_set_edca_params {
2038 struct mwl8k_cmd_pkt header;
2040 /* See MWL8K_SET_EDCA_XXX below */
2043 /* TX opportunity in units of 32 us */
2046 /* Log exponent of max contention period: 0...15*/
2049 /* Log exponent of min contention period: 0...15 */
2052 /* Adaptive interframe spacing in units of 32us */
2055 /* TX queue to configure */
2057 } __attribute__((packed));
2059 #define MWL8K_SET_EDCA_CW 0x01
2060 #define MWL8K_SET_EDCA_TXOP 0x02
2061 #define MWL8K_SET_EDCA_AIFS 0x04
2063 #define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
2064 MWL8K_SET_EDCA_TXOP | \
2065 MWL8K_SET_EDCA_AIFS)
2068 mwl8k_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
2069 __u16 cw_min, __u16 cw_max,
2070 __u8 aifs, __u16 txop)
2072 struct mwl8k_cmd_set_edca_params *cmd;
2075 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2080 * Queues 0 (BE) and 1 (BK) are swapped in hardware for
2083 qnum ^= !(qnum >> 1);
2085 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
2086 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2087 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
2088 cmd->txop = cpu_to_le16(txop);
2089 cmd->log_cw_max = (u8)ilog2(cw_max + 1);
2090 cmd->log_cw_min = (u8)ilog2(cw_min + 1);
2094 rc = mwl8k_post_cmd(hw, &cmd->header);
2101 * CMD_FINALIZE_JOIN.
2104 /* FJ beacon buffer size is compiled into the firmware. */
2105 #define MWL8K_FJ_BEACON_MAXLEN 128
2107 struct mwl8k_cmd_finalize_join {
2108 struct mwl8k_cmd_pkt header;
2109 __le32 sleep_interval; /* Number of beacon periods to sleep */
2110 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
2111 } __attribute__((packed));
2113 static int mwl8k_finalize_join(struct ieee80211_hw *hw, void *frame,
2114 __u16 framelen, __u16 dtim)
2116 struct mwl8k_cmd_finalize_join *cmd;
2117 struct ieee80211_mgmt *payload = frame;
2125 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2129 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
2130 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2131 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
2133 hdrlen = ieee80211_hdrlen(payload->frame_control);
2135 payload_len = framelen > hdrlen ? framelen - hdrlen : 0;
2137 /* XXX TBD Might just have to abort and return an error */
2138 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2139 printk(KERN_ERR "%s(): WARNING: Incomplete beacon "
2140 "sent to firmware. Sz=%u MAX=%u\n", __func__,
2141 payload_len, MWL8K_FJ_BEACON_MAXLEN);
2143 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2144 payload_len = MWL8K_FJ_BEACON_MAXLEN;
2146 if (payload && payload_len)
2147 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
2149 rc = mwl8k_post_cmd(hw, &cmd->header);
2157 struct mwl8k_cmd_update_sta_db {
2158 struct mwl8k_cmd_pkt header;
2160 /* See STADB_ACTION_TYPE */
2163 /* Peer MAC address */
2164 __u8 peer_addr[ETH_ALEN];
2168 /* Peer info - valid during add/update. */
2169 struct peer_capability_info peer_info;
2170 } __attribute__((packed));
2172 static int mwl8k_cmd_update_sta_db(struct ieee80211_hw *hw,
2173 struct ieee80211_vif *vif, __u32 action)
2175 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2176 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2177 struct mwl8k_cmd_update_sta_db *cmd;
2178 struct peer_capability_info *peer_info;
2179 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2183 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2187 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
2188 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2190 cmd->action = cpu_to_le32(action);
2191 peer_info = &cmd->peer_info;
2192 memcpy(cmd->peer_addr, mv_vif->bssid, ETH_ALEN);
2195 case MWL8K_STA_DB_ADD_ENTRY:
2196 case MWL8K_STA_DB_MODIFY_ENTRY:
2197 /* Build peer_info block */
2198 peer_info->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
2199 peer_info->basic_caps = cpu_to_le16(info->assoc_capability);
2200 peer_info->interop = 1;
2201 peer_info->amsdu_enabled = 0;
2203 rates = peer_info->legacy_rates;
2204 for (count = 0; count < mv_vif->legacy_nrates; count++)
2205 rates[count] = bitrates[count].hw_value;
2207 rc = mwl8k_post_cmd(hw, &cmd->header);
2209 mv_vif->peer_id = peer_info->station_id;
2213 case MWL8K_STA_DB_DEL_ENTRY:
2214 case MWL8K_STA_DB_FLUSH:
2216 rc = mwl8k_post_cmd(hw, &cmd->header);
2218 mv_vif->peer_id = 0;
2229 #define MWL8K_RATE_INDEX_MAX_ARRAY 14
2231 #define MWL8K_FRAME_PROT_DISABLED 0x00
2232 #define MWL8K_FRAME_PROT_11G 0x07
2233 #define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
2234 #define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
2236 struct mwl8k_cmd_update_set_aid {
2237 struct mwl8k_cmd_pkt header;
2240 /* AP's MAC address (BSSID) */
2241 __u8 bssid[ETH_ALEN];
2242 __le16 protection_mode;
2243 __u8 supp_rates[MWL8K_RATE_INDEX_MAX_ARRAY];
2244 } __attribute__((packed));
2246 static int mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
2247 struct ieee80211_vif *vif)
2249 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2250 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2251 struct mwl8k_cmd_update_set_aid *cmd;
2252 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2257 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2261 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
2262 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2263 cmd->aid = cpu_to_le16(info->aid);
2265 memcpy(cmd->bssid, mv_vif->bssid, ETH_ALEN);
2267 if (info->use_cts_prot) {
2268 prot_mode = MWL8K_FRAME_PROT_11G;
2270 switch (info->ht_operation_mode &
2271 IEEE80211_HT_OP_MODE_PROTECTION) {
2272 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2273 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
2275 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2276 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
2279 prot_mode = MWL8K_FRAME_PROT_DISABLED;
2283 cmd->protection_mode = cpu_to_le16(prot_mode);
2285 for (count = 0; count < mv_vif->legacy_nrates; count++)
2286 cmd->supp_rates[count] = bitrates[count].hw_value;
2288 rc = mwl8k_post_cmd(hw, &cmd->header);
2297 struct mwl8k_cmd_update_rateset {
2298 struct mwl8k_cmd_pkt header;
2299 __u8 legacy_rates[MWL8K_RATE_INDEX_MAX_ARRAY];
2301 /* Bitmap for supported MCS codes. */
2302 __u8 mcs_set[MWL8K_IEEE_LEGACY_DATA_RATES];
2303 __u8 reserved[MWL8K_IEEE_LEGACY_DATA_RATES];
2304 } __attribute__((packed));
2306 static int mwl8k_update_rateset(struct ieee80211_hw *hw,
2307 struct ieee80211_vif *vif)
2309 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2310 struct mwl8k_cmd_update_rateset *cmd;
2311 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2315 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2319 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
2320 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2322 for (count = 0; count < mv_vif->legacy_nrates; count++)
2323 cmd->legacy_rates[count] = bitrates[count].hw_value;
2325 rc = mwl8k_post_cmd(hw, &cmd->header);
2332 * CMD_USE_FIXED_RATE.
2334 #define MWL8K_RATE_TABLE_SIZE 8
2335 #define MWL8K_UCAST_RATE 0
2336 #define MWL8K_USE_AUTO_RATE 0x0002
2338 struct mwl8k_rate_entry {
2339 /* Set to 1 if HT rate, 0 if legacy. */
2342 /* Set to 1 to use retry_count field. */
2343 __le32 enable_retry;
2345 /* Specified legacy rate or MCS. */
2348 /* Number of allowed retries. */
2350 } __attribute__((packed));
2352 struct mwl8k_rate_table {
2353 /* 1 to allow specified rate and below */
2354 __le32 allow_rate_drop;
2356 struct mwl8k_rate_entry rate_entry[MWL8K_RATE_TABLE_SIZE];
2357 } __attribute__((packed));
2359 struct mwl8k_cmd_use_fixed_rate {
2360 struct mwl8k_cmd_pkt header;
2362 struct mwl8k_rate_table rate_table;
2364 /* Unicast, Broadcast or Multicast */
2368 } __attribute__((packed));
2370 static int mwl8k_cmd_use_fixed_rate(struct ieee80211_hw *hw,
2371 u32 action, u32 rate_type, struct mwl8k_rate_table *rate_table)
2373 struct mwl8k_cmd_use_fixed_rate *cmd;
2377 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2381 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2382 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2384 cmd->action = cpu_to_le32(action);
2385 cmd->rate_type = cpu_to_le32(rate_type);
2387 if (rate_table != NULL) {
2389 * Copy over each field manually so that endian
2390 * conversion can be done.
2392 cmd->rate_table.allow_rate_drop =
2393 cpu_to_le32(rate_table->allow_rate_drop);
2394 cmd->rate_table.num_rates =
2395 cpu_to_le32(rate_table->num_rates);
2397 for (count = 0; count < rate_table->num_rates; count++) {
2398 struct mwl8k_rate_entry *dst =
2399 &cmd->rate_table.rate_entry[count];
2400 struct mwl8k_rate_entry *src =
2401 &rate_table->rate_entry[count];
2403 dst->is_ht_rate = cpu_to_le32(src->is_ht_rate);
2404 dst->enable_retry = cpu_to_le32(src->enable_retry);
2405 dst->rate = cpu_to_le32(src->rate);
2406 dst->retry_count = cpu_to_le32(src->retry_count);
2410 rc = mwl8k_post_cmd(hw, &cmd->header);
2418 * Interrupt handling.
2420 static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
2422 struct ieee80211_hw *hw = dev_id;
2423 struct mwl8k_priv *priv = hw->priv;
2426 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2427 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2432 if (status & MWL8K_A2H_INT_TX_DONE)
2433 tasklet_schedule(&priv->tx_reclaim_task);
2435 if (status & MWL8K_A2H_INT_RX_READY) {
2436 while (rxq_process(hw, 0, 1))
2437 rxq_refill(hw, 0, 1);
2440 if (status & MWL8K_A2H_INT_OPC_DONE) {
2441 if (priv->hostcmd_wait != NULL)
2442 complete(priv->hostcmd_wait);
2445 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
2446 if (!mutex_is_locked(&priv->fw_mutex) &&
2447 priv->radio_on && priv->pending_tx_pkts)
2448 mwl8k_tx_start(priv);
2456 * Core driver operations.
2458 static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2460 struct mwl8k_priv *priv = hw->priv;
2461 int index = skb_get_queue_mapping(skb);
2464 if (priv->current_channel == NULL) {
2465 printk(KERN_DEBUG "%s: dropped TX frame since radio "
2466 "disabled\n", wiphy_name(hw->wiphy));
2468 return NETDEV_TX_OK;
2471 rc = mwl8k_txq_xmit(hw, index, skb);
2476 static int mwl8k_start(struct ieee80211_hw *hw)
2478 struct mwl8k_priv *priv = hw->priv;
2481 rc = request_irq(priv->pdev->irq, &mwl8k_interrupt,
2482 IRQF_SHARED, MWL8K_NAME, hw);
2484 printk(KERN_ERR "%s: failed to register IRQ handler\n",
2485 wiphy_name(hw->wiphy));
2489 /* Enable tx reclaim tasklet */
2490 tasklet_enable(&priv->tx_reclaim_task);
2492 /* Enable interrupts */
2493 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2495 rc = mwl8k_fw_lock(hw);
2497 rc = mwl8k_cmd_802_11_radio_enable(hw);
2500 rc = mwl8k_cmd_set_pre_scan(hw);
2503 rc = mwl8k_cmd_set_post_scan(hw,
2504 "\x00\x00\x00\x00\x00\x00");
2507 rc = mwl8k_cmd_setrateadaptmode(hw, 0);
2510 rc = mwl8k_set_wmm(hw, 0);
2513 rc = mwl8k_enable_sniffer(hw, 0);
2515 mwl8k_fw_unlock(hw);
2519 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2520 free_irq(priv->pdev->irq, hw);
2521 tasklet_disable(&priv->tx_reclaim_task);
2527 static void mwl8k_stop(struct ieee80211_hw *hw)
2529 struct mwl8k_priv *priv = hw->priv;
2532 mwl8k_cmd_802_11_radio_disable(hw);
2534 ieee80211_stop_queues(hw);
2536 /* Disable interrupts */
2537 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2538 free_irq(priv->pdev->irq, hw);
2540 /* Stop finalize join worker */
2541 cancel_work_sync(&priv->finalize_join_worker);
2542 if (priv->beacon_skb != NULL)
2543 dev_kfree_skb(priv->beacon_skb);
2545 /* Stop tx reclaim tasklet */
2546 tasklet_disable(&priv->tx_reclaim_task);
2548 /* Return all skbs to mac80211 */
2549 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2550 mwl8k_txq_reclaim(hw, i, 1);
2553 static int mwl8k_add_interface(struct ieee80211_hw *hw,
2554 struct ieee80211_if_init_conf *conf)
2556 struct mwl8k_priv *priv = hw->priv;
2557 struct mwl8k_vif *mwl8k_vif;
2560 * We only support one active interface at a time.
2562 if (priv->vif != NULL)
2566 * We only support managed interfaces for now.
2568 if (conf->type != NL80211_IFTYPE_STATION)
2572 * Reject interface creation if sniffer mode is active, as
2573 * STA operation is mutually exclusive with hardware sniffer
2576 if (priv->sniffer_enabled) {
2577 printk(KERN_INFO "%s: unable to create STA "
2578 "interface due to sniffer mode being enabled\n",
2579 wiphy_name(hw->wiphy));
2583 /* Clean out driver private area */
2584 mwl8k_vif = MWL8K_VIF(conf->vif);
2585 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
2587 /* Set and save the mac address */
2588 mwl8k_set_mac_addr(hw, conf->mac_addr);
2589 memcpy(mwl8k_vif->mac_addr, conf->mac_addr, ETH_ALEN);
2591 /* Back pointer to parent config block */
2592 mwl8k_vif->priv = priv;
2594 /* Setup initial PHY parameters */
2595 memcpy(mwl8k_vif->legacy_rates,
2596 priv->rates, sizeof(mwl8k_vif->legacy_rates));
2597 mwl8k_vif->legacy_nrates = ARRAY_SIZE(priv->rates);
2599 /* Set Initial sequence number to zero */
2600 mwl8k_vif->seqno = 0;
2602 priv->vif = conf->vif;
2603 priv->current_channel = NULL;
2608 static void mwl8k_remove_interface(struct ieee80211_hw *hw,
2609 struct ieee80211_if_init_conf *conf)
2611 struct mwl8k_priv *priv = hw->priv;
2613 if (priv->vif == NULL)
2616 mwl8k_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
2621 static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
2623 struct ieee80211_conf *conf = &hw->conf;
2624 struct mwl8k_priv *priv = hw->priv;
2627 if (conf->flags & IEEE80211_CONF_IDLE) {
2628 mwl8k_cmd_802_11_radio_disable(hw);
2629 priv->current_channel = NULL;
2633 rc = mwl8k_fw_lock(hw);
2637 rc = mwl8k_cmd_802_11_radio_enable(hw);
2641 rc = mwl8k_cmd_set_rf_channel(hw, conf->channel);
2645 priv->current_channel = conf->channel;
2647 if (conf->power_level > 18)
2648 conf->power_level = 18;
2649 rc = mwl8k_cmd_802_11_rf_tx_power(hw, conf->power_level);
2653 if (mwl8k_cmd_mimo_config(hw, 0x7, 0x7))
2657 mwl8k_fw_unlock(hw);
2662 static void mwl8k_bss_info_changed(struct ieee80211_hw *hw,
2663 struct ieee80211_vif *vif,
2664 struct ieee80211_bss_conf *info,
2667 struct mwl8k_priv *priv = hw->priv;
2668 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
2671 if (changed & BSS_CHANGED_BSSID)
2672 memcpy(mwl8k_vif->bssid, info->bssid, ETH_ALEN);
2674 if ((changed & BSS_CHANGED_ASSOC) == 0)
2677 priv->capture_beacon = false;
2679 rc = mwl8k_fw_lock(hw);
2684 memcpy(&mwl8k_vif->bss_info, info,
2685 sizeof(struct ieee80211_bss_conf));
2688 rc = mwl8k_update_rateset(hw, vif);
2692 /* Turn on rate adaptation */
2693 rc = mwl8k_cmd_use_fixed_rate(hw, MWL8K_USE_AUTO_RATE,
2694 MWL8K_UCAST_RATE, NULL);
2698 /* Set radio preamble */
2699 rc = mwl8k_set_radio_preamble(hw, info->use_short_preamble);
2704 rc = mwl8k_cmd_set_slot(hw, info->use_short_slot);
2708 /* Update peer rate info */
2709 rc = mwl8k_cmd_update_sta_db(hw, vif,
2710 MWL8K_STA_DB_MODIFY_ENTRY);
2715 rc = mwl8k_cmd_set_aid(hw, vif);
2720 * Finalize the join. Tell rx handler to process
2721 * next beacon from our BSSID.
2723 memcpy(priv->capture_bssid, mwl8k_vif->bssid, ETH_ALEN);
2724 priv->capture_beacon = true;
2726 rc = mwl8k_cmd_update_sta_db(hw, vif, MWL8K_STA_DB_DEL_ENTRY);
2727 memset(&mwl8k_vif->bss_info, 0,
2728 sizeof(struct ieee80211_bss_conf));
2729 memset(mwl8k_vif->bssid, 0, ETH_ALEN);
2733 mwl8k_fw_unlock(hw);
2736 static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
2737 int mc_count, struct dev_addr_list *mclist)
2739 struct mwl8k_cmd_pkt *cmd;
2742 * Synthesize and return a command packet that programs the
2743 * hardware multicast address filter. At this point we don't
2744 * know whether FIF_ALLMULTI is being requested, but if it is,
2745 * we'll end up throwing this packet away and creating a new
2746 * one in mwl8k_configure_filter().
2748 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_count, mclist);
2750 return (unsigned long)cmd;
2754 mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw,
2755 unsigned int changed_flags,
2756 unsigned int *total_flags)
2758 struct mwl8k_priv *priv = hw->priv;
2761 * Hardware sniffer mode is mutually exclusive with STA
2762 * operation, so refuse to enable sniffer mode if a STA
2763 * interface is active.
2765 if (priv->vif != NULL) {
2766 if (net_ratelimit())
2767 printk(KERN_INFO "%s: not enabling sniffer "
2768 "mode because STA interface is active\n",
2769 wiphy_name(hw->wiphy));
2773 if (!priv->sniffer_enabled) {
2774 if (mwl8k_enable_sniffer(hw, 1))
2776 priv->sniffer_enabled = true;
2779 *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI |
2780 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL |
2786 static void mwl8k_configure_filter(struct ieee80211_hw *hw,
2787 unsigned int changed_flags,
2788 unsigned int *total_flags,
2791 struct mwl8k_priv *priv = hw->priv;
2792 struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast;
2795 * Enable hardware sniffer mode if FIF_CONTROL or
2796 * FIF_OTHER_BSS is requested.
2798 if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) &&
2799 mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) {
2804 /* Clear unsupported feature flags */
2805 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
2807 if (mwl8k_fw_lock(hw))
2810 if (priv->sniffer_enabled) {
2811 mwl8k_enable_sniffer(hw, 0);
2812 priv->sniffer_enabled = false;
2815 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
2816 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
2818 * Disable the BSS filter.
2820 mwl8k_cmd_set_pre_scan(hw);
2825 * Enable the BSS filter.
2827 * If there is an active STA interface, use that
2828 * interface's BSSID, otherwise use a dummy one
2829 * (where the OUI part needs to be nonzero for
2830 * the BSSID to be accepted by POST_SCAN).
2832 bssid = "\x01\x00\x00\x00\x00\x00";
2833 if (priv->vif != NULL)
2834 bssid = MWL8K_VIF(priv->vif)->bssid;
2836 mwl8k_cmd_set_post_scan(hw, bssid);
2841 * If FIF_ALLMULTI is being requested, throw away the command
2842 * packet that ->prepare_multicast() built and replace it with
2843 * a command packet that enables reception of all multicast
2846 if (*total_flags & FIF_ALLMULTI) {
2848 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, 0, NULL);
2852 mwl8k_post_cmd(hw, cmd);
2856 mwl8k_fw_unlock(hw);
2859 static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2861 return mwl8k_rts_threshold(hw, MWL8K_CMD_SET, value);
2864 static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2865 const struct ieee80211_tx_queue_params *params)
2867 struct mwl8k_priv *priv = hw->priv;
2870 rc = mwl8k_fw_lock(hw);
2872 if (!priv->wmm_enabled)
2873 rc = mwl8k_set_wmm(hw, 1);
2876 rc = mwl8k_set_edca_params(hw, queue,
2882 mwl8k_fw_unlock(hw);
2888 static int mwl8k_get_tx_stats(struct ieee80211_hw *hw,
2889 struct ieee80211_tx_queue_stats *stats)
2891 struct mwl8k_priv *priv = hw->priv;
2892 struct mwl8k_tx_queue *txq;
2895 spin_lock_bh(&priv->tx_lock);
2896 for (index = 0; index < MWL8K_TX_QUEUES; index++) {
2897 txq = priv->txq + index;
2898 memcpy(&stats[index], &txq->stats,
2899 sizeof(struct ieee80211_tx_queue_stats));
2901 spin_unlock_bh(&priv->tx_lock);
2906 static int mwl8k_get_stats(struct ieee80211_hw *hw,
2907 struct ieee80211_low_level_stats *stats)
2909 return mwl8k_cmd_802_11_get_stat(hw, stats);
2912 static const struct ieee80211_ops mwl8k_ops = {
2914 .start = mwl8k_start,
2916 .add_interface = mwl8k_add_interface,
2917 .remove_interface = mwl8k_remove_interface,
2918 .config = mwl8k_config,
2919 .bss_info_changed = mwl8k_bss_info_changed,
2920 .prepare_multicast = mwl8k_prepare_multicast,
2921 .configure_filter = mwl8k_configure_filter,
2922 .set_rts_threshold = mwl8k_set_rts_threshold,
2923 .conf_tx = mwl8k_conf_tx,
2924 .get_tx_stats = mwl8k_get_tx_stats,
2925 .get_stats = mwl8k_get_stats,
2928 static void mwl8k_tx_reclaim_handler(unsigned long data)
2931 struct ieee80211_hw *hw = (struct ieee80211_hw *) data;
2932 struct mwl8k_priv *priv = hw->priv;
2934 spin_lock_bh(&priv->tx_lock);
2935 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2936 mwl8k_txq_reclaim(hw, i, 0);
2938 if (priv->tx_wait != NULL && !priv->pending_tx_pkts) {
2939 complete(priv->tx_wait);
2940 priv->tx_wait = NULL;
2942 spin_unlock_bh(&priv->tx_lock);
2945 static void mwl8k_finalize_join_worker(struct work_struct *work)
2947 struct mwl8k_priv *priv =
2948 container_of(work, struct mwl8k_priv, finalize_join_worker);
2949 struct sk_buff *skb = priv->beacon_skb;
2950 u8 dtim = MWL8K_VIF(priv->vif)->bss_info.dtim_period;
2952 mwl8k_finalize_join(priv->hw, skb->data, skb->len, dtim);
2955 priv->beacon_skb = NULL;
2958 static struct mwl8k_device_info di_8687 = {
2959 .part_name = "88w8687",
2960 .helper_image = "mwl8k/helper_8687.fw",
2961 .fw_image = "mwl8k/fmimage_8687.fw",
2964 static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = {
2966 PCI_VDEVICE(MARVELL, 0x2a2b),
2967 .driver_data = (unsigned long)&di_8687,
2969 PCI_VDEVICE(MARVELL, 0x2a30),
2970 .driver_data = (unsigned long)&di_8687,
2974 MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table);
2976 static int __devinit mwl8k_probe(struct pci_dev *pdev,
2977 const struct pci_device_id *id)
2979 static int printed_version = 0;
2980 struct ieee80211_hw *hw;
2981 struct mwl8k_priv *priv;
2985 if (!printed_version) {
2986 printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
2987 printed_version = 1;
2990 rc = pci_enable_device(pdev);
2992 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
2997 rc = pci_request_regions(pdev, MWL8K_NAME);
2999 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
3004 pci_set_master(pdev);
3006 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
3008 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
3016 priv->device_info = (void *)id->driver_data;
3017 priv->sniffer_enabled = false;
3018 priv->wmm_enabled = false;
3019 priv->pending_tx_pkts = 0;
3021 SET_IEEE80211_DEV(hw, &pdev->dev);
3022 pci_set_drvdata(pdev, hw);
3024 priv->sram = pci_iomap(pdev, 0, 0x10000);
3025 if (priv->sram == NULL) {
3026 printk(KERN_ERR "%s: Cannot map device SRAM\n",
3027 wiphy_name(hw->wiphy));
3032 * If BAR0 is a 32 bit BAR, the register BAR will be BAR1.
3033 * If BAR0 is a 64 bit BAR, the register BAR will be BAR2.
3035 priv->regs = pci_iomap(pdev, 1, 0x10000);
3036 if (priv->regs == NULL) {
3037 priv->regs = pci_iomap(pdev, 2, 0x10000);
3038 if (priv->regs == NULL) {
3039 printk(KERN_ERR "%s: Cannot map device registers\n",
3040 wiphy_name(hw->wiphy));
3045 memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels));
3046 priv->band.band = IEEE80211_BAND_2GHZ;
3047 priv->band.channels = priv->channels;
3048 priv->band.n_channels = ARRAY_SIZE(mwl8k_channels);
3049 priv->band.bitrates = priv->rates;
3050 priv->band.n_bitrates = ARRAY_SIZE(mwl8k_rates);
3051 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
3053 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(mwl8k_rates));
3054 memcpy(priv->rates, mwl8k_rates, sizeof(mwl8k_rates));
3057 * Extra headroom is the size of the required DMA header
3058 * minus the size of the smallest 802.11 frame (CTS frame).
3060 hw->extra_tx_headroom =
3061 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
3063 hw->channel_change_time = 10;
3065 hw->queues = MWL8K_TX_QUEUES;
3067 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
3069 /* Set rssi and noise values to dBm */
3070 hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM;
3071 hw->vif_data_size = sizeof(struct mwl8k_vif);
3074 /* Set default radio state and preamble */
3076 priv->radio_short_preamble = 0;
3078 /* Finalize join worker */
3079 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
3081 /* TX reclaim tasklet */
3082 tasklet_init(&priv->tx_reclaim_task,
3083 mwl8k_tx_reclaim_handler, (unsigned long)hw);
3084 tasklet_disable(&priv->tx_reclaim_task);
3086 /* Power management cookie */
3087 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
3088 if (priv->cookie == NULL)
3091 rc = mwl8k_rxq_init(hw, 0);
3094 rxq_refill(hw, 0, INT_MAX);
3096 mutex_init(&priv->fw_mutex);
3097 priv->fw_mutex_owner = NULL;
3098 priv->fw_mutex_depth = 0;
3099 priv->hostcmd_wait = NULL;
3101 spin_lock_init(&priv->tx_lock);
3103 priv->tx_wait = NULL;
3105 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
3106 rc = mwl8k_txq_init(hw, i);
3108 goto err_free_queues;
3111 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
3112 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3113 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
3114 iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
3116 rc = request_irq(priv->pdev->irq, &mwl8k_interrupt,
3117 IRQF_SHARED, MWL8K_NAME, hw);
3119 printk(KERN_ERR "%s: failed to register IRQ handler\n",
3120 wiphy_name(hw->wiphy));
3121 goto err_free_queues;
3124 /* Reset firmware and hardware */
3125 mwl8k_hw_reset(priv);
3127 /* Ask userland hotplug daemon for the device firmware */
3128 rc = mwl8k_request_firmware(priv);
3130 printk(KERN_ERR "%s: Firmware files not found\n",
3131 wiphy_name(hw->wiphy));
3135 /* Load firmware into hardware */
3136 rc = mwl8k_load_firmware(hw);
3138 printk(KERN_ERR "%s: Cannot start firmware\n",
3139 wiphy_name(hw->wiphy));
3140 goto err_stop_firmware;
3143 /* Reclaim memory once firmware is successfully loaded */
3144 mwl8k_release_firmware(priv);
3147 * Temporarily enable interrupts. Initial firmware host
3148 * commands use interrupts and avoids polling. Disable
3149 * interrupts when done.
3151 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3153 /* Get config data, mac addrs etc */
3154 rc = mwl8k_cmd_get_hw_spec(hw);
3156 printk(KERN_ERR "%s: Cannot initialise firmware\n",
3157 wiphy_name(hw->wiphy));
3158 goto err_stop_firmware;
3161 /* Turn radio off */
3162 rc = mwl8k_cmd_802_11_radio_disable(hw);
3164 printk(KERN_ERR "%s: Cannot disable\n", wiphy_name(hw->wiphy));
3165 goto err_stop_firmware;
3168 /* Clear MAC address */
3169 rc = mwl8k_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
3171 printk(KERN_ERR "%s: Cannot clear MAC address\n",
3172 wiphy_name(hw->wiphy));
3173 goto err_stop_firmware;
3176 /* Disable interrupts */
3177 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3178 free_irq(priv->pdev->irq, hw);
3180 rc = ieee80211_register_hw(hw);
3182 printk(KERN_ERR "%s: Cannot register device\n",
3183 wiphy_name(hw->wiphy));
3184 goto err_stop_firmware;
3187 printk(KERN_INFO "%s: %s v%d, %pM, %s firmware %u.%u.%u.%u\n",
3188 wiphy_name(hw->wiphy), priv->device_info->part_name,
3189 priv->hw_rev, hw->wiphy->perm_addr,
3190 priv->ap_fw ? "AP" : "STA",
3191 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
3192 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
3197 mwl8k_hw_reset(priv);
3198 mwl8k_release_firmware(priv);
3201 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3202 free_irq(priv->pdev->irq, hw);
3205 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3206 mwl8k_txq_deinit(hw, i);
3207 mwl8k_rxq_deinit(hw, 0);
3210 if (priv->cookie != NULL)
3211 pci_free_consistent(priv->pdev, 4,
3212 priv->cookie, priv->cookie_dma);
3214 if (priv->regs != NULL)
3215 pci_iounmap(pdev, priv->regs);
3217 if (priv->sram != NULL)
3218 pci_iounmap(pdev, priv->sram);
3220 pci_set_drvdata(pdev, NULL);
3221 ieee80211_free_hw(hw);
3224 pci_release_regions(pdev);
3225 pci_disable_device(pdev);
3230 static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
3232 printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
3235 static void __devexit mwl8k_remove(struct pci_dev *pdev)
3237 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
3238 struct mwl8k_priv *priv;
3245 ieee80211_stop_queues(hw);
3247 ieee80211_unregister_hw(hw);
3249 /* Remove tx reclaim tasklet */
3250 tasklet_kill(&priv->tx_reclaim_task);
3253 mwl8k_hw_reset(priv);
3255 /* Return all skbs to mac80211 */
3256 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3257 mwl8k_txq_reclaim(hw, i, 1);
3259 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3260 mwl8k_txq_deinit(hw, i);
3262 mwl8k_rxq_deinit(hw, 0);
3264 pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
3266 pci_iounmap(pdev, priv->regs);
3267 pci_iounmap(pdev, priv->sram);
3268 pci_set_drvdata(pdev, NULL);
3269 ieee80211_free_hw(hw);
3270 pci_release_regions(pdev);
3271 pci_disable_device(pdev);
3274 static struct pci_driver mwl8k_driver = {
3276 .id_table = mwl8k_pci_id_table,
3277 .probe = mwl8k_probe,
3278 .remove = __devexit_p(mwl8k_remove),
3279 .shutdown = __devexit_p(mwl8k_shutdown),
3282 static int __init mwl8k_init(void)
3284 return pci_register_driver(&mwl8k_driver);
3287 static void __exit mwl8k_exit(void)
3289 pci_unregister_driver(&mwl8k_driver);
3292 module_init(mwl8k_init);
3293 module_exit(mwl8k_exit);
3295 MODULE_DESCRIPTION(MWL8K_DESC);
3296 MODULE_VERSION(MWL8K_VERSION);
3297 MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
3298 MODULE_LICENSE("GPL");