drivers/net/wireless/rt2x00/rt2800pci.c

   1 /*
   2         Copyright (C) 2009 Ivo van Doorn <IvDoorn@gmail.com>
   3         Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   4         Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
   5         Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
   6         Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
   7         Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
   8         Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
   9         Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
  10         <http://rt2x00.serialmonkey.com>
  11
  12         This program is free software; you can redistribute it and/or modify
  13         it under the terms of the GNU General Public License as published by
  14         the Free Software Foundation; either version 2 of the License, or
  15         (at your option) any later version.
  16
  17         This program is distributed in the hope that it will be useful,
  18         but WITHOUT ANY WARRANTY; without even the implied warranty of
  19         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20         GNU General Public License for more details.
  21
  22         You should have received a copy of the GNU General Public License
  23         along with this program; if not, write to the
  24         Free Software Foundation, Inc.,
  25         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  26  */
  27
  28 /*
  29         Module: rt2800pci
  30         Abstract: rt2800pci device specific routines.
  31         Supported chipsets: RT2800E & RT2800ED.
  32  */
  33
  34 #include <linux/crc-ccitt.h>
  35 #include <linux/delay.h>
  36 #include <linux/etherdevice.h>
  37 #include <linux/init.h>
  38 #include <linux/kernel.h>
  39 #include <linux/module.h>
  40 #include <linux/pci.h>
  41 #include <linux/platform_device.h>
  42 #include <linux/eeprom_93cx6.h>
  43
  44 #include "rt2x00.h"
  45 #include "rt2x00pci.h"
  46 #include "rt2x00soc.h"
  47 #include "rt2800lib.h"
  48 #include "rt2800.h"
  49 #include "rt2800pci.h"
  50
  51 /*
  52  * Allow hardware encryption to be disabled.
  53  */
  54 static int modparam_nohwcrypt = 0;
  55 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
  56 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  57
  58 static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
  59 {
  60         unsigned int i;
  61         u32 reg;
  62
  63         /*
  64          * SOC devices don't support MCU requests.
  65          */
  66         if (rt2x00_is_soc(rt2x00dev))
  67                 return;
  68
  69         for (i = 0; i < 200; i++) {
  70                 rt2800_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
  71
  72                 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
  73                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
  74                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
  75                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
  76                         break;
  77
  78                 udelay(REGISTER_BUSY_DELAY);
  79         }
  80
  81         if (i == 200)
  82                 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
  83
  84         rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
  85         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
  86 }
  87
  88 #ifdef CONFIG_RT2800PCI_SOC
  89 static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
  90 {
  91         u32 *base_addr = (u32 *) KSEG1ADDR(0x1F040000); /* XXX for RT3052 */
  92
  93         memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
  94 }
  95 #else
  96 static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
  97 {
  98 }
  99 #endif /* CONFIG_RT2800PCI_SOC */
 100
 101 #ifdef CONFIG_RT2800PCI_PCI
 102 static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 103 {
 104         struct rt2x00_dev *rt2x00dev = eeprom->data;
 105         u32 reg;
 106
 107         rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
 108
 109         eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
 110         eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
 111         eeprom->reg_data_clock =
 112             !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
 113         eeprom->reg_chip_select =
 114             !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
 115 }
 116
 117 static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 118 {
 119         struct rt2x00_dev *rt2x00dev = eeprom->data;
 120         u32 reg = 0;
 121
 122         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
 123         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
 124         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
 125                            !!eeprom->reg_data_clock);
 126         rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
 127                            !!eeprom->reg_chip_select);
 128
 129         rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
 130 }
 131
 132 static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
 133 {
 134         struct eeprom_93cx6 eeprom;
 135         u32 reg;
 136
 137         rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
 138
 139         eeprom.data = rt2x00dev;
 140         eeprom.register_read = rt2800pci_eepromregister_read;
 141         eeprom.register_write = rt2800pci_eepromregister_write;
 142         eeprom.width = !rt2x00_get_field32(reg, E2PROM_CSR_TYPE) ?
 143             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
 144         eeprom.reg_data_in = 0;
 145         eeprom.reg_data_out = 0;
 146         eeprom.reg_data_clock = 0;
 147         eeprom.reg_chip_select = 0;
 148
 149         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
 150                                EEPROM_SIZE / sizeof(u16));
 151 }
 152
 153 static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
 154 {
 155         return rt2800_efuse_detect(rt2x00dev);
 156 }
 157
 158 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
 159 {
 160         rt2800_read_eeprom_efuse(rt2x00dev);
 161 }
 162 #else
 163 static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
 164 {
 165 }
 166
 167 static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
 168 {
 169         return 0;
 170 }
 171
 172 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
 173 {
 174 }
 175 #endif /* CONFIG_RT2800PCI_PCI */
 176
 177 /*
 178  * Firmware functions
 179  */
 180 static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
 181 {
 182         return FIRMWARE_RT2860;
 183 }
 184
 185 static int rt2800pci_check_firmware(struct rt2x00_dev *rt2x00dev,
 186                                     const u8 *data, const size_t len)
 187 {
 188         u16 fw_crc;
 189         u16 crc;
 190
 191         /*
 192          * Only support 8kb firmware files.
 193          */
 194         if (len != 8192)
 195                 return FW_BAD_LENGTH;
 196
 197         /*
 198          * The last 2 bytes in the firmware array are the crc checksum itself,
 199          * this means that we should never pass those 2 bytes to the crc
 200          * algorithm.
 201          */
 202         fw_crc = (data[len - 2] << 8 | data[len - 1]);
 203
 204         /*
 205          * Use the crc ccitt algorithm.
 206          * This will return the same value as the legacy driver which
 207          * used bit ordering reversion on the both the firmware bytes
 208          * before input input as well as on the final output.
 209          * Obviously using crc ccitt directly is much more efficient.
 210          */
 211         crc = crc_ccitt(~0, data, len - 2);
 212
 213         /*
 214          * There is a small difference between the crc-itu-t + bitrev and
 215          * the crc-ccitt crc calculation. In the latter method the 2 bytes
 216          * will be swapped, use swab16 to convert the crc to the correct
 217          * value.
 218          */
 219         crc = swab16(crc);
 220
 221         return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
 222 }
 223
 224 static int rt2800pci_load_firmware(struct rt2x00_dev *rt2x00dev,
 225                                    const u8 *data, const size_t len)
 226 {
 227         unsigned int i;
 228         u32 reg;
 229
 230         /*
 231          * Wait for stable hardware.
 232          */
 233         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 234                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
 235                 if (reg && reg != ~0)
 236                         break;
 237                 msleep(1);
 238         }
 239
 240         if (i == REGISTER_BUSY_COUNT) {
 241                 ERROR(rt2x00dev, "Unstable hardware.\n");
 242                 return -EBUSY;
 243         }
 244
 245         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
 246         rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
 247
 248         /*
 249          * Disable DMA, will be reenabled later when enabling
 250          * the radio.
 251          */
 252         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 253         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 254         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
 255         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 256         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
 257         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 258         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 259
 260         /*
 261          * enable Host program ram write selection
 262          */
 263         reg = 0;
 264         rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
 265         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
 266
 267         /*
 268          * Write firmware to device.
 269          */
 270         rt2800_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
 271                                       data, len);
 272
 273         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
 274         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
 275
 276         /*
 277          * Wait for device to stabilize.
 278          */
 279         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 280                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
 281                 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
 282                         break;
 283                 msleep(1);
 284         }
 285
 286         if (i == REGISTER_BUSY_COUNT) {
 287                 ERROR(rt2x00dev, "PBF system register not ready.\n");
 288                 return -EBUSY;
 289         }
 290
 291         /*
 292          * Disable interrupts
 293          */
 294         rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_RADIO_IRQ_OFF);
 295
 296         /*
 297          * Initialize BBP R/W access agent
 298          */
 299         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
 300         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
 301
 302         return 0;
 303 }
 304
 305 /*
 306  * Initialization functions.
 307  */
 308 static bool rt2800pci_get_entry_state(struct queue_entry *entry)
 309 {
 310         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 311         u32 word;
 312
 313         if (entry->queue->qid == QID_RX) {
 314                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 315
 316                 return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
 317         } else {
 318                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 319
 320                 return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
 321         }
 322 }
 323
 324 static void rt2800pci_clear_entry(struct queue_entry *entry)
 325 {
 326         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 327         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 328         u32 word;
 329
 330         if (entry->queue->qid == QID_RX) {
 331                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 332                 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
 333                 rt2x00_desc_write(entry_priv->desc, 0, word);
 334
 335                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 336                 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
 337                 rt2x00_desc_write(entry_priv->desc, 1, word);
 338         } else {
 339                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 340                 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
 341                 rt2x00_desc_write(entry_priv->desc, 1, word);
 342         }
 343 }
 344
 345 static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
 346 {
 347         struct queue_entry_priv_pci *entry_priv;
 348         u32 reg;
 349
 350         /*
 351          * Initialize registers.
 352          */
 353         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
 354         rt2800_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
 355         rt2800_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
 356         rt2800_register_write(rt2x00dev, TX_CTX_IDX0, 0);
 357         rt2800_register_write(rt2x00dev, TX_DTX_IDX0, 0);
 358
 359         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
 360         rt2800_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
 361         rt2800_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
 362         rt2800_register_write(rt2x00dev, TX_CTX_IDX1, 0);
 363         rt2800_register_write(rt2x00dev, TX_DTX_IDX1, 0);
 364
 365         entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
 366         rt2800_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
 367         rt2800_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
 368         rt2800_register_write(rt2x00dev, TX_CTX_IDX2, 0);
 369         rt2800_register_write(rt2x00dev, TX_DTX_IDX2, 0);
 370
 371         entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
 372         rt2800_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
 373         rt2800_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
 374         rt2800_register_write(rt2x00dev, TX_CTX_IDX3, 0);
 375         rt2800_register_write(rt2x00dev, TX_DTX_IDX3, 0);
 376
 377         entry_priv = rt2x00dev->rx->entries[0].priv_data;
 378         rt2800_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
 379         rt2800_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
 380         rt2800_register_write(rt2x00dev, RX_CRX_IDX, rt2x00dev->rx[0].limit - 1);
 381         rt2800_register_write(rt2x00dev, RX_DRX_IDX, 0);
 382
 383         /*
 384          * Enable global DMA configuration
 385          */
 386         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 387         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 388         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 389         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 390         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 391
 392         rt2800_register_write(rt2x00dev, DELAY_INT_CFG, 0);
 393
 394         return 0;
 395 }
 396
 397 /*
 398  * Device state switch handlers.
 399  */
 400 static void rt2800pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
 401                                 enum dev_state state)
 402 {
 403         u32 reg;
 404
 405         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
 406         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
 407                            (state == STATE_RADIO_RX_ON) ||
 408                            (state == STATE_RADIO_RX_ON_LINK));
 409         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
 410 }
 411
 412 static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
 413                                  enum dev_state state)
 414 {
 415         int mask = (state == STATE_RADIO_IRQ_ON);
 416         u32 reg;
 417
 418         /*
 419          * When interrupts are being enabled, the interrupt registers
 420          * should clear the register to assure a clean state.
 421          */
 422         if (state == STATE_RADIO_IRQ_ON) {
 423                 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
 424                 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
 425         }
 426
 427         rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg);
 428         rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, mask);
 429         rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, mask);
 430         rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
 431         rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, mask);
 432         rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, mask);
 433         rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, mask);
 434         rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, mask);
 435         rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, mask);
 436         rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, mask);
 437         rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, mask);
 438         rt2x00_set_field32(&reg, INT_MASK_CSR_RXTX_COHERENT, mask);
 439         rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, mask);
 440         rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, mask);
 441         rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, mask);
 442         rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, mask);
 443         rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, mask);
 444         rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, mask);
 445         rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, mask);
 446         rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
 447 }
 448
 449 static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
 450 {
 451         u32 reg;
 452
 453         /*
 454          * Reset DMA indexes
 455          */
 456         rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
 457         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
 458         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
 459         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
 460         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
 461         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
 462         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
 463         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
 464         rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
 465
 466         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
 467         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
 468
 469         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
 470
 471         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
 472         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
 473         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
 474         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
 475
 476         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
 477
 478         return 0;
 479 }
 480
 481 static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
 482 {
 483         u32 reg;
 484         u16 word;
 485
 486         /*
 487          * Initialize all registers.
 488          */
 489         if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
 490                      rt2800pci_init_queues(rt2x00dev) ||
 491                      rt2800_init_registers(rt2x00dev) ||
 492                      rt2800_wait_wpdma_ready(rt2x00dev) ||
 493                      rt2800_init_bbp(rt2x00dev) ||
 494                      rt2800_init_rfcsr(rt2x00dev)))
 495                 return -EIO;
 496
 497         /*
 498          * Send signal to firmware during boot time.
 499          */
 500         rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
 501
 502         /*
 503          * Enable RX.
 504          */
 505         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
 506         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
 507         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
 508         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
 509
 510         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 511         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
 512         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
 513         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
 514         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 515         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 516
 517         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
 518         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
 519         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
 520         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
 521
 522         /*
 523          * Initialize LED control
 524          */
 525         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
 526         rt2800_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
 527                               word & 0xff, (word >> 8) & 0xff);
 528
 529         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
 530         rt2800_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
 531                               word & 0xff, (word >> 8) & 0xff);
 532
 533         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
 534         rt2800_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
 535                               word & 0xff, (word >> 8) & 0xff);
 536
 537         return 0;
 538 }
 539
 540 static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
 541 {
 542         u32 reg;
 543
 544         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 545         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 546         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
 547         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 548         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
 549         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 550         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 551
 552         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
 553         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
 554         rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
 555
 556         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280);
 557
 558         rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
 559         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
 560         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
 561         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
 562         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
 563         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
 564         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
 565         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
 566         rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
 567
 568         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
 569         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
 570
 571         /* Wait for DMA, ignore error */
 572         rt2800_wait_wpdma_ready(rt2x00dev);
 573 }
 574
 575 static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
 576                                enum dev_state state)
 577 {
 578         /*
 579          * Always put the device to sleep (even when we intend to wakeup!)
 580          * if the device is booting and wasn't asleep it will return
 581          * failure when attempting to wakeup.
 582          */
 583         rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
 584
 585         if (state == STATE_AWAKE) {
 586                 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0);
 587                 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP);
 588         }
 589
 590         return 0;
 591 }
 592
 593 static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
 594                                       enum dev_state state)
 595 {
 596         int retval = 0;
 597
 598         switch (state) {
 599         case STATE_RADIO_ON:
 600                 /*
 601                  * Before the radio can be enabled, the device first has
 602                  * to be woken up. After that it needs a bit of time
 603                  * to be fully awake and then the radio can be enabled.
 604                  */
 605                 rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
 606                 msleep(1);
 607                 retval = rt2800pci_enable_radio(rt2x00dev);
 608                 break;
 609         case STATE_RADIO_OFF:
 610                 /*
 611                  * After the radio has been disabled, the device should
 612                  * be put to sleep for powersaving.
 613                  */
 614                 rt2800pci_disable_radio(rt2x00dev);
 615                 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
 616                 break;
 617         case STATE_RADIO_RX_ON:
 618         case STATE_RADIO_RX_ON_LINK:
 619         case STATE_RADIO_RX_OFF:
 620         case STATE_RADIO_RX_OFF_LINK:
 621                 rt2800pci_toggle_rx(rt2x00dev, state);
 622                 break;
 623         case STATE_RADIO_IRQ_ON:
 624         case STATE_RADIO_IRQ_OFF:
 625                 rt2800pci_toggle_irq(rt2x00dev, state);
 626                 break;
 627         case STATE_DEEP_SLEEP:
 628         case STATE_SLEEP:
 629         case STATE_STANDBY:
 630         case STATE_AWAKE:
 631                 retval = rt2800pci_set_state(rt2x00dev, state);
 632                 break;
 633         default:
 634                 retval = -ENOTSUPP;
 635                 break;
 636         }
 637
 638         if (unlikely(retval))
 639                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
 640                       state, retval);
 641
 642         return retval;
 643 }
 644
 645 /*
 646  * TX descriptor initialization
 647  */
 648 static void rt2800pci_write_tx_data(struct queue_entry* entry,
 649                                     struct txentry_desc *txdesc)
 650 {
 651         __le32 *txwi = (__le32 *) entry->skb->data;
 652
 653         rt2800_write_txwi(txwi, txdesc);
 654 }
 655
 656
 657 static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
 658                                     struct sk_buff *skb,
 659                                     struct txentry_desc *txdesc)
 660 {
 661         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
 662         struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
 663         __le32 *txd = entry_priv->desc;
 664         u32 word;
 665
 666         /*
 667          * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
 668          * must contains a TXWI structure + 802.11 header + padding + 802.11
 669          * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
 670          * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
 671          * data. It means that LAST_SEC0 is always 0.
 672          */
 673
 674         /*
 675          * Initialize TX descriptor
 676          */
 677         rt2x00_desc_read(txd, 0, &word);
 678         rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
 679         rt2x00_desc_write(txd, 0, word);
 680
 681         rt2x00_desc_read(txd, 1, &word);
 682         rt2x00_set_field32(&word, TXD_W1_SD_LEN1, skb->len);
 683         rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
 684                            !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
 685         rt2x00_set_field32(&word, TXD_W1_BURST,
 686                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
 687         rt2x00_set_field32(&word, TXD_W1_SD_LEN0, TXWI_DESC_SIZE);
 688         rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
 689         rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
 690         rt2x00_desc_write(txd, 1, word);
 691
 692         rt2x00_desc_read(txd, 2, &word);
 693         rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
 694                            skbdesc->skb_dma + TXWI_DESC_SIZE);
 695         rt2x00_desc_write(txd, 2, word);
 696
 697         rt2x00_desc_read(txd, 3, &word);
 698         rt2x00_set_field32(&word, TXD_W3_WIV,
 699                            !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
 700         rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
 701         rt2x00_desc_write(txd, 3, word);
 702
 703         /*
 704          * Register descriptor details in skb frame descriptor.
 705          */
 706         skbdesc->desc = txd;
 707         skbdesc->desc_len = TXD_DESC_SIZE;
 708 }
 709
 710 /*
 711  * TX data initialization
 712  */
 713 static void rt2800pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
 714                                     const enum data_queue_qid queue_idx)
 715 {
 716         struct data_queue *queue;
 717         unsigned int idx, qidx = 0;
 718
 719         if (queue_idx > QID_HCCA && queue_idx != QID_MGMT)
 720                 return;
 721
 722         queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
 723         idx = queue->index[Q_INDEX];
 724
 725         if (queue_idx == QID_MGMT)
 726                 qidx = 5;
 727         else
 728                 qidx = queue_idx;
 729
 730         rt2800_register_write(rt2x00dev, TX_CTX_IDX(qidx), idx);
 731 }
 732
 733 static void rt2800pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
 734                                     const enum data_queue_qid qid)
 735 {
 736         u32 reg;
 737
 738         if (qid == QID_BEACON) {
 739                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, 0);
 740                 return;
 741         }
 742
 743         rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
 744         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, (qid == QID_AC_BE));
 745         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, (qid == QID_AC_BK));
 746         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, (qid == QID_AC_VI));
 747         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, (qid == QID_AC_VO));
 748         rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
 749 }
 750
 751 /*
 752  * RX control handlers
 753  */
 754 static void rt2800pci_fill_rxdone(struct queue_entry *entry,
 755                                   struct rxdone_entry_desc *rxdesc)
 756 {
 757         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 758         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 759         __le32 *rxd = entry_priv->desc;
 760         u32 word;
 761
 762         rt2x00_desc_read(rxd, 3, &word);
 763
 764         if (rt2x00_get_field32(word, RXD_W3_CRC_ERROR))
 765                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
 766
 767         /*
 768          * Unfortunately we don't know the cipher type used during
 769          * decryption. This prevents us from correct providing
 770          * correct statistics through debugfs.
 771          */
 772         rxdesc->cipher_status = rt2x00_get_field32(word, RXD_W3_CIPHER_ERROR);
 773
 774         if (rt2x00_get_field32(word, RXD_W3_DECRYPTED)) {
 775                 /*
 776                  * Hardware has stripped IV/EIV data from 802.11 frame during
 777                  * decryption. Unfortunately the descriptor doesn't contain
 778                  * any fields with the EIV/IV data either, so they can't
 779                  * be restored by rt2x00lib.
 780                  */
 781                 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
 782
 783                 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
 784                         rxdesc->flags |= RX_FLAG_DECRYPTED;
 785                 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
 786                         rxdesc->flags |= RX_FLAG_MMIC_ERROR;
 787         }
 788
 789         if (rt2x00_get_field32(word, RXD_W3_MY_BSS))
 790                 rxdesc->dev_flags |= RXDONE_MY_BSS;
 791
 792         if (rt2x00_get_field32(word, RXD_W3_L2PAD))
 793                 rxdesc->dev_flags |= RXDONE_L2PAD;
 794
 795         /*
 796          * Process the RXWI structure that is at the start of the buffer.
 797          */
 798         rt2800_process_rxwi(entry->skb, rxdesc);
 799
 800         /*
 801          * Set RX IDX in register to inform hardware that we have handled
 802          * this entry and it is available for reuse again.
 803          */
 804         rt2800_register_write(rt2x00dev, RX_CRX_IDX, entry->entry_idx);
 805 }
 806
 807 /*
 808  * Interrupt functions.
 809  */
 810 static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
 811 {
 812         struct data_queue *queue;
 813         struct queue_entry *entry;
 814         __le32 *txwi;
 815         struct txdone_entry_desc txdesc;
 816         u32 word;
 817         u32 reg;
 818         int wcid, ack, pid, tx_wcid, tx_ack, tx_pid;
 819         u16 mcs, real_mcs;
 820         int i;
 821
 822         /*
 823          * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO
 824          * at most X times and also stop processing once the TX_STA_FIFO_VALID
 825          * flag is not set anymore.
 826          *
 827          * The legacy drivers use X=TX_RING_SIZE but state in a comment
 828          * that the TX_STA_FIFO stack has a size of 16. We stick to our
 829          * tx ring size for now.
 830          */
 831         for (i = 0; i < TX_ENTRIES; i++) {
 832                 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &reg);
 833                 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
 834                         break;
 835
 836                 wcid    = rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
 837                 ack     = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED);
 838                 pid     = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
 839
 840                 /*
 841                  * Skip this entry when it contains an invalid
 842                  * queue identication number.
 843                  */
 844                 if (pid <= 0 || pid > QID_RX)
 845                         continue;
 846
 847                 queue = rt2x00queue_get_queue(rt2x00dev, pid - 1);
 848                 if (unlikely(!queue))
 849                         continue;
 850
 851                 /*
 852                  * Inside each queue, we process each entry in a chronological
 853                  * order. We first check that the queue is not empty.
 854                  */
 855                 if (rt2x00queue_empty(queue))
 856                         continue;
 857                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
 858
 859                 /* Check if we got a match by looking at WCID/ACK/PID
 860                  * fields */
 861                 txwi = (__le32 *) entry->skb->data;
 862
 863                 rt2x00_desc_read(txwi, 1, &word);
 864                 tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
 865                 tx_ack  = rt2x00_get_field32(word, TXWI_W1_ACK);
 866                 tx_pid  = rt2x00_get_field32(word, TXWI_W1_PACKETID);
 867
 868                 if ((wcid != tx_wcid) || (ack != tx_ack) || (pid != tx_pid))
 869                         WARNING(rt2x00dev, "invalid TX_STA_FIFO content\n");
 870
 871                 /*
 872                  * Obtain the status about this packet.
 873                  */
 874                 txdesc.flags = 0;
 875                 rt2x00_desc_read(txwi, 0, &word);
 876                 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
 877                 real_mcs = rt2x00_get_field32(reg, TX_STA_FIFO_MCS);
 878
 879                 /*
 880                  * Ralink has a retry mechanism using a global fallback
 881                  * table. We setup this fallback table to try the immediate
 882                  * lower rate for all rates. In the TX_STA_FIFO, the MCS field
 883                  * always contains the MCS used for the last transmission, be
 884                  * it successful or not.
 885                  */
 886                 if (rt2x00_get_field32(reg, TX_STA_FIFO_TX_SUCCESS)) {
 887                         /*
 888                          * Transmission succeeded. The number of retries is
 889                          * mcs - real_mcs
 890                          */
 891                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
 892                         txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
 893                 } else {
 894                         /*
 895                          * Transmission failed. The number of retries is
 896                          * always 7 in this case (for a total number of 8
 897                          * frames sent).
 898                          */
 899                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
 900                         txdesc.retry = 7;
 901                 }
 902
 903                 /*
 904                  * the frame was retried at least once
 905                  * -> hw used fallback rates
 906                  */
 907                 if (txdesc.retry)
 908                         __set_bit(TXDONE_FALLBACK, &txdesc.flags);
 909
 910                 rt2x00lib_txdone(entry, &txdesc);
 911         }
 912 }
 913
 914 static void rt2800pci_wakeup(struct rt2x00_dev *rt2x00dev)
 915 {
 916         struct ieee80211_conf conf = { .flags = 0 };
 917         struct rt2x00lib_conf libconf = { .conf = &conf };
 918
 919         rt2800_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
 920 }
 921
 922 static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
 923 {
 924         struct rt2x00_dev *rt2x00dev = dev_instance;
 925         u32 reg;
 926
 927         /* Read status and ACK all interrupts */
 928         rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
 929         rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
 930
 931         if (!reg)
 932                 return IRQ_NONE;
 933
 934         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
 935                 return IRQ_HANDLED;
 936
 937         /*
 938          * 1 - Rx ring done interrupt.
 939          */
 940         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
 941                 rt2x00pci_rxdone(rt2x00dev);
 942
 943         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS))
 944                 rt2800pci_txdone(rt2x00dev);
 945
 946         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP))
 947                 rt2800pci_wakeup(rt2x00dev);
 948
 949         return IRQ_HANDLED;
 950 }
 951
 952 /*
 953  * Device probe functions.
 954  */
 955 static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
 956 {
 957         /*
 958          * Read EEPROM into buffer
 959          */
 960         if (rt2x00_is_soc(rt2x00dev))
 961                 rt2800pci_read_eeprom_soc(rt2x00dev);
 962         else if (rt2800pci_efuse_detect(rt2x00dev))
 963                 rt2800pci_read_eeprom_efuse(rt2x00dev);
 964         else
 965                 rt2800pci_read_eeprom_pci(rt2x00dev);
 966
 967         return rt2800_validate_eeprom(rt2x00dev);
 968 }
 969
 970 static const struct rt2800_ops rt2800pci_rt2800_ops = {
 971         .register_read          = rt2x00pci_register_read,
 972         .register_read_lock     = rt2x00pci_register_read, /* same for PCI */
 973         .register_write         = rt2x00pci_register_write,
 974         .register_write_lock    = rt2x00pci_register_write, /* same for PCI */
 975
 976         .register_multiread     = rt2x00pci_register_multiread,
 977         .register_multiwrite    = rt2x00pci_register_multiwrite,
 978
 979         .regbusy_read           = rt2x00pci_regbusy_read,
 980
 981         .drv_init_registers     = rt2800pci_init_registers,
 982 };
 983
 984 static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
 985 {
 986         int retval;
 987
 988         rt2x00dev->priv = (void *)&rt2800pci_rt2800_ops;
 989
 990         /*
 991          * Allocate eeprom data.
 992          */
 993         retval = rt2800pci_validate_eeprom(rt2x00dev);
 994         if (retval)
 995                 return retval;
 996
 997         retval = rt2800_init_eeprom(rt2x00dev);
 998         if (retval)
 999                 return retval;
1000
1001         /*
1002          * Initialize hw specifications.
1003          */
1004         retval = rt2800_probe_hw_mode(rt2x00dev);
1005         if (retval)
1006                 return retval;
1007
1008         /*
1009          * This device has multiple filters for control frames
1010          * and has a separate filter for PS Poll frames.
1011          */
1012         __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
1013         __set_bit(DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL, &rt2x00dev->flags);
1014
1015         /*
1016          * This device requires firmware.
1017          */
1018         if (!rt2x00_is_soc(rt2x00dev))
1019                 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
1020         __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1021         __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags);
1022         if (!modparam_nohwcrypt)
1023                 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
1024
1025         /*
1026          * Set the rssi offset.
1027          */
1028         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1029
1030         return 0;
1031 }
1032
1033 static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
1034         .irq_handler            = rt2800pci_interrupt,
1035         .probe_hw               = rt2800pci_probe_hw,
1036         .get_firmware_name      = rt2800pci_get_firmware_name,
1037         .check_firmware         = rt2800pci_check_firmware,
1038         .load_firmware          = rt2800pci_load_firmware,
1039         .initialize             = rt2x00pci_initialize,
1040         .uninitialize           = rt2x00pci_uninitialize,
1041         .get_entry_state        = rt2800pci_get_entry_state,
1042         .clear_entry            = rt2800pci_clear_entry,
1043         .set_device_state       = rt2800pci_set_device_state,
1044         .rfkill_poll            = rt2800_rfkill_poll,
1045         .link_stats             = rt2800_link_stats,
1046         .reset_tuner            = rt2800_reset_tuner,
1047         .link_tuner             = rt2800_link_tuner,
1048         .write_tx_desc          = rt2800pci_write_tx_desc,
1049         .write_tx_data          = rt2800pci_write_tx_data,
1050         .write_beacon           = rt2800_write_beacon,
1051         .kick_tx_queue          = rt2800pci_kick_tx_queue,
1052         .kill_tx_queue          = rt2800pci_kill_tx_queue,
1053         .fill_rxdone            = rt2800pci_fill_rxdone,
1054         .config_shared_key      = rt2800_config_shared_key,
1055         .config_pairwise_key    = rt2800_config_pairwise_key,
1056         .config_filter          = rt2800_config_filter,
1057         .config_intf            = rt2800_config_intf,
1058         .config_erp             = rt2800_config_erp,
1059         .config_ant             = rt2800_config_ant,
1060         .config                 = rt2800_config,
1061 };
1062
1063 static const struct data_queue_desc rt2800pci_queue_rx = {
1064         .entry_num              = RX_ENTRIES,
1065         .data_size              = AGGREGATION_SIZE,
1066         .desc_size              = RXD_DESC_SIZE,
1067         .priv_size              = sizeof(struct queue_entry_priv_pci),
1068 };
1069
1070 static const struct data_queue_desc rt2800pci_queue_tx = {
1071         .entry_num              = TX_ENTRIES,
1072         .data_size              = AGGREGATION_SIZE,
1073         .desc_size              = TXD_DESC_SIZE,
1074         .priv_size              = sizeof(struct queue_entry_priv_pci),
1075 };
1076
1077 static const struct data_queue_desc rt2800pci_queue_bcn = {
1078         .entry_num              = 8 * BEACON_ENTRIES,
1079         .data_size              = 0, /* No DMA required for beacons */
1080         .desc_size              = TXWI_DESC_SIZE,
1081         .priv_size              = sizeof(struct queue_entry_priv_pci),
1082 };
1083
1084 static const struct rt2x00_ops rt2800pci_ops = {
1085         .name                   = KBUILD_MODNAME,
1086         .max_sta_intf           = 1,
1087         .max_ap_intf            = 8,
1088         .eeprom_size            = EEPROM_SIZE,
1089         .rf_size                = RF_SIZE,
1090         .tx_queues              = NUM_TX_QUEUES,
1091         .extra_tx_headroom      = TXWI_DESC_SIZE,
1092         .rx                     = &rt2800pci_queue_rx,
1093         .tx                     = &rt2800pci_queue_tx,
1094         .bcn                    = &rt2800pci_queue_bcn,
1095         .lib                    = &rt2800pci_rt2x00_ops,
1096         .hw                     = &rt2800_mac80211_ops,
1097 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1098         .debugfs                = &rt2800_rt2x00debug,
1099 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1100 };
1101
1102 /*
1103  * RT2800pci module information.
1104  */
1105 #ifdef CONFIG_RT2800PCI_PCI
1106 static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
1107         { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
1108         { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
1109         { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
1110         { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
1111         { PCI_DEVICE(0x1432, 0x7708), PCI_DEVICE_DATA(&rt2800pci_ops) },
1112         { PCI_DEVICE(0x1432, 0x7727), PCI_DEVICE_DATA(&rt2800pci_ops) },
1113         { PCI_DEVICE(0x1432, 0x7728), PCI_DEVICE_DATA(&rt2800pci_ops) },
1114         { PCI_DEVICE(0x1432, 0x7738), PCI_DEVICE_DATA(&rt2800pci_ops) },
1115         { PCI_DEVICE(0x1432, 0x7748), PCI_DEVICE_DATA(&rt2800pci_ops) },
1116         { PCI_DEVICE(0x1432, 0x7758), PCI_DEVICE_DATA(&rt2800pci_ops) },
1117         { PCI_DEVICE(0x1432, 0x7768), PCI_DEVICE_DATA(&rt2800pci_ops) },
1118         { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
1119 #ifdef CONFIG_RT2800PCI_RT30XX
1120         { PCI_DEVICE(0x1814, 0x3090), PCI_DEVICE_DATA(&rt2800pci_ops) },
1121         { PCI_DEVICE(0x1814, 0x3091), PCI_DEVICE_DATA(&rt2800pci_ops) },
1122         { PCI_DEVICE(0x1814, 0x3092), PCI_DEVICE_DATA(&rt2800pci_ops) },
1123         { PCI_DEVICE(0x1462, 0x891a), PCI_DEVICE_DATA(&rt2800pci_ops) },
1124 #endif
1125 #ifdef CONFIG_RT2800PCI_RT35XX
1126         { PCI_DEVICE(0x1814, 0x3060), PCI_DEVICE_DATA(&rt2800pci_ops) },
1127         { PCI_DEVICE(0x1814, 0x3062), PCI_DEVICE_DATA(&rt2800pci_ops) },
1128         { PCI_DEVICE(0x1814, 0x3562), PCI_DEVICE_DATA(&rt2800pci_ops) },
1129         { PCI_DEVICE(0x1814, 0x3592), PCI_DEVICE_DATA(&rt2800pci_ops) },
1130         { PCI_DEVICE(0x1814, 0x3593), PCI_DEVICE_DATA(&rt2800pci_ops) },
1131 #endif
1132         { 0, }
1133 };
1134 #endif /* CONFIG_RT2800PCI_PCI */
1135
1136 MODULE_AUTHOR(DRV_PROJECT);
1137 MODULE_VERSION(DRV_VERSION);
1138 MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
1139 MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
1140 #ifdef CONFIG_RT2800PCI_PCI
1141 MODULE_FIRMWARE(FIRMWARE_RT2860);
1142 MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
1143 #endif /* CONFIG_RT2800PCI_PCI */
1144 MODULE_LICENSE("GPL");
1145
1146 #ifdef CONFIG_RT2800PCI_SOC
1147 static int rt2800soc_probe(struct platform_device *pdev)
1148 {
1149         return rt2x00soc_probe(pdev, &rt2800pci_ops);
1150 }
1151
1152 static struct platform_driver rt2800soc_driver = {
1153         .driver         = {
1154                 .name           = "rt2800_wmac",
1155                 .owner          = THIS_MODULE,
1156                 .mod_name       = KBUILD_MODNAME,
1157         },
1158         .probe          = rt2800soc_probe,
1159         .remove         = __devexit_p(rt2x00soc_remove),
1160         .suspend        = rt2x00soc_suspend,
1161         .resume         = rt2x00soc_resume,
1162 };
1163 #endif /* CONFIG_RT2800PCI_SOC */
1164
1165 #ifdef CONFIG_RT2800PCI_PCI
1166 static struct pci_driver rt2800pci_driver = {
1167         .name           = KBUILD_MODNAME,
1168         .id_table       = rt2800pci_device_table,
1169         .probe          = rt2x00pci_probe,
1170         .remove         = __devexit_p(rt2x00pci_remove),
1171         .suspend        = rt2x00pci_suspend,
1172         .resume         = rt2x00pci_resume,
1173 };
1174 #endif /* CONFIG_RT2800PCI_PCI */
1175
1176 static int __init rt2800pci_init(void)
1177 {
1178         int ret = 0;
1179
1180 #ifdef CONFIG_RT2800PCI_SOC
1181         ret = platform_driver_register(&rt2800soc_driver);
1182         if (ret)
1183                 return ret;
1184 #endif
1185 #ifdef CONFIG_RT2800PCI_PCI
1186         ret = pci_register_driver(&rt2800pci_driver);
1187         if (ret) {
1188 #ifdef CONFIG_RT2800PCI_SOC
1189                 platform_driver_unregister(&rt2800soc_driver);
1190 #endif
1191                 return ret;
1192         }
1193 #endif
1194
1195         return ret;
1196 }
1197
1198 static void __exit rt2800pci_exit(void)
1199 {
1200 #ifdef CONFIG_RT2800PCI_PCI
1201         pci_unregister_driver(&rt2800pci_driver);
1202 #endif
1203 #ifdef CONFIG_RT2800PCI_SOC
1204         platform_driver_unregister(&rt2800soc_driver);
1205 #endif
1206 }
1207
1208 module_init(rt2800pci_init);
1209 module_exit(rt2800pci_exit);