2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #include <linux/aer.h>
16 #include <linux/async.h>
17 #include <linux/blkdev.h>
18 #include <linux/blk-mq.h>
19 #include <linux/blk-mq-pci.h>
20 #include <linux/dmi.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
25 #include <linux/module.h>
26 #include <linux/mutex.h>
27 #include <linux/once.h>
28 #include <linux/pci.h>
29 #include <linux/t10-pi.h>
30 #include <linux/types.h>
31 #include <linux/io-64-nonatomic-lo-hi.h>
32 #include <linux/sed-opal.h>
33 #include <linux/pci-p2pdma.h>
38 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
39 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
41 #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
44 * These can be higher, but we need to ensure that any command doesn't
45 * require an sg allocation that needs more than a page of data.
47 #define NVME_MAX_KB_SZ 4096
48 #define NVME_MAX_SEGS 127
50 static int use_threaded_interrupts;
51 module_param(use_threaded_interrupts, int, 0);
53 static bool use_cmb_sqes = true;
54 module_param(use_cmb_sqes, bool, 0444);
55 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
57 static unsigned int max_host_mem_size_mb = 128;
58 module_param(max_host_mem_size_mb, uint, 0444);
59 MODULE_PARM_DESC(max_host_mem_size_mb,
60 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
62 static unsigned int sgl_threshold = SZ_32K;
63 module_param(sgl_threshold, uint, 0644);
64 MODULE_PARM_DESC(sgl_threshold,
65 "Use SGLs when average request segment size is larger or equal to "
66 "this size. Use 0 to disable SGLs.");
68 static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
69 static const struct kernel_param_ops io_queue_depth_ops = {
70 .set = io_queue_depth_set,
74 static int io_queue_depth = 1024;
75 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
76 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
78 static int queue_count_set(const char *val, const struct kernel_param *kp);
79 static const struct kernel_param_ops queue_count_ops = {
80 .set = queue_count_set,
84 static int write_queues;
85 module_param_cb(write_queues, &queue_count_ops, &write_queues, 0644);
86 MODULE_PARM_DESC(write_queues,
87 "Number of queues to use for writes. If not set, reads and writes "
88 "will share a queue set.");
90 static int poll_queues = 0;
91 module_param_cb(poll_queues, &queue_count_ops, &poll_queues, 0644);
92 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
97 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
100 * Represents an NVM Express device. Each nvme_dev is a PCI function.
103 struct nvme_queue *queues;
104 struct blk_mq_tag_set tagset;
105 struct blk_mq_tag_set admin_tagset;
108 struct dma_pool *prp_page_pool;
109 struct dma_pool *prp_small_pool;
110 unsigned online_queues;
112 unsigned io_queues[HCTX_MAX_TYPES];
113 unsigned int num_vecs;
117 unsigned long bar_mapped_size;
118 struct work_struct remove_work;
119 struct mutex shutdown_lock;
125 struct nvme_ctrl ctrl;
127 mempool_t *iod_mempool;
129 /* shadow doorbell buffer support: */
131 dma_addr_t dbbuf_dbs_dma_addr;
133 dma_addr_t dbbuf_eis_dma_addr;
135 /* host memory buffer support: */
137 u32 nr_host_mem_descs;
138 dma_addr_t host_mem_descs_dma;
139 struct nvme_host_mem_buf_desc *host_mem_descs;
140 void **host_mem_desc_bufs;
143 static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
147 ret = kstrtoint(val, 10, &n);
148 if (ret != 0 || n < 2)
151 return param_set_int(val, kp);
154 static int queue_count_set(const char *val, const struct kernel_param *kp)
158 ret = kstrtoint(val, 10, &n);
159 if (n > num_possible_cpus())
160 n = num_possible_cpus();
162 return param_set_int(val, kp);
165 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
167 return qid * 2 * stride;
170 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
172 return (qid * 2 + 1) * stride;
175 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
177 return container_of(ctrl, struct nvme_dev, ctrl);
181 * An NVM Express queue. Each device has at least two (one for admin
182 * commands and one for I/O commands).
185 struct device *q_dmadev;
186 struct nvme_dev *dev;
188 struct nvme_command *sq_cmds;
189 /* only used for poll queues: */
190 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
191 volatile struct nvme_completion *cqes;
192 struct blk_mq_tags **tags;
193 dma_addr_t sq_dma_addr;
194 dma_addr_t cq_dma_addr;
205 #define NVMEQ_ENABLED 0
206 #define NVMEQ_SQ_CMB 1
207 #define NVMEQ_DELETE_ERROR 2
212 struct completion delete_done;
216 * The nvme_iod describes the data in an I/O, including the list of PRP
217 * entries. You can't see it in this data structure because C doesn't let
218 * me express that. Use nvme_init_iod to ensure there's enough space
219 * allocated to store the PRP list.
222 struct nvme_request req;
223 struct nvme_queue *nvmeq;
226 int npages; /* In the PRP list. 0 means small pool in use */
227 int nents; /* Used in scatterlist */
228 int length; /* Of data, in bytes */
229 dma_addr_t first_dma;
230 struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
231 struct scatterlist *sg;
232 struct scatterlist inline_sg[0];
236 * Check we didin't inadvertently grow the command struct
238 static inline void _nvme_check_size(void)
240 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
241 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
242 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
243 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
244 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
245 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
246 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
247 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
248 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE);
249 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE);
250 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
251 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
252 BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
255 static unsigned int max_io_queues(void)
257 return num_possible_cpus() + write_queues + poll_queues;
260 static unsigned int max_queue_count(void)
262 /* IO queues + admin queue */
263 return 1 + max_io_queues();
266 static inline unsigned int nvme_dbbuf_size(u32 stride)
268 return (max_queue_count() * 8 * stride);
271 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
273 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
278 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
279 &dev->dbbuf_dbs_dma_addr,
283 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
284 &dev->dbbuf_eis_dma_addr,
286 if (!dev->dbbuf_eis) {
287 dma_free_coherent(dev->dev, mem_size,
288 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
289 dev->dbbuf_dbs = NULL;
296 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
298 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
300 if (dev->dbbuf_dbs) {
301 dma_free_coherent(dev->dev, mem_size,
302 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
303 dev->dbbuf_dbs = NULL;
305 if (dev->dbbuf_eis) {
306 dma_free_coherent(dev->dev, mem_size,
307 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
308 dev->dbbuf_eis = NULL;
312 static void nvme_dbbuf_init(struct nvme_dev *dev,
313 struct nvme_queue *nvmeq, int qid)
315 if (!dev->dbbuf_dbs || !qid)
318 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
319 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
320 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
321 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
324 static void nvme_dbbuf_set(struct nvme_dev *dev)
326 struct nvme_command c;
331 memset(&c, 0, sizeof(c));
332 c.dbbuf.opcode = nvme_admin_dbbuf;
333 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
334 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
336 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
337 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
338 /* Free memory and continue on */
339 nvme_dbbuf_dma_free(dev);
343 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
345 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
348 /* Update dbbuf and return true if an MMIO is required */
349 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
350 volatile u32 *dbbuf_ei)
356 * Ensure that the queue is written before updating
357 * the doorbell in memory
361 old_value = *dbbuf_db;
365 * Ensure that the doorbell is updated before reading the event
366 * index from memory. The controller needs to provide similar
367 * ordering to ensure the envent index is updated before reading
372 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
380 * Max size of iod being embedded in the request payload
382 #define NVME_INT_PAGES 2
383 #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
386 * Will slightly overestimate the number of pages needed. This is OK
387 * as it only leads to a small amount of wasted memory for the lifetime of
390 static int nvme_npages(unsigned size, struct nvme_dev *dev)
392 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
393 dev->ctrl.page_size);
394 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
398 * Calculates the number of pages needed for the SGL segments. For example a 4k
399 * page can accommodate 256 SGL descriptors.
401 static int nvme_pci_npages_sgl(unsigned int num_seg)
403 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE);
406 static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev,
407 unsigned int size, unsigned int nseg, bool use_sgl)
412 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg);
414 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev);
416 return alloc_size + sizeof(struct scatterlist) * nseg;
419 static unsigned int nvme_pci_cmd_size(struct nvme_dev *dev, bool use_sgl)
421 unsigned int alloc_size = nvme_pci_iod_alloc_size(dev,
422 NVME_INT_BYTES(dev), NVME_INT_PAGES,
425 return sizeof(struct nvme_iod) + alloc_size;
428 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
429 unsigned int hctx_idx)
431 struct nvme_dev *dev = data;
432 struct nvme_queue *nvmeq = &dev->queues[0];
434 WARN_ON(hctx_idx != 0);
435 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
436 WARN_ON(nvmeq->tags);
438 hctx->driver_data = nvmeq;
439 nvmeq->tags = &dev->admin_tagset.tags[0];
443 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
445 struct nvme_queue *nvmeq = hctx->driver_data;
450 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
451 unsigned int hctx_idx)
453 struct nvme_dev *dev = data;
454 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
457 nvmeq->tags = &dev->tagset.tags[hctx_idx];
459 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
460 hctx->driver_data = nvmeq;
464 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
465 unsigned int hctx_idx, unsigned int numa_node)
467 struct nvme_dev *dev = set->driver_data;
468 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
469 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
470 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
475 nvme_req(req)->ctrl = &dev->ctrl;
479 static int queue_irq_offset(struct nvme_dev *dev)
481 /* if we have more than 1 vec, admin queue offsets us by 1 */
482 if (dev->num_vecs > 1)
488 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
490 struct nvme_dev *dev = set->driver_data;
493 offset = queue_irq_offset(dev);
494 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
495 struct blk_mq_queue_map *map = &set->map[i];
497 map->nr_queues = dev->io_queues[i];
498 if (!map->nr_queues) {
499 BUG_ON(i == HCTX_TYPE_DEFAULT);
504 * The poll queue(s) doesn't have an IRQ (and hence IRQ
505 * affinity), so use the regular blk-mq cpu mapping
507 map->queue_offset = qoff;
508 if (i != HCTX_TYPE_POLL)
509 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
511 blk_mq_map_queues(map);
512 qoff += map->nr_queues;
513 offset += map->nr_queues;
520 * Write sq tail if we are asked to, or if the next command would wrap.
522 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
525 u16 next_tail = nvmeq->sq_tail + 1;
527 if (next_tail == nvmeq->q_depth)
529 if (next_tail != nvmeq->last_sq_tail)
533 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
534 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
535 writel(nvmeq->sq_tail, nvmeq->q_db);
536 nvmeq->last_sq_tail = nvmeq->sq_tail;
540 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
541 * @nvmeq: The queue to use
542 * @cmd: The command to send
543 * @write_sq: whether to write to the SQ doorbell
545 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
548 spin_lock(&nvmeq->sq_lock);
549 memcpy(&nvmeq->sq_cmds[nvmeq->sq_tail], cmd, sizeof(*cmd));
550 if (++nvmeq->sq_tail == nvmeq->q_depth)
552 nvme_write_sq_db(nvmeq, write_sq);
553 spin_unlock(&nvmeq->sq_lock);
556 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
558 struct nvme_queue *nvmeq = hctx->driver_data;
560 spin_lock(&nvmeq->sq_lock);
561 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
562 nvme_write_sq_db(nvmeq, true);
563 spin_unlock(&nvmeq->sq_lock);
566 static void **nvme_pci_iod_list(struct request *req)
568 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
569 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
572 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
574 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
575 int nseg = blk_rq_nr_phys_segments(req);
576 unsigned int avg_seg_size;
581 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
583 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
585 if (!iod->nvmeq->qid)
587 if (!sgl_threshold || avg_seg_size < sgl_threshold)
592 static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev)
594 struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
595 int nseg = blk_rq_nr_phys_segments(rq);
596 unsigned int size = blk_rq_payload_bytes(rq);
598 iod->use_sgl = nvme_pci_use_sgls(dev, rq);
600 if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
601 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
603 return BLK_STS_RESOURCE;
605 iod->sg = iod->inline_sg;
616 static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
618 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
619 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1;
620 dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
624 if (iod->npages == 0)
625 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
628 for (i = 0; i < iod->npages; i++) {
629 void *addr = nvme_pci_iod_list(req)[i];
632 struct nvme_sgl_desc *sg_list = addr;
635 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
637 __le64 *prp_list = addr;
639 next_dma_addr = le64_to_cpu(prp_list[last_prp]);
642 dma_pool_free(dev->prp_page_pool, addr, dma_addr);
643 dma_addr = next_dma_addr;
646 if (iod->sg != iod->inline_sg)
647 mempool_free(iod->sg, dev->iod_mempool);
650 static void nvme_print_sgl(struct scatterlist *sgl, int nents)
653 struct scatterlist *sg;
655 for_each_sg(sgl, sg, nents, i) {
656 dma_addr_t phys = sg_phys(sg);
657 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
658 "dma_address:%pad dma_length:%d\n",
659 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
664 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
665 struct request *req, struct nvme_rw_command *cmnd)
667 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
668 struct dma_pool *pool;
669 int length = blk_rq_payload_bytes(req);
670 struct scatterlist *sg = iod->sg;
671 int dma_len = sg_dma_len(sg);
672 u64 dma_addr = sg_dma_address(sg);
673 u32 page_size = dev->ctrl.page_size;
674 int offset = dma_addr & (page_size - 1);
676 void **list = nvme_pci_iod_list(req);
680 length -= (page_size - offset);
686 dma_len -= (page_size - offset);
688 dma_addr += (page_size - offset);
691 dma_addr = sg_dma_address(sg);
692 dma_len = sg_dma_len(sg);
695 if (length <= page_size) {
696 iod->first_dma = dma_addr;
700 nprps = DIV_ROUND_UP(length, page_size);
701 if (nprps <= (256 / 8)) {
702 pool = dev->prp_small_pool;
705 pool = dev->prp_page_pool;
709 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
711 iod->first_dma = dma_addr;
713 return BLK_STS_RESOURCE;
716 iod->first_dma = prp_dma;
719 if (i == page_size >> 3) {
720 __le64 *old_prp_list = prp_list;
721 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
723 return BLK_STS_RESOURCE;
724 list[iod->npages++] = prp_list;
725 prp_list[0] = old_prp_list[i - 1];
726 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
729 prp_list[i++] = cpu_to_le64(dma_addr);
730 dma_len -= page_size;
731 dma_addr += page_size;
737 if (unlikely(dma_len < 0))
740 dma_addr = sg_dma_address(sg);
741 dma_len = sg_dma_len(sg);
745 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
746 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
751 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
752 "Invalid SGL for payload:%d nents:%d\n",
753 blk_rq_payload_bytes(req), iod->nents);
754 return BLK_STS_IOERR;
757 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
758 struct scatterlist *sg)
760 sge->addr = cpu_to_le64(sg_dma_address(sg));
761 sge->length = cpu_to_le32(sg_dma_len(sg));
762 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
765 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
766 dma_addr_t dma_addr, int entries)
768 sge->addr = cpu_to_le64(dma_addr);
769 if (entries < SGES_PER_PAGE) {
770 sge->length = cpu_to_le32(entries * sizeof(*sge));
771 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
773 sge->length = cpu_to_le32(PAGE_SIZE);
774 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
778 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
779 struct request *req, struct nvme_rw_command *cmd, int entries)
781 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
782 struct dma_pool *pool;
783 struct nvme_sgl_desc *sg_list;
784 struct scatterlist *sg = iod->sg;
788 /* setting the transfer type as SGL */
789 cmd->flags = NVME_CMD_SGL_METABUF;
792 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
796 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
797 pool = dev->prp_small_pool;
800 pool = dev->prp_page_pool;
804 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
807 return BLK_STS_RESOURCE;
810 nvme_pci_iod_list(req)[0] = sg_list;
811 iod->first_dma = sgl_dma;
813 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
816 if (i == SGES_PER_PAGE) {
817 struct nvme_sgl_desc *old_sg_desc = sg_list;
818 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
820 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
822 return BLK_STS_RESOURCE;
825 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
826 sg_list[i++] = *link;
827 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
830 nvme_pci_sgl_set_data(&sg_list[i++], sg);
832 } while (--entries > 0);
837 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
838 struct nvme_command *cmnd)
840 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
841 struct request_queue *q = req->q;
842 enum dma_data_direction dma_dir = rq_data_dir(req) ?
843 DMA_TO_DEVICE : DMA_FROM_DEVICE;
844 blk_status_t ret = BLK_STS_IOERR;
847 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
848 iod->nents = blk_rq_map_sg(q, req, iod->sg);
852 ret = BLK_STS_RESOURCE;
854 if (is_pci_p2pdma_page(sg_page(iod->sg)))
855 nr_mapped = pci_p2pdma_map_sg(dev->dev, iod->sg, iod->nents,
858 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
859 dma_dir, DMA_ATTR_NO_WARN);
864 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
866 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
868 if (ret != BLK_STS_OK)
872 if (blk_integrity_rq(req)) {
873 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
876 sg_init_table(&iod->meta_sg, 1);
877 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
880 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
883 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
889 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
894 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
896 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
897 enum dma_data_direction dma_dir = rq_data_dir(req) ?
898 DMA_TO_DEVICE : DMA_FROM_DEVICE;
901 /* P2PDMA requests do not need to be unmapped */
902 if (!is_pci_p2pdma_page(sg_page(iod->sg)))
903 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
905 if (blk_integrity_rq(req))
906 dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
909 nvme_cleanup_cmd(req);
910 nvme_free_iod(dev, req);
914 * NOTE: ns is NULL when called on the admin queue.
916 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
917 const struct blk_mq_queue_data *bd)
919 struct nvme_ns *ns = hctx->queue->queuedata;
920 struct nvme_queue *nvmeq = hctx->driver_data;
921 struct nvme_dev *dev = nvmeq->dev;
922 struct request *req = bd->rq;
923 struct nvme_command cmnd;
927 * We should not need to do this, but we're still using this to
928 * ensure we can drain requests on a dying queue.
930 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
931 return BLK_STS_IOERR;
933 ret = nvme_setup_cmd(ns, req, &cmnd);
937 ret = nvme_init_iod(req, dev);
941 if (blk_rq_nr_phys_segments(req)) {
942 ret = nvme_map_data(dev, req, &cmnd);
944 goto out_cleanup_iod;
947 blk_mq_start_request(req);
948 nvme_submit_cmd(nvmeq, &cmnd, bd->last);
951 nvme_free_iod(dev, req);
953 nvme_cleanup_cmd(req);
957 static void nvme_pci_complete_rq(struct request *req)
959 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
961 nvme_unmap_data(iod->nvmeq->dev, req);
962 nvme_complete_rq(req);
965 /* We read the CQE phase first to check if the rest of the entry is valid */
966 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
968 return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
972 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
974 u16 head = nvmeq->cq_head;
976 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
978 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
981 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
983 volatile struct nvme_completion *cqe = &nvmeq->cqes[idx];
986 if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
987 dev_warn(nvmeq->dev->ctrl.device,
988 "invalid id %d completed on queue %d\n",
989 cqe->command_id, le16_to_cpu(cqe->sq_id));
994 * AEN requests are special as they don't time out and can
995 * survive any kind of queue freeze and often don't respond to
996 * aborts. We don't even bother to allocate a struct request
997 * for them but rather special case them here.
999 if (unlikely(nvmeq->qid == 0 &&
1000 cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) {
1001 nvme_complete_async_event(&nvmeq->dev->ctrl,
1002 cqe->status, &cqe->result);
1006 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id);
1007 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
1008 nvme_end_request(req, cqe->status, cqe->result);
1011 static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end)
1013 while (start != end) {
1014 nvme_handle_cqe(nvmeq, start);
1015 if (++start == nvmeq->q_depth)
1020 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1022 if (++nvmeq->cq_head == nvmeq->q_depth) {
1024 nvmeq->cq_phase = !nvmeq->cq_phase;
1028 static inline int nvme_process_cq(struct nvme_queue *nvmeq, u16 *start,
1029 u16 *end, unsigned int tag)
1033 *start = nvmeq->cq_head;
1034 while (nvme_cqe_pending(nvmeq)) {
1035 if (tag == -1U || nvmeq->cqes[nvmeq->cq_head].command_id == tag)
1037 nvme_update_cq_head(nvmeq);
1039 *end = nvmeq->cq_head;
1042 nvme_ring_cq_doorbell(nvmeq);
1046 static irqreturn_t nvme_irq(int irq, void *data)
1048 struct nvme_queue *nvmeq = data;
1049 irqreturn_t ret = IRQ_NONE;
1053 * The rmb/wmb pair ensures we see all updates from a previous run of
1054 * the irq handler, even if that was on another CPU.
1057 if (nvmeq->cq_head != nvmeq->last_cq_head)
1059 nvme_process_cq(nvmeq, &start, &end, -1);
1060 nvmeq->last_cq_head = nvmeq->cq_head;
1064 nvme_complete_cqes(nvmeq, start, end);
1071 static irqreturn_t nvme_irq_check(int irq, void *data)
1073 struct nvme_queue *nvmeq = data;
1074 if (nvme_cqe_pending(nvmeq))
1075 return IRQ_WAKE_THREAD;
1080 * Poll for completions any queue, including those not dedicated to polling.
1081 * Can be called from any context.
1083 static int nvme_poll_irqdisable(struct nvme_queue *nvmeq, unsigned int tag)
1085 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1090 * For a poll queue we need to protect against the polling thread
1091 * using the CQ lock. For normal interrupt driven threads we have
1092 * to disable the interrupt to avoid racing with it.
1094 if (nvmeq->cq_vector == -1) {
1095 spin_lock(&nvmeq->cq_poll_lock);
1096 found = nvme_process_cq(nvmeq, &start, &end, tag);
1097 spin_unlock(&nvmeq->cq_poll_lock);
1099 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1100 found = nvme_process_cq(nvmeq, &start, &end, tag);
1101 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1104 nvme_complete_cqes(nvmeq, start, end);
1108 static int nvme_poll(struct blk_mq_hw_ctx *hctx)
1110 struct nvme_queue *nvmeq = hctx->driver_data;
1114 if (!nvme_cqe_pending(nvmeq))
1117 spin_lock(&nvmeq->cq_poll_lock);
1118 found = nvme_process_cq(nvmeq, &start, &end, -1);
1119 spin_unlock(&nvmeq->cq_poll_lock);
1121 nvme_complete_cqes(nvmeq, start, end);
1125 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
1127 struct nvme_dev *dev = to_nvme_dev(ctrl);
1128 struct nvme_queue *nvmeq = &dev->queues[0];
1129 struct nvme_command c;
1131 memset(&c, 0, sizeof(c));
1132 c.common.opcode = nvme_admin_async_event;
1133 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1134 nvme_submit_cmd(nvmeq, &c, true);
1137 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1139 struct nvme_command c;
1141 memset(&c, 0, sizeof(c));
1142 c.delete_queue.opcode = opcode;
1143 c.delete_queue.qid = cpu_to_le16(id);
1145 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1148 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1149 struct nvme_queue *nvmeq, s16 vector)
1151 struct nvme_command c;
1152 int flags = NVME_QUEUE_PHYS_CONTIG;
1155 flags |= NVME_CQ_IRQ_ENABLED;
1158 * Note: we (ab)use the fact that the prp fields survive if no data
1159 * is attached to the request.
1161 memset(&c, 0, sizeof(c));
1162 c.create_cq.opcode = nvme_admin_create_cq;
1163 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1164 c.create_cq.cqid = cpu_to_le16(qid);
1165 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1166 c.create_cq.cq_flags = cpu_to_le16(flags);
1168 c.create_cq.irq_vector = cpu_to_le16(vector);
1170 c.create_cq.irq_vector = 0;
1172 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1175 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1176 struct nvme_queue *nvmeq)
1178 struct nvme_ctrl *ctrl = &dev->ctrl;
1179 struct nvme_command c;
1180 int flags = NVME_QUEUE_PHYS_CONTIG;
1183 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1184 * set. Since URGENT priority is zeroes, it makes all queues
1187 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1188 flags |= NVME_SQ_PRIO_MEDIUM;
1191 * Note: we (ab)use the fact that the prp fields survive if no data
1192 * is attached to the request.
1194 memset(&c, 0, sizeof(c));
1195 c.create_sq.opcode = nvme_admin_create_sq;
1196 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1197 c.create_sq.sqid = cpu_to_le16(qid);
1198 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1199 c.create_sq.sq_flags = cpu_to_le16(flags);
1200 c.create_sq.cqid = cpu_to_le16(qid);
1202 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1205 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1207 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1210 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1212 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1215 static void abort_endio(struct request *req, blk_status_t error)
1217 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1218 struct nvme_queue *nvmeq = iod->nvmeq;
1220 dev_warn(nvmeq->dev->ctrl.device,
1221 "Abort status: 0x%x", nvme_req(req)->status);
1222 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1223 blk_mq_free_request(req);
1226 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1229 /* If true, indicates loss of adapter communication, possibly by a
1230 * NVMe Subsystem reset.
1232 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1234 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1235 switch (dev->ctrl.state) {
1236 case NVME_CTRL_RESETTING:
1237 case NVME_CTRL_CONNECTING:
1243 /* We shouldn't reset unless the controller is on fatal error state
1244 * _or_ if we lost the communication with it.
1246 if (!(csts & NVME_CSTS_CFS) && !nssro)
1252 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1254 /* Read a config register to help see what died. */
1258 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1260 if (result == PCIBIOS_SUCCESSFUL)
1261 dev_warn(dev->ctrl.device,
1262 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1265 dev_warn(dev->ctrl.device,
1266 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1270 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1272 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1273 struct nvme_queue *nvmeq = iod->nvmeq;
1274 struct nvme_dev *dev = nvmeq->dev;
1275 struct request *abort_req;
1276 struct nvme_command cmd;
1277 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1279 /* If PCI error recovery process is happening, we cannot reset or
1280 * the recovery mechanism will surely fail.
1283 if (pci_channel_offline(to_pci_dev(dev->dev)))
1284 return BLK_EH_RESET_TIMER;
1287 * Reset immediately if the controller is failed
1289 if (nvme_should_reset(dev, csts)) {
1290 nvme_warn_reset(dev, csts);
1291 nvme_dev_disable(dev, false);
1292 nvme_reset_ctrl(&dev->ctrl);
1297 * Did we miss an interrupt?
1299 if (nvme_poll_irqdisable(nvmeq, req->tag)) {
1300 dev_warn(dev->ctrl.device,
1301 "I/O %d QID %d timeout, completion polled\n",
1302 req->tag, nvmeq->qid);
1307 * Shutdown immediately if controller times out while starting. The
1308 * reset work will see the pci device disabled when it gets the forced
1309 * cancellation error. All outstanding requests are completed on
1310 * shutdown, so we return BLK_EH_DONE.
1312 switch (dev->ctrl.state) {
1313 case NVME_CTRL_CONNECTING:
1314 case NVME_CTRL_RESETTING:
1315 dev_warn_ratelimited(dev->ctrl.device,
1316 "I/O %d QID %d timeout, disable controller\n",
1317 req->tag, nvmeq->qid);
1318 nvme_dev_disable(dev, false);
1319 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1326 * Shutdown the controller immediately and schedule a reset if the
1327 * command was already aborted once before and still hasn't been
1328 * returned to the driver, or if this is the admin queue.
1330 if (!nvmeq->qid || iod->aborted) {
1331 dev_warn(dev->ctrl.device,
1332 "I/O %d QID %d timeout, reset controller\n",
1333 req->tag, nvmeq->qid);
1334 nvme_dev_disable(dev, false);
1335 nvme_reset_ctrl(&dev->ctrl);
1337 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1341 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1342 atomic_inc(&dev->ctrl.abort_limit);
1343 return BLK_EH_RESET_TIMER;
1347 memset(&cmd, 0, sizeof(cmd));
1348 cmd.abort.opcode = nvme_admin_abort_cmd;
1349 cmd.abort.cid = req->tag;
1350 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1352 dev_warn(nvmeq->dev->ctrl.device,
1353 "I/O %d QID %d timeout, aborting\n",
1354 req->tag, nvmeq->qid);
1356 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
1357 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1358 if (IS_ERR(abort_req)) {
1359 atomic_inc(&dev->ctrl.abort_limit);
1360 return BLK_EH_RESET_TIMER;
1363 abort_req->timeout = ADMIN_TIMEOUT;
1364 abort_req->end_io_data = NULL;
1365 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
1368 * The aborted req will be completed on receiving the abort req.
1369 * We enable the timer again. If hit twice, it'll cause a device reset,
1370 * as the device then is in a faulty state.
1372 return BLK_EH_RESET_TIMER;
1375 static void nvme_free_queue(struct nvme_queue *nvmeq)
1377 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1378 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1379 if (!nvmeq->sq_cmds)
1382 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
1383 pci_free_p2pmem(to_pci_dev(nvmeq->q_dmadev),
1384 nvmeq->sq_cmds, SQ_SIZE(nvmeq->q_depth));
1386 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1387 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1391 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1395 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1396 dev->ctrl.queue_count--;
1397 nvme_free_queue(&dev->queues[i]);
1402 * nvme_suspend_queue - put queue into suspended state
1403 * @nvmeq: queue to suspend
1405 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1407 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
1410 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
1413 nvmeq->dev->online_queues--;
1414 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1415 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
1416 if (nvmeq->cq_vector == -1)
1418 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
1419 nvmeq->cq_vector = -1;
1423 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1425 struct nvme_queue *nvmeq = &dev->queues[0];
1428 nvme_shutdown_ctrl(&dev->ctrl);
1430 nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
1432 nvme_poll_irqdisable(nvmeq, -1);
1435 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1438 int q_depth = dev->q_depth;
1439 unsigned q_size_aligned = roundup(q_depth * entry_size,
1440 dev->ctrl.page_size);
1442 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1443 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1444 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1445 q_depth = div_u64(mem_per_q, entry_size);
1448 * Ensure the reduced q_depth is above some threshold where it
1449 * would be better to map queues in system memory with the
1459 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1462 struct pci_dev *pdev = to_pci_dev(dev->dev);
1464 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1465 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(depth));
1466 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1468 if (nvmeq->sq_dma_addr) {
1469 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1474 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1475 &nvmeq->sq_dma_addr, GFP_KERNEL);
1476 if (!nvmeq->sq_cmds)
1481 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
1483 struct nvme_queue *nvmeq = &dev->queues[qid];
1485 if (dev->ctrl.queue_count > qid)
1488 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1489 &nvmeq->cq_dma_addr, GFP_KERNEL);
1493 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1496 nvmeq->q_dmadev = dev->dev;
1498 spin_lock_init(&nvmeq->sq_lock);
1499 spin_lock_init(&nvmeq->cq_poll_lock);
1501 nvmeq->cq_phase = 1;
1502 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1503 nvmeq->q_depth = depth;
1505 nvmeq->cq_vector = -1;
1506 dev->ctrl.queue_count++;
1511 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1512 nvmeq->cq_dma_addr);
1517 static int queue_request_irq(struct nvme_queue *nvmeq)
1519 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1520 int nr = nvmeq->dev->ctrl.instance;
1522 if (use_threaded_interrupts) {
1523 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1524 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1526 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1527 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1531 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1533 struct nvme_dev *dev = nvmeq->dev;
1536 nvmeq->last_sq_tail = 0;
1538 nvmeq->cq_phase = 1;
1539 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1540 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1541 nvme_dbbuf_init(dev, nvmeq, qid);
1542 dev->online_queues++;
1543 wmb(); /* ensure the first interrupt sees the initialization */
1546 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
1548 struct nvme_dev *dev = nvmeq->dev;
1552 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1555 * A queue's vector matches the queue identifier unless the controller
1556 * has only one vector available.
1559 vector = dev->num_vecs == 1 ? 0 : qid;
1563 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
1567 result = adapter_alloc_sq(dev, qid, nvmeq);
1573 nvmeq->cq_vector = vector;
1574 nvme_init_queue(nvmeq, qid);
1577 result = queue_request_irq(nvmeq);
1582 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1586 nvmeq->cq_vector = -1;
1587 dev->online_queues--;
1588 adapter_delete_sq(dev, qid);
1590 adapter_delete_cq(dev, qid);
1594 static const struct blk_mq_ops nvme_mq_admin_ops = {
1595 .queue_rq = nvme_queue_rq,
1596 .complete = nvme_pci_complete_rq,
1597 .init_hctx = nvme_admin_init_hctx,
1598 .exit_hctx = nvme_admin_exit_hctx,
1599 .init_request = nvme_init_request,
1600 .timeout = nvme_timeout,
1603 static const struct blk_mq_ops nvme_mq_ops = {
1604 .queue_rq = nvme_queue_rq,
1605 .complete = nvme_pci_complete_rq,
1606 .commit_rqs = nvme_commit_rqs,
1607 .init_hctx = nvme_init_hctx,
1608 .init_request = nvme_init_request,
1609 .map_queues = nvme_pci_map_queues,
1610 .timeout = nvme_timeout,
1614 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1616 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1618 * If the controller was reset during removal, it's possible
1619 * user requests may be waiting on a stopped queue. Start the
1620 * queue to flush these to completion.
1622 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1623 blk_cleanup_queue(dev->ctrl.admin_q);
1624 blk_mq_free_tag_set(&dev->admin_tagset);
1628 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1630 if (!dev->ctrl.admin_q) {
1631 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1632 dev->admin_tagset.nr_hw_queues = 1;
1634 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
1635 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1636 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1637 dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false);
1638 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1639 dev->admin_tagset.driver_data = dev;
1641 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1643 dev->ctrl.admin_tagset = &dev->admin_tagset;
1645 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1646 if (IS_ERR(dev->ctrl.admin_q)) {
1647 blk_mq_free_tag_set(&dev->admin_tagset);
1650 if (!blk_get_queue(dev->ctrl.admin_q)) {
1651 nvme_dev_remove_admin(dev);
1652 dev->ctrl.admin_q = NULL;
1656 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1661 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1663 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1666 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1668 struct pci_dev *pdev = to_pci_dev(dev->dev);
1670 if (size <= dev->bar_mapped_size)
1672 if (size > pci_resource_len(pdev, 0))
1676 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1678 dev->bar_mapped_size = 0;
1681 dev->bar_mapped_size = size;
1682 dev->dbs = dev->bar + NVME_REG_DBS;
1687 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1691 struct nvme_queue *nvmeq;
1693 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1697 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1698 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1700 if (dev->subsystem &&
1701 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1702 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1704 result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
1708 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1712 nvmeq = &dev->queues[0];
1713 aqa = nvmeq->q_depth - 1;
1716 writel(aqa, dev->bar + NVME_REG_AQA);
1717 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1718 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1720 result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap);
1724 nvmeq->cq_vector = 0;
1725 nvme_init_queue(nvmeq, 0);
1726 result = queue_request_irq(nvmeq);
1728 nvmeq->cq_vector = -1;
1732 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1736 static int nvme_create_io_queues(struct nvme_dev *dev)
1738 unsigned i, max, rw_queues;
1741 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1742 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
1748 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1749 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1750 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1751 dev->io_queues[HCTX_TYPE_READ];
1756 for (i = dev->online_queues; i <= max; i++) {
1757 bool polled = i > rw_queues;
1759 ret = nvme_create_queue(&dev->queues[i], i, polled);
1765 * Ignore failing Create SQ/CQ commands, we can continue with less
1766 * than the desired amount of queues, and even a controller without
1767 * I/O queues can still be used to issue admin commands. This might
1768 * be useful to upgrade a buggy firmware for example.
1770 return ret >= 0 ? 0 : ret;
1773 static ssize_t nvme_cmb_show(struct device *dev,
1774 struct device_attribute *attr,
1777 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1779 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
1780 ndev->cmbloc, ndev->cmbsz);
1782 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1784 static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
1786 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1788 return 1ULL << (12 + 4 * szu);
1791 static u32 nvme_cmb_size(struct nvme_dev *dev)
1793 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1796 static void nvme_map_cmb(struct nvme_dev *dev)
1799 resource_size_t bar_size;
1800 struct pci_dev *pdev = to_pci_dev(dev->dev);
1806 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1809 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1811 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1812 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
1813 bar = NVME_CMB_BIR(dev->cmbloc);
1814 bar_size = pci_resource_len(pdev, bar);
1816 if (offset > bar_size)
1820 * Controllers may support a CMB size larger than their BAR,
1821 * for example, due to being behind a bridge. Reduce the CMB to
1822 * the reported size of the BAR
1824 if (size > bar_size - offset)
1825 size = bar_size - offset;
1827 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1828 dev_warn(dev->ctrl.device,
1829 "failed to register the CMB\n");
1833 dev->cmb_size = size;
1834 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1836 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1837 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1838 pci_p2pmem_publish(pdev, true);
1840 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1841 &dev_attr_cmb.attr, NULL))
1842 dev_warn(dev->ctrl.device,
1843 "failed to add sysfs attribute for CMB\n");
1846 static inline void nvme_release_cmb(struct nvme_dev *dev)
1848 if (dev->cmb_size) {
1849 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1850 &dev_attr_cmb.attr, NULL);
1855 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1857 u64 dma_addr = dev->host_mem_descs_dma;
1858 struct nvme_command c;
1861 memset(&c, 0, sizeof(c));
1862 c.features.opcode = nvme_admin_set_features;
1863 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1864 c.features.dword11 = cpu_to_le32(bits);
1865 c.features.dword12 = cpu_to_le32(dev->host_mem_size >>
1866 ilog2(dev->ctrl.page_size));
1867 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1868 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1869 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1871 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1873 dev_warn(dev->ctrl.device,
1874 "failed to set host mem (err %d, flags %#x).\n",
1880 static void nvme_free_host_mem(struct nvme_dev *dev)
1884 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1885 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1886 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1888 dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i],
1889 le64_to_cpu(desc->addr));
1892 kfree(dev->host_mem_desc_bufs);
1893 dev->host_mem_desc_bufs = NULL;
1894 dma_free_coherent(dev->dev,
1895 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1896 dev->host_mem_descs, dev->host_mem_descs_dma);
1897 dev->host_mem_descs = NULL;
1898 dev->nr_host_mem_descs = 0;
1901 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1904 struct nvme_host_mem_buf_desc *descs;
1905 u32 max_entries, len;
1906 dma_addr_t descs_dma;
1911 tmp = (preferred + chunk_size - 1);
1912 do_div(tmp, chunk_size);
1915 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1916 max_entries = dev->ctrl.hmmaxd;
1918 descs = dma_zalloc_coherent(dev->dev, max_entries * sizeof(*descs),
1919 &descs_dma, GFP_KERNEL);
1923 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1925 goto out_free_descs;
1927 for (size = 0; size < preferred && i < max_entries; size += len) {
1928 dma_addr_t dma_addr;
1930 len = min_t(u64, chunk_size, preferred - size);
1931 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1932 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1936 descs[i].addr = cpu_to_le64(dma_addr);
1937 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1944 dev->nr_host_mem_descs = i;
1945 dev->host_mem_size = size;
1946 dev->host_mem_descs = descs;
1947 dev->host_mem_descs_dma = descs_dma;
1948 dev->host_mem_desc_bufs = bufs;
1953 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1955 dma_free_coherent(dev->dev, size, bufs[i],
1956 le64_to_cpu(descs[i].addr));
1961 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1964 dev->host_mem_descs = NULL;
1968 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1972 /* start big and work our way down */
1973 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
1974 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
1976 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1977 if (!min || dev->host_mem_size >= min)
1979 nvme_free_host_mem(dev);
1986 static int nvme_setup_host_mem(struct nvme_dev *dev)
1988 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1989 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1990 u64 min = (u64)dev->ctrl.hmmin * 4096;
1991 u32 enable_bits = NVME_HOST_MEM_ENABLE;
1994 preferred = min(preferred, max);
1996 dev_warn(dev->ctrl.device,
1997 "min host memory (%lld MiB) above limit (%d MiB).\n",
1998 min >> ilog2(SZ_1M), max_host_mem_size_mb);
1999 nvme_free_host_mem(dev);
2004 * If we already have a buffer allocated check if we can reuse it.
2006 if (dev->host_mem_descs) {
2007 if (dev->host_mem_size >= min)
2008 enable_bits |= NVME_HOST_MEM_RETURN;
2010 nvme_free_host_mem(dev);
2013 if (!dev->host_mem_descs) {
2014 if (nvme_alloc_host_mem(dev, min, preferred)) {
2015 dev_warn(dev->ctrl.device,
2016 "failed to allocate host memory buffer.\n");
2017 return 0; /* controller must work without HMB */
2020 dev_info(dev->ctrl.device,
2021 "allocated %lld MiB host memory buffer.\n",
2022 dev->host_mem_size >> ilog2(SZ_1M));
2025 ret = nvme_set_host_mem(dev, enable_bits);
2027 nvme_free_host_mem(dev);
2031 static void nvme_calc_io_queues(struct nvme_dev *dev, unsigned int irq_queues)
2033 unsigned int this_w_queues = write_queues;
2036 * Setup read/write queue split
2038 if (irq_queues == 1) {
2039 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2040 dev->io_queues[HCTX_TYPE_READ] = 0;
2045 * If 'write_queues' is set, ensure it leaves room for at least
2048 if (this_w_queues >= irq_queues)
2049 this_w_queues = irq_queues - 1;
2052 * If 'write_queues' is set to zero, reads and writes will share
2055 if (!this_w_queues) {
2056 dev->io_queues[HCTX_TYPE_DEFAULT] = irq_queues;
2057 dev->io_queues[HCTX_TYPE_READ] = 0;
2059 dev->io_queues[HCTX_TYPE_DEFAULT] = this_w_queues;
2060 dev->io_queues[HCTX_TYPE_READ] = irq_queues - this_w_queues;
2064 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
2066 struct pci_dev *pdev = to_pci_dev(dev->dev);
2068 struct irq_affinity affd = {
2070 .nr_sets = ARRAY_SIZE(irq_sets),
2074 unsigned int irq_queues, this_p_queues;
2077 * Poll queues don't need interrupts, but we need at least one IO
2078 * queue left over for non-polled IO.
2080 this_p_queues = poll_queues;
2081 if (this_p_queues >= nr_io_queues) {
2082 this_p_queues = nr_io_queues - 1;
2085 irq_queues = nr_io_queues - this_p_queues;
2087 dev->io_queues[HCTX_TYPE_POLL] = this_p_queues;
2090 * For irq sets, we have to ask for minvec == maxvec. This passes
2091 * any reduction back to us, so we can adjust our queue counts and
2095 nvme_calc_io_queues(dev, irq_queues);
2096 irq_sets[0] = dev->io_queues[HCTX_TYPE_DEFAULT];
2097 irq_sets[1] = dev->io_queues[HCTX_TYPE_READ];
2102 * If we got a failure and we're down to asking for just
2103 * 1 + 1 queues, just ask for a single vector. We'll share
2104 * that between the single IO queue and the admin queue.
2106 if (result >= 0 && irq_queues > 1)
2107 irq_queues = irq_sets[0] + irq_sets[1] + 1;
2109 result = pci_alloc_irq_vectors_affinity(pdev, irq_queues,
2111 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
2114 * Need to reduce our vec counts. If we get ENOSPC, the
2115 * platform should support mulitple vecs, we just need
2116 * to decrease our ask. If we get EINVAL, the platform
2117 * likely does not. Back down to ask for just one vector.
2119 if (result == -ENOSPC) {
2124 } else if (result == -EINVAL) {
2127 } else if (result <= 0)
2135 static int nvme_setup_io_queues(struct nvme_dev *dev)
2137 struct nvme_queue *adminq = &dev->queues[0];
2138 struct pci_dev *pdev = to_pci_dev(dev->dev);
2139 int result, nr_io_queues;
2142 nr_io_queues = max_io_queues();
2143 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2147 if (nr_io_queues == 0)
2150 clear_bit(NVMEQ_ENABLED, &adminq->flags);
2152 if (dev->cmb_use_sqes) {
2153 result = nvme_cmb_qdepth(dev, nr_io_queues,
2154 sizeof(struct nvme_command));
2156 dev->q_depth = result;
2158 dev->cmb_use_sqes = false;
2162 size = db_bar_size(dev, nr_io_queues);
2163 result = nvme_remap_bar(dev, size);
2166 if (!--nr_io_queues)
2169 adminq->q_db = dev->dbs;
2171 /* Deregister the admin queue's interrupt */
2172 pci_free_irq(pdev, 0, adminq);
2175 * If we enable msix early due to not intx, disable it again before
2176 * setting up the full range we need.
2178 pci_free_irq_vectors(pdev);
2180 result = nvme_setup_irqs(dev, nr_io_queues);
2184 dev->num_vecs = result;
2185 result = max(result - 1, 1);
2186 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
2188 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2189 dev->io_queues[HCTX_TYPE_DEFAULT],
2190 dev->io_queues[HCTX_TYPE_READ],
2191 dev->io_queues[HCTX_TYPE_POLL]);
2194 * Should investigate if there's a performance win from allocating
2195 * more queues than interrupt vectors; it might allow the submission
2196 * path to scale better, even if the receive path is limited by the
2197 * number of interrupts.
2200 result = queue_request_irq(adminq);
2202 adminq->cq_vector = -1;
2205 set_bit(NVMEQ_ENABLED, &adminq->flags);
2206 return nvme_create_io_queues(dev);
2209 static void nvme_del_queue_end(struct request *req, blk_status_t error)
2211 struct nvme_queue *nvmeq = req->end_io_data;
2213 blk_mq_free_request(req);
2214 complete(&nvmeq->delete_done);
2217 static void nvme_del_cq_end(struct request *req, blk_status_t error)
2219 struct nvme_queue *nvmeq = req->end_io_data;
2222 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
2224 nvme_del_queue_end(req, error);
2227 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
2229 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2230 struct request *req;
2231 struct nvme_command cmd;
2233 memset(&cmd, 0, sizeof(cmd));
2234 cmd.delete_queue.opcode = opcode;
2235 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2237 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
2239 return PTR_ERR(req);
2241 req->timeout = ADMIN_TIMEOUT;
2242 req->end_io_data = nvmeq;
2244 init_completion(&nvmeq->delete_done);
2245 blk_execute_rq_nowait(q, NULL, req, false,
2246 opcode == nvme_admin_delete_cq ?
2247 nvme_del_cq_end : nvme_del_queue_end);
2251 static bool nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
2253 int nr_queues = dev->online_queues - 1, sent = 0;
2254 unsigned long timeout;
2257 timeout = ADMIN_TIMEOUT;
2258 while (nr_queues > 0) {
2259 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2265 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2267 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
2272 /* handle any remaining CQEs */
2273 if (opcode == nvme_admin_delete_cq &&
2274 !test_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags))
2275 nvme_poll_irqdisable(nvmeq, -1);
2285 * return error value only when tagset allocation failed
2287 static int nvme_dev_add(struct nvme_dev *dev)
2291 if (!dev->ctrl.tagset) {
2292 dev->tagset.ops = &nvme_mq_ops;
2293 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2294 dev->tagset.nr_maps = 2; /* default + read */
2295 if (dev->io_queues[HCTX_TYPE_POLL])
2296 dev->tagset.nr_maps++;
2297 dev->tagset.nr_maps = HCTX_MAX_TYPES;
2298 dev->tagset.timeout = NVME_IO_TIMEOUT;
2299 dev->tagset.numa_node = dev_to_node(dev->dev);
2300 dev->tagset.queue_depth =
2301 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
2302 dev->tagset.cmd_size = nvme_pci_cmd_size(dev, false);
2303 if ((dev->ctrl.sgls & ((1 << 0) | (1 << 1))) && sgl_threshold) {
2304 dev->tagset.cmd_size = max(dev->tagset.cmd_size,
2305 nvme_pci_cmd_size(dev, true));
2307 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2308 dev->tagset.driver_data = dev;
2310 ret = blk_mq_alloc_tag_set(&dev->tagset);
2312 dev_warn(dev->ctrl.device,
2313 "IO queues tagset allocation failed %d\n", ret);
2316 dev->ctrl.tagset = &dev->tagset;
2318 nvme_dbbuf_set(dev);
2320 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2322 /* Free previously allocated queues that are no longer usable */
2323 nvme_free_queues(dev, dev->online_queues);
2329 static int nvme_pci_enable(struct nvme_dev *dev)
2331 int result = -ENOMEM;
2332 struct pci_dev *pdev = to_pci_dev(dev->dev);
2334 if (pci_enable_device_mem(pdev))
2337 pci_set_master(pdev);
2339 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
2340 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
2343 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
2349 * Some devices and/or platforms don't advertise or work with INTx
2350 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2351 * adjust this later.
2353 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2357 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
2359 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2361 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
2362 dev->dbs = dev->bar + 4096;
2365 * Temporary fix for the Apple controller found in the MacBook8,1 and
2366 * some MacBook7,1 to avoid controller resets and data loss.
2368 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2370 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2371 "set queue depth=%u to work around controller resets\n",
2373 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2374 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
2375 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2377 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2378 "set queue depth=%u\n", dev->q_depth);
2383 pci_enable_pcie_error_reporting(pdev);
2384 pci_save_state(pdev);
2388 pci_disable_device(pdev);
2392 static void nvme_dev_unmap(struct nvme_dev *dev)
2396 pci_release_mem_regions(to_pci_dev(dev->dev));
2399 static void nvme_pci_disable(struct nvme_dev *dev)
2401 struct pci_dev *pdev = to_pci_dev(dev->dev);
2403 pci_free_irq_vectors(pdev);
2405 if (pci_is_enabled(pdev)) {
2406 pci_disable_pcie_error_reporting(pdev);
2407 pci_disable_device(pdev);
2411 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2415 struct pci_dev *pdev = to_pci_dev(dev->dev);
2417 mutex_lock(&dev->shutdown_lock);
2418 if (pci_is_enabled(pdev)) {
2419 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2421 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2422 dev->ctrl.state == NVME_CTRL_RESETTING)
2423 nvme_start_freeze(&dev->ctrl);
2424 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2425 pdev->error_state != pci_channel_io_normal);
2429 * Give the controller a chance to complete all entered requests if
2430 * doing a safe shutdown.
2434 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2437 nvme_stop_queues(&dev->ctrl);
2439 if (!dead && dev->ctrl.queue_count > 0) {
2440 if (nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2441 nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2442 nvme_disable_admin_queue(dev, shutdown);
2444 for (i = dev->ctrl.queue_count - 1; i >= 0; i--)
2445 nvme_suspend_queue(&dev->queues[i]);
2447 nvme_pci_disable(dev);
2449 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2450 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
2453 * The driver will not be starting up queues again if shutting down so
2454 * must flush all entered requests to their failed completion to avoid
2455 * deadlocking blk-mq hot-cpu notifier.
2458 nvme_start_queues(&dev->ctrl);
2459 mutex_unlock(&dev->shutdown_lock);
2462 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2464 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2465 PAGE_SIZE, PAGE_SIZE, 0);
2466 if (!dev->prp_page_pool)
2469 /* Optimisation for I/Os between 4k and 128k */
2470 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2472 if (!dev->prp_small_pool) {
2473 dma_pool_destroy(dev->prp_page_pool);
2479 static void nvme_release_prp_pools(struct nvme_dev *dev)
2481 dma_pool_destroy(dev->prp_page_pool);
2482 dma_pool_destroy(dev->prp_small_pool);
2485 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2487 struct nvme_dev *dev = to_nvme_dev(ctrl);
2489 nvme_dbbuf_dma_free(dev);
2490 put_device(dev->dev);
2491 if (dev->tagset.tags)
2492 blk_mq_free_tag_set(&dev->tagset);
2493 if (dev->ctrl.admin_q)
2494 blk_put_queue(dev->ctrl.admin_q);
2496 free_opal_dev(dev->ctrl.opal_dev);
2497 mempool_destroy(dev->iod_mempool);
2501 static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
2503 dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
2505 nvme_get_ctrl(&dev->ctrl);
2506 nvme_dev_disable(dev, false);
2507 nvme_kill_queues(&dev->ctrl);
2508 if (!queue_work(nvme_wq, &dev->remove_work))
2509 nvme_put_ctrl(&dev->ctrl);
2512 static void nvme_reset_work(struct work_struct *work)
2514 struct nvme_dev *dev =
2515 container_of(work, struct nvme_dev, ctrl.reset_work);
2516 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2517 int result = -ENODEV;
2518 enum nvme_ctrl_state new_state = NVME_CTRL_LIVE;
2520 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING))
2524 * If we're called to reset a live controller first shut it down before
2527 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2528 nvme_dev_disable(dev, false);
2531 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2532 * initializing procedure here.
2534 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2535 dev_warn(dev->ctrl.device,
2536 "failed to mark controller CONNECTING\n");
2540 result = nvme_pci_enable(dev);
2544 result = nvme_pci_configure_admin_queue(dev);
2548 result = nvme_alloc_admin_tags(dev);
2553 * Limit the max command size to prevent iod->sg allocations going
2554 * over a single page.
2556 dev->ctrl.max_hw_sectors = NVME_MAX_KB_SZ << 1;
2557 dev->ctrl.max_segments = NVME_MAX_SEGS;
2559 result = nvme_init_identify(&dev->ctrl);
2563 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2564 if (!dev->ctrl.opal_dev)
2565 dev->ctrl.opal_dev =
2566 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2567 else if (was_suspend)
2568 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2570 free_opal_dev(dev->ctrl.opal_dev);
2571 dev->ctrl.opal_dev = NULL;
2574 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2575 result = nvme_dbbuf_dma_alloc(dev);
2578 "unable to allocate dma for dbbuf\n");
2581 if (dev->ctrl.hmpre) {
2582 result = nvme_setup_host_mem(dev);
2587 result = nvme_setup_io_queues(dev);
2592 * Keep the controller around but remove all namespaces if we don't have
2593 * any working I/O queue.
2595 if (dev->online_queues < 2) {
2596 dev_warn(dev->ctrl.device, "IO queues not created\n");
2597 nvme_kill_queues(&dev->ctrl);
2598 nvme_remove_namespaces(&dev->ctrl);
2599 new_state = NVME_CTRL_ADMIN_ONLY;
2601 nvme_start_queues(&dev->ctrl);
2602 nvme_wait_freeze(&dev->ctrl);
2603 /* hit this only when allocate tagset fails */
2604 if (nvme_dev_add(dev))
2605 new_state = NVME_CTRL_ADMIN_ONLY;
2606 nvme_unfreeze(&dev->ctrl);
2610 * If only admin queue live, keep it to do further investigation or
2613 if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) {
2614 dev_warn(dev->ctrl.device,
2615 "failed to mark controller state %d\n", new_state);
2619 nvme_start_ctrl(&dev->ctrl);
2623 nvme_remove_dead_ctrl(dev, result);
2626 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2628 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2629 struct pci_dev *pdev = to_pci_dev(dev->dev);
2631 if (pci_get_drvdata(pdev))
2632 device_release_driver(&pdev->dev);
2633 nvme_put_ctrl(&dev->ctrl);
2636 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2638 *val = readl(to_nvme_dev(ctrl)->bar + off);
2642 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2644 writel(val, to_nvme_dev(ctrl)->bar + off);
2648 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2650 *val = readq(to_nvme_dev(ctrl)->bar + off);
2654 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2656 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2658 return snprintf(buf, size, "%s", dev_name(&pdev->dev));
2661 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2663 .module = THIS_MODULE,
2664 .flags = NVME_F_METADATA_SUPPORTED |
2666 .reg_read32 = nvme_pci_reg_read32,
2667 .reg_write32 = nvme_pci_reg_write32,
2668 .reg_read64 = nvme_pci_reg_read64,
2669 .free_ctrl = nvme_pci_free_ctrl,
2670 .submit_async_event = nvme_pci_submit_async_event,
2671 .get_address = nvme_pci_get_address,
2674 static int nvme_dev_map(struct nvme_dev *dev)
2676 struct pci_dev *pdev = to_pci_dev(dev->dev);
2678 if (pci_request_mem_regions(pdev, "nvme"))
2681 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2686 pci_release_mem_regions(pdev);
2690 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
2692 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2694 * Several Samsung devices seem to drop off the PCIe bus
2695 * randomly when APST is on and uses the deepest sleep state.
2696 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2697 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2698 * 950 PRO 256GB", but it seems to be restricted to two Dell
2701 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2702 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2703 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2704 return NVME_QUIRK_NO_DEEPEST_PS;
2705 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2707 * Samsung SSD 960 EVO drops off the PCIe bus after system
2708 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2709 * within few minutes after bootup on a Coffee Lake board -
2712 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
2713 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2714 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
2715 return NVME_QUIRK_NO_APST;
2721 static void nvme_async_probe(void *data, async_cookie_t cookie)
2723 struct nvme_dev *dev = data;
2725 nvme_reset_ctrl_sync(&dev->ctrl);
2726 flush_work(&dev->ctrl.scan_work);
2727 nvme_put_ctrl(&dev->ctrl);
2730 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2732 int node, result = -ENOMEM;
2733 struct nvme_dev *dev;
2734 unsigned long quirks = id->driver_data;
2737 node = dev_to_node(&pdev->dev);
2738 if (node == NUMA_NO_NODE)
2739 set_dev_node(&pdev->dev, first_memory_node);
2741 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2745 dev->queues = kcalloc_node(max_queue_count(), sizeof(struct nvme_queue),
2750 dev->dev = get_device(&pdev->dev);
2751 pci_set_drvdata(pdev, dev);
2753 result = nvme_dev_map(dev);
2757 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2758 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2759 mutex_init(&dev->shutdown_lock);
2761 result = nvme_setup_prp_pools(dev);
2765 quirks |= check_vendor_combination_bug(pdev);
2768 * Double check that our mempool alloc size will cover the biggest
2769 * command we support.
2771 alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ,
2772 NVME_MAX_SEGS, true);
2773 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2775 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2777 (void *) alloc_size,
2779 if (!dev->iod_mempool) {
2784 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2787 goto release_mempool;
2789 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2791 nvme_get_ctrl(&dev->ctrl);
2792 async_schedule(nvme_async_probe, dev);
2797 mempool_destroy(dev->iod_mempool);
2799 nvme_release_prp_pools(dev);
2801 nvme_dev_unmap(dev);
2803 put_device(dev->dev);
2810 static void nvme_reset_prepare(struct pci_dev *pdev)
2812 struct nvme_dev *dev = pci_get_drvdata(pdev);
2813 nvme_dev_disable(dev, false);
2816 static void nvme_reset_done(struct pci_dev *pdev)
2818 struct nvme_dev *dev = pci_get_drvdata(pdev);
2819 nvme_reset_ctrl_sync(&dev->ctrl);
2822 static void nvme_shutdown(struct pci_dev *pdev)
2824 struct nvme_dev *dev = pci_get_drvdata(pdev);
2825 nvme_dev_disable(dev, true);
2829 * The driver's remove may be called on a device in a partially initialized
2830 * state. This function must not have any dependencies on the device state in
2833 static void nvme_remove(struct pci_dev *pdev)
2835 struct nvme_dev *dev = pci_get_drvdata(pdev);
2837 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2838 pci_set_drvdata(pdev, NULL);
2840 if (!pci_device_is_present(pdev)) {
2841 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
2842 nvme_dev_disable(dev, true);
2843 nvme_dev_remove_admin(dev);
2846 flush_work(&dev->ctrl.reset_work);
2847 nvme_stop_ctrl(&dev->ctrl);
2848 nvme_remove_namespaces(&dev->ctrl);
2849 nvme_dev_disable(dev, true);
2850 nvme_release_cmb(dev);
2851 nvme_free_host_mem(dev);
2852 nvme_dev_remove_admin(dev);
2853 nvme_free_queues(dev, 0);
2854 nvme_uninit_ctrl(&dev->ctrl);
2855 nvme_release_prp_pools(dev);
2856 nvme_dev_unmap(dev);
2857 nvme_put_ctrl(&dev->ctrl);
2860 #ifdef CONFIG_PM_SLEEP
2861 static int nvme_suspend(struct device *dev)
2863 struct pci_dev *pdev = to_pci_dev(dev);
2864 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2866 nvme_dev_disable(ndev, true);
2870 static int nvme_resume(struct device *dev)
2872 struct pci_dev *pdev = to_pci_dev(dev);
2873 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2875 nvme_reset_ctrl(&ndev->ctrl);
2880 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2882 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2883 pci_channel_state_t state)
2885 struct nvme_dev *dev = pci_get_drvdata(pdev);
2888 * A frozen channel requires a reset. When detected, this method will
2889 * shutdown the controller to quiesce. The controller will be restarted
2890 * after the slot reset through driver's slot_reset callback.
2893 case pci_channel_io_normal:
2894 return PCI_ERS_RESULT_CAN_RECOVER;
2895 case pci_channel_io_frozen:
2896 dev_warn(dev->ctrl.device,
2897 "frozen state error detected, reset controller\n");
2898 nvme_dev_disable(dev, false);
2899 return PCI_ERS_RESULT_NEED_RESET;
2900 case pci_channel_io_perm_failure:
2901 dev_warn(dev->ctrl.device,
2902 "failure state error detected, request disconnect\n");
2903 return PCI_ERS_RESULT_DISCONNECT;
2905 return PCI_ERS_RESULT_NEED_RESET;
2908 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2910 struct nvme_dev *dev = pci_get_drvdata(pdev);
2912 dev_info(dev->ctrl.device, "restart after slot reset\n");
2913 pci_restore_state(pdev);
2914 nvme_reset_ctrl(&dev->ctrl);
2915 return PCI_ERS_RESULT_RECOVERED;
2918 static void nvme_error_resume(struct pci_dev *pdev)
2920 struct nvme_dev *dev = pci_get_drvdata(pdev);
2922 flush_work(&dev->ctrl.reset_work);
2925 static const struct pci_error_handlers nvme_err_handler = {
2926 .error_detected = nvme_error_detected,
2927 .slot_reset = nvme_slot_reset,
2928 .resume = nvme_error_resume,
2929 .reset_prepare = nvme_reset_prepare,
2930 .reset_done = nvme_reset_done,
2933 static const struct pci_device_id nvme_id_table[] = {
2934 { PCI_VDEVICE(INTEL, 0x0953),
2935 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2936 NVME_QUIRK_DEALLOCATE_ZEROES, },
2937 { PCI_VDEVICE(INTEL, 0x0a53),
2938 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2939 NVME_QUIRK_DEALLOCATE_ZEROES, },
2940 { PCI_VDEVICE(INTEL, 0x0a54),
2941 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2942 NVME_QUIRK_DEALLOCATE_ZEROES, },
2943 { PCI_VDEVICE(INTEL, 0x0a55),
2944 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2945 NVME_QUIRK_DEALLOCATE_ZEROES, },
2946 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
2947 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
2948 NVME_QUIRK_MEDIUM_PRIO_SQ },
2949 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
2950 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
2951 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
2952 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2953 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
2954 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2955 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
2956 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2957 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
2958 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2959 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
2960 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2961 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
2962 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2963 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
2964 .driver_data = NVME_QUIRK_LIGHTNVM, },
2965 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
2966 .driver_data = NVME_QUIRK_LIGHTNVM, },
2967 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
2968 .driver_data = NVME_QUIRK_LIGHTNVM, },
2969 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2970 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2971 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
2974 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2976 static struct pci_driver nvme_driver = {
2978 .id_table = nvme_id_table,
2979 .probe = nvme_probe,
2980 .remove = nvme_remove,
2981 .shutdown = nvme_shutdown,
2983 .pm = &nvme_dev_pm_ops,
2985 .sriov_configure = pci_sriov_configure_simple,
2986 .err_handler = &nvme_err_handler,
2989 static int __init nvme_init(void)
2991 return pci_register_driver(&nvme_driver);
2994 static void __exit nvme_exit(void)
2996 pci_unregister_driver(&nvme_driver);
2997 flush_workqueue(nvme_wq);
3001 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3002 MODULE_LICENSE("GPL");
3003 MODULE_VERSION("1.0");
3004 module_init(nvme_init);
3005 module_exit(nvme_exit);