drivers/nvme/host/pci.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * NVM Express device driver
   4  * Copyright (c) 2011-2014, Intel Corporation.
   5  */
   6
   7 #include <linux/acpi.h>
   8 #include <linux/aer.h>
   9 #include <linux/async.h>
  10 #include <linux/blkdev.h>
  11 #include <linux/blk-mq.h>
  12 #include <linux/blk-mq-pci.h>
  13 #include <linux/blk-integrity.h>
  14 #include <linux/dmi.h>
  15 #include <linux/init.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/io.h>
  18 #include <linux/mm.h>
  19 #include <linux/module.h>
  20 #include <linux/mutex.h>
  21 #include <linux/once.h>
  22 #include <linux/pci.h>
  23 #include <linux/suspend.h>
  24 #include <linux/t10-pi.h>
  25 #include <linux/types.h>
  26 #include <linux/io-64-nonatomic-lo-hi.h>
  27 #include <linux/io-64-nonatomic-hi-lo.h>
  28 #include <linux/sed-opal.h>
  29 #include <linux/pci-p2pdma.h>
  30
  31 #include "trace.h"
  32 #include "nvme.h"
  33
  34 #define SQ_SIZE(q)      ((q)->q_depth << (q)->sqes)
  35 #define CQ_SIZE(q)      ((q)->q_depth * sizeof(struct nvme_completion))
  36
  37 #define SGES_PER_PAGE   (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
  38
  39 /*
  40  * These can be higher, but we need to ensure that any command doesn't
  41  * require an sg allocation that needs more than a page of data.
  42  */
  43 #define NVME_MAX_KB_SZ  4096
  44 #define NVME_MAX_SEGS   127
  45
  46 static int use_threaded_interrupts;
  47 module_param(use_threaded_interrupts, int, 0);
  48
  49 static bool use_cmb_sqes = true;
  50 module_param(use_cmb_sqes, bool, 0444);
  51 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
  52
  53 static unsigned int max_host_mem_size_mb = 128;
  54 module_param(max_host_mem_size_mb, uint, 0444);
  55 MODULE_PARM_DESC(max_host_mem_size_mb,
  56         "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
  57
  58 static unsigned int sgl_threshold = SZ_32K;
  59 module_param(sgl_threshold, uint, 0644);
  60 MODULE_PARM_DESC(sgl_threshold,
  61                 "Use SGLs when average request segment size is larger or equal to "
  62                 "this size. Use 0 to disable SGLs.");
  63
  64 #define NVME_PCI_MIN_QUEUE_SIZE 2
  65 #define NVME_PCI_MAX_QUEUE_SIZE 4095
  66 static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
  67 static const struct kernel_param_ops io_queue_depth_ops = {
  68         .set = io_queue_depth_set,
  69         .get = param_get_uint,
  70 };
  71
  72 static unsigned int io_queue_depth = 1024;
  73 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
  74 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096");
  75
  76 static int io_queue_count_set(const char *val, const struct kernel_param *kp)
  77 {
  78         unsigned int n;
  79         int ret;
  80
  81         ret = kstrtouint(val, 10, &n);
  82         if (ret != 0 || n > num_possible_cpus())
  83                 return -EINVAL;
  84         return param_set_uint(val, kp);
  85 }
  86
  87 static const struct kernel_param_ops io_queue_count_ops = {
  88         .set = io_queue_count_set,
  89         .get = param_get_uint,
  90 };
  91
  92 static unsigned int write_queues;
  93 module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
  94 MODULE_PARM_DESC(write_queues,
  95         "Number of queues to use for writes. If not set, reads and writes "
  96         "will share a queue set.");
  97
  98 static unsigned int poll_queues;
  99 module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
 100 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
 101
 102 static bool noacpi;
 103 module_param(noacpi, bool, 0444);
 104 MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
 105
 106 struct nvme_dev;
 107 struct nvme_queue;
 108
 109 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
 110 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
 111
 112 /*
 113  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
 114  */
 115 struct nvme_dev {
 116         struct nvme_queue *queues;
 117         struct blk_mq_tag_set tagset;
 118         struct blk_mq_tag_set admin_tagset;
 119         u32 __iomem *dbs;
 120         struct device *dev;
 121         struct dma_pool *prp_page_pool;
 122         struct dma_pool *prp_small_pool;
 123         unsigned online_queues;
 124         unsigned max_qid;
 125         unsigned io_queues[HCTX_MAX_TYPES];
 126         unsigned int num_vecs;
 127         u32 q_depth;
 128         int io_sqes;
 129         u32 db_stride;
 130         void __iomem *bar;
 131         unsigned long bar_mapped_size;
 132         struct work_struct remove_work;
 133         struct mutex shutdown_lock;
 134         bool subsystem;
 135         u64 cmb_size;
 136         bool cmb_use_sqes;
 137         u32 cmbsz;
 138         u32 cmbloc;
 139         struct nvme_ctrl ctrl;
 140         u32 last_ps;
 141         bool hmb;
 142
 143         mempool_t *iod_mempool;
 144
 145         /* shadow doorbell buffer support: */
 146         u32 *dbbuf_dbs;
 147         dma_addr_t dbbuf_dbs_dma_addr;
 148         u32 *dbbuf_eis;
 149         dma_addr_t dbbuf_eis_dma_addr;
 150
 151         /* host memory buffer support: */
 152         u64 host_mem_size;
 153         u32 nr_host_mem_descs;
 154         dma_addr_t host_mem_descs_dma;
 155         struct nvme_host_mem_buf_desc *host_mem_descs;
 156         void **host_mem_desc_bufs;
 157         unsigned int nr_allocated_queues;
 158         unsigned int nr_write_queues;
 159         unsigned int nr_poll_queues;
 160
 161         bool attrs_added;
 162 };
 163
 164 static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
 165 {
 166         return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE,
 167                         NVME_PCI_MAX_QUEUE_SIZE);
 168 }
 169
 170 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
 171 {
 172         return qid * 2 * stride;
 173 }
 174
 175 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
 176 {
 177         return (qid * 2 + 1) * stride;
 178 }
 179
 180 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
 181 {
 182         return container_of(ctrl, struct nvme_dev, ctrl);
 183 }
 184
 185 /*
 186  * An NVM Express queue.  Each device has at least two (one for admin
 187  * commands and one for I/O commands).
 188  */
 189 struct nvme_queue {
 190         struct nvme_dev *dev;
 191         spinlock_t sq_lock;
 192         void *sq_cmds;
 193          /* only used for poll queues: */
 194         spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
 195         struct nvme_completion *cqes;
 196         dma_addr_t sq_dma_addr;
 197         dma_addr_t cq_dma_addr;
 198         u32 __iomem *q_db;
 199         u32 q_depth;
 200         u16 cq_vector;
 201         u16 sq_tail;
 202         u16 last_sq_tail;
 203         u16 cq_head;
 204         u16 qid;
 205         u8 cq_phase;
 206         u8 sqes;
 207         unsigned long flags;
 208 #define NVMEQ_ENABLED           0
 209 #define NVMEQ_SQ_CMB            1
 210 #define NVMEQ_DELETE_ERROR      2
 211 #define NVMEQ_POLLED            3
 212         u32 *dbbuf_sq_db;
 213         u32 *dbbuf_cq_db;
 214         u32 *dbbuf_sq_ei;
 215         u32 *dbbuf_cq_ei;
 216         struct completion delete_done;
 217 };
 218
 219 /*
 220  * The nvme_iod describes the data in an I/O.
 221  *
 222  * The sg pointer contains the list of PRP/SGL chunk allocations in addition
 223  * to the actual struct scatterlist.
 224  */
 225 struct nvme_iod {
 226         struct nvme_request req;
 227         struct nvme_command cmd;
 228         struct nvme_queue *nvmeq;
 229         bool use_sgl;
 230         int aborted;
 231         int npages;             /* In the PRP list. 0 means small pool in use */
 232         int nents;              /* Used in scatterlist */
 233         dma_addr_t first_dma;
 234         unsigned int dma_len;   /* length of single DMA segment mapping */
 235         dma_addr_t meta_dma;
 236         struct scatterlist *sg;
 237 };
 238
 239 static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
 240 {
 241         return dev->nr_allocated_queues * 8 * dev->db_stride;
 242 }
 243
 244 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
 245 {
 246         unsigned int mem_size = nvme_dbbuf_size(dev);
 247
 248         if (dev->dbbuf_dbs) {
 249                 /*
 250                  * Clear the dbbuf memory so the driver doesn't observe stale
 251                  * values from the previous instantiation.
 252                  */
 253                 memset(dev->dbbuf_dbs, 0, mem_size);
 254                 memset(dev->dbbuf_eis, 0, mem_size);
 255                 return 0;
 256         }
 257
 258         dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
 259                                             &dev->dbbuf_dbs_dma_addr,
 260                                             GFP_KERNEL);
 261         if (!dev->dbbuf_dbs)
 262                 return -ENOMEM;
 263         dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
 264                                             &dev->dbbuf_eis_dma_addr,
 265                                             GFP_KERNEL);
 266         if (!dev->dbbuf_eis) {
 267                 dma_free_coherent(dev->dev, mem_size,
 268                                   dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
 269                 dev->dbbuf_dbs = NULL;
 270                 return -ENOMEM;
 271         }
 272
 273         return 0;
 274 }
 275
 276 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
 277 {
 278         unsigned int mem_size = nvme_dbbuf_size(dev);
 279
 280         if (dev->dbbuf_dbs) {
 281                 dma_free_coherent(dev->dev, mem_size,
 282                                   dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
 283                 dev->dbbuf_dbs = NULL;
 284         }
 285         if (dev->dbbuf_eis) {
 286                 dma_free_coherent(dev->dev, mem_size,
 287                                   dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
 288                 dev->dbbuf_eis = NULL;
 289         }
 290 }
 291
 292 static void nvme_dbbuf_init(struct nvme_dev *dev,
 293                             struct nvme_queue *nvmeq, int qid)
 294 {
 295         if (!dev->dbbuf_dbs || !qid)
 296                 return;
 297
 298         nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
 299         nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
 300         nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
 301         nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
 302 }
 303
 304 static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
 305 {
 306         if (!nvmeq->qid)
 307                 return;
 308
 309         nvmeq->dbbuf_sq_db = NULL;
 310         nvmeq->dbbuf_cq_db = NULL;
 311         nvmeq->dbbuf_sq_ei = NULL;
 312         nvmeq->dbbuf_cq_ei = NULL;
 313 }
 314
 315 static void nvme_dbbuf_set(struct nvme_dev *dev)
 316 {
 317         struct nvme_command c = { };
 318         unsigned int i;
 319
 320         if (!dev->dbbuf_dbs)
 321                 return;
 322
 323         c.dbbuf.opcode = nvme_admin_dbbuf;
 324         c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
 325         c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
 326
 327         if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
 328                 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
 329                 /* Free memory and continue on */
 330                 nvme_dbbuf_dma_free(dev);
 331
 332                 for (i = 1; i <= dev->online_queues; i++)
 333                         nvme_dbbuf_free(&dev->queues[i]);
 334         }
 335 }
 336
 337 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
 338 {
 339         return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
 340 }
 341
 342 /* Update dbbuf and return true if an MMIO is required */
 343 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
 344                                               volatile u32 *dbbuf_ei)
 345 {
 346         if (dbbuf_db) {
 347                 u16 old_value;
 348
 349                 /*
 350                  * Ensure that the queue is written before updating
 351                  * the doorbell in memory
 352                  */
 353                 wmb();
 354
 355                 old_value = *dbbuf_db;
 356                 *dbbuf_db = value;
 357
 358                 /*
 359                  * Ensure that the doorbell is updated before reading the event
 360                  * index from memory.  The controller needs to provide similar
 361                  * ordering to ensure the envent index is updated before reading
 362                  * the doorbell.
 363                  */
 364                 mb();
 365
 366                 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
 367                         return false;
 368         }
 369
 370         return true;
 371 }
 372
 373 /*
 374  * Will slightly overestimate the number of pages needed.  This is OK
 375  * as it only leads to a small amount of wasted memory for the lifetime of
 376  * the I/O.
 377  */
 378 static int nvme_pci_npages_prp(void)
 379 {
 380         unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE,
 381                                       NVME_CTRL_PAGE_SIZE);
 382         return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
 383 }
 384
 385 /*
 386  * Calculates the number of pages needed for the SGL segments. For example a 4k
 387  * page can accommodate 256 SGL descriptors.
 388  */
 389 static int nvme_pci_npages_sgl(void)
 390 {
 391         return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc),
 392                         PAGE_SIZE);
 393 }
 394
 395 static size_t nvme_pci_iod_alloc_size(void)
 396 {
 397         size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl());
 398
 399         return sizeof(__le64 *) * npages +
 400                 sizeof(struct scatterlist) * NVME_MAX_SEGS;
 401 }
 402
 403 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 404                                 unsigned int hctx_idx)
 405 {
 406         struct nvme_dev *dev = data;
 407         struct nvme_queue *nvmeq = &dev->queues[0];
 408
 409         WARN_ON(hctx_idx != 0);
 410         WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
 411
 412         hctx->driver_data = nvmeq;
 413         return 0;
 414 }
 415
 416 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 417                           unsigned int hctx_idx)
 418 {
 419         struct nvme_dev *dev = data;
 420         struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
 421
 422         WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
 423         hctx->driver_data = nvmeq;
 424         return 0;
 425 }
 426
 427 static int nvme_pci_init_request(struct blk_mq_tag_set *set,
 428                 struct request *req, unsigned int hctx_idx,
 429                 unsigned int numa_node)
 430 {
 431         struct nvme_dev *dev = set->driver_data;
 432         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 433         int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
 434         struct nvme_queue *nvmeq = &dev->queues[queue_idx];
 435
 436         BUG_ON(!nvmeq);
 437         iod->nvmeq = nvmeq;
 438
 439         nvme_req(req)->ctrl = &dev->ctrl;
 440         nvme_req(req)->cmd = &iod->cmd;
 441         return 0;
 442 }
 443
 444 static int queue_irq_offset(struct nvme_dev *dev)
 445 {
 446         /* if we have more than 1 vec, admin queue offsets us by 1 */
 447         if (dev->num_vecs > 1)
 448                 return 1;
 449
 450         return 0;
 451 }
 452
 453 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
 454 {
 455         struct nvme_dev *dev = set->driver_data;
 456         int i, qoff, offset;
 457
 458         offset = queue_irq_offset(dev);
 459         for (i = 0, qoff = 0; i < set->nr_maps; i++) {
 460                 struct blk_mq_queue_map *map = &set->map[i];
 461
 462                 map->nr_queues = dev->io_queues[i];
 463                 if (!map->nr_queues) {
 464                         BUG_ON(i == HCTX_TYPE_DEFAULT);
 465                         continue;
 466                 }
 467
 468                 /*
 469                  * The poll queue(s) doesn't have an IRQ (and hence IRQ
 470                  * affinity), so use the regular blk-mq cpu mapping
 471                  */
 472                 map->queue_offset = qoff;
 473                 if (i != HCTX_TYPE_POLL && offset)
 474                         blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
 475                 else
 476                         blk_mq_map_queues(map);
 477                 qoff += map->nr_queues;
 478                 offset += map->nr_queues;
 479         }
 480
 481         return 0;
 482 }
 483
 484 /*
 485  * Write sq tail if we are asked to, or if the next command would wrap.
 486  */
 487 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
 488 {
 489         if (!write_sq) {
 490                 u16 next_tail = nvmeq->sq_tail + 1;
 491
 492                 if (next_tail == nvmeq->q_depth)
 493                         next_tail = 0;
 494                 if (next_tail != nvmeq->last_sq_tail)
 495                         return;
 496         }
 497
 498         if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
 499                         nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
 500                 writel(nvmeq->sq_tail, nvmeq->q_db);
 501         nvmeq->last_sq_tail = nvmeq->sq_tail;
 502 }
 503
 504 static inline void nvme_sq_copy_cmd(struct nvme_queue *nvmeq,
 505                                     struct nvme_command *cmd)
 506 {
 507         memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
 508                 absolute_pointer(cmd), sizeof(*cmd));
 509         if (++nvmeq->sq_tail == nvmeq->q_depth)
 510                 nvmeq->sq_tail = 0;
 511 }
 512
 513 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
 514 {
 515         struct nvme_queue *nvmeq = hctx->driver_data;
 516
 517         spin_lock(&nvmeq->sq_lock);
 518         if (nvmeq->sq_tail != nvmeq->last_sq_tail)
 519                 nvme_write_sq_db(nvmeq, true);
 520         spin_unlock(&nvmeq->sq_lock);
 521 }
 522
 523 static void **nvme_pci_iod_list(struct request *req)
 524 {
 525         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 526         return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
 527 }
 528
 529 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
 530 {
 531         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 532         int nseg = blk_rq_nr_phys_segments(req);
 533         unsigned int avg_seg_size;
 534
 535         avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
 536
 537         if (!nvme_ctrl_sgl_supported(&dev->ctrl))
 538                 return false;
 539         if (!iod->nvmeq->qid)
 540                 return false;
 541         if (!sgl_threshold || avg_seg_size < sgl_threshold)
 542                 return false;
 543         return true;
 544 }
 545
 546 static void nvme_free_prps(struct nvme_dev *dev, struct request *req)
 547 {
 548         const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
 549         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 550         dma_addr_t dma_addr = iod->first_dma;
 551         int i;
 552
 553         for (i = 0; i < iod->npages; i++) {
 554                 __le64 *prp_list = nvme_pci_iod_list(req)[i];
 555                 dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]);
 556
 557                 dma_pool_free(dev->prp_page_pool, prp_list, dma_addr);
 558                 dma_addr = next_dma_addr;
 559         }
 560 }
 561
 562 static void nvme_free_sgls(struct nvme_dev *dev, struct request *req)
 563 {
 564         const int last_sg = SGES_PER_PAGE - 1;
 565         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 566         dma_addr_t dma_addr = iod->first_dma;
 567         int i;
 568
 569         for (i = 0; i < iod->npages; i++) {
 570                 struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i];
 571                 dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr);
 572
 573                 dma_pool_free(dev->prp_page_pool, sg_list, dma_addr);
 574                 dma_addr = next_dma_addr;
 575         }
 576 }
 577
 578 static void nvme_unmap_sg(struct nvme_dev *dev, struct request *req)
 579 {
 580         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 581
 582         if (is_pci_p2pdma_page(sg_page(iod->sg)))
 583                 pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents,
 584                                     rq_dma_dir(req));
 585         else
 586                 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req));
 587 }
 588
 589 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
 590 {
 591         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 592
 593         if (iod->dma_len) {
 594                 dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len,
 595                                rq_dma_dir(req));
 596                 return;
 597         }
 598
 599         WARN_ON_ONCE(!iod->nents);
 600
 601         nvme_unmap_sg(dev, req);
 602         if (iod->npages == 0)
 603                 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
 604                               iod->first_dma);
 605         else if (iod->use_sgl)
 606                 nvme_free_sgls(dev, req);
 607         else
 608                 nvme_free_prps(dev, req);
 609         mempool_free(iod->sg, dev->iod_mempool);
 610 }
 611
 612 static void nvme_print_sgl(struct scatterlist *sgl, int nents)
 613 {
 614         int i;
 615         struct scatterlist *sg;
 616
 617         for_each_sg(sgl, sg, nents, i) {
 618                 dma_addr_t phys = sg_phys(sg);
 619                 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
 620                         "dma_address:%pad dma_length:%d\n",
 621                         i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
 622                         sg_dma_len(sg));
 623         }
 624 }
 625
 626 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
 627                 struct request *req, struct nvme_rw_command *cmnd)
 628 {
 629         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 630         struct dma_pool *pool;
 631         int length = blk_rq_payload_bytes(req);
 632         struct scatterlist *sg = iod->sg;
 633         int dma_len = sg_dma_len(sg);
 634         u64 dma_addr = sg_dma_address(sg);
 635         int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
 636         __le64 *prp_list;
 637         void **list = nvme_pci_iod_list(req);
 638         dma_addr_t prp_dma;
 639         int nprps, i;
 640
 641         length -= (NVME_CTRL_PAGE_SIZE - offset);
 642         if (length <= 0) {
 643                 iod->first_dma = 0;
 644                 goto done;
 645         }
 646
 647         dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
 648         if (dma_len) {
 649                 dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
 650         } else {
 651                 sg = sg_next(sg);
 652                 dma_addr = sg_dma_address(sg);
 653                 dma_len = sg_dma_len(sg);
 654         }
 655
 656         if (length <= NVME_CTRL_PAGE_SIZE) {
 657                 iod->first_dma = dma_addr;
 658                 goto done;
 659         }
 660
 661         nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE);
 662         if (nprps <= (256 / 8)) {
 663                 pool = dev->prp_small_pool;
 664                 iod->npages = 0;
 665         } else {
 666                 pool = dev->prp_page_pool;
 667                 iod->npages = 1;
 668         }
 669
 670         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 671         if (!prp_list) {
 672                 iod->first_dma = dma_addr;
 673                 iod->npages = -1;
 674                 return BLK_STS_RESOURCE;
 675         }
 676         list[0] = prp_list;
 677         iod->first_dma = prp_dma;
 678         i = 0;
 679         for (;;) {
 680                 if (i == NVME_CTRL_PAGE_SIZE >> 3) {
 681                         __le64 *old_prp_list = prp_list;
 682                         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 683                         if (!prp_list)
 684                                 goto free_prps;
 685                         list[iod->npages++] = prp_list;
 686                         prp_list[0] = old_prp_list[i - 1];
 687                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
 688                         i = 1;
 689                 }
 690                 prp_list[i++] = cpu_to_le64(dma_addr);
 691                 dma_len -= NVME_CTRL_PAGE_SIZE;
 692                 dma_addr += NVME_CTRL_PAGE_SIZE;
 693                 length -= NVME_CTRL_PAGE_SIZE;
 694                 if (length <= 0)
 695                         break;
 696                 if (dma_len > 0)
 697                         continue;
 698                 if (unlikely(dma_len < 0))
 699                         goto bad_sgl;
 700                 sg = sg_next(sg);
 701                 dma_addr = sg_dma_address(sg);
 702                 dma_len = sg_dma_len(sg);
 703         }
 704 done:
 705         cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
 706         cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
 707         return BLK_STS_OK;
 708 free_prps:
 709         nvme_free_prps(dev, req);
 710         return BLK_STS_RESOURCE;
 711 bad_sgl:
 712         WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
 713                         "Invalid SGL for payload:%d nents:%d\n",
 714                         blk_rq_payload_bytes(req), iod->nents);
 715         return BLK_STS_IOERR;
 716 }
 717
 718 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
 719                 struct scatterlist *sg)
 720 {
 721         sge->addr = cpu_to_le64(sg_dma_address(sg));
 722         sge->length = cpu_to_le32(sg_dma_len(sg));
 723         sge->type = NVME_SGL_FMT_DATA_DESC << 4;
 724 }
 725
 726 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
 727                 dma_addr_t dma_addr, int entries)
 728 {
 729         sge->addr = cpu_to_le64(dma_addr);
 730         if (entries < SGES_PER_PAGE) {
 731                 sge->length = cpu_to_le32(entries * sizeof(*sge));
 732                 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
 733         } else {
 734                 sge->length = cpu_to_le32(PAGE_SIZE);
 735                 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
 736         }
 737 }
 738
 739 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
 740                 struct request *req, struct nvme_rw_command *cmd, int entries)
 741 {
 742         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 743         struct dma_pool *pool;
 744         struct nvme_sgl_desc *sg_list;
 745         struct scatterlist *sg = iod->sg;
 746         dma_addr_t sgl_dma;
 747         int i = 0;
 748
 749         /* setting the transfer type as SGL */
 750         cmd->flags = NVME_CMD_SGL_METABUF;
 751
 752         if (entries == 1) {
 753                 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
 754                 return BLK_STS_OK;
 755         }
 756
 757         if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
 758                 pool = dev->prp_small_pool;
 759                 iod->npages = 0;
 760         } else {
 761                 pool = dev->prp_page_pool;
 762                 iod->npages = 1;
 763         }
 764
 765         sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
 766         if (!sg_list) {
 767                 iod->npages = -1;
 768                 return BLK_STS_RESOURCE;
 769         }
 770
 771         nvme_pci_iod_list(req)[0] = sg_list;
 772         iod->first_dma = sgl_dma;
 773
 774         nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
 775
 776         do {
 777                 if (i == SGES_PER_PAGE) {
 778                         struct nvme_sgl_desc *old_sg_desc = sg_list;
 779                         struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
 780
 781                         sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
 782                         if (!sg_list)
 783                                 goto free_sgls;
 784
 785                         i = 0;
 786                         nvme_pci_iod_list(req)[iod->npages++] = sg_list;
 787                         sg_list[i++] = *link;
 788                         nvme_pci_sgl_set_seg(link, sgl_dma, entries);
 789                 }
 790
 791                 nvme_pci_sgl_set_data(&sg_list[i++], sg);
 792                 sg = sg_next(sg);
 793         } while (--entries > 0);
 794
 795         return BLK_STS_OK;
 796 free_sgls:
 797         nvme_free_sgls(dev, req);
 798         return BLK_STS_RESOURCE;
 799 }
 800
 801 static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
 802                 struct request *req, struct nvme_rw_command *cmnd,
 803                 struct bio_vec *bv)
 804 {
 805         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 806         unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
 807         unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
 808
 809         iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
 810         if (dma_mapping_error(dev->dev, iod->first_dma))
 811                 return BLK_STS_RESOURCE;
 812         iod->dma_len = bv->bv_len;
 813
 814         cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
 815         if (bv->bv_len > first_prp_len)
 816                 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
 817         return BLK_STS_OK;
 818 }
 819
 820 static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
 821                 struct request *req, struct nvme_rw_command *cmnd,
 822                 struct bio_vec *bv)
 823 {
 824         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 825
 826         iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
 827         if (dma_mapping_error(dev->dev, iod->first_dma))
 828                 return BLK_STS_RESOURCE;
 829         iod->dma_len = bv->bv_len;
 830
 831         cmnd->flags = NVME_CMD_SGL_METABUF;
 832         cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
 833         cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
 834         cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
 835         return BLK_STS_OK;
 836 }
 837
 838 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
 839                 struct nvme_command *cmnd)
 840 {
 841         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 842         blk_status_t ret = BLK_STS_RESOURCE;
 843         int nr_mapped;
 844
 845         if (blk_rq_nr_phys_segments(req) == 1) {
 846                 struct bio_vec bv = req_bvec(req);
 847
 848                 if (!is_pci_p2pdma_page(bv.bv_page)) {
 849                         if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
 850                                 return nvme_setup_prp_simple(dev, req,
 851                                                              &cmnd->rw, &bv);
 852
 853                         if (iod->nvmeq->qid && sgl_threshold &&
 854                             nvme_ctrl_sgl_supported(&dev->ctrl))
 855                                 return nvme_setup_sgl_simple(dev, req,
 856                                                              &cmnd->rw, &bv);
 857                 }
 858         }
 859
 860         iod->dma_len = 0;
 861         iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
 862         if (!iod->sg)
 863                 return BLK_STS_RESOURCE;
 864         sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
 865         iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
 866         if (!iod->nents)
 867                 goto out_free_sg;
 868
 869         if (is_pci_p2pdma_page(sg_page(iod->sg)))
 870                 nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg,
 871                                 iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN);
 872         else
 873                 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
 874                                              rq_dma_dir(req), DMA_ATTR_NO_WARN);
 875         if (!nr_mapped)
 876                 goto out_free_sg;
 877
 878         iod->use_sgl = nvme_pci_use_sgls(dev, req);
 879         if (iod->use_sgl)
 880                 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
 881         else
 882                 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
 883         if (ret != BLK_STS_OK)
 884                 goto out_unmap_sg;
 885         return BLK_STS_OK;
 886
 887 out_unmap_sg:
 888         nvme_unmap_sg(dev, req);
 889 out_free_sg:
 890         mempool_free(iod->sg, dev->iod_mempool);
 891         return ret;
 892 }
 893
 894 static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
 895                 struct nvme_command *cmnd)
 896 {
 897         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 898
 899         iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
 900                         rq_dma_dir(req), 0);
 901         if (dma_mapping_error(dev->dev, iod->meta_dma))
 902                 return BLK_STS_IOERR;
 903         cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
 904         return BLK_STS_OK;
 905 }
 906
 907 static blk_status_t nvme_prep_rq(struct nvme_dev *dev, struct request *req)
 908 {
 909         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 910         blk_status_t ret;
 911
 912         iod->aborted = 0;
 913         iod->npages = -1;
 914         iod->nents = 0;
 915
 916         ret = nvme_setup_cmd(req->q->queuedata, req);
 917         if (ret)
 918                 return ret;
 919
 920         if (blk_rq_nr_phys_segments(req)) {
 921                 ret = nvme_map_data(dev, req, &iod->cmd);
 922                 if (ret)
 923                         goto out_free_cmd;
 924         }
 925
 926         if (blk_integrity_rq(req)) {
 927                 ret = nvme_map_metadata(dev, req, &iod->cmd);
 928                 if (ret)
 929                         goto out_unmap_data;
 930         }
 931
 932         blk_mq_start_request(req);
 933         return BLK_STS_OK;
 934 out_unmap_data:
 935         nvme_unmap_data(dev, req);
 936 out_free_cmd:
 937         nvme_cleanup_cmd(req);
 938         return ret;
 939 }
 940
 941 /*
 942  * NOTE: ns is NULL when called on the admin queue.
 943  */
 944 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
 945                          const struct blk_mq_queue_data *bd)
 946 {
 947         struct nvme_queue *nvmeq = hctx->driver_data;
 948         struct nvme_dev *dev = nvmeq->dev;
 949         struct request *req = bd->rq;
 950         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 951         blk_status_t ret;
 952
 953         /*
 954          * We should not need to do this, but we're still using this to
 955          * ensure we can drain requests on a dying queue.
 956          */
 957         if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
 958                 return BLK_STS_IOERR;
 959
 960         if (unlikely(!nvme_check_ready(&dev->ctrl, req, true)))
 961                 return nvme_fail_nonready_command(&dev->ctrl, req);
 962
 963         ret = nvme_prep_rq(dev, req);
 964         if (unlikely(ret))
 965                 return ret;
 966         spin_lock(&nvmeq->sq_lock);
 967         nvme_sq_copy_cmd(nvmeq, &iod->cmd);
 968         nvme_write_sq_db(nvmeq, bd->last);
 969         spin_unlock(&nvmeq->sq_lock);
 970         return BLK_STS_OK;
 971 }
 972
 973 static void nvme_submit_cmds(struct nvme_queue *nvmeq, struct request **rqlist)
 974 {
 975         spin_lock(&nvmeq->sq_lock);
 976         while (!rq_list_empty(*rqlist)) {
 977                 struct request *req = rq_list_pop(rqlist);
 978                 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 979
 980                 nvme_sq_copy_cmd(nvmeq, &iod->cmd);
 981         }
 982         nvme_write_sq_db(nvmeq, true);
 983         spin_unlock(&nvmeq->sq_lock);
 984 }
 985
 986 static bool nvme_prep_rq_batch(struct nvme_queue *nvmeq, struct request *req)
 987 {
 988         /*
 989          * We should not need to do this, but we're still using this to
 990          * ensure we can drain requests on a dying queue.
 991          */
 992         if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
 993                 return false;
 994         if (unlikely(!nvme_check_ready(&nvmeq->dev->ctrl, req, true)))
 995                 return false;
 996
 997         req->mq_hctx->tags->rqs[req->tag] = req;
 998         return nvme_prep_rq(nvmeq->dev, req) == BLK_STS_OK;
 999 }
1000
1001 static void nvme_queue_rqs(struct request **rqlist)
1002 {
1003         struct request *req, *next, *prev = NULL;
1004         struct request *requeue_list = NULL;
1005
1006         rq_list_for_each_safe(rqlist, req, next) {
1007                 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
1008
1009                 if (!nvme_prep_rq_batch(nvmeq, req)) {
1010                         /* detach 'req' and add to remainder list */
1011                         rq_list_move(rqlist, &requeue_list, req, prev);
1012
1013                         req = prev;
1014                         if (!req)
1015                                 continue;
1016                 }
1017
1018                 if (!next || req->mq_hctx != next->mq_hctx) {
1019                         /* detach rest of list, and submit */
1020                         req->rq_next = NULL;
1021                         nvme_submit_cmds(nvmeq, rqlist);
1022                         *rqlist = next;
1023                         prev = NULL;
1024                 } else
1025                         prev = req;
1026         }
1027
1028         *rqlist = requeue_list;
1029 }
1030
1031 static __always_inline void nvme_pci_unmap_rq(struct request *req)
1032 {
1033         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1034         struct nvme_dev *dev = iod->nvmeq->dev;
1035
1036         if (blk_integrity_rq(req))
1037                 dma_unmap_page(dev->dev, iod->meta_dma,
1038                                rq_integrity_vec(req)->bv_len, rq_data_dir(req));
1039         if (blk_rq_nr_phys_segments(req))
1040                 nvme_unmap_data(dev, req);
1041 }
1042
1043 static void nvme_pci_complete_rq(struct request *req)
1044 {
1045         nvme_pci_unmap_rq(req);
1046         nvme_complete_rq(req);
1047 }
1048
1049 static void nvme_pci_complete_batch(struct io_comp_batch *iob)
1050 {
1051         nvme_complete_batch(iob, nvme_pci_unmap_rq);
1052 }
1053
1054 /* We read the CQE phase first to check if the rest of the entry is valid */
1055 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
1056 {
1057         struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
1058
1059         return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
1060 }
1061
1062 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
1063 {
1064         u16 head = nvmeq->cq_head;
1065
1066         if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
1067                                               nvmeq->dbbuf_cq_ei))
1068                 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
1069 }
1070
1071 static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
1072 {
1073         if (!nvmeq->qid)
1074                 return nvmeq->dev->admin_tagset.tags[0];
1075         return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
1076 }
1077
1078 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq,
1079                                    struct io_comp_batch *iob, u16 idx)
1080 {
1081         struct nvme_completion *cqe = &nvmeq->cqes[idx];
1082         __u16 command_id = READ_ONCE(cqe->command_id);
1083         struct request *req;
1084
1085         /*
1086          * AEN requests are special as they don't time out and can
1087          * survive any kind of queue freeze and often don't respond to
1088          * aborts.  We don't even bother to allocate a struct request
1089          * for them but rather special case them here.
1090          */
1091         if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) {
1092                 nvme_complete_async_event(&nvmeq->dev->ctrl,
1093                                 cqe->status, &cqe->result);
1094                 return;
1095         }
1096
1097         req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id);
1098         if (unlikely(!req)) {
1099                 dev_warn(nvmeq->dev->ctrl.device,
1100                         "invalid id %d completed on queue %d\n",
1101                         command_id, le16_to_cpu(cqe->sq_id));
1102                 return;
1103         }
1104
1105         trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
1106         if (!nvme_try_complete_req(req, cqe->status, cqe->result) &&
1107             !blk_mq_add_to_batch(req, iob, nvme_req(req)->status,
1108                                         nvme_pci_complete_batch))
1109                 nvme_pci_complete_rq(req);
1110 }
1111
1112 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1113 {
1114         u32 tmp = nvmeq->cq_head + 1;
1115
1116         if (tmp == nvmeq->q_depth) {
1117                 nvmeq->cq_head = 0;
1118                 nvmeq->cq_phase ^= 1;
1119         } else {
1120                 nvmeq->cq_head = tmp;
1121         }
1122 }
1123
1124 static inline int nvme_poll_cq(struct nvme_queue *nvmeq,
1125                                struct io_comp_batch *iob)
1126 {
1127         int found = 0;
1128
1129         while (nvme_cqe_pending(nvmeq)) {
1130                 found++;
1131                 /*
1132                  * load-load control dependency between phase and the rest of
1133                  * the cqe requires a full read memory barrier
1134                  */
1135                 dma_rmb();
1136                 nvme_handle_cqe(nvmeq, iob, nvmeq->cq_head);
1137                 nvme_update_cq_head(nvmeq);
1138         }
1139
1140         if (found)
1141                 nvme_ring_cq_doorbell(nvmeq);
1142         return found;
1143 }
1144
1145 static irqreturn_t nvme_irq(int irq, void *data)
1146 {
1147         struct nvme_queue *nvmeq = data;
1148         DEFINE_IO_COMP_BATCH(iob);
1149
1150         if (nvme_poll_cq(nvmeq, &iob)) {
1151                 if (!rq_list_empty(iob.req_list))
1152                         nvme_pci_complete_batch(&iob);
1153                 return IRQ_HANDLED;
1154         }
1155         return IRQ_NONE;
1156 }
1157
1158 static irqreturn_t nvme_irq_check(int irq, void *data)
1159 {
1160         struct nvme_queue *nvmeq = data;
1161
1162         if (nvme_cqe_pending(nvmeq))
1163                 return IRQ_WAKE_THREAD;
1164         return IRQ_NONE;
1165 }
1166
1167 /*
1168  * Poll for completions for any interrupt driven queue
1169  * Can be called from any context.
1170  */
1171 static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
1172 {
1173         struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1174
1175         WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
1176
1177         disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1178         nvme_poll_cq(nvmeq, NULL);
1179         enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1180 }
1181
1182 static int nvme_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob)
1183 {
1184         struct nvme_queue *nvmeq = hctx->driver_data;
1185         bool found;
1186
1187         if (!nvme_cqe_pending(nvmeq))
1188                 return 0;
1189
1190         spin_lock(&nvmeq->cq_poll_lock);
1191         found = nvme_poll_cq(nvmeq, iob);
1192         spin_unlock(&nvmeq->cq_poll_lock);
1193
1194         return found;
1195 }
1196
1197 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
1198 {
1199         struct nvme_dev *dev = to_nvme_dev(ctrl);
1200         struct nvme_queue *nvmeq = &dev->queues[0];
1201         struct nvme_command c = { };
1202
1203         c.common.opcode = nvme_admin_async_event;
1204         c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1205
1206         spin_lock(&nvmeq->sq_lock);
1207         nvme_sq_copy_cmd(nvmeq, &c);
1208         nvme_write_sq_db(nvmeq, true);
1209         spin_unlock(&nvmeq->sq_lock);
1210 }
1211
1212 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1213 {
1214         struct nvme_command c = { };
1215
1216         c.delete_queue.opcode = opcode;
1217         c.delete_queue.qid = cpu_to_le16(id);
1218
1219         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1220 }
1221
1222 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1223                 struct nvme_queue *nvmeq, s16 vector)
1224 {
1225         struct nvme_command c = { };
1226         int flags = NVME_QUEUE_PHYS_CONTIG;
1227
1228         if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
1229                 flags |= NVME_CQ_IRQ_ENABLED;
1230
1231         /*
1232          * Note: we (ab)use the fact that the prp fields survive if no data
1233          * is attached to the request.
1234          */
1235         c.create_cq.opcode = nvme_admin_create_cq;
1236         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1237         c.create_cq.cqid = cpu_to_le16(qid);
1238         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1239         c.create_cq.cq_flags = cpu_to_le16(flags);
1240         c.create_cq.irq_vector = cpu_to_le16(vector);
1241
1242         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1243 }
1244
1245 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1246                                                 struct nvme_queue *nvmeq)
1247 {
1248         struct nvme_ctrl *ctrl = &dev->ctrl;
1249         struct nvme_command c = { };
1250         int flags = NVME_QUEUE_PHYS_CONTIG;
1251
1252         /*
1253          * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1254          * set. Since URGENT priority is zeroes, it makes all queues
1255          * URGENT.
1256          */
1257         if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1258                 flags |= NVME_SQ_PRIO_MEDIUM;
1259
1260         /*
1261          * Note: we (ab)use the fact that the prp fields survive if no data
1262          * is attached to the request.
1263          */
1264         c.create_sq.opcode = nvme_admin_create_sq;
1265         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1266         c.create_sq.sqid = cpu_to_le16(qid);
1267         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1268         c.create_sq.sq_flags = cpu_to_le16(flags);
1269         c.create_sq.cqid = cpu_to_le16(qid);
1270
1271         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1272 }
1273
1274 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1275 {
1276         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1277 }
1278
1279 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1280 {
1281         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1282 }
1283
1284 static void abort_endio(struct request *req, blk_status_t error)
1285 {
1286         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1287         struct nvme_queue *nvmeq = iod->nvmeq;
1288
1289         dev_warn(nvmeq->dev->ctrl.device,
1290                  "Abort status: 0x%x", nvme_req(req)->status);
1291         atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1292         blk_mq_free_request(req);
1293 }
1294
1295 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1296 {
1297         /* If true, indicates loss of adapter communication, possibly by a
1298          * NVMe Subsystem reset.
1299          */
1300         bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1301
1302         /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1303         switch (dev->ctrl.state) {
1304         case NVME_CTRL_RESETTING:
1305         case NVME_CTRL_CONNECTING:
1306                 return false;
1307         default:
1308                 break;
1309         }
1310
1311         /* We shouldn't reset unless the controller is on fatal error state
1312          * _or_ if we lost the communication with it.
1313          */
1314         if (!(csts & NVME_CSTS_CFS) && !nssro)
1315                 return false;
1316
1317         return true;
1318 }
1319
1320 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1321 {
1322         /* Read a config register to help see what died. */
1323         u16 pci_status;
1324         int result;
1325
1326         result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1327                                       &pci_status);
1328         if (result == PCIBIOS_SUCCESSFUL)
1329                 dev_warn(dev->ctrl.device,
1330                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1331                          csts, pci_status);
1332         else
1333                 dev_warn(dev->ctrl.device,
1334                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1335                          csts, result);
1336 }
1337
1338 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1339 {
1340         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1341         struct nvme_queue *nvmeq = iod->nvmeq;
1342         struct nvme_dev *dev = nvmeq->dev;
1343         struct request *abort_req;
1344         struct nvme_command cmd = { };
1345         u32 csts = readl(dev->bar + NVME_REG_CSTS);
1346
1347         /* If PCI error recovery process is happening, we cannot reset or
1348          * the recovery mechanism will surely fail.
1349          */
1350         mb();
1351         if (pci_channel_offline(to_pci_dev(dev->dev)))
1352                 return BLK_EH_RESET_TIMER;
1353
1354         /*
1355          * Reset immediately if the controller is failed
1356          */
1357         if (nvme_should_reset(dev, csts)) {
1358                 nvme_warn_reset(dev, csts);
1359                 nvme_dev_disable(dev, false);
1360                 nvme_reset_ctrl(&dev->ctrl);
1361                 return BLK_EH_DONE;
1362         }
1363
1364         /*
1365          * Did we miss an interrupt?
1366          */
1367         if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
1368                 nvme_poll(req->mq_hctx, NULL);
1369         else
1370                 nvme_poll_irqdisable(nvmeq);
1371
1372         if (blk_mq_request_completed(req)) {
1373                 dev_warn(dev->ctrl.device,
1374                          "I/O %d QID %d timeout, completion polled\n",
1375                          req->tag, nvmeq->qid);
1376                 return BLK_EH_DONE;
1377         }
1378
1379         /*
1380          * Shutdown immediately if controller times out while starting. The
1381          * reset work will see the pci device disabled when it gets the forced
1382          * cancellation error. All outstanding requests are completed on
1383          * shutdown, so we return BLK_EH_DONE.
1384          */
1385         switch (dev->ctrl.state) {
1386         case NVME_CTRL_CONNECTING:
1387                 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
1388                 fallthrough;
1389         case NVME_CTRL_DELETING:
1390                 dev_warn_ratelimited(dev->ctrl.device,
1391                          "I/O %d QID %d timeout, disable controller\n",
1392                          req->tag, nvmeq->qid);
1393                 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1394                 nvme_dev_disable(dev, true);
1395                 return BLK_EH_DONE;
1396         case NVME_CTRL_RESETTING:
1397                 return BLK_EH_RESET_TIMER;
1398         default:
1399                 break;
1400         }
1401
1402         /*
1403          * Shutdown the controller immediately and schedule a reset if the
1404          * command was already aborted once before and still hasn't been
1405          * returned to the driver, or if this is the admin queue.
1406          */
1407         if (!nvmeq->qid || iod->aborted) {
1408                 dev_warn(dev->ctrl.device,
1409                          "I/O %d QID %d timeout, reset controller\n",
1410                          req->tag, nvmeq->qid);
1411                 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1412                 nvme_dev_disable(dev, false);
1413                 nvme_reset_ctrl(&dev->ctrl);
1414
1415                 return BLK_EH_DONE;
1416         }
1417
1418         if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1419                 atomic_inc(&dev->ctrl.abort_limit);
1420                 return BLK_EH_RESET_TIMER;
1421         }
1422         iod->aborted = 1;
1423
1424         cmd.abort.opcode = nvme_admin_abort_cmd;
1425         cmd.abort.cid = nvme_cid(req);
1426         cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1427
1428         dev_warn(nvmeq->dev->ctrl.device,
1429                 "I/O %d QID %d timeout, aborting\n",
1430                  req->tag, nvmeq->qid);
1431
1432         abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, nvme_req_op(&cmd),
1433                                          BLK_MQ_REQ_NOWAIT);
1434         if (IS_ERR(abort_req)) {
1435                 atomic_inc(&dev->ctrl.abort_limit);
1436                 return BLK_EH_RESET_TIMER;
1437         }
1438         nvme_init_request(abort_req, &cmd);
1439
1440         abort_req->end_io_data = NULL;
1441         blk_execute_rq_nowait(abort_req, false, abort_endio);
1442
1443         /*
1444          * The aborted req will be completed on receiving the abort req.
1445          * We enable the timer again. If hit twice, it'll cause a device reset,
1446          * as the device then is in a faulty state.
1447          */
1448         return BLK_EH_RESET_TIMER;
1449 }
1450
1451 static void nvme_free_queue(struct nvme_queue *nvmeq)
1452 {
1453         dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
1454                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1455         if (!nvmeq->sq_cmds)
1456                 return;
1457
1458         if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
1459                 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
1460                                 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1461         } else {
1462                 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
1463                                 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1464         }
1465 }
1466
1467 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1468 {
1469         int i;
1470
1471         for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1472                 dev->ctrl.queue_count--;
1473                 nvme_free_queue(&dev->queues[i]);
1474         }
1475 }
1476
1477 /**
1478  * nvme_suspend_queue - put queue into suspended state
1479  * @nvmeq: queue to suspend
1480  */
1481 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1482 {
1483         if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
1484                 return 1;
1485
1486         /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
1487         mb();
1488
1489         nvmeq->dev->online_queues--;
1490         if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1491                 nvme_stop_admin_queue(&nvmeq->dev->ctrl);
1492         if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1493                 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
1494         return 0;
1495 }
1496
1497 static void nvme_suspend_io_queues(struct nvme_dev *dev)
1498 {
1499         int i;
1500
1501         for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1502                 nvme_suspend_queue(&dev->queues[i]);
1503 }
1504
1505 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1506 {
1507         struct nvme_queue *nvmeq = &dev->queues[0];
1508
1509         if (shutdown)
1510                 nvme_shutdown_ctrl(&dev->ctrl);
1511         else
1512                 nvme_disable_ctrl(&dev->ctrl);
1513
1514         nvme_poll_irqdisable(nvmeq);
1515 }
1516
1517 /*
1518  * Called only on a device that has been disabled and after all other threads
1519  * that can check this device's completion queues have synced, except
1520  * nvme_poll(). This is the last chance for the driver to see a natural
1521  * completion before nvme_cancel_request() terminates all incomplete requests.
1522  */
1523 static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1524 {
1525         int i;
1526
1527         for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1528                 spin_lock(&dev->queues[i].cq_poll_lock);
1529                 nvme_poll_cq(&dev->queues[i], NULL);
1530                 spin_unlock(&dev->queues[i].cq_poll_lock);
1531         }
1532 }
1533
1534 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1535                                 int entry_size)
1536 {
1537         int q_depth = dev->q_depth;
1538         unsigned q_size_aligned = roundup(q_depth * entry_size,
1539                                           NVME_CTRL_PAGE_SIZE);
1540
1541         if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1542                 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1543
1544                 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
1545                 q_depth = div_u64(mem_per_q, entry_size);
1546
1547                 /*
1548                  * Ensure the reduced q_depth is above some threshold where it
1549                  * would be better to map queues in system memory with the
1550                  * original depth
1551                  */
1552                 if (q_depth < 64)
1553                         return -ENOMEM;
1554         }
1555
1556         return q_depth;
1557 }
1558
1559 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1560                                 int qid)
1561 {
1562         struct pci_dev *pdev = to_pci_dev(dev->dev);
1563
1564         if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1565                 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
1566                 if (nvmeq->sq_cmds) {
1567                         nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1568                                                         nvmeq->sq_cmds);
1569                         if (nvmeq->sq_dma_addr) {
1570                                 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1571                                 return 0;
1572                         }
1573
1574                         pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1575                 }
1576         }
1577
1578         nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
1579                                 &nvmeq->sq_dma_addr, GFP_KERNEL);
1580         if (!nvmeq->sq_cmds)
1581                 return -ENOMEM;
1582         return 0;
1583 }
1584
1585 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
1586 {
1587         struct nvme_queue *nvmeq = &dev->queues[qid];
1588
1589         if (dev->ctrl.queue_count > qid)
1590                 return 0;
1591
1592         nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
1593         nvmeq->q_depth = depth;
1594         nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
1595                                          &nvmeq->cq_dma_addr, GFP_KERNEL);
1596         if (!nvmeq->cqes)
1597                 goto free_nvmeq;
1598
1599         if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
1600                 goto free_cqdma;
1601
1602         nvmeq->dev = dev;
1603         spin_lock_init(&nvmeq->sq_lock);
1604         spin_lock_init(&nvmeq->cq_poll_lock);
1605         nvmeq->cq_head = 0;
1606         nvmeq->cq_phase = 1;
1607         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1608         nvmeq->qid = qid;
1609         dev->ctrl.queue_count++;
1610
1611         return 0;
1612
1613  free_cqdma:
1614         dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1615                           nvmeq->cq_dma_addr);
1616  free_nvmeq:
1617         return -ENOMEM;
1618 }
1619
1620 static int queue_request_irq(struct nvme_queue *nvmeq)
1621 {
1622         struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1623         int nr = nvmeq->dev->ctrl.instance;
1624
1625         if (use_threaded_interrupts) {
1626                 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1627                                 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1628         } else {
1629                 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1630                                 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1631         }
1632 }
1633
1634 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1635 {
1636         struct nvme_dev *dev = nvmeq->dev;
1637
1638         nvmeq->sq_tail = 0;
1639         nvmeq->last_sq_tail = 0;
1640         nvmeq->cq_head = 0;
1641         nvmeq->cq_phase = 1;
1642         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1643         memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
1644         nvme_dbbuf_init(dev, nvmeq, qid);
1645         dev->online_queues++;
1646         wmb(); /* ensure the first interrupt sees the initialization */
1647 }
1648
1649 /*
1650  * Try getting shutdown_lock while setting up IO queues.
1651  */
1652 static int nvme_setup_io_queues_trylock(struct nvme_dev *dev)
1653 {
1654         /*
1655          * Give up if the lock is being held by nvme_dev_disable.
1656          */
1657         if (!mutex_trylock(&dev->shutdown_lock))
1658                 return -ENODEV;
1659
1660         /*
1661          * Controller is in wrong state, fail early.
1662          */
1663         if (dev->ctrl.state != NVME_CTRL_CONNECTING) {
1664                 mutex_unlock(&dev->shutdown_lock);
1665                 return -ENODEV;
1666         }
1667
1668         return 0;
1669 }
1670
1671 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
1672 {
1673         struct nvme_dev *dev = nvmeq->dev;
1674         int result;
1675         u16 vector = 0;
1676
1677         clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1678
1679         /*
1680          * A queue's vector matches the queue identifier unless the controller
1681          * has only one vector available.
1682          */
1683         if (!polled)
1684                 vector = dev->num_vecs == 1 ? 0 : qid;
1685         else
1686                 set_bit(NVMEQ_POLLED, &nvmeq->flags);
1687
1688         result = adapter_alloc_cq(dev, qid, nvmeq, vector);
1689         if (result)
1690                 return result;
1691
1692         result = adapter_alloc_sq(dev, qid, nvmeq);
1693         if (result < 0)
1694                 return result;
1695         if (result)
1696                 goto release_cq;
1697
1698         nvmeq->cq_vector = vector;
1699
1700         result = nvme_setup_io_queues_trylock(dev);
1701         if (result)
1702                 return result;
1703         nvme_init_queue(nvmeq, qid);
1704         if (!polled) {
1705                 result = queue_request_irq(nvmeq);
1706                 if (result < 0)
1707                         goto release_sq;
1708         }
1709
1710         set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1711         mutex_unlock(&dev->shutdown_lock);
1712         return result;
1713
1714 release_sq:
1715         dev->online_queues--;
1716         mutex_unlock(&dev->shutdown_lock);
1717         adapter_delete_sq(dev, qid);
1718 release_cq:
1719         adapter_delete_cq(dev, qid);
1720         return result;
1721 }
1722
1723 static const struct blk_mq_ops nvme_mq_admin_ops = {
1724         .queue_rq       = nvme_queue_rq,
1725         .complete       = nvme_pci_complete_rq,
1726         .init_hctx      = nvme_admin_init_hctx,
1727         .init_request   = nvme_pci_init_request,
1728         .timeout        = nvme_timeout,
1729 };
1730
1731 static const struct blk_mq_ops nvme_mq_ops = {
1732         .queue_rq       = nvme_queue_rq,
1733         .queue_rqs      = nvme_queue_rqs,
1734         .complete       = nvme_pci_complete_rq,
1735         .commit_rqs     = nvme_commit_rqs,
1736         .init_hctx      = nvme_init_hctx,
1737         .init_request   = nvme_pci_init_request,
1738         .map_queues     = nvme_pci_map_queues,
1739         .timeout        = nvme_timeout,
1740         .poll           = nvme_poll,
1741 };
1742
1743 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1744 {
1745         if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1746                 /*
1747                  * If the controller was reset during removal, it's possible
1748                  * user requests may be waiting on a stopped queue. Start the
1749                  * queue to flush these to completion.
1750                  */
1751                 nvme_start_admin_queue(&dev->ctrl);
1752                 blk_cleanup_queue(dev->ctrl.admin_q);
1753                 blk_mq_free_tag_set(&dev->admin_tagset);
1754         }
1755 }
1756
1757 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1758 {
1759         if (!dev->ctrl.admin_q) {
1760                 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1761                 dev->admin_tagset.nr_hw_queues = 1;
1762
1763                 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
1764                 dev->admin_tagset.timeout = NVME_ADMIN_TIMEOUT;
1765                 dev->admin_tagset.numa_node = dev->ctrl.numa_node;
1766                 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod);
1767                 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1768                 dev->admin_tagset.driver_data = dev;
1769
1770                 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1771                         return -ENOMEM;
1772                 dev->ctrl.admin_tagset = &dev->admin_tagset;
1773
1774                 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1775                 if (IS_ERR(dev->ctrl.admin_q)) {
1776                         blk_mq_free_tag_set(&dev->admin_tagset);
1777                         return -ENOMEM;
1778                 }
1779                 if (!blk_get_queue(dev->ctrl.admin_q)) {
1780                         nvme_dev_remove_admin(dev);
1781                         dev->ctrl.admin_q = NULL;
1782                         return -ENODEV;
1783                 }
1784         } else
1785                 nvme_start_admin_queue(&dev->ctrl);
1786
1787         return 0;
1788 }
1789
1790 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1791 {
1792         return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1793 }
1794
1795 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1796 {
1797         struct pci_dev *pdev = to_pci_dev(dev->dev);
1798
1799         if (size <= dev->bar_mapped_size)
1800                 return 0;
1801         if (size > pci_resource_len(pdev, 0))
1802                 return -ENOMEM;
1803         if (dev->bar)
1804                 iounmap(dev->bar);
1805         dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1806         if (!dev->bar) {
1807                 dev->bar_mapped_size = 0;
1808                 return -ENOMEM;
1809         }
1810         dev->bar_mapped_size = size;
1811         dev->dbs = dev->bar + NVME_REG_DBS;
1812
1813         return 0;
1814 }
1815
1816 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1817 {
1818         int result;
1819         u32 aqa;
1820         struct nvme_queue *nvmeq;
1821
1822         result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1823         if (result < 0)
1824                 return result;
1825
1826         dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1827                                 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1828
1829         if (dev->subsystem &&
1830             (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1831                 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1832
1833         result = nvme_disable_ctrl(&dev->ctrl);
1834         if (result < 0)
1835                 return result;
1836
1837         result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1838         if (result)
1839                 return result;
1840
1841         dev->ctrl.numa_node = dev_to_node(dev->dev);
1842
1843         nvmeq = &dev->queues[0];
1844         aqa = nvmeq->q_depth - 1;
1845         aqa |= aqa << 16;
1846
1847         writel(aqa, dev->bar + NVME_REG_AQA);
1848         lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1849         lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1850
1851         result = nvme_enable_ctrl(&dev->ctrl);
1852         if (result)
1853                 return result;
1854
1855         nvmeq->cq_vector = 0;
1856         nvme_init_queue(nvmeq, 0);
1857         result = queue_request_irq(nvmeq);
1858         if (result) {
1859                 dev->online_queues--;
1860                 return result;
1861         }
1862
1863         set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1864         return result;
1865 }
1866
1867 static int nvme_create_io_queues(struct nvme_dev *dev)
1868 {
1869         unsigned i, max, rw_queues;
1870         int ret = 0;
1871
1872         for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1873                 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
1874                         ret = -ENOMEM;
1875                         break;
1876                 }
1877         }
1878
1879         max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1880         if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1881                 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1882                                 dev->io_queues[HCTX_TYPE_READ];
1883         } else {
1884                 rw_queues = max;
1885         }
1886
1887         for (i = dev->online_queues; i <= max; i++) {
1888                 bool polled = i > rw_queues;
1889
1890                 ret = nvme_create_queue(&dev->queues[i], i, polled);
1891                 if (ret)
1892                         break;
1893         }
1894
1895         /*
1896          * Ignore failing Create SQ/CQ commands, we can continue with less
1897          * than the desired amount of queues, and even a controller without
1898          * I/O queues can still be used to issue admin commands.  This might
1899          * be useful to upgrade a buggy firmware for example.
1900          */
1901         return ret >= 0 ? 0 : ret;
1902 }
1903
1904 static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
1905 {
1906         u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1907
1908         return 1ULL << (12 + 4 * szu);
1909 }
1910
1911 static u32 nvme_cmb_size(struct nvme_dev *dev)
1912 {
1913         return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1914 }
1915
1916 static void nvme_map_cmb(struct nvme_dev *dev)
1917 {
1918         u64 size, offset;
1919         resource_size_t bar_size;
1920         struct pci_dev *pdev = to_pci_dev(dev->dev);
1921         int bar;
1922
1923         if (dev->cmb_size)
1924                 return;
1925
1926         if (NVME_CAP_CMBS(dev->ctrl.cap))
1927                 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC);
1928
1929         dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1930         if (!dev->cmbsz)
1931                 return;
1932         dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1933
1934         size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1935         offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
1936         bar = NVME_CMB_BIR(dev->cmbloc);
1937         bar_size = pci_resource_len(pdev, bar);
1938
1939         if (offset > bar_size)
1940                 return;
1941
1942         /*
1943          * Tell the controller about the host side address mapping the CMB,
1944          * and enable CMB decoding for the NVMe 1.4+ scheme:
1945          */
1946         if (NVME_CAP_CMBS(dev->ctrl.cap)) {
1947                 hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE |
1948                              (pci_bus_address(pdev, bar) + offset),
1949                              dev->bar + NVME_REG_CMBMSC);
1950         }
1951
1952         /*
1953          * Controllers may support a CMB size larger than their BAR,
1954          * for example, due to being behind a bridge. Reduce the CMB to
1955          * the reported size of the BAR
1956          */
1957         if (size > bar_size - offset)
1958                 size = bar_size - offset;
1959
1960         if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1961                 dev_warn(dev->ctrl.device,
1962                          "failed to register the CMB\n");
1963                 return;
1964         }
1965
1966         dev->cmb_size = size;
1967         dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1968
1969         if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1970                         (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1971                 pci_p2pmem_publish(pdev, true);
1972 }
1973
1974 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1975 {
1976         u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
1977         u64 dma_addr = dev->host_mem_descs_dma;
1978         struct nvme_command c = { };
1979         int ret;
1980
1981         c.features.opcode       = nvme_admin_set_features;
1982         c.features.fid          = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1983         c.features.dword11      = cpu_to_le32(bits);
1984         c.features.dword12      = cpu_to_le32(host_mem_size);
1985         c.features.dword13      = cpu_to_le32(lower_32_bits(dma_addr));
1986         c.features.dword14      = cpu_to_le32(upper_32_bits(dma_addr));
1987         c.features.dword15      = cpu_to_le32(dev->nr_host_mem_descs);
1988
1989         ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1990         if (ret) {
1991                 dev_warn(dev->ctrl.device,
1992                          "failed to set host mem (err %d, flags %#x).\n",
1993                          ret, bits);
1994         } else
1995                 dev->hmb = bits & NVME_HOST_MEM_ENABLE;
1996
1997         return ret;
1998 }
1999
2000 static void nvme_free_host_mem(struct nvme_dev *dev)
2001 {
2002         int i;
2003
2004         for (i = 0; i < dev->nr_host_mem_descs; i++) {
2005                 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
2006                 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
2007
2008                 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
2009                                le64_to_cpu(desc->addr),
2010                                DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
2011         }
2012
2013         kfree(dev->host_mem_desc_bufs);
2014         dev->host_mem_desc_bufs = NULL;
2015         dma_free_coherent(dev->dev,
2016                         dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
2017                         dev->host_mem_descs, dev->host_mem_descs_dma);
2018         dev->host_mem_descs = NULL;
2019         dev->nr_host_mem_descs = 0;
2020 }
2021
2022 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
2023                 u32 chunk_size)
2024 {
2025         struct nvme_host_mem_buf_desc *descs;
2026         u32 max_entries, len;
2027         dma_addr_t descs_dma;
2028         int i = 0;
2029         void **bufs;
2030         u64 size, tmp;
2031
2032         tmp = (preferred + chunk_size - 1);
2033         do_div(tmp, chunk_size);
2034         max_entries = tmp;
2035
2036         if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
2037                 max_entries = dev->ctrl.hmmaxd;
2038
2039         descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
2040                                    &descs_dma, GFP_KERNEL);
2041         if (!descs)
2042                 goto out;
2043
2044         bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
2045         if (!bufs)
2046                 goto out_free_descs;
2047
2048         for (size = 0; size < preferred && i < max_entries; size += len) {
2049                 dma_addr_t dma_addr;
2050
2051                 len = min_t(u64, chunk_size, preferred - size);
2052                 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
2053                                 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
2054                 if (!bufs[i])
2055                         break;
2056
2057                 descs[i].addr = cpu_to_le64(dma_addr);
2058                 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
2059                 i++;
2060         }
2061
2062         if (!size)
2063                 goto out_free_bufs;
2064
2065         dev->nr_host_mem_descs = i;
2066         dev->host_mem_size = size;
2067         dev->host_mem_descs = descs;
2068         dev->host_mem_descs_dma = descs_dma;
2069         dev->host_mem_desc_bufs = bufs;
2070         return 0;
2071
2072 out_free_bufs:
2073         while (--i >= 0) {
2074                 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE;
2075
2076                 dma_free_attrs(dev->dev, size, bufs[i],
2077                                le64_to_cpu(descs[i].addr),
2078                                DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
2079         }
2080
2081         kfree(bufs);
2082 out_free_descs:
2083         dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
2084                         descs_dma);
2085 out:
2086         dev->host_mem_descs = NULL;
2087         return -ENOMEM;
2088 }
2089
2090 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
2091 {
2092         u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
2093         u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
2094         u64 chunk_size;
2095
2096         /* start big and work our way down */
2097         for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
2098                 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
2099                         if (!min || dev->host_mem_size >= min)
2100                                 return 0;
2101                         nvme_free_host_mem(dev);
2102                 }
2103         }
2104
2105         return -ENOMEM;
2106 }
2107
2108 static int nvme_setup_host_mem(struct nvme_dev *dev)
2109 {
2110         u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2111         u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2112         u64 min = (u64)dev->ctrl.hmmin * 4096;
2113         u32 enable_bits = NVME_HOST_MEM_ENABLE;
2114         int ret;
2115
2116         preferred = min(preferred, max);
2117         if (min > max) {
2118                 dev_warn(dev->ctrl.device,
2119                         "min host memory (%lld MiB) above limit (%d MiB).\n",
2120                         min >> ilog2(SZ_1M), max_host_mem_size_mb);
2121                 nvme_free_host_mem(dev);
2122                 return 0;
2123         }
2124
2125         /*
2126          * If we already have a buffer allocated check if we can reuse it.
2127          */
2128         if (dev->host_mem_descs) {
2129                 if (dev->host_mem_size >= min)
2130                         enable_bits |= NVME_HOST_MEM_RETURN;
2131                 else
2132                         nvme_free_host_mem(dev);
2133         }
2134
2135         if (!dev->host_mem_descs) {
2136                 if (nvme_alloc_host_mem(dev, min, preferred)) {
2137                         dev_warn(dev->ctrl.device,
2138                                 "failed to allocate host memory buffer.\n");
2139                         return 0; /* controller must work without HMB */
2140                 }
2141
2142                 dev_info(dev->ctrl.device,
2143                         "allocated %lld MiB host memory buffer.\n",
2144                         dev->host_mem_size >> ilog2(SZ_1M));
2145         }
2146
2147         ret = nvme_set_host_mem(dev, enable_bits);
2148         if (ret)
2149                 nvme_free_host_mem(dev);
2150         return ret;
2151 }
2152
2153 static ssize_t cmb_show(struct device *dev, struct device_attribute *attr,
2154                 char *buf)
2155 {
2156         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2157
2158         return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz  : x%08x\n",
2159                        ndev->cmbloc, ndev->cmbsz);
2160 }
2161 static DEVICE_ATTR_RO(cmb);
2162
2163 static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr,
2164                 char *buf)
2165 {
2166         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2167
2168         return sysfs_emit(buf, "%u\n", ndev->cmbloc);
2169 }
2170 static DEVICE_ATTR_RO(cmbloc);
2171
2172 static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr,
2173                 char *buf)
2174 {
2175         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2176
2177         return sysfs_emit(buf, "%u\n", ndev->cmbsz);
2178 }
2179 static DEVICE_ATTR_RO(cmbsz);
2180
2181 static ssize_t hmb_show(struct device *dev, struct device_attribute *attr,
2182                         char *buf)
2183 {
2184         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2185
2186         return sysfs_emit(buf, "%d\n", ndev->hmb);
2187 }
2188
2189 static ssize_t hmb_store(struct device *dev, struct device_attribute *attr,
2190                          const char *buf, size_t count)
2191 {
2192         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2193         bool new;
2194         int ret;
2195
2196         if (strtobool(buf, &new) < 0)
2197                 return -EINVAL;
2198
2199         if (new == ndev->hmb)
2200                 return count;
2201
2202         if (new) {
2203                 ret = nvme_setup_host_mem(ndev);
2204         } else {
2205                 ret = nvme_set_host_mem(ndev, 0);
2206                 if (!ret)
2207                         nvme_free_host_mem(ndev);
2208         }
2209
2210         if (ret < 0)
2211                 return ret;
2212
2213         return count;
2214 }
2215 static DEVICE_ATTR_RW(hmb);
2216
2217 static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj,
2218                 struct attribute *a, int n)
2219 {
2220         struct nvme_ctrl *ctrl =
2221                 dev_get_drvdata(container_of(kobj, struct device, kobj));
2222         struct nvme_dev *dev = to_nvme_dev(ctrl);
2223
2224         if (a == &dev_attr_cmb.attr ||
2225             a == &dev_attr_cmbloc.attr ||
2226             a == &dev_attr_cmbsz.attr) {
2227                 if (!dev->cmbsz)
2228                         return 0;
2229         }
2230         if (a == &dev_attr_hmb.attr && !ctrl->hmpre)
2231                 return 0;
2232
2233         return a->mode;
2234 }
2235
2236 static struct attribute *nvme_pci_attrs[] = {
2237         &dev_attr_cmb.attr,
2238         &dev_attr_cmbloc.attr,
2239         &dev_attr_cmbsz.attr,
2240         &dev_attr_hmb.attr,
2241         NULL,
2242 };
2243
2244 static const struct attribute_group nvme_pci_attr_group = {
2245         .attrs          = nvme_pci_attrs,
2246         .is_visible     = nvme_pci_attrs_are_visible,
2247 };
2248
2249 /*
2250  * nirqs is the number of interrupts available for write and read
2251  * queues. The core already reserved an interrupt for the admin queue.
2252  */
2253 static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
2254 {
2255         struct nvme_dev *dev = affd->priv;
2256         unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
2257
2258         /*
2259          * If there is no interrupt available for queues, ensure that
2260          * the default queue is set to 1. The affinity set size is
2261          * also set to one, but the irq core ignores it for this case.
2262          *
2263          * If only one interrupt is available or 'write_queue' == 0, combine
2264          * write and read queues.
2265          *
2266          * If 'write_queues' > 0, ensure it leaves room for at least one read
2267          * queue.
2268          */
2269         if (!nrirqs) {
2270                 nrirqs = 1;
2271                 nr_read_queues = 0;
2272         } else if (nrirqs == 1 || !nr_write_queues) {
2273                 nr_read_queues = 0;
2274         } else if (nr_write_queues >= nrirqs) {
2275                 nr_read_queues = 1;
2276         } else {
2277                 nr_read_queues = nrirqs - nr_write_queues;
2278         }
2279
2280         dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2281         affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2282         dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2283         affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2284         affd->nr_sets = nr_read_queues ? 2 : 1;
2285 }
2286
2287 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
2288 {
2289         struct pci_dev *pdev = to_pci_dev(dev->dev);
2290         struct irq_affinity affd = {
2291                 .pre_vectors    = 1,
2292                 .calc_sets      = nvme_calc_irq_sets,
2293                 .priv           = dev,
2294         };
2295         unsigned int irq_queues, poll_queues;
2296
2297         /*
2298          * Poll queues don't need interrupts, but we need at least one I/O queue
2299          * left over for non-polled I/O.
2300          */
2301         poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2302         dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
2303
2304         /*
2305          * Initialize for the single interrupt case, will be updated in
2306          * nvme_calc_irq_sets().
2307          */
2308         dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2309         dev->io_queues[HCTX_TYPE_READ] = 0;
2310
2311         /*
2312          * We need interrupts for the admin queue and each non-polled I/O queue,
2313          * but some Apple controllers require all queues to use the first
2314          * vector.
2315          */
2316         irq_queues = 1;
2317         if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2318                 irq_queues += (nr_io_queues - poll_queues);
2319         return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2320                               PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
2321 }
2322
2323 static void nvme_disable_io_queues(struct nvme_dev *dev)
2324 {
2325         if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2326                 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2327 }
2328
2329 static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2330 {
2331         /*
2332          * If tags are shared with admin queue (Apple bug), then
2333          * make sure we only use one IO queue.
2334          */
2335         if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2336                 return 1;
2337         return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2338 }
2339
2340 static int nvme_setup_io_queues(struct nvme_dev *dev)
2341 {
2342         struct nvme_queue *adminq = &dev->queues[0];
2343         struct pci_dev *pdev = to_pci_dev(dev->dev);
2344         unsigned int nr_io_queues;
2345         unsigned long size;
2346         int result;
2347
2348         /*
2349          * Sample the module parameters once at reset time so that we have
2350          * stable values to work with.
2351          */
2352         dev->nr_write_queues = write_queues;
2353         dev->nr_poll_queues = poll_queues;
2354
2355         nr_io_queues = dev->nr_allocated_queues - 1;
2356         result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2357         if (result < 0)
2358                 return result;
2359
2360         if (nr_io_queues == 0)
2361                 return 0;
2362
2363         /*
2364          * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions
2365          * from set to unset. If there is a window to it is truely freed,
2366          * pci_free_irq_vectors() jumping into this window will crash.
2367          * And take lock to avoid racing with pci_free_irq_vectors() in
2368          * nvme_dev_disable() path.
2369          */
2370         result = nvme_setup_io_queues_trylock(dev);
2371         if (result)
2372                 return result;
2373         if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2374                 pci_free_irq(pdev, 0, adminq);
2375
2376         if (dev->cmb_use_sqes) {
2377                 result = nvme_cmb_qdepth(dev, nr_io_queues,
2378                                 sizeof(struct nvme_command));
2379                 if (result > 0)
2380                         dev->q_depth = result;
2381                 else
2382                         dev->cmb_use_sqes = false;
2383         }
2384
2385         do {
2386                 size = db_bar_size(dev, nr_io_queues);
2387                 result = nvme_remap_bar(dev, size);
2388                 if (!result)
2389                         break;
2390                 if (!--nr_io_queues) {
2391                         result = -ENOMEM;
2392                         goto out_unlock;
2393                 }
2394         } while (1);
2395         adminq->q_db = dev->dbs;
2396
2397  retry:
2398         /* Deregister the admin queue's interrupt */
2399         if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2400                 pci_free_irq(pdev, 0, adminq);
2401
2402         /*
2403          * If we enable msix early due to not intx, disable it again before
2404          * setting up the full range we need.
2405          */
2406         pci_free_irq_vectors(pdev);
2407
2408         result = nvme_setup_irqs(dev, nr_io_queues);
2409         if (result <= 0) {
2410                 result = -EIO;
2411                 goto out_unlock;
2412         }
2413
2414         dev->num_vecs = result;
2415         result = max(result - 1, 1);
2416         dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
2417
2418         /*
2419          * Should investigate if there's a performance win from allocating
2420          * more queues than interrupt vectors; it might allow the submission
2421          * path to scale better, even if the receive path is limited by the
2422          * number of interrupts.
2423          */
2424         result = queue_request_irq(adminq);
2425         if (result)
2426                 goto out_unlock;
2427         set_bit(NVMEQ_ENABLED, &adminq->flags);
2428         mutex_unlock(&dev->shutdown_lock);
2429
2430         result = nvme_create_io_queues(dev);
2431         if (result || dev->online_queues < 2)
2432                 return result;
2433
2434         if (dev->online_queues - 1 < dev->max_qid) {
2435                 nr_io_queues = dev->online_queues - 1;
2436                 nvme_disable_io_queues(dev);
2437                 result = nvme_setup_io_queues_trylock(dev);
2438                 if (result)
2439                         return result;
2440                 nvme_suspend_io_queues(dev);
2441                 goto retry;
2442         }
2443         dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2444                                         dev->io_queues[HCTX_TYPE_DEFAULT],
2445                                         dev->io_queues[HCTX_TYPE_READ],
2446                                         dev->io_queues[HCTX_TYPE_POLL]);
2447         return 0;
2448 out_unlock:
2449         mutex_unlock(&dev->shutdown_lock);
2450         return result;
2451 }
2452
2453 static void nvme_del_queue_end(struct request *req, blk_status_t error)
2454 {
2455         struct nvme_queue *nvmeq = req->end_io_data;
2456
2457         blk_mq_free_request(req);
2458         complete(&nvmeq->delete_done);
2459 }
2460
2461 static void nvme_del_cq_end(struct request *req, blk_status_t error)
2462 {
2463         struct nvme_queue *nvmeq = req->end_io_data;
2464
2465         if (error)
2466                 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
2467
2468         nvme_del_queue_end(req, error);
2469 }
2470
2471 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
2472 {
2473         struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2474         struct request *req;
2475         struct nvme_command cmd = { };
2476
2477         cmd.delete_queue.opcode = opcode;
2478         cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2479
2480         req = blk_mq_alloc_request(q, nvme_req_op(&cmd), BLK_MQ_REQ_NOWAIT);
2481         if (IS_ERR(req))
2482                 return PTR_ERR(req);
2483         nvme_init_request(req, &cmd);
2484
2485         req->end_io_data = nvmeq;
2486
2487         init_completion(&nvmeq->delete_done);
2488         blk_execute_rq_nowait(req, false, opcode == nvme_admin_delete_cq ?
2489                         nvme_del_cq_end : nvme_del_queue_end);
2490         return 0;
2491 }
2492
2493 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
2494 {
2495         int nr_queues = dev->online_queues - 1, sent = 0;
2496         unsigned long timeout;
2497
2498  retry:
2499         timeout = NVME_ADMIN_TIMEOUT;
2500         while (nr_queues > 0) {
2501                 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2502                         break;
2503                 nr_queues--;
2504                 sent++;
2505         }
2506         while (sent) {
2507                 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2508
2509                 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
2510                                 timeout);
2511                 if (timeout == 0)
2512                         return false;
2513
2514                 sent--;
2515                 if (nr_queues)
2516                         goto retry;
2517         }
2518         return true;
2519 }
2520
2521 static void nvme_dev_add(struct nvme_dev *dev)
2522 {
2523         int ret;
2524
2525         if (!dev->ctrl.tagset) {
2526                 dev->tagset.ops = &nvme_mq_ops;
2527                 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2528                 dev->tagset.nr_maps = 2; /* default + read */
2529                 if (dev->io_queues[HCTX_TYPE_POLL])
2530                         dev->tagset.nr_maps++;
2531                 dev->tagset.timeout = NVME_IO_TIMEOUT;
2532                 dev->tagset.numa_node = dev->ctrl.numa_node;
2533                 dev->tagset.queue_depth = min_t(unsigned int, dev->q_depth,
2534                                                 BLK_MQ_MAX_DEPTH) - 1;
2535                 dev->tagset.cmd_size = sizeof(struct nvme_iod);
2536                 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2537                 dev->tagset.driver_data = dev;
2538
2539                 /*
2540                  * Some Apple controllers requires tags to be unique
2541                  * across admin and IO queue, so reserve the first 32
2542                  * tags of the IO queue.
2543                  */
2544                 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2545                         dev->tagset.reserved_tags = NVME_AQ_DEPTH;
2546
2547                 ret = blk_mq_alloc_tag_set(&dev->tagset);
2548                 if (ret) {
2549                         dev_warn(dev->ctrl.device,
2550                                 "IO queues tagset allocation failed %d\n", ret);
2551                         return;
2552                 }
2553                 dev->ctrl.tagset = &dev->tagset;
2554         } else {
2555                 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2556
2557                 /* Free previously allocated queues that are no longer usable */
2558                 nvme_free_queues(dev, dev->online_queues);
2559         }
2560
2561         nvme_dbbuf_set(dev);
2562 }
2563
2564 static int nvme_pci_enable(struct nvme_dev *dev)
2565 {
2566         int result = -ENOMEM;
2567         struct pci_dev *pdev = to_pci_dev(dev->dev);
2568         int dma_address_bits = 64;
2569
2570         if (pci_enable_device_mem(pdev))
2571                 return result;
2572
2573         pci_set_master(pdev);
2574
2575         if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48)
2576                 dma_address_bits = 48;
2577         if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits)))
2578                 goto disable;
2579
2580         if (readl(dev->bar + NVME_REG_CSTS) == -1) {
2581                 result = -ENODEV;
2582                 goto disable;
2583         }
2584
2585         /*
2586          * Some devices and/or platforms don't advertise or work with INTx
2587          * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2588          * adjust this later.
2589          */
2590         result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2591         if (result < 0)
2592                 return result;
2593
2594         dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
2595
2596         dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2597                                 io_queue_depth);
2598         dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
2599         dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
2600         dev->dbs = dev->bar + 4096;
2601
2602         /*
2603          * Some Apple controllers require a non-standard SQE size.
2604          * Interestingly they also seem to ignore the CC:IOSQES register
2605          * so we don't bother updating it here.
2606          */
2607         if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2608                 dev->io_sqes = 7;
2609         else
2610                 dev->io_sqes = NVME_NVM_IOSQES;
2611
2612         /*
2613          * Temporary fix for the Apple controller found in the MacBook8,1 and
2614          * some MacBook7,1 to avoid controller resets and data loss.
2615          */
2616         if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2617                 dev->q_depth = 2;
2618                 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2619                         "set queue depth=%u to work around controller resets\n",
2620                         dev->q_depth);
2621         } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2622                    (pdev->device == 0xa821 || pdev->device == 0xa822) &&
2623                    NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2624                 dev->q_depth = 64;
2625                 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2626                         "set queue depth=%u\n", dev->q_depth);
2627         }
2628
2629         /*
2630          * Controllers with the shared tags quirk need the IO queue to be
2631          * big enough so that we get 32 tags for the admin queue
2632          */
2633         if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2634             (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2635                 dev->q_depth = NVME_AQ_DEPTH + 2;
2636                 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2637                          dev->q_depth);
2638         }
2639
2640
2641         nvme_map_cmb(dev);
2642
2643         pci_enable_pcie_error_reporting(pdev);
2644         pci_save_state(pdev);
2645         return 0;
2646
2647  disable:
2648         pci_disable_device(pdev);
2649         return result;
2650 }
2651
2652 static void nvme_dev_unmap(struct nvme_dev *dev)
2653 {
2654         if (dev->bar)
2655                 iounmap(dev->bar);
2656         pci_release_mem_regions(to_pci_dev(dev->dev));
2657 }
2658
2659 static void nvme_pci_disable(struct nvme_dev *dev)
2660 {
2661         struct pci_dev *pdev = to_pci_dev(dev->dev);
2662
2663         pci_free_irq_vectors(pdev);
2664
2665         if (pci_is_enabled(pdev)) {
2666                 pci_disable_pcie_error_reporting(pdev);
2667                 pci_disable_device(pdev);
2668         }
2669 }
2670
2671 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2672 {
2673         bool dead = true, freeze = false;
2674         struct pci_dev *pdev = to_pci_dev(dev->dev);
2675
2676         mutex_lock(&dev->shutdown_lock);
2677         if (pci_is_enabled(pdev)) {
2678                 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2679
2680                 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2681                     dev->ctrl.state == NVME_CTRL_RESETTING) {
2682                         freeze = true;
2683                         nvme_start_freeze(&dev->ctrl);
2684                 }
2685                 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2686                         pdev->error_state  != pci_channel_io_normal);
2687         }
2688
2689         /*
2690          * Give the controller a chance to complete all entered requests if
2691          * doing a safe shutdown.
2692          */
2693         if (!dead && shutdown && freeze)
2694                 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2695
2696         nvme_stop_queues(&dev->ctrl);
2697
2698         if (!dead && dev->ctrl.queue_count > 0) {
2699                 nvme_disable_io_queues(dev);
2700                 nvme_disable_admin_queue(dev, shutdown);
2701         }
2702         nvme_suspend_io_queues(dev);
2703         nvme_suspend_queue(&dev->queues[0]);
2704         nvme_pci_disable(dev);
2705         nvme_reap_pending_cqes(dev);
2706
2707         blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2708         blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
2709         blk_mq_tagset_wait_completed_request(&dev->tagset);
2710         blk_mq_tagset_wait_completed_request(&dev->admin_tagset);
2711
2712         /*
2713          * The driver will not be starting up queues again if shutting down so
2714          * must flush all entered requests to their failed completion to avoid
2715          * deadlocking blk-mq hot-cpu notifier.
2716          */
2717         if (shutdown) {
2718                 nvme_start_queues(&dev->ctrl);
2719                 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2720                         nvme_start_admin_queue(&dev->ctrl);
2721         }
2722         mutex_unlock(&dev->shutdown_lock);
2723 }
2724
2725 static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2726 {
2727         if (!nvme_wait_reset(&dev->ctrl))
2728                 return -EBUSY;
2729         nvme_dev_disable(dev, shutdown);
2730         return 0;
2731 }
2732
2733 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2734 {
2735         dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2736                                                 NVME_CTRL_PAGE_SIZE,
2737                                                 NVME_CTRL_PAGE_SIZE, 0);
2738         if (!dev->prp_page_pool)
2739                 return -ENOMEM;
2740
2741         /* Optimisation for I/Os between 4k and 128k */
2742         dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2743                                                 256, 256, 0);
2744         if (!dev->prp_small_pool) {
2745                 dma_pool_destroy(dev->prp_page_pool);
2746                 return -ENOMEM;
2747         }
2748         return 0;
2749 }
2750
2751 static void nvme_release_prp_pools(struct nvme_dev *dev)
2752 {
2753         dma_pool_destroy(dev->prp_page_pool);
2754         dma_pool_destroy(dev->prp_small_pool);
2755 }
2756
2757 static void nvme_free_tagset(struct nvme_dev *dev)
2758 {
2759         if (dev->tagset.tags)
2760                 blk_mq_free_tag_set(&dev->tagset);
2761         dev->ctrl.tagset = NULL;
2762 }
2763
2764 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2765 {
2766         struct nvme_dev *dev = to_nvme_dev(ctrl);
2767
2768         nvme_dbbuf_dma_free(dev);
2769         nvme_free_tagset(dev);
2770         if (dev->ctrl.admin_q)
2771                 blk_put_queue(dev->ctrl.admin_q);
2772         free_opal_dev(dev->ctrl.opal_dev);
2773         mempool_destroy(dev->iod_mempool);
2774         put_device(dev->dev);
2775         kfree(dev->queues);
2776         kfree(dev);
2777 }
2778
2779 static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
2780 {
2781         /*
2782          * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2783          * may be holding this pci_dev's device lock.
2784          */
2785         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2786         nvme_get_ctrl(&dev->ctrl);
2787         nvme_dev_disable(dev, false);
2788         nvme_kill_queues(&dev->ctrl);
2789         if (!queue_work(nvme_wq, &dev->remove_work))
2790                 nvme_put_ctrl(&dev->ctrl);
2791 }
2792
2793 static void nvme_reset_work(struct work_struct *work)
2794 {
2795         struct nvme_dev *dev =
2796                 container_of(work, struct nvme_dev, ctrl.reset_work);
2797         bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2798         int result;
2799
2800         if (dev->ctrl.state != NVME_CTRL_RESETTING) {
2801                 dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n",
2802                          dev->ctrl.state);
2803                 result = -ENODEV;
2804                 goto out;
2805         }
2806
2807         /*
2808          * If we're called to reset a live controller first shut it down before
2809          * moving on.
2810          */
2811         if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2812                 nvme_dev_disable(dev, false);
2813         nvme_sync_queues(&dev->ctrl);
2814
2815         mutex_lock(&dev->shutdown_lock);
2816         result = nvme_pci_enable(dev);
2817         if (result)
2818                 goto out_unlock;
2819
2820         result = nvme_pci_configure_admin_queue(dev);
2821         if (result)
2822                 goto out_unlock;
2823
2824         result = nvme_alloc_admin_tags(dev);
2825         if (result)
2826                 goto out_unlock;
2827
2828         /*
2829          * Limit the max command size to prevent iod->sg allocations going
2830          * over a single page.
2831          */
2832         dev->ctrl.max_hw_sectors = min_t(u32,
2833                 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9);
2834         dev->ctrl.max_segments = NVME_MAX_SEGS;
2835
2836         /*
2837          * Don't limit the IOMMU merged segment size.
2838          */
2839         dma_set_max_seg_size(dev->dev, 0xffffffff);
2840         dma_set_min_align_mask(dev->dev, NVME_CTRL_PAGE_SIZE - 1);
2841
2842         mutex_unlock(&dev->shutdown_lock);
2843
2844         /*
2845          * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2846          * initializing procedure here.
2847          */
2848         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2849                 dev_warn(dev->ctrl.device,
2850                         "failed to mark controller CONNECTING\n");
2851                 result = -EBUSY;
2852                 goto out;
2853         }
2854
2855         /*
2856          * We do not support an SGL for metadata (yet), so we are limited to a
2857          * single integrity segment for the separate metadata pointer.
2858          */
2859         dev->ctrl.max_integrity_segments = 1;
2860
2861         result = nvme_init_ctrl_finish(&dev->ctrl);
2862         if (result)
2863                 goto out;
2864
2865         if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2866                 if (!dev->ctrl.opal_dev)
2867                         dev->ctrl.opal_dev =
2868                                 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2869                 else if (was_suspend)
2870                         opal_unlock_from_suspend(dev->ctrl.opal_dev);
2871         } else {
2872                 free_opal_dev(dev->ctrl.opal_dev);
2873                 dev->ctrl.opal_dev = NULL;
2874         }
2875
2876         if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2877                 result = nvme_dbbuf_dma_alloc(dev);
2878                 if (result)
2879                         dev_warn(dev->dev,
2880                                  "unable to allocate dma for dbbuf\n");
2881         }
2882
2883         if (dev->ctrl.hmpre) {
2884                 result = nvme_setup_host_mem(dev);
2885                 if (result < 0)
2886                         goto out;
2887         }
2888
2889         result = nvme_setup_io_queues(dev);
2890         if (result)
2891                 goto out;
2892
2893         /*
2894          * Keep the controller around but remove all namespaces if we don't have
2895          * any working I/O queue.
2896          */
2897         if (dev->online_queues < 2) {
2898                 dev_warn(dev->ctrl.device, "IO queues not created\n");
2899                 nvme_kill_queues(&dev->ctrl);
2900                 nvme_remove_namespaces(&dev->ctrl);
2901                 nvme_free_tagset(dev);
2902         } else {
2903                 nvme_start_queues(&dev->ctrl);
2904                 nvme_wait_freeze(&dev->ctrl);
2905                 nvme_dev_add(dev);
2906                 nvme_unfreeze(&dev->ctrl);
2907         }
2908
2909         /*
2910          * If only admin queue live, keep it to do further investigation or
2911          * recovery.
2912          */
2913         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2914                 dev_warn(dev->ctrl.device,
2915                         "failed to mark controller live state\n");
2916                 result = -ENODEV;
2917                 goto out;
2918         }
2919
2920         if (!dev->attrs_added && !sysfs_create_group(&dev->ctrl.device->kobj,
2921                         &nvme_pci_attr_group))
2922                 dev->attrs_added = true;
2923
2924         nvme_start_ctrl(&dev->ctrl);
2925         return;
2926
2927  out_unlock:
2928         mutex_unlock(&dev->shutdown_lock);
2929  out:
2930         if (result)
2931                 dev_warn(dev->ctrl.device,
2932                          "Removing after probe failure status: %d\n", result);
2933         nvme_remove_dead_ctrl(dev);
2934 }
2935
2936 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2937 {
2938         struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2939         struct pci_dev *pdev = to_pci_dev(dev->dev);
2940
2941         if (pci_get_drvdata(pdev))
2942                 device_release_driver(&pdev->dev);
2943         nvme_put_ctrl(&dev->ctrl);
2944 }
2945
2946 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2947 {
2948         *val = readl(to_nvme_dev(ctrl)->bar + off);
2949         return 0;
2950 }
2951
2952 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2953 {
2954         writel(val, to_nvme_dev(ctrl)->bar + off);
2955         return 0;
2956 }
2957
2958 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2959 {
2960         *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
2961         return 0;
2962 }
2963
2964 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2965 {
2966         struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2967
2968         return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
2969 }
2970
2971 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2972         .name                   = "pcie",
2973         .module                 = THIS_MODULE,
2974         .flags                  = NVME_F_METADATA_SUPPORTED |
2975                                   NVME_F_PCI_P2PDMA,
2976         .reg_read32             = nvme_pci_reg_read32,
2977         .reg_write32            = nvme_pci_reg_write32,
2978         .reg_read64             = nvme_pci_reg_read64,
2979         .free_ctrl              = nvme_pci_free_ctrl,
2980         .submit_async_event     = nvme_pci_submit_async_event,
2981         .get_address            = nvme_pci_get_address,
2982 };
2983
2984 static int nvme_dev_map(struct nvme_dev *dev)
2985 {
2986         struct pci_dev *pdev = to_pci_dev(dev->dev);
2987
2988         if (pci_request_mem_regions(pdev, "nvme"))
2989                 return -ENODEV;
2990
2991         if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2992                 goto release;
2993
2994         return 0;
2995   release:
2996         pci_release_mem_regions(pdev);
2997         return -ENODEV;
2998 }
2999
3000 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
3001 {
3002         if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
3003                 /*
3004                  * Several Samsung devices seem to drop off the PCIe bus
3005                  * randomly when APST is on and uses the deepest sleep state.
3006                  * This has been observed on a Samsung "SM951 NVMe SAMSUNG
3007                  * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
3008                  * 950 PRO 256GB", but it seems to be restricted to two Dell
3009                  * laptops.
3010                  */
3011                 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
3012                     (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
3013                      dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
3014                         return NVME_QUIRK_NO_DEEPEST_PS;
3015         } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
3016                 /*
3017                  * Samsung SSD 960 EVO drops off the PCIe bus after system
3018                  * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
3019                  * within few minutes after bootup on a Coffee Lake board -
3020                  * ASUS PRIME Z370-A
3021                  */
3022                 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
3023                     (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
3024                      dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
3025                         return NVME_QUIRK_NO_APST;
3026         } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
3027                     pdev->device == 0xa808 || pdev->device == 0xa809)) ||
3028                    (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
3029                 /*
3030                  * Forcing to use host managed nvme power settings for
3031                  * lowest idle power with quick resume latency on
3032                  * Samsung and Toshiba SSDs based on suspend behavior
3033                  * on Coffee Lake board for LENOVO C640
3034                  */
3035                 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
3036                      dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
3037                         return NVME_QUIRK_SIMPLE_SUSPEND;
3038         }
3039
3040         return 0;
3041 }
3042
3043 static void nvme_async_probe(void *data, async_cookie_t cookie)
3044 {
3045         struct nvme_dev *dev = data;
3046
3047         flush_work(&dev->ctrl.reset_work);
3048         flush_work(&dev->ctrl.scan_work);
3049         nvme_put_ctrl(&dev->ctrl);
3050 }
3051
3052 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
3053 {
3054         int node, result = -ENOMEM;
3055         struct nvme_dev *dev;
3056         unsigned long quirks = id->driver_data;
3057         size_t alloc_size;
3058
3059         node = dev_to_node(&pdev->dev);
3060         if (node == NUMA_NO_NODE)
3061                 set_dev_node(&pdev->dev, first_memory_node);
3062
3063         dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
3064         if (!dev)
3065                 return -ENOMEM;
3066
3067         dev->nr_write_queues = write_queues;
3068         dev->nr_poll_queues = poll_queues;
3069         dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
3070         dev->queues = kcalloc_node(dev->nr_allocated_queues,
3071                         sizeof(struct nvme_queue), GFP_KERNEL, node);
3072         if (!dev->queues)
3073                 goto free;
3074
3075         dev->dev = get_device(&pdev->dev);
3076         pci_set_drvdata(pdev, dev);
3077
3078         result = nvme_dev_map(dev);
3079         if (result)
3080                 goto put_pci;
3081
3082         INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
3083         INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
3084         mutex_init(&dev->shutdown_lock);
3085
3086         result = nvme_setup_prp_pools(dev);
3087         if (result)
3088                 goto unmap;
3089
3090         quirks |= check_vendor_combination_bug(pdev);
3091
3092         if (!noacpi && acpi_storage_d3(&pdev->dev)) {
3093                 /*
3094                  * Some systems use a bios work around to ask for D3 on
3095                  * platforms that support kernel managed suspend.
3096                  */
3097                 dev_info(&pdev->dev,
3098                          "platform quirk: setting simple suspend\n");
3099                 quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
3100         }
3101
3102         /*
3103          * Double check that our mempool alloc size will cover the biggest
3104          * command we support.
3105          */
3106         alloc_size = nvme_pci_iod_alloc_size();
3107         WARN_ON_ONCE(alloc_size > PAGE_SIZE);
3108
3109         dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
3110                                                 mempool_kfree,
3111                                                 (void *) alloc_size,
3112                                                 GFP_KERNEL, node);
3113         if (!dev->iod_mempool) {
3114                 result = -ENOMEM;
3115                 goto release_pools;
3116         }
3117
3118         result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
3119                         quirks);
3120         if (result)
3121                 goto release_mempool;
3122
3123         dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
3124
3125         nvme_reset_ctrl(&dev->ctrl);
3126         async_schedule(nvme_async_probe, dev);
3127
3128         return 0;
3129
3130  release_mempool:
3131         mempool_destroy(dev->iod_mempool);
3132  release_pools:
3133         nvme_release_prp_pools(dev);
3134  unmap:
3135         nvme_dev_unmap(dev);
3136  put_pci:
3137         put_device(dev->dev);
3138  free:
3139         kfree(dev->queues);
3140         kfree(dev);
3141         return result;
3142 }
3143
3144 static void nvme_reset_prepare(struct pci_dev *pdev)
3145 {
3146         struct nvme_dev *dev = pci_get_drvdata(pdev);
3147
3148         /*
3149          * We don't need to check the return value from waiting for the reset
3150          * state as pci_dev device lock is held, making it impossible to race
3151          * with ->remove().
3152          */
3153         nvme_disable_prepare_reset(dev, false);
3154         nvme_sync_queues(&dev->ctrl);
3155 }
3156
3157 static void nvme_reset_done(struct pci_dev *pdev)
3158 {
3159         struct nvme_dev *dev = pci_get_drvdata(pdev);
3160
3161         if (!nvme_try_sched_reset(&dev->ctrl))
3162                 flush_work(&dev->ctrl.reset_work);
3163 }
3164
3165 static void nvme_shutdown(struct pci_dev *pdev)
3166 {
3167         struct nvme_dev *dev = pci_get_drvdata(pdev);
3168
3169         nvme_disable_prepare_reset(dev, true);
3170 }
3171
3172 static void nvme_remove_attrs(struct nvme_dev *dev)
3173 {
3174         if (dev->attrs_added)
3175                 sysfs_remove_group(&dev->ctrl.device->kobj,
3176                                    &nvme_pci_attr_group);
3177 }
3178
3179 /*
3180  * The driver's remove may be called on a device in a partially initialized
3181  * state. This function must not have any dependencies on the device state in
3182  * order to proceed.
3183  */
3184 static void nvme_remove(struct pci_dev *pdev)
3185 {
3186         struct nvme_dev *dev = pci_get_drvdata(pdev);
3187
3188         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
3189         pci_set_drvdata(pdev, NULL);
3190
3191         if (!pci_device_is_present(pdev)) {
3192                 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
3193                 nvme_dev_disable(dev, true);
3194         }
3195
3196         flush_work(&dev->ctrl.reset_work);
3197         nvme_stop_ctrl(&dev->ctrl);
3198         nvme_remove_namespaces(&dev->ctrl);
3199         nvme_dev_disable(dev, true);
3200         nvme_remove_attrs(dev);
3201         nvme_free_host_mem(dev);
3202         nvme_dev_remove_admin(dev);
3203         nvme_free_queues(dev, 0);
3204         nvme_release_prp_pools(dev);
3205         nvme_dev_unmap(dev);
3206         nvme_uninit_ctrl(&dev->ctrl);
3207 }
3208
3209 #ifdef CONFIG_PM_SLEEP
3210 static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
3211 {
3212         return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
3213 }
3214
3215 static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
3216 {
3217         return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
3218 }
3219
3220 static int nvme_resume(struct device *dev)
3221 {
3222         struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3223         struct nvme_ctrl *ctrl = &ndev->ctrl;
3224
3225         if (ndev->last_ps == U32_MAX ||
3226             nvme_set_power_state(ctrl, ndev->last_ps) != 0)
3227                 goto reset;
3228         if (ctrl->hmpre && nvme_setup_host_mem(ndev))
3229                 goto reset;
3230
3231         return 0;
3232 reset:
3233         return nvme_try_sched_reset(ctrl);
3234 }
3235
3236 static int nvme_suspend(struct device *dev)
3237 {
3238         struct pci_dev *pdev = to_pci_dev(dev);
3239         struct nvme_dev *ndev = pci_get_drvdata(pdev);
3240         struct nvme_ctrl *ctrl = &ndev->ctrl;
3241         int ret = -EBUSY;
3242
3243         ndev->last_ps = U32_MAX;
3244
3245         /*
3246          * The platform does not remove power for a kernel managed suspend so
3247          * use host managed nvme power settings for lowest idle power if
3248          * possible. This should have quicker resume latency than a full device
3249          * shutdown.  But if the firmware is involved after the suspend or the
3250          * device does not support any non-default power states, shut down the
3251          * device fully.
3252          *
3253          * If ASPM is not enabled for the device, shut down the device and allow
3254          * the PCI bus layer to put it into D3 in order to take the PCIe link
3255          * down, so as to allow the platform to achieve its minimum low-power
3256          * state (which may not be possible if the link is up).
3257          */
3258         if (pm_suspend_via_firmware() || !ctrl->npss ||
3259             !pcie_aspm_enabled(pdev) ||
3260             (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3261                 return nvme_disable_prepare_reset(ndev, true);
3262
3263         nvme_start_freeze(ctrl);
3264         nvme_wait_freeze(ctrl);
3265         nvme_sync_queues(ctrl);
3266
3267         if (ctrl->state != NVME_CTRL_LIVE)
3268                 goto unfreeze;
3269
3270         /*
3271          * Host memory access may not be successful in a system suspend state,
3272          * but the specification allows the controller to access memory in a
3273          * non-operational power state.
3274          */
3275         if (ndev->hmb) {
3276                 ret = nvme_set_host_mem(ndev, 0);
3277                 if (ret < 0)
3278                         goto unfreeze;
3279         }
3280
3281         ret = nvme_get_power_state(ctrl, &ndev->last_ps);
3282         if (ret < 0)
3283                 goto unfreeze;
3284
3285         /*
3286          * A saved state prevents pci pm from generically controlling the
3287          * device's power. If we're using protocol specific settings, we don't
3288          * want pci interfering.
3289          */
3290         pci_save_state(pdev);
3291
3292         ret = nvme_set_power_state(ctrl, ctrl->npss);
3293         if (ret < 0)
3294                 goto unfreeze;
3295
3296         if (ret) {
3297                 /* discard the saved state */
3298                 pci_load_saved_state(pdev, NULL);
3299
3300                 /*
3301                  * Clearing npss forces a controller reset on resume. The
3302                  * correct value will be rediscovered then.
3303                  */
3304                 ret = nvme_disable_prepare_reset(ndev, true);
3305                 ctrl->npss = 0;
3306         }
3307 unfreeze:
3308         nvme_unfreeze(ctrl);
3309         return ret;
3310 }
3311
3312 static int nvme_simple_suspend(struct device *dev)
3313 {
3314         struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3315
3316         return nvme_disable_prepare_reset(ndev, true);
3317 }
3318
3319 static int nvme_simple_resume(struct device *dev)
3320 {
3321         struct pci_dev *pdev = to_pci_dev(dev);
3322         struct nvme_dev *ndev = pci_get_drvdata(pdev);
3323
3324         return nvme_try_sched_reset(&ndev->ctrl);
3325 }
3326
3327 static const struct dev_pm_ops nvme_dev_pm_ops = {
3328         .suspend        = nvme_suspend,
3329         .resume         = nvme_resume,
3330         .freeze         = nvme_simple_suspend,
3331         .thaw           = nvme_simple_resume,
3332         .poweroff       = nvme_simple_suspend,
3333         .restore        = nvme_simple_resume,
3334 };
3335 #endif /* CONFIG_PM_SLEEP */
3336
3337 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3338                                                 pci_channel_state_t state)
3339 {
3340         struct nvme_dev *dev = pci_get_drvdata(pdev);
3341
3342         /*
3343          * A frozen channel requires a reset. When detected, this method will
3344          * shutdown the controller to quiesce. The controller will be restarted
3345          * after the slot reset through driver's slot_reset callback.
3346          */
3347         switch (state) {
3348         case pci_channel_io_normal:
3349                 return PCI_ERS_RESULT_CAN_RECOVER;
3350         case pci_channel_io_frozen:
3351                 dev_warn(dev->ctrl.device,
3352                         "frozen state error detected, reset controller\n");
3353                 nvme_dev_disable(dev, false);
3354                 return PCI_ERS_RESULT_NEED_RESET;
3355         case pci_channel_io_perm_failure:
3356                 dev_warn(dev->ctrl.device,
3357                         "failure state error detected, request disconnect\n");
3358                 return PCI_ERS_RESULT_DISCONNECT;
3359         }
3360         return PCI_ERS_RESULT_NEED_RESET;
3361 }
3362
3363 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3364 {
3365         struct nvme_dev *dev = pci_get_drvdata(pdev);
3366
3367         dev_info(dev->ctrl.device, "restart after slot reset\n");
3368         pci_restore_state(pdev);
3369         nvme_reset_ctrl(&dev->ctrl);
3370         return PCI_ERS_RESULT_RECOVERED;
3371 }
3372
3373 static void nvme_error_resume(struct pci_dev *pdev)
3374 {
3375         struct nvme_dev *dev = pci_get_drvdata(pdev);
3376
3377         flush_work(&dev->ctrl.reset_work);
3378 }
3379
3380 static const struct pci_error_handlers nvme_err_handler = {
3381         .error_detected = nvme_error_detected,
3382         .slot_reset     = nvme_slot_reset,
3383         .resume         = nvme_error_resume,
3384         .reset_prepare  = nvme_reset_prepare,
3385         .reset_done     = nvme_reset_done,
3386 };
3387
3388 static const struct pci_device_id nvme_id_table[] = {
3389         { PCI_VDEVICE(INTEL, 0x0953),   /* Intel 750/P3500/P3600/P3700 */
3390                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3391                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
3392         { PCI_VDEVICE(INTEL, 0x0a53),   /* Intel P3520 */
3393                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3394                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
3395         { PCI_VDEVICE(INTEL, 0x0a54),   /* Intel P4500/P4600 */
3396                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3397                                 NVME_QUIRK_DEALLOCATE_ZEROES |
3398                                 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3399         { PCI_VDEVICE(INTEL, 0x0a55),   /* Dell Express Flash P4600 */
3400                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3401                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
3402         { PCI_VDEVICE(INTEL, 0xf1a5),   /* Intel 600P/P3100 */
3403                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3404                                 NVME_QUIRK_MEDIUM_PRIO_SQ |
3405                                 NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
3406                                 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3407         { PCI_VDEVICE(INTEL, 0xf1a6),   /* Intel 760p/Pro 7600p */
3408                 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3409         { PCI_VDEVICE(INTEL, 0x5845),   /* Qemu emulated controller */
3410                 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
3411                                 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3412         { PCI_DEVICE(0x126f, 0x2263),   /* Silicon Motion unidentified */
3413                 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST, },
3414         { PCI_DEVICE(0x1bb1, 0x0100),   /* Seagate Nytro Flash Storage */
3415                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3416                                 NVME_QUIRK_NO_NS_DESC_LIST, },
3417         { PCI_DEVICE(0x1c58, 0x0003),   /* HGST adapter */
3418                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3419         { PCI_DEVICE(0x1c58, 0x0023),   /* WDC SN200 adapter */
3420                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3421         { PCI_DEVICE(0x1c5f, 0x0540),   /* Memblaze Pblaze4 adapter */
3422                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3423         { PCI_DEVICE(0x144d, 0xa821),   /* Samsung PM1725 */
3424                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3425         { PCI_DEVICE(0x144d, 0xa822),   /* Samsung PM1725a */
3426                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3427                                 NVME_QUIRK_DISABLE_WRITE_ZEROES|
3428                                 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3429         { PCI_DEVICE(0x1987, 0x5016),   /* Phison E16 */
3430                 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3431         { PCI_DEVICE(0x1b4b, 0x1092),   /* Lexar 256 GB SSD */
3432                 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3433                                 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3434         { PCI_DEVICE(0x10ec, 0x5762),   /* ADATA SX6000LNP */
3435                 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3436         { PCI_DEVICE(0x1cc1, 0x8201),   /* ADATA SX8200PNP 512GB */
3437                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3438                                 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3439         { PCI_DEVICE(0x1c5c, 0x1504),   /* SK Hynix PC400 */
3440                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3441         { PCI_DEVICE(0x15b7, 0x2001),   /*  Sandisk Skyhawk */
3442                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3443         { PCI_DEVICE(0x1d97, 0x2263),   /* SPCC */
3444                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3445         { PCI_DEVICE(0x2646, 0x2262),   /* KINGSTON SKC2000 NVMe SSD */
3446                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3447         { PCI_DEVICE(0x2646, 0x2263),   /* KINGSTON A2000 NVMe SSD  */
3448                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3449         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061),
3450                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3451         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065),
3452                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3453         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061),
3454                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3455         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00),
3456                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3457         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01),
3458                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3459         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02),
3460                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3461         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3462                 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
3463         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
3464         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3465                 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
3466                                 NVME_QUIRK_128_BYTES_SQES |
3467                                 NVME_QUIRK_SHARED_TAGS |
3468                                 NVME_QUIRK_SKIP_CID_GEN },
3469
3470         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3471         { 0, }
3472 };
3473 MODULE_DEVICE_TABLE(pci, nvme_id_table);
3474
3475 static struct pci_driver nvme_driver = {
3476         .name           = "nvme",
3477         .id_table       = nvme_id_table,
3478         .probe          = nvme_probe,
3479         .remove         = nvme_remove,
3480         .shutdown       = nvme_shutdown,
3481 #ifdef CONFIG_PM_SLEEP
3482         .driver         = {
3483                 .pm     = &nvme_dev_pm_ops,
3484         },
3485 #endif
3486         .sriov_configure = pci_sriov_configure_simple,
3487         .err_handler    = &nvme_err_handler,
3488 };
3489
3490 static int __init nvme_init(void)
3491 {
3492         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3493         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3494         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
3495         BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
3496
3497         return pci_register_driver(&nvme_driver);
3498 }
3499
3500 static void __exit nvme_exit(void)
3501 {
3502         pci_unregister_driver(&nvme_driver);
3503         flush_workqueue(nvme_wq);
3504 }
3505
3506 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3507 MODULE_LICENSE("GPL");
3508 MODULE_VERSION("1.0");
3509 module_init(nvme_init);
3510 module_exit(nvme_exit);