2 * Synopsys Designware PCIe host controller driver
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * Author: Jingoo Han <jg1.han@samsung.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/irq.h>
15 #include <linux/irqdomain.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/msi.h>
19 #include <linux/of_address.h>
20 #include <linux/of_pci.h>
21 #include <linux/pci.h>
22 #include <linux/pci_regs.h>
23 #include <linux/platform_device.h>
24 #include <linux/types.h>
26 #include "pcie-designware.h"
28 /* Synopsis specific PCIE configuration registers */
29 #define PCIE_PORT_LINK_CONTROL 0x710
30 #define PORT_LINK_MODE_MASK (0x3f << 16)
31 #define PORT_LINK_MODE_1_LANES (0x1 << 16)
32 #define PORT_LINK_MODE_2_LANES (0x3 << 16)
33 #define PORT_LINK_MODE_4_LANES (0x7 << 16)
35 #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
36 #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
37 #define PORT_LOGIC_LINK_WIDTH_MASK (0x1ff << 8)
38 #define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
39 #define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
40 #define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
42 #define PCIE_MSI_ADDR_LO 0x820
43 #define PCIE_MSI_ADDR_HI 0x824
44 #define PCIE_MSI_INTR0_ENABLE 0x828
45 #define PCIE_MSI_INTR0_MASK 0x82C
46 #define PCIE_MSI_INTR0_STATUS 0x830
48 #define PCIE_ATU_VIEWPORT 0x900
49 #define PCIE_ATU_REGION_INBOUND (0x1 << 31)
50 #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
51 #define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
52 #define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
53 #define PCIE_ATU_CR1 0x904
54 #define PCIE_ATU_TYPE_MEM (0x0 << 0)
55 #define PCIE_ATU_TYPE_IO (0x2 << 0)
56 #define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
57 #define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
58 #define PCIE_ATU_CR2 0x908
59 #define PCIE_ATU_ENABLE (0x1 << 31)
60 #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
61 #define PCIE_ATU_LOWER_BASE 0x90C
62 #define PCIE_ATU_UPPER_BASE 0x910
63 #define PCIE_ATU_LIMIT 0x914
64 #define PCIE_ATU_LOWER_TARGET 0x918
65 #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
66 #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
67 #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
68 #define PCIE_ATU_UPPER_TARGET 0x91C
70 static struct hw_pci dw_pci;
72 static unsigned long global_io_offset;
74 static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys)
76 BUG_ON(!sys->private_data);
78 return sys->private_data;
81 int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val)
86 *val = (*val >> (8 * (where & 3))) & 0xff;
88 *val = (*val >> (8 * (where & 3))) & 0xffff;
90 return PCIBIOS_BAD_REGISTER_NUMBER;
92 return PCIBIOS_SUCCESSFUL;
95 int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val)
100 writew(val, addr + (where & 2));
102 writeb(val, addr + (where & 3));
104 return PCIBIOS_BAD_REGISTER_NUMBER;
106 return PCIBIOS_SUCCESSFUL;
109 static inline void dw_pcie_readl_rc(struct pcie_port *pp, u32 reg, u32 *val)
111 if (pp->ops->readl_rc)
112 pp->ops->readl_rc(pp, pp->dbi_base + reg, val);
114 *val = readl(pp->dbi_base + reg);
117 static inline void dw_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg)
119 if (pp->ops->writel_rc)
120 pp->ops->writel_rc(pp, val, pp->dbi_base + reg);
122 writel(val, pp->dbi_base + reg);
125 static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
130 if (pp->ops->rd_own_conf)
131 ret = pp->ops->rd_own_conf(pp, where, size, val);
133 ret = dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where,
139 static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
144 if (pp->ops->wr_own_conf)
145 ret = pp->ops->wr_own_conf(pp, where, size, val);
147 ret = dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3), where,
153 static struct irq_chip dw_msi_irq_chip = {
155 .irq_enable = unmask_msi_irq,
156 .irq_disable = mask_msi_irq,
157 .irq_mask = mask_msi_irq,
158 .irq_unmask = unmask_msi_irq,
161 /* MSI int handler */
162 irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
166 irqreturn_t ret = IRQ_NONE;
168 for (i = 0; i < MAX_MSI_CTRLS; i++) {
169 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4,
174 while ((pos = find_next_bit(&val, 32, pos)) != 32) {
175 irq = irq_find_mapping(pp->irq_domain,
177 dw_pcie_wr_own_conf(pp,
178 PCIE_MSI_INTR0_STATUS + i * 12,
180 generic_handle_irq(irq);
189 void dw_pcie_msi_init(struct pcie_port *pp)
191 pp->msi_data = __get_free_pages(GFP_KERNEL, 0);
193 /* program the msi_data */
194 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
195 virt_to_phys((void *)pp->msi_data));
196 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0);
199 static int find_valid_pos0(struct pcie_port *pp, int msgvec, int pos, int *pos0)
204 pos = find_next_zero_bit(pp->msi_irq_in_use,
206 /*if you have reached to the end then get out from here.*/
207 if (pos == MAX_MSI_IRQS)
210 * Check if this position is at correct offset.nvec is always a
211 * power of two. pos0 must be nvec bit aligned.
214 pos += msgvec - (pos % msgvec);
223 static void dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
225 unsigned int res, bit, val;
227 res = (irq / 32) * 12;
229 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
231 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
234 static void clear_irq_range(struct pcie_port *pp, unsigned int irq_base,
235 unsigned int nvec, unsigned int pos)
239 for (i = 0; i < nvec; i++) {
240 irq_set_msi_desc_off(irq_base, i, NULL);
241 clear_bit(pos + i, pp->msi_irq_in_use);
242 /* Disable corresponding interrupt on MSI controller */
243 if (pp->ops->msi_clear_irq)
244 pp->ops->msi_clear_irq(pp, pos + i);
246 dw_pcie_msi_clear_irq(pp, pos + i);
250 static void dw_pcie_msi_set_irq(struct pcie_port *pp, int irq)
252 unsigned int res, bit, val;
254 res = (irq / 32) * 12;
256 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
258 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
261 static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos)
263 int irq, pos0, pos1, i;
264 struct pcie_port *pp = sys_to_pcie(desc->dev->bus->sysdata);
266 pos0 = find_first_zero_bit(pp->msi_irq_in_use,
268 if (pos0 % no_irqs) {
269 if (find_valid_pos0(pp, no_irqs, pos0, &pos0))
273 pos1 = find_next_bit(pp->msi_irq_in_use,
275 /* there must be nvec number of consecutive free bits */
276 while ((pos1 - pos0) < no_irqs) {
277 if (find_valid_pos0(pp, no_irqs, pos1, &pos0))
279 pos1 = find_next_bit(pp->msi_irq_in_use,
284 irq = irq_find_mapping(pp->irq_domain, pos0);
289 * irq_create_mapping (called from dw_pcie_host_init) pre-allocates
290 * descs so there is no need to allocate descs here. We can therefore
291 * assume that if irq_find_mapping above returns non-zero, then the
292 * descs are also successfully allocated.
295 for (i = 0; i < no_irqs; i++) {
296 if (irq_set_msi_desc_off(irq, i, desc) != 0) {
297 clear_irq_range(pp, irq, i, pos0);
300 set_bit(pos0 + i, pp->msi_irq_in_use);
301 /*Enable corresponding interrupt in MSI interrupt controller */
302 if (pp->ops->msi_set_irq)
303 pp->ops->msi_set_irq(pp, pos0 + i);
305 dw_pcie_msi_set_irq(pp, pos0 + i);
316 static void clear_irq(unsigned int irq)
318 unsigned int pos, nvec;
319 struct msi_desc *msi;
320 struct pcie_port *pp;
321 struct irq_data *data = irq_get_irq_data(irq);
323 /* get the port structure */
324 msi = irq_data_get_msi(data);
325 pp = sys_to_pcie(msi->dev->bus->sysdata);
327 /* undo what was done in assign_irq */
329 nvec = 1 << msi->msi_attrib.multiple;
331 clear_irq_range(pp, irq, nvec, pos);
333 /* all irqs cleared; reset attributes */
335 msi->msi_attrib.multiple = 0;
338 static int dw_msi_setup_irq(struct msi_chip *chip, struct pci_dev *pdev,
339 struct msi_desc *desc)
341 int irq, pos, msgvec;
344 struct pcie_port *pp = sys_to_pcie(pdev->bus->sysdata);
346 pci_read_config_word(pdev, pdev->msi_cap + PCI_MSI_FLAGS, &msg_ctr);
347 msgvec = (msg_ctr & PCI_MSI_FLAGS_QSIZE) >> 4;
349 msgvec = (msg_ctr & PCI_MSI_FLAGS_QMASK) >> 1;
353 irq = assign_irq((1 << msgvec), desc, &pos);
358 * write_msi_msg() will update PCI_MSI_FLAGS so there is
359 * no need to explicitly call pci_write_config_word().
361 desc->msi_attrib.multiple = msgvec;
363 if (pp->ops->get_msi_addr)
364 msg.address_lo = pp->ops->get_msi_addr(pp);
366 msg.address_lo = virt_to_phys((void *)pp->msi_data);
367 msg.address_hi = 0x0;
369 if (pp->ops->get_msi_data)
370 msg.data = pp->ops->get_msi_data(pp, pos);
374 write_msi_msg(irq, &msg);
379 static void dw_msi_teardown_irq(struct msi_chip *chip, unsigned int irq)
384 static struct msi_chip dw_pcie_msi_chip = {
385 .setup_irq = dw_msi_setup_irq,
386 .teardown_irq = dw_msi_teardown_irq,
389 int dw_pcie_link_up(struct pcie_port *pp)
391 if (pp->ops->link_up)
392 return pp->ops->link_up(pp);
397 static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
398 irq_hw_number_t hwirq)
400 irq_set_chip_and_handler(irq, &dw_msi_irq_chip, handle_simple_irq);
401 irq_set_chip_data(irq, domain->host_data);
402 set_irq_flags(irq, IRQF_VALID);
407 static const struct irq_domain_ops msi_domain_ops = {
408 .map = dw_pcie_msi_map,
411 int __init dw_pcie_host_init(struct pcie_port *pp)
413 struct device_node *np = pp->dev->of_node;
414 struct platform_device *pdev = to_platform_device(pp->dev);
415 struct of_pci_range range;
416 struct of_pci_range_parser parser;
417 struct resource *cfg_res;
422 /* Find the address cell size and the number of cells in order to get
423 * the untranslated address.
425 of_property_read_u32(np, "#address-cells", &na);
426 ns = of_n_size_cells(np);
428 cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
430 pp->cfg0_size = resource_size(cfg_res)/2;
431 pp->cfg1_size = resource_size(cfg_res)/2;
432 pp->cfg0_base = cfg_res->start;
433 pp->cfg1_base = cfg_res->start + pp->cfg0_size;
435 /* Find the untranslated configuration space address */
436 index = of_property_match_string(np, "reg-names", "config");
437 addrp = of_get_address(np, index, NULL, NULL);
438 pp->cfg0_mod_base = of_read_number(addrp, ns);
439 pp->cfg1_mod_base = pp->cfg0_mod_base + pp->cfg0_size;
441 dev_err(pp->dev, "missing *config* reg space\n");
444 if (of_pci_range_parser_init(&parser, np)) {
445 dev_err(pp->dev, "missing ranges property\n");
449 /* Get the I/O and memory ranges from DT */
450 for_each_of_pci_range(&parser, &range) {
451 unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
452 if (restype == IORESOURCE_IO) {
453 of_pci_range_to_resource(&range, np, &pp->io);
455 pp->io.start = max_t(resource_size_t,
457 range.pci_addr + global_io_offset);
458 pp->io.end = min_t(resource_size_t,
460 range.pci_addr + range.size
461 + global_io_offset - 1);
462 pp->io_size = resource_size(&pp->io);
463 pp->io_bus_addr = range.pci_addr;
464 pp->io_base = range.cpu_addr;
466 /* Find the untranslated IO space address */
467 pp->io_mod_base = of_read_number(parser.range -
470 if (restype == IORESOURCE_MEM) {
471 of_pci_range_to_resource(&range, np, &pp->mem);
472 pp->mem.name = "MEM";
473 pp->mem_size = resource_size(&pp->mem);
474 pp->mem_bus_addr = range.pci_addr;
476 /* Find the untranslated MEM space address */
477 pp->mem_mod_base = of_read_number(parser.range -
481 of_pci_range_to_resource(&range, np, &pp->cfg);
482 pp->cfg0_size = resource_size(&pp->cfg)/2;
483 pp->cfg1_size = resource_size(&pp->cfg)/2;
484 pp->cfg0_base = pp->cfg.start;
485 pp->cfg1_base = pp->cfg.start + pp->cfg0_size;
487 /* Find the untranslated configuration space address */
488 pp->cfg0_mod_base = of_read_number(parser.range -
490 pp->cfg1_mod_base = pp->cfg0_mod_base +
495 ret = of_pci_parse_bus_range(np, &pp->busn);
497 pp->busn.name = np->name;
500 pp->busn.flags = IORESOURCE_BUS;
501 dev_dbg(pp->dev, "failed to parse bus-range property: %d, using default %pR\n",
506 pp->dbi_base = devm_ioremap(pp->dev, pp->cfg.start,
507 resource_size(&pp->cfg));
509 dev_err(pp->dev, "error with ioremap\n");
514 pp->mem_base = pp->mem.start;
516 if (!pp->va_cfg0_base) {
517 pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
519 if (!pp->va_cfg0_base) {
520 dev_err(pp->dev, "error with ioremap in function\n");
525 if (!pp->va_cfg1_base) {
526 pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base,
528 if (!pp->va_cfg1_base) {
529 dev_err(pp->dev, "error with ioremap\n");
534 if (of_property_read_u32(np, "num-lanes", &pp->lanes)) {
535 dev_err(pp->dev, "Failed to parse the number of lanes\n");
539 if (IS_ENABLED(CONFIG_PCI_MSI)) {
540 if (!pp->ops->msi_host_init) {
541 pp->irq_domain = irq_domain_add_linear(pp->dev->of_node,
542 MAX_MSI_IRQS, &msi_domain_ops,
544 if (!pp->irq_domain) {
545 dev_err(pp->dev, "irq domain init failed\n");
549 for (i = 0; i < MAX_MSI_IRQS; i++)
550 irq_create_mapping(pp->irq_domain, i);
552 ret = pp->ops->msi_host_init(pp, &dw_pcie_msi_chip);
558 if (pp->ops->host_init)
559 pp->ops->host_init(pp);
561 dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
563 /* program correct class for RC */
564 dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
566 dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
567 val |= PORT_LOGIC_SPEED_CHANGE;
568 dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
570 dw_pci.nr_controllers = 1;
571 dw_pci.private_data = (void **)&pp;
573 pci_common_init_dev(pp->dev, &dw_pci);
574 #ifdef CONFIG_PCI_DOMAINS
581 static void dw_pcie_prog_viewport_cfg0(struct pcie_port *pp, u32 busdev)
583 /* Program viewport 0 : OUTBOUND : CFG0 */
584 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
586 dw_pcie_writel_rc(pp, pp->cfg0_mod_base, PCIE_ATU_LOWER_BASE);
587 dw_pcie_writel_rc(pp, (pp->cfg0_mod_base >> 32), PCIE_ATU_UPPER_BASE);
588 dw_pcie_writel_rc(pp, pp->cfg0_mod_base + pp->cfg0_size - 1,
590 dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
591 dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
592 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG0, PCIE_ATU_CR1);
593 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
596 static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev)
598 /* Program viewport 1 : OUTBOUND : CFG1 */
599 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
601 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1);
602 dw_pcie_writel_rc(pp, pp->cfg1_mod_base, PCIE_ATU_LOWER_BASE);
603 dw_pcie_writel_rc(pp, (pp->cfg1_mod_base >> 32), PCIE_ATU_UPPER_BASE);
604 dw_pcie_writel_rc(pp, pp->cfg1_mod_base + pp->cfg1_size - 1,
606 dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
607 dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
608 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
611 static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
613 /* Program viewport 0 : OUTBOUND : MEM */
614 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
616 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
617 dw_pcie_writel_rc(pp, pp->mem_mod_base, PCIE_ATU_LOWER_BASE);
618 dw_pcie_writel_rc(pp, (pp->mem_mod_base >> 32), PCIE_ATU_UPPER_BASE);
619 dw_pcie_writel_rc(pp, pp->mem_mod_base + pp->mem_size - 1,
621 dw_pcie_writel_rc(pp, pp->mem_bus_addr, PCIE_ATU_LOWER_TARGET);
622 dw_pcie_writel_rc(pp, upper_32_bits(pp->mem_bus_addr),
623 PCIE_ATU_UPPER_TARGET);
624 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
627 static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
629 /* Program viewport 1 : OUTBOUND : IO */
630 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
632 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_IO, PCIE_ATU_CR1);
633 dw_pcie_writel_rc(pp, pp->io_mod_base, PCIE_ATU_LOWER_BASE);
634 dw_pcie_writel_rc(pp, (pp->io_mod_base >> 32), PCIE_ATU_UPPER_BASE);
635 dw_pcie_writel_rc(pp, pp->io_mod_base + pp->io_size - 1,
637 dw_pcie_writel_rc(pp, pp->io_bus_addr, PCIE_ATU_LOWER_TARGET);
638 dw_pcie_writel_rc(pp, upper_32_bits(pp->io_bus_addr),
639 PCIE_ATU_UPPER_TARGET);
640 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
643 static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
644 u32 devfn, int where, int size, u32 *val)
646 int ret = PCIBIOS_SUCCESSFUL;
649 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
650 PCIE_ATU_FUNC(PCI_FUNC(devfn));
651 address = where & ~0x3;
653 if (bus->parent->number == pp->root_bus_nr) {
654 dw_pcie_prog_viewport_cfg0(pp, busdev);
655 ret = dw_pcie_cfg_read(pp->va_cfg0_base + address, where, size,
657 dw_pcie_prog_viewport_mem_outbound(pp);
659 dw_pcie_prog_viewport_cfg1(pp, busdev);
660 ret = dw_pcie_cfg_read(pp->va_cfg1_base + address, where, size,
662 dw_pcie_prog_viewport_io_outbound(pp);
668 static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
669 u32 devfn, int where, int size, u32 val)
671 int ret = PCIBIOS_SUCCESSFUL;
674 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
675 PCIE_ATU_FUNC(PCI_FUNC(devfn));
676 address = where & ~0x3;
678 if (bus->parent->number == pp->root_bus_nr) {
679 dw_pcie_prog_viewport_cfg0(pp, busdev);
680 ret = dw_pcie_cfg_write(pp->va_cfg0_base + address, where, size,
682 dw_pcie_prog_viewport_mem_outbound(pp);
684 dw_pcie_prog_viewport_cfg1(pp, busdev);
685 ret = dw_pcie_cfg_write(pp->va_cfg1_base + address, where, size,
687 dw_pcie_prog_viewport_io_outbound(pp);
693 static int dw_pcie_valid_config(struct pcie_port *pp,
694 struct pci_bus *bus, int dev)
696 /* If there is no link, then there is no device */
697 if (bus->number != pp->root_bus_nr) {
698 if (!dw_pcie_link_up(pp))
702 /* access only one slot on each root port */
703 if (bus->number == pp->root_bus_nr && dev > 0)
707 * do not read more than one device on the bus directly attached
708 * to RC's (Virtual Bridge's) DS side.
710 if (bus->primary == pp->root_bus_nr && dev > 0)
716 static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
719 struct pcie_port *pp = sys_to_pcie(bus->sysdata);
722 if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) {
724 return PCIBIOS_DEVICE_NOT_FOUND;
727 if (bus->number != pp->root_bus_nr)
728 if (pp->ops->rd_other_conf)
729 ret = pp->ops->rd_other_conf(pp, bus, devfn,
732 ret = dw_pcie_rd_other_conf(pp, bus, devfn,
735 ret = dw_pcie_rd_own_conf(pp, where, size, val);
740 static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
741 int where, int size, u32 val)
743 struct pcie_port *pp = sys_to_pcie(bus->sysdata);
746 if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0)
747 return PCIBIOS_DEVICE_NOT_FOUND;
749 if (bus->number != pp->root_bus_nr)
750 if (pp->ops->wr_other_conf)
751 ret = pp->ops->wr_other_conf(pp, bus, devfn,
754 ret = dw_pcie_wr_other_conf(pp, bus, devfn,
757 ret = dw_pcie_wr_own_conf(pp, where, size, val);
762 static struct pci_ops dw_pcie_ops = {
763 .read = dw_pcie_rd_conf,
764 .write = dw_pcie_wr_conf,
767 static int dw_pcie_setup(int nr, struct pci_sys_data *sys)
769 struct pcie_port *pp;
771 pp = sys_to_pcie(sys);
773 if (global_io_offset < SZ_1M && pp->io_size > 0) {
774 sys->io_offset = global_io_offset - pp->io_bus_addr;
775 pci_ioremap_io(global_io_offset, pp->io_base);
776 global_io_offset += SZ_64K;
777 pci_add_resource_offset(&sys->resources, &pp->io,
781 sys->mem_offset = pp->mem.start - pp->mem_bus_addr;
782 pci_add_resource_offset(&sys->resources, &pp->mem, sys->mem_offset);
783 pci_add_resource(&sys->resources, &pp->busn);
788 static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys)
791 struct pcie_port *pp = sys_to_pcie(sys);
793 pp->root_bus_nr = sys->busnr;
794 bus = pci_create_root_bus(pp->dev, sys->busnr,
795 &dw_pcie_ops, sys, &sys->resources);
799 pci_scan_child_bus(bus);
801 if (bus && pp->ops->scan_bus)
802 pp->ops->scan_bus(pp);
807 static int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
809 struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata);
812 irq = of_irq_parse_and_map_pci(dev, slot, pin);
819 static void dw_pcie_add_bus(struct pci_bus *bus)
821 if (IS_ENABLED(CONFIG_PCI_MSI)) {
822 struct pcie_port *pp = sys_to_pcie(bus->sysdata);
824 dw_pcie_msi_chip.dev = pp->dev;
825 bus->msi = &dw_pcie_msi_chip;
829 static struct hw_pci dw_pci = {
830 .setup = dw_pcie_setup,
831 .scan = dw_pcie_scan_bus,
832 .map_irq = dw_pcie_map_irq,
833 .add_bus = dw_pcie_add_bus,
836 void dw_pcie_setup_rc(struct pcie_port *pp)
842 /* set the number of lanes */
843 dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val);
844 val &= ~PORT_LINK_MODE_MASK;
847 val |= PORT_LINK_MODE_1_LANES;
850 val |= PORT_LINK_MODE_2_LANES;
853 val |= PORT_LINK_MODE_4_LANES;
856 dw_pcie_writel_rc(pp, val, PCIE_PORT_LINK_CONTROL);
858 /* set link width speed control register */
859 dw_pcie_readl_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, &val);
860 val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
863 val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
866 val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
869 val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
872 dw_pcie_writel_rc(pp, val, PCIE_LINK_WIDTH_SPEED_CONTROL);
875 dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0);
876 dw_pcie_writel_rc(pp, 0x00000000, PCI_BASE_ADDRESS_1);
878 /* setup interrupt pins */
879 dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE, &val);
882 dw_pcie_writel_rc(pp, val, PCI_INTERRUPT_LINE);
884 /* setup bus numbers */
885 dw_pcie_readl_rc(pp, PCI_PRIMARY_BUS, &val);
888 dw_pcie_writel_rc(pp, val, PCI_PRIMARY_BUS);
890 /* setup memory base, memory limit */
891 membase = ((u32)pp->mem_base & 0xfff00000) >> 16;
892 memlimit = (pp->mem_size + (u32)pp->mem_base) & 0xfff00000;
893 val = memlimit | membase;
894 dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE);
896 /* setup command register */
897 dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
899 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
900 PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
901 dw_pcie_writel_rc(pp, val, PCI_COMMAND);
904 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
905 MODULE_DESCRIPTION("Designware PCIe host controller driver");
906 MODULE_LICENSE("GPL v2");