1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe driver for Renesas R-Car SoCs
4 * Copyright (C) 2014 Renesas Electronics Europe Ltd
7 * arch/sh/drivers/pci/pcie-sh7786.c
8 * arch/sh/drivers/pci/ops-sh7786.c
9 * Copyright (C) 2009 - 2011 Paul Mundt
11 * Author: Phil Edworthy <phil.edworthy@renesas.com>
14 #include <linux/bitops.h>
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/interrupt.h>
18 #include <linux/irq.h>
19 #include <linux/irqdomain.h>
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/msi.h>
23 #include <linux/of_address.h>
24 #include <linux/of_irq.h>
25 #include <linux/of_pci.h>
26 #include <linux/of_platform.h>
27 #include <linux/pci.h>
28 #include <linux/phy/phy.h>
29 #include <linux/platform_device.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/slab.h>
33 #define PCIECAR 0x000010
34 #define PCIECCTLR 0x000018
35 #define CONFIG_SEND_ENABLE BIT(31)
36 #define TYPE0 (0 << 8)
38 #define PCIECDR 0x000020
39 #define PCIEMSR 0x000028
40 #define PCIEINTXR 0x000400
41 #define PCIEPHYSR 0x0007f0
43 #define PCIEMSITXR 0x000840
45 /* Transfer control */
46 #define PCIETCTLR 0x02000
48 #define PCIETSTR 0x02004
49 #define DATA_LINK_ACTIVE 1
50 #define PCIEERRFR 0x02020
51 #define UNSUPPORTED_REQUEST BIT(4)
52 #define PCIEMSIFR 0x02044
53 #define PCIEMSIALR 0x02048
55 #define PCIEMSIAUR 0x0204c
56 #define PCIEMSIIER 0x02050
58 /* root port address */
59 #define PCIEPRAR(x) (0x02080 + ((x) * 0x4))
61 /* local address reg & mask */
62 #define PCIELAR(x) (0x02200 + ((x) * 0x20))
63 #define PCIELAMR(x) (0x02208 + ((x) * 0x20))
64 #define LAM_PREFETCH BIT(3)
65 #define LAM_64BIT BIT(2)
66 #define LAR_ENABLE BIT(1)
68 /* PCIe address reg & mask */
69 #define PCIEPALR(x) (0x03400 + ((x) * 0x20))
70 #define PCIEPAUR(x) (0x03404 + ((x) * 0x20))
71 #define PCIEPAMR(x) (0x03408 + ((x) * 0x20))
72 #define PCIEPTCTLR(x) (0x0340c + ((x) * 0x20))
73 #define PAR_ENABLE BIT(31)
74 #define IO_SPACE BIT(8)
77 #define PCICONF(x) (0x010000 + ((x) * 0x4))
78 #define PMCAP(x) (0x010040 + ((x) * 0x4))
79 #define EXPCAP(x) (0x010070 + ((x) * 0x4))
80 #define VCCAP(x) (0x010100 + ((x) * 0x4))
83 #define IDSETR1 0x011004
84 #define TLCTLR 0x011048
85 #define MACSR 0x011054
86 #define SPCHGFIN BIT(4)
87 #define SPCHGFAIL BIT(6)
88 #define SPCHGSUC BIT(7)
89 #define LINK_SPEED (0xf << 16)
90 #define LINK_SPEED_2_5GTS (1 << 16)
91 #define LINK_SPEED_5_0GTS (2 << 16)
92 #define MACCTLR 0x011058
93 #define SPEED_CHANGE BIT(24)
94 #define SCRAMBLE_DISABLE BIT(27)
95 #define MACS2R 0x011078
96 #define MACCGSPSETR 0x011084
97 #define SPCNGRSN BIT(31)
100 #define H1_PCIEPHYADRR 0x04000c
101 #define WRITE_CMD BIT(16)
102 #define PHY_ACK BIT(24)
106 #define H1_PCIEPHYDOUTR 0x040014
109 #define GEN2_PCIEPHYADDR 0x780
110 #define GEN2_PCIEPHYDATA 0x784
111 #define GEN2_PCIEPHYCTRL 0x78c
113 #define INT_PCI_MSI_NR 32
115 #define RCONF(x) (PCICONF(0) + (x))
116 #define RPMCAP(x) (PMCAP(0) + (x))
117 #define REXPCAP(x) (EXPCAP(0) + (x))
118 #define RVCCAP(x) (VCCAP(0) + (x))
120 #define PCIE_CONF_BUS(b) (((b) & 0xff) << 24)
121 #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 19)
122 #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 16)
124 #define RCAR_PCI_MAX_RESOURCES 4
125 #define MAX_NR_INBOUND_MAPS 6
128 DECLARE_BITMAP(used, INT_PCI_MSI_NR);
129 struct irq_domain *domain;
130 struct msi_controller chip;
137 static inline struct rcar_msi *to_rcar_msi(struct msi_controller *chip)
139 return container_of(chip, struct rcar_msi, chip);
142 /* Structure representing the PCIe interface */
147 struct list_head resources;
153 static void rcar_pci_write_reg(struct rcar_pcie *pcie, unsigned long val,
156 writel(val, pcie->base + reg);
159 static unsigned long rcar_pci_read_reg(struct rcar_pcie *pcie,
162 return readl(pcie->base + reg);
166 RCAR_PCI_ACCESS_READ,
167 RCAR_PCI_ACCESS_WRITE,
170 static void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data)
172 int shift = 8 * (where & 3);
173 u32 val = rcar_pci_read_reg(pcie, where & ~3);
175 val &= ~(mask << shift);
176 val |= data << shift;
177 rcar_pci_write_reg(pcie, val, where & ~3);
180 static u32 rcar_read_conf(struct rcar_pcie *pcie, int where)
182 int shift = 8 * (where & 3);
183 u32 val = rcar_pci_read_reg(pcie, where & ~3);
188 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
189 static int rcar_pcie_config_access(struct rcar_pcie *pcie,
190 unsigned char access_type, struct pci_bus *bus,
191 unsigned int devfn, int where, u32 *data)
193 int dev, func, reg, index;
195 dev = PCI_SLOT(devfn);
196 func = PCI_FUNC(devfn);
201 * While each channel has its own memory-mapped extended config
202 * space, it's generally only accessible when in endpoint mode.
203 * When in root complex mode, the controller is unable to target
204 * itself with either type 0 or type 1 accesses, and indeed, any
205 * controller initiated target transfer to its own config space
206 * result in a completer abort.
208 * Each channel effectively only supports a single device, but as
209 * the same channel <-> device access works for any PCI_SLOT()
210 * value, we cheat a bit here and bind the controller's config
211 * space to devfn 0 in order to enable self-enumeration. In this
212 * case the regular ECAR/ECDR path is sidelined and the mangled
213 * config access itself is initiated as an internal bus transaction.
215 if (pci_is_root_bus(bus)) {
217 return PCIBIOS_DEVICE_NOT_FOUND;
219 if (access_type == RCAR_PCI_ACCESS_READ) {
220 *data = rcar_pci_read_reg(pcie, PCICONF(index));
222 /* Keep an eye out for changes to the root bus number */
223 if (pci_is_root_bus(bus) && (reg == PCI_PRIMARY_BUS))
224 pcie->root_bus_nr = *data & 0xff;
226 rcar_pci_write_reg(pcie, *data, PCICONF(index));
229 return PCIBIOS_SUCCESSFUL;
232 if (pcie->root_bus_nr < 0)
233 return PCIBIOS_DEVICE_NOT_FOUND;
236 rcar_pci_write_reg(pcie, rcar_pci_read_reg(pcie, PCIEERRFR), PCIEERRFR);
238 /* Set the PIO address */
239 rcar_pci_write_reg(pcie, PCIE_CONF_BUS(bus->number) |
240 PCIE_CONF_DEV(dev) | PCIE_CONF_FUNC(func) | reg, PCIECAR);
242 /* Enable the configuration access */
243 if (bus->parent->number == pcie->root_bus_nr)
244 rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE0, PCIECCTLR);
246 rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE1, PCIECCTLR);
248 /* Check for errors */
249 if (rcar_pci_read_reg(pcie, PCIEERRFR) & UNSUPPORTED_REQUEST)
250 return PCIBIOS_DEVICE_NOT_FOUND;
252 /* Check for master and target aborts */
253 if (rcar_read_conf(pcie, RCONF(PCI_STATUS)) &
254 (PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT))
255 return PCIBIOS_DEVICE_NOT_FOUND;
257 if (access_type == RCAR_PCI_ACCESS_READ)
258 *data = rcar_pci_read_reg(pcie, PCIECDR);
260 rcar_pci_write_reg(pcie, *data, PCIECDR);
262 /* Disable the configuration access */
263 rcar_pci_write_reg(pcie, 0, PCIECCTLR);
265 return PCIBIOS_SUCCESSFUL;
268 static int rcar_pcie_read_conf(struct pci_bus *bus, unsigned int devfn,
269 int where, int size, u32 *val)
271 struct rcar_pcie *pcie = bus->sysdata;
274 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_READ,
275 bus, devfn, where, val);
276 if (ret != PCIBIOS_SUCCESSFUL) {
282 *val = (*val >> (8 * (where & 3))) & 0xff;
284 *val = (*val >> (8 * (where & 2))) & 0xffff;
286 dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08lx\n",
287 bus->number, devfn, where, size, (unsigned long)*val);
292 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
293 static int rcar_pcie_write_conf(struct pci_bus *bus, unsigned int devfn,
294 int where, int size, u32 val)
296 struct rcar_pcie *pcie = bus->sysdata;
300 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_READ,
301 bus, devfn, where, &data);
302 if (ret != PCIBIOS_SUCCESSFUL)
305 dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08lx\n",
306 bus->number, devfn, where, size, (unsigned long)val);
309 shift = 8 * (where & 3);
310 data &= ~(0xff << shift);
311 data |= ((val & 0xff) << shift);
312 } else if (size == 2) {
313 shift = 8 * (where & 2);
314 data &= ~(0xffff << shift);
315 data |= ((val & 0xffff) << shift);
319 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_WRITE,
320 bus, devfn, where, &data);
325 static struct pci_ops rcar_pcie_ops = {
326 .read = rcar_pcie_read_conf,
327 .write = rcar_pcie_write_conf,
330 static void rcar_pcie_setup_window(int win, struct rcar_pcie *pcie,
331 struct resource *res)
333 /* Setup PCIe address space mappings for each resource */
334 resource_size_t size;
335 resource_size_t res_start;
338 rcar_pci_write_reg(pcie, 0x00000000, PCIEPTCTLR(win));
341 * The PAMR mask is calculated in units of 128Bytes, which
342 * keeps things pretty simple.
344 size = resource_size(res);
345 mask = (roundup_pow_of_two(size) / SZ_128) - 1;
346 rcar_pci_write_reg(pcie, mask << 7, PCIEPAMR(win));
348 if (res->flags & IORESOURCE_IO)
349 res_start = pci_pio_to_address(res->start);
351 res_start = res->start;
353 rcar_pci_write_reg(pcie, upper_32_bits(res_start), PCIEPAUR(win));
354 rcar_pci_write_reg(pcie, lower_32_bits(res_start) & ~0x7F,
357 /* First resource is for IO */
359 if (res->flags & IORESOURCE_IO)
362 rcar_pci_write_reg(pcie, mask, PCIEPTCTLR(win));
365 static int rcar_pcie_setup(struct list_head *resource, struct rcar_pcie *pci)
367 struct resource_entry *win;
370 /* Setup PCI resources */
371 resource_list_for_each_entry(win, &pci->resources) {
372 struct resource *res = win->res;
377 switch (resource_type(res)) {
380 rcar_pcie_setup_window(i, pci, res);
384 pci->root_bus_nr = res->start;
390 pci_add_resource(resource, res);
396 static void rcar_pcie_force_speedup(struct rcar_pcie *pcie)
398 struct device *dev = pcie->dev;
399 unsigned int timeout = 1000;
402 if ((rcar_pci_read_reg(pcie, MACS2R) & LINK_SPEED) != LINK_SPEED_5_0GTS)
405 if (rcar_pci_read_reg(pcie, MACCTLR) & SPEED_CHANGE) {
406 dev_err(dev, "Speed change already in progress\n");
410 macsr = rcar_pci_read_reg(pcie, MACSR);
411 if ((macsr & LINK_SPEED) == LINK_SPEED_5_0GTS)
414 /* Set target link speed to 5.0 GT/s */
415 rcar_rmw32(pcie, EXPCAP(12), PCI_EXP_LNKSTA_CLS,
416 PCI_EXP_LNKSTA_CLS_5_0GB);
418 /* Set speed change reason as intentional factor */
419 rcar_rmw32(pcie, MACCGSPSETR, SPCNGRSN, 0);
421 /* Clear SPCHGFIN, SPCHGSUC, and SPCHGFAIL */
422 if (macsr & (SPCHGFIN | SPCHGSUC | SPCHGFAIL))
423 rcar_pci_write_reg(pcie, macsr, MACSR);
425 /* Start link speed change */
426 rcar_rmw32(pcie, MACCTLR, SPEED_CHANGE, SPEED_CHANGE);
429 macsr = rcar_pci_read_reg(pcie, MACSR);
430 if (macsr & SPCHGFIN) {
431 /* Clear the interrupt bits */
432 rcar_pci_write_reg(pcie, macsr, MACSR);
434 if (macsr & SPCHGFAIL)
435 dev_err(dev, "Speed change failed\n");
443 dev_err(dev, "Speed change timed out\n");
446 dev_info(dev, "Current link speed is %s GT/s\n",
447 (macsr & LINK_SPEED) == LINK_SPEED_5_0GTS ? "5" : "2.5");
450 static int rcar_pcie_enable(struct rcar_pcie *pcie)
452 struct device *dev = pcie->dev;
453 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
454 struct pci_bus *bus, *child;
457 /* Try setting 5 GT/s link speed */
458 rcar_pcie_force_speedup(pcie);
460 rcar_pcie_setup(&bridge->windows, pcie);
462 pci_add_flags(PCI_REASSIGN_ALL_BUS);
464 bridge->dev.parent = dev;
465 bridge->sysdata = pcie;
466 bridge->busnr = pcie->root_bus_nr;
467 bridge->ops = &rcar_pcie_ops;
468 bridge->map_irq = of_irq_parse_and_map_pci;
469 bridge->swizzle_irq = pci_common_swizzle;
470 if (IS_ENABLED(CONFIG_PCI_MSI))
471 bridge->msi = &pcie->msi.chip;
473 ret = pci_scan_root_bus_bridge(bridge);
479 pci_bus_size_bridges(bus);
480 pci_bus_assign_resources(bus);
482 list_for_each_entry(child, &bus->children, node)
483 pcie_bus_configure_settings(child);
485 pci_bus_add_devices(bus);
490 static int phy_wait_for_ack(struct rcar_pcie *pcie)
492 struct device *dev = pcie->dev;
493 unsigned int timeout = 100;
496 if (rcar_pci_read_reg(pcie, H1_PCIEPHYADRR) & PHY_ACK)
502 dev_err(dev, "Access to PCIe phy timed out\n");
507 static void phy_write_reg(struct rcar_pcie *pcie,
508 unsigned int rate, unsigned int addr,
509 unsigned int lane, unsigned int data)
511 unsigned long phyaddr;
513 phyaddr = WRITE_CMD |
514 ((rate & 1) << RATE_POS) |
515 ((lane & 0xf) << LANE_POS) |
516 ((addr & 0xff) << ADR_POS);
519 rcar_pci_write_reg(pcie, data, H1_PCIEPHYDOUTR);
520 rcar_pci_write_reg(pcie, phyaddr, H1_PCIEPHYADRR);
522 /* Ignore errors as they will be dealt with if the data link is down */
523 phy_wait_for_ack(pcie);
526 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYDOUTR);
527 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYADRR);
529 /* Ignore errors as they will be dealt with if the data link is down */
530 phy_wait_for_ack(pcie);
533 static int rcar_pcie_wait_for_phyrdy(struct rcar_pcie *pcie)
535 unsigned int timeout = 10;
538 if (rcar_pci_read_reg(pcie, PCIEPHYSR) & PHYRDY)
547 static int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie)
549 unsigned int timeout = 10000;
552 if ((rcar_pci_read_reg(pcie, PCIETSTR) & DATA_LINK_ACTIVE))
562 static int rcar_pcie_hw_init(struct rcar_pcie *pcie)
566 /* Begin initialization */
567 rcar_pci_write_reg(pcie, 0, PCIETCTLR);
570 rcar_pci_write_reg(pcie, 1, PCIEMSR);
572 err = rcar_pcie_wait_for_phyrdy(pcie);
577 * Initial header for port config space is type 1, set the device
578 * class to match. Hardware takes care of propagating the IDSETR
579 * settings, so there is no need to bother with a quirk.
581 rcar_pci_write_reg(pcie, PCI_CLASS_BRIDGE_PCI << 16, IDSETR1);
584 * Setup Secondary Bus Number & Subordinate Bus Number, even though
585 * they aren't used, to avoid bridge being detected as broken.
587 rcar_rmw32(pcie, RCONF(PCI_SECONDARY_BUS), 0xff, 1);
588 rcar_rmw32(pcie, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1);
590 /* Initialize default capabilities. */
591 rcar_rmw32(pcie, REXPCAP(0), 0xff, PCI_CAP_ID_EXP);
592 rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS),
593 PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ROOT_PORT << 4);
594 rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), 0x7f,
595 PCI_HEADER_TYPE_BRIDGE);
597 /* Enable data link layer active state reporting */
598 rcar_rmw32(pcie, REXPCAP(PCI_EXP_LNKCAP), PCI_EXP_LNKCAP_DLLLARC,
599 PCI_EXP_LNKCAP_DLLLARC);
601 /* Write out the physical slot number = 0 */
602 rcar_rmw32(pcie, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0);
604 /* Set the completion timer timeout to the maximum 50ms. */
605 rcar_rmw32(pcie, TLCTLR + 1, 0x3f, 50);
607 /* Terminate list of capabilities (Next Capability Offset=0) */
608 rcar_rmw32(pcie, RVCCAP(0), 0xfff00000, 0);
611 if (IS_ENABLED(CONFIG_PCI_MSI))
612 rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR);
614 /* Finish initialization - establish a PCI Express link */
615 rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
617 /* This will timeout if we don't have a link. */
618 err = rcar_pcie_wait_for_dl(pcie);
622 /* Enable INTx interrupts */
623 rcar_rmw32(pcie, PCIEINTXR, 0, 0xF << 8);
630 static int rcar_pcie_phy_init_h1(struct rcar_pcie *pcie)
632 /* Initialize the phy */
633 phy_write_reg(pcie, 0, 0x42, 0x1, 0x0EC34191);
634 phy_write_reg(pcie, 1, 0x42, 0x1, 0x0EC34180);
635 phy_write_reg(pcie, 0, 0x43, 0x1, 0x00210188);
636 phy_write_reg(pcie, 1, 0x43, 0x1, 0x00210188);
637 phy_write_reg(pcie, 0, 0x44, 0x1, 0x015C0014);
638 phy_write_reg(pcie, 1, 0x44, 0x1, 0x015C0014);
639 phy_write_reg(pcie, 1, 0x4C, 0x1, 0x786174A0);
640 phy_write_reg(pcie, 1, 0x4D, 0x1, 0x048000BB);
641 phy_write_reg(pcie, 0, 0x51, 0x1, 0x079EC062);
642 phy_write_reg(pcie, 0, 0x52, 0x1, 0x20000000);
643 phy_write_reg(pcie, 1, 0x52, 0x1, 0x20000000);
644 phy_write_reg(pcie, 1, 0x56, 0x1, 0x00003806);
646 phy_write_reg(pcie, 0, 0x60, 0x1, 0x004B03A5);
647 phy_write_reg(pcie, 0, 0x64, 0x1, 0x3F0F1F0F);
648 phy_write_reg(pcie, 0, 0x66, 0x1, 0x00008000);
653 static int rcar_pcie_phy_init_gen2(struct rcar_pcie *pcie)
656 * These settings come from the R-Car Series, 2nd Generation User's
657 * Manual, section 50.3.1 (2) Initialization of the physical layer.
659 rcar_pci_write_reg(pcie, 0x000f0030, GEN2_PCIEPHYADDR);
660 rcar_pci_write_reg(pcie, 0x00381203, GEN2_PCIEPHYDATA);
661 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL);
662 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL);
664 rcar_pci_write_reg(pcie, 0x000f0054, GEN2_PCIEPHYADDR);
665 /* The following value is for DC connection, no termination resistor */
666 rcar_pci_write_reg(pcie, 0x13802007, GEN2_PCIEPHYDATA);
667 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL);
668 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL);
673 static int rcar_pcie_phy_init_gen3(struct rcar_pcie *pcie)
677 err = phy_init(pcie->phy);
681 return phy_power_on(pcie->phy);
684 static int rcar_msi_alloc(struct rcar_msi *chip)
688 mutex_lock(&chip->lock);
690 msi = find_first_zero_bit(chip->used, INT_PCI_MSI_NR);
691 if (msi < INT_PCI_MSI_NR)
692 set_bit(msi, chip->used);
696 mutex_unlock(&chip->lock);
701 static int rcar_msi_alloc_region(struct rcar_msi *chip, int no_irqs)
705 mutex_lock(&chip->lock);
706 msi = bitmap_find_free_region(chip->used, INT_PCI_MSI_NR,
707 order_base_2(no_irqs));
708 mutex_unlock(&chip->lock);
713 static void rcar_msi_free(struct rcar_msi *chip, unsigned long irq)
715 mutex_lock(&chip->lock);
716 clear_bit(irq, chip->used);
717 mutex_unlock(&chip->lock);
720 static irqreturn_t rcar_pcie_msi_irq(int irq, void *data)
722 struct rcar_pcie *pcie = data;
723 struct rcar_msi *msi = &pcie->msi;
724 struct device *dev = pcie->dev;
727 reg = rcar_pci_read_reg(pcie, PCIEMSIFR);
729 /* MSI & INTx share an interrupt - we only handle MSI here */
734 unsigned int index = find_first_bit(®, 32);
737 /* clear the interrupt */
738 rcar_pci_write_reg(pcie, 1 << index, PCIEMSIFR);
740 irq = irq_find_mapping(msi->domain, index);
742 if (test_bit(index, msi->used))
743 generic_handle_irq(irq);
745 dev_info(dev, "unhandled MSI\n");
747 /* Unknown MSI, just clear it */
748 dev_dbg(dev, "unexpected MSI\n");
751 /* see if there's any more pending in this vector */
752 reg = rcar_pci_read_reg(pcie, PCIEMSIFR);
758 static int rcar_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev,
759 struct msi_desc *desc)
761 struct rcar_msi *msi = to_rcar_msi(chip);
762 struct rcar_pcie *pcie = container_of(chip, struct rcar_pcie, msi.chip);
767 hwirq = rcar_msi_alloc(msi);
771 irq = irq_find_mapping(msi->domain, hwirq);
773 rcar_msi_free(msi, hwirq);
777 irq_set_msi_desc(irq, desc);
779 msg.address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE;
780 msg.address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR);
783 pci_write_msi_msg(irq, &msg);
788 static int rcar_msi_setup_irqs(struct msi_controller *chip,
789 struct pci_dev *pdev, int nvec, int type)
791 struct rcar_pcie *pcie = container_of(chip, struct rcar_pcie, msi.chip);
792 struct rcar_msi *msi = to_rcar_msi(chip);
793 struct msi_desc *desc;
799 /* MSI-X interrupts are not supported */
800 if (type == PCI_CAP_ID_MSIX)
803 WARN_ON(!list_is_singular(&pdev->dev.msi_list));
804 desc = list_entry(pdev->dev.msi_list.next, struct msi_desc, list);
806 hwirq = rcar_msi_alloc_region(msi, nvec);
810 irq = irq_find_mapping(msi->domain, hwirq);
814 for (i = 0; i < nvec; i++) {
816 * irq_create_mapping() called from rcar_pcie_probe() pre-
817 * allocates descs, so there is no need to allocate descs here.
818 * We can therefore assume that if irq_find_mapping() above
819 * returns non-zero, then the descs are also successfully
822 if (irq_set_msi_desc_off(irq, i, desc)) {
828 desc->nvec_used = nvec;
829 desc->msi_attrib.multiple = order_base_2(nvec);
831 msg.address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE;
832 msg.address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR);
835 pci_write_msi_msg(irq, &msg);
840 static void rcar_msi_teardown_irq(struct msi_controller *chip, unsigned int irq)
842 struct rcar_msi *msi = to_rcar_msi(chip);
843 struct irq_data *d = irq_get_irq_data(irq);
845 rcar_msi_free(msi, d->hwirq);
848 static struct irq_chip rcar_msi_irq_chip = {
849 .name = "R-Car PCIe MSI",
850 .irq_enable = pci_msi_unmask_irq,
851 .irq_disable = pci_msi_mask_irq,
852 .irq_mask = pci_msi_mask_irq,
853 .irq_unmask = pci_msi_unmask_irq,
856 static int rcar_msi_map(struct irq_domain *domain, unsigned int irq,
857 irq_hw_number_t hwirq)
859 irq_set_chip_and_handler(irq, &rcar_msi_irq_chip, handle_simple_irq);
860 irq_set_chip_data(irq, domain->host_data);
865 static const struct irq_domain_ops msi_domain_ops = {
869 static int rcar_pcie_enable_msi(struct rcar_pcie *pcie)
871 struct device *dev = pcie->dev;
872 struct rcar_msi *msi = &pcie->msi;
876 mutex_init(&msi->lock);
879 msi->chip.setup_irq = rcar_msi_setup_irq;
880 msi->chip.setup_irqs = rcar_msi_setup_irqs;
881 msi->chip.teardown_irq = rcar_msi_teardown_irq;
883 msi->domain = irq_domain_add_linear(dev->of_node, INT_PCI_MSI_NR,
884 &msi_domain_ops, &msi->chip);
886 dev_err(dev, "failed to create IRQ domain\n");
890 for (i = 0; i < INT_PCI_MSI_NR; i++)
891 irq_create_mapping(msi->domain, i);
893 /* Two irqs are for MSI, but they are also used for non-MSI irqs */
894 err = devm_request_irq(dev, msi->irq1, rcar_pcie_msi_irq,
895 IRQF_SHARED | IRQF_NO_THREAD,
896 rcar_msi_irq_chip.name, pcie);
898 dev_err(dev, "failed to request IRQ: %d\n", err);
902 err = devm_request_irq(dev, msi->irq2, rcar_pcie_msi_irq,
903 IRQF_SHARED | IRQF_NO_THREAD,
904 rcar_msi_irq_chip.name, pcie);
906 dev_err(dev, "failed to request IRQ: %d\n", err);
910 /* setup MSI data target */
911 msi->pages = __get_free_pages(GFP_KERNEL, 0);
912 base = virt_to_phys((void *)msi->pages);
914 rcar_pci_write_reg(pcie, base | MSIFE, PCIEMSIALR);
915 rcar_pci_write_reg(pcie, 0, PCIEMSIAUR);
917 /* enable all MSI interrupts */
918 rcar_pci_write_reg(pcie, 0xffffffff, PCIEMSIIER);
923 irq_domain_remove(msi->domain);
927 static int rcar_pcie_get_resources(struct rcar_pcie *pcie)
929 struct device *dev = pcie->dev;
933 pcie->phy = devm_phy_optional_get(dev, "pcie");
934 if (IS_ERR(pcie->phy))
935 return PTR_ERR(pcie->phy);
937 err = of_address_to_resource(dev->of_node, 0, &res);
941 pcie->base = devm_ioremap_resource(dev, &res);
942 if (IS_ERR(pcie->base))
943 return PTR_ERR(pcie->base);
945 pcie->bus_clk = devm_clk_get(dev, "pcie_bus");
946 if (IS_ERR(pcie->bus_clk)) {
947 dev_err(dev, "cannot get pcie bus clock\n");
948 return PTR_ERR(pcie->bus_clk);
951 i = irq_of_parse_and_map(dev->of_node, 0);
953 dev_err(dev, "cannot get platform resources for msi interrupt\n");
959 i = irq_of_parse_and_map(dev->of_node, 1);
961 dev_err(dev, "cannot get platform resources for msi interrupt\n");
970 irq_dispose_mapping(pcie->msi.irq1);
975 static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie,
976 struct of_pci_range *range,
979 u64 restype = range->flags;
980 u64 cpu_addr = range->cpu_addr;
981 u64 cpu_end = range->cpu_addr + range->size;
982 u64 pci_addr = range->pci_addr;
983 u32 flags = LAM_64BIT | LAR_ENABLE;
988 if (restype & IORESOURCE_PREFETCH)
989 flags |= LAM_PREFETCH;
992 * If the size of the range is larger than the alignment of the start
993 * address, we have to use multiple entries to perform the mapping.
996 unsigned long nr_zeros = __ffs64(cpu_addr);
997 u64 alignment = 1ULL << nr_zeros;
999 size = min(range->size, alignment);
1003 /* Hardware supports max 4GiB inbound region */
1004 size = min(size, 1ULL << 32);
1006 mask = roundup_pow_of_two(size) - 1;
1009 while (cpu_addr < cpu_end) {
1011 * Set up 64-bit inbound regions as the range parser doesn't
1012 * distinguish between 32 and 64-bit types.
1014 rcar_pci_write_reg(pcie, lower_32_bits(pci_addr),
1016 rcar_pci_write_reg(pcie, lower_32_bits(cpu_addr), PCIELAR(idx));
1017 rcar_pci_write_reg(pcie, lower_32_bits(mask) | flags,
1020 rcar_pci_write_reg(pcie, upper_32_bits(pci_addr),
1022 rcar_pci_write_reg(pcie, upper_32_bits(cpu_addr),
1024 rcar_pci_write_reg(pcie, 0, PCIELAMR(idx + 1));
1030 if (idx > MAX_NR_INBOUND_MAPS) {
1031 dev_err(pcie->dev, "Failed to map inbound regions!\n");
1040 static int rcar_pcie_parse_map_dma_ranges(struct rcar_pcie *pcie,
1041 struct device_node *np)
1043 struct of_pci_range range;
1044 struct of_pci_range_parser parser;
1048 if (of_pci_dma_range_parser_init(&parser, np))
1051 /* Get the dma-ranges from DT */
1052 for_each_of_pci_range(&parser, &range) {
1053 u64 end = range.cpu_addr + range.size - 1;
1055 dev_dbg(pcie->dev, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n",
1056 range.flags, range.cpu_addr, end, range.pci_addr);
1058 err = rcar_pcie_inbound_ranges(pcie, &range, &index);
1066 static const struct of_device_id rcar_pcie_of_match[] = {
1067 { .compatible = "renesas,pcie-r8a7779",
1068 .data = rcar_pcie_phy_init_h1 },
1069 { .compatible = "renesas,pcie-r8a7790",
1070 .data = rcar_pcie_phy_init_gen2 },
1071 { .compatible = "renesas,pcie-r8a7791",
1072 .data = rcar_pcie_phy_init_gen2 },
1073 { .compatible = "renesas,pcie-rcar-gen2",
1074 .data = rcar_pcie_phy_init_gen2 },
1075 { .compatible = "renesas,pcie-r8a7795",
1076 .data = rcar_pcie_phy_init_gen3 },
1077 { .compatible = "renesas,pcie-rcar-gen3",
1078 .data = rcar_pcie_phy_init_gen3 },
1082 static int rcar_pcie_probe(struct platform_device *pdev)
1084 struct device *dev = &pdev->dev;
1085 struct rcar_pcie *pcie;
1088 int (*phy_init_fn)(struct rcar_pcie *);
1089 struct pci_host_bridge *bridge;
1091 bridge = pci_alloc_host_bridge(sizeof(*pcie));
1095 pcie = pci_host_bridge_priv(bridge);
1099 err = pci_parse_request_of_pci_ranges(dev, &pcie->resources, NULL);
1101 goto err_free_bridge;
1103 pm_runtime_enable(pcie->dev);
1104 err = pm_runtime_get_sync(pcie->dev);
1106 dev_err(pcie->dev, "pm_runtime_get_sync failed\n");
1107 goto err_pm_disable;
1110 err = rcar_pcie_get_resources(pcie);
1112 dev_err(dev, "failed to request resources: %d\n", err);
1116 err = clk_prepare_enable(pcie->bus_clk);
1118 dev_err(dev, "failed to enable bus clock: %d\n", err);
1119 goto err_unmap_msi_irqs;
1122 err = rcar_pcie_parse_map_dma_ranges(pcie, dev->of_node);
1124 goto err_clk_disable;
1126 phy_init_fn = of_device_get_match_data(dev);
1127 err = phy_init_fn(pcie);
1129 dev_err(dev, "failed to init PCIe PHY\n");
1130 goto err_clk_disable;
1133 /* Failure to get a link might just be that no cards are inserted */
1134 if (rcar_pcie_hw_init(pcie)) {
1135 dev_info(dev, "PCIe link down\n");
1137 goto err_clk_disable;
1140 data = rcar_pci_read_reg(pcie, MACSR);
1141 dev_info(dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f);
1143 if (IS_ENABLED(CONFIG_PCI_MSI)) {
1144 err = rcar_pcie_enable_msi(pcie);
1147 "failed to enable MSI support: %d\n",
1149 goto err_clk_disable;
1153 err = rcar_pcie_enable(pcie);
1155 goto err_clk_disable;
1160 clk_disable_unprepare(pcie->bus_clk);
1163 irq_dispose_mapping(pcie->msi.irq2);
1164 irq_dispose_mapping(pcie->msi.irq1);
1167 pm_runtime_put(dev);
1170 pm_runtime_disable(dev);
1171 pci_free_resource_list(&pcie->resources);
1174 pci_free_host_bridge(bridge);
1179 static struct platform_driver rcar_pcie_driver = {
1181 .name = "rcar-pcie",
1182 .of_match_table = rcar_pcie_of_match,
1183 .suppress_bind_attrs = true,
1185 .probe = rcar_pcie_probe,
1187 builtin_platform_driver(rcar_pcie_driver);