2 * probe.c - PCI detection and setup code
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
9 #include <linux/pci_hotplug.h>
10 #include <linux/slab.h>
11 #include <linux/module.h>
12 #include <linux/cpumask.h>
13 #include <linux/pci-aspm.h>
14 #include <asm-generic/pci-bridge.h>
17 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
18 #define CARDBUS_RESERVE_BUSNR 3
20 static struct resource busn_resource = {
24 .flags = IORESOURCE_BUS,
27 /* Ugh. Need to stop exporting this to modules. */
28 LIST_HEAD(pci_root_buses);
29 EXPORT_SYMBOL(pci_root_buses);
31 static LIST_HEAD(pci_domain_busn_res_list);
33 struct pci_domain_busn_res {
34 struct list_head list;
39 static struct resource *get_pci_domain_busn_res(int domain_nr)
41 struct pci_domain_busn_res *r;
43 list_for_each_entry(r, &pci_domain_busn_res_list, list)
44 if (r->domain_nr == domain_nr)
47 r = kzalloc(sizeof(*r), GFP_KERNEL);
51 r->domain_nr = domain_nr;
54 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
56 list_add_tail(&r->list, &pci_domain_busn_res_list);
61 static int find_anything(struct device *dev, void *data)
67 * Some device drivers need know if pci is initiated.
68 * Basically, we think pci is not initiated when there
69 * is no device to be found on the pci_bus_type.
71 int no_pci_devices(void)
76 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
77 no_devices = (dev == NULL);
81 EXPORT_SYMBOL(no_pci_devices);
86 static void release_pcibus_dev(struct device *dev)
88 struct pci_bus *pci_bus = to_pci_bus(dev);
91 put_device(pci_bus->bridge);
92 pci_bus_remove_resources(pci_bus);
93 pci_release_bus_of_node(pci_bus);
97 static struct class pcibus_class = {
99 .dev_release = &release_pcibus_dev,
100 .dev_groups = pcibus_groups,
103 static int __init pcibus_class_init(void)
105 return class_register(&pcibus_class);
107 postcore_initcall(pcibus_class_init);
109 static u64 pci_size(u64 base, u64 maxbase, u64 mask)
111 u64 size = mask & maxbase; /* Find the significant bits */
115 /* Get the lowest of them to find the decode size, and
116 from that the extent. */
117 size = (size & ~(size-1)) - 1;
119 /* base == maxbase can be valid only if the BAR has
120 already been programmed with all 1s. */
121 if (base == maxbase && ((base | size) & mask) != mask)
127 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
132 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
133 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
134 flags |= IORESOURCE_IO;
138 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
139 flags |= IORESOURCE_MEM;
140 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
141 flags |= IORESOURCE_PREFETCH;
143 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
145 case PCI_BASE_ADDRESS_MEM_TYPE_32:
147 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
148 /* 1M mem BAR treated as 32-bit BAR */
150 case PCI_BASE_ADDRESS_MEM_TYPE_64:
151 flags |= IORESOURCE_MEM_64;
154 /* mem unknown type treated as 32-bit BAR */
160 #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
163 * pci_read_base - read a PCI BAR
164 * @dev: the PCI device
165 * @type: type of the BAR
166 * @res: resource buffer to be filled in
167 * @pos: BAR position in the config space
169 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
171 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
172 struct resource *res, unsigned int pos)
175 u64 l64, sz64, mask64;
177 struct pci_bus_region region, inverted_region;
178 bool bar_too_big = false, bar_too_high = false, bar_invalid = false;
180 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
182 /* No printks while decoding is disabled! */
183 if (!dev->mmio_always_on) {
184 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
185 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
186 pci_write_config_word(dev, PCI_COMMAND,
187 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
191 res->name = pci_name(dev);
193 pci_read_config_dword(dev, pos, &l);
194 pci_write_config_dword(dev, pos, l | mask);
195 pci_read_config_dword(dev, pos, &sz);
196 pci_write_config_dword(dev, pos, l);
199 * All bits set in sz means the device isn't working properly.
200 * If the BAR isn't implemented, all bits must be 0. If it's a
201 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
204 if (!sz || sz == 0xffffffff)
208 * I don't know how l can have all bits set. Copied from old code.
209 * Maybe it fixes a bug on some ancient platform.
214 if (type == pci_bar_unknown) {
215 res->flags = decode_bar(dev, l);
216 res->flags |= IORESOURCE_SIZEALIGN;
217 if (res->flags & IORESOURCE_IO) {
218 l &= PCI_BASE_ADDRESS_IO_MASK;
219 mask = PCI_BASE_ADDRESS_IO_MASK & (u32) IO_SPACE_LIMIT;
221 l &= PCI_BASE_ADDRESS_MEM_MASK;
222 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
225 res->flags |= (l & IORESOURCE_ROM_ENABLE);
226 l &= PCI_ROM_ADDRESS_MASK;
227 mask = (u32)PCI_ROM_ADDRESS_MASK;
230 if (res->flags & IORESOURCE_MEM_64) {
233 mask64 = mask | (u64)~0 << 32;
235 pci_read_config_dword(dev, pos + 4, &l);
236 pci_write_config_dword(dev, pos + 4, ~0);
237 pci_read_config_dword(dev, pos + 4, &sz);
238 pci_write_config_dword(dev, pos + 4, l);
240 l64 |= ((u64)l << 32);
241 sz64 |= ((u64)sz << 32);
243 sz64 = pci_size(l64, sz64, mask64);
248 if ((sizeof(dma_addr_t) < 8 || sizeof(resource_size_t) < 8) &&
249 sz64 > 0x100000000ULL) {
250 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
257 if ((sizeof(dma_addr_t) < 8) && l) {
258 /* Above 32-bit boundary; try to reallocate */
259 res->flags |= IORESOURCE_UNSET;
266 region.end = l64 + sz64;
269 sz = pci_size(l, sz, mask);
278 pcibios_bus_to_resource(dev->bus, res, ®ion);
279 pcibios_resource_to_bus(dev->bus, &inverted_region, res);
282 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
283 * the corresponding resource address (the physical address used by
284 * the CPU. Converting that resource address back to a bus address
285 * should yield the original BAR value:
287 * resource_to_bus(bus_to_resource(A)) == A
289 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
290 * be claimed by the device.
292 if (inverted_region.start != region.start) {
293 res->flags |= IORESOURCE_UNSET;
295 res->end = region.end - region.start;
305 if (!dev->mmio_always_on &&
306 (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
307 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
310 dev_err(&dev->dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
311 pos, (unsigned long long) sz64);
313 dev_info(&dev->dev, "reg 0x%x: can't handle BAR above 4G (bus address %#010llx)\n",
314 pos, (unsigned long long) l64);
316 dev_info(&dev->dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
317 pos, (unsigned long long) region.start);
319 dev_printk(KERN_DEBUG, &dev->dev, "reg 0x%x: %pR\n", pos, res);
321 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
324 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
326 unsigned int pos, reg;
328 for (pos = 0; pos < howmany; pos++) {
329 struct resource *res = &dev->resource[pos];
330 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
331 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
335 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
336 dev->rom_base_reg = rom;
337 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
338 IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
339 IORESOURCE_SIZEALIGN;
340 __pci_read_base(dev, pci_bar_mem32, res, rom);
344 static void pci_read_bridge_io(struct pci_bus *child)
346 struct pci_dev *dev = child->self;
347 u8 io_base_lo, io_limit_lo;
348 unsigned long io_mask, io_granularity, base, limit;
349 struct pci_bus_region region;
350 struct resource *res;
352 io_mask = PCI_IO_RANGE_MASK;
353 io_granularity = 0x1000;
354 if (dev->io_window_1k) {
355 /* Support 1K I/O space granularity */
356 io_mask = PCI_IO_1K_RANGE_MASK;
357 io_granularity = 0x400;
360 res = child->resource[0];
361 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
362 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
363 base = (io_base_lo & io_mask) << 8;
364 limit = (io_limit_lo & io_mask) << 8;
366 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
367 u16 io_base_hi, io_limit_hi;
369 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
370 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
371 base |= ((unsigned long) io_base_hi << 16);
372 limit |= ((unsigned long) io_limit_hi << 16);
376 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
378 region.end = limit + io_granularity - 1;
379 pcibios_bus_to_resource(dev->bus, res, ®ion);
380 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
384 static void pci_read_bridge_mmio(struct pci_bus *child)
386 struct pci_dev *dev = child->self;
387 u16 mem_base_lo, mem_limit_lo;
388 unsigned long base, limit;
389 struct pci_bus_region region;
390 struct resource *res;
392 res = child->resource[1];
393 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
394 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
395 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
396 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
398 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
400 region.end = limit + 0xfffff;
401 pcibios_bus_to_resource(dev->bus, res, ®ion);
402 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
406 static void pci_read_bridge_mmio_pref(struct pci_bus *child)
408 struct pci_dev *dev = child->self;
409 u16 mem_base_lo, mem_limit_lo;
410 unsigned long base, limit;
411 struct pci_bus_region region;
412 struct resource *res;
414 res = child->resource[2];
415 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
416 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
417 base = ((unsigned long) mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
418 limit = ((unsigned long) mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
420 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
421 u32 mem_base_hi, mem_limit_hi;
423 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
424 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
427 * Some bridges set the base > limit by default, and some
428 * (broken) BIOSes do not initialize them. If we find
429 * this, just assume they are not being used.
431 if (mem_base_hi <= mem_limit_hi) {
432 #if BITS_PER_LONG == 64
433 base |= ((unsigned long) mem_base_hi) << 32;
434 limit |= ((unsigned long) mem_limit_hi) << 32;
436 if (mem_base_hi || mem_limit_hi) {
437 dev_err(&dev->dev, "can't handle 64-bit address space for bridge\n");
444 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
445 IORESOURCE_MEM | IORESOURCE_PREFETCH;
446 if (res->flags & PCI_PREF_RANGE_TYPE_64)
447 res->flags |= IORESOURCE_MEM_64;
449 region.end = limit + 0xfffff;
450 pcibios_bus_to_resource(dev->bus, res, ®ion);
451 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
455 void pci_read_bridge_bases(struct pci_bus *child)
457 struct pci_dev *dev = child->self;
458 struct resource *res;
461 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
464 dev_info(&dev->dev, "PCI bridge to %pR%s\n",
466 dev->transparent ? " (subtractive decode)" : "");
468 pci_bus_remove_resources(child);
469 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
470 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
472 pci_read_bridge_io(child);
473 pci_read_bridge_mmio(child);
474 pci_read_bridge_mmio_pref(child);
476 if (dev->transparent) {
477 pci_bus_for_each_resource(child->parent, res, i) {
478 if (res && res->flags) {
479 pci_bus_add_resource(child, res,
480 PCI_SUBTRACTIVE_DECODE);
481 dev_printk(KERN_DEBUG, &dev->dev,
482 " bridge window %pR (subtractive decode)\n",
489 static struct pci_bus *pci_alloc_bus(void)
493 b = kzalloc(sizeof(*b), GFP_KERNEL);
497 INIT_LIST_HEAD(&b->node);
498 INIT_LIST_HEAD(&b->children);
499 INIT_LIST_HEAD(&b->devices);
500 INIT_LIST_HEAD(&b->slots);
501 INIT_LIST_HEAD(&b->resources);
502 b->max_bus_speed = PCI_SPEED_UNKNOWN;
503 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
507 static void pci_release_host_bridge_dev(struct device *dev)
509 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
511 if (bridge->release_fn)
512 bridge->release_fn(bridge);
514 pci_free_resource_list(&bridge->windows);
519 static struct pci_host_bridge *pci_alloc_host_bridge(struct pci_bus *b)
521 struct pci_host_bridge *bridge;
523 bridge = kzalloc(sizeof(*bridge), GFP_KERNEL);
527 INIT_LIST_HEAD(&bridge->windows);
532 static const unsigned char pcix_bus_speed[] = {
533 PCI_SPEED_UNKNOWN, /* 0 */
534 PCI_SPEED_66MHz_PCIX, /* 1 */
535 PCI_SPEED_100MHz_PCIX, /* 2 */
536 PCI_SPEED_133MHz_PCIX, /* 3 */
537 PCI_SPEED_UNKNOWN, /* 4 */
538 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
539 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
540 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
541 PCI_SPEED_UNKNOWN, /* 8 */
542 PCI_SPEED_66MHz_PCIX_266, /* 9 */
543 PCI_SPEED_100MHz_PCIX_266, /* A */
544 PCI_SPEED_133MHz_PCIX_266, /* B */
545 PCI_SPEED_UNKNOWN, /* C */
546 PCI_SPEED_66MHz_PCIX_533, /* D */
547 PCI_SPEED_100MHz_PCIX_533, /* E */
548 PCI_SPEED_133MHz_PCIX_533 /* F */
551 const unsigned char pcie_link_speed[] = {
552 PCI_SPEED_UNKNOWN, /* 0 */
553 PCIE_SPEED_2_5GT, /* 1 */
554 PCIE_SPEED_5_0GT, /* 2 */
555 PCIE_SPEED_8_0GT, /* 3 */
556 PCI_SPEED_UNKNOWN, /* 4 */
557 PCI_SPEED_UNKNOWN, /* 5 */
558 PCI_SPEED_UNKNOWN, /* 6 */
559 PCI_SPEED_UNKNOWN, /* 7 */
560 PCI_SPEED_UNKNOWN, /* 8 */
561 PCI_SPEED_UNKNOWN, /* 9 */
562 PCI_SPEED_UNKNOWN, /* A */
563 PCI_SPEED_UNKNOWN, /* B */
564 PCI_SPEED_UNKNOWN, /* C */
565 PCI_SPEED_UNKNOWN, /* D */
566 PCI_SPEED_UNKNOWN, /* E */
567 PCI_SPEED_UNKNOWN /* F */
570 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
572 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
574 EXPORT_SYMBOL_GPL(pcie_update_link_speed);
576 static unsigned char agp_speeds[] = {
584 static enum pci_bus_speed agp_speed(int agp3, int agpstat)
590 else if (agpstat & 2)
592 else if (agpstat & 1)
604 return agp_speeds[index];
607 static void pci_set_bus_speed(struct pci_bus *bus)
609 struct pci_dev *bridge = bus->self;
612 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
614 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
618 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
619 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
621 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
622 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
625 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
628 enum pci_bus_speed max;
630 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
633 if (status & PCI_X_SSTATUS_533MHZ) {
634 max = PCI_SPEED_133MHz_PCIX_533;
635 } else if (status & PCI_X_SSTATUS_266MHZ) {
636 max = PCI_SPEED_133MHz_PCIX_266;
637 } else if (status & PCI_X_SSTATUS_133MHZ) {
638 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2)
639 max = PCI_SPEED_133MHz_PCIX_ECC;
641 max = PCI_SPEED_133MHz_PCIX;
643 max = PCI_SPEED_66MHz_PCIX;
646 bus->max_bus_speed = max;
647 bus->cur_bus_speed = pcix_bus_speed[
648 (status & PCI_X_SSTATUS_FREQ) >> 6];
653 if (pci_is_pcie(bridge)) {
657 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
658 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
660 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
661 pcie_update_link_speed(bus, linksta);
665 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
666 struct pci_dev *bridge, int busnr)
668 struct pci_bus *child;
673 * Allocate a new bus, and inherit stuff from the parent..
675 child = pci_alloc_bus();
679 child->parent = parent;
680 child->ops = parent->ops;
681 child->msi = parent->msi;
682 child->sysdata = parent->sysdata;
683 child->bus_flags = parent->bus_flags;
685 /* initialize some portions of the bus device, but don't register it
686 * now as the parent is not properly set up yet.
688 child->dev.class = &pcibus_class;
689 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
692 * Set up the primary, secondary and subordinate
695 child->number = child->busn_res.start = busnr;
696 child->primary = parent->busn_res.start;
697 child->busn_res.end = 0xff;
700 child->dev.parent = parent->bridge;
704 child->self = bridge;
705 child->bridge = get_device(&bridge->dev);
706 child->dev.parent = child->bridge;
707 pci_set_bus_of_node(child);
708 pci_set_bus_speed(child);
710 /* Set up default resource pointers and names.. */
711 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
712 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
713 child->resource[i]->name = child->name;
715 bridge->subordinate = child;
718 ret = device_register(&child->dev);
721 pcibios_add_bus(child);
723 /* Create legacy_io and legacy_mem files for this bus */
724 pci_create_legacy_files(child);
729 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
732 struct pci_bus *child;
734 child = pci_alloc_child_bus(parent, dev, busnr);
736 down_write(&pci_bus_sem);
737 list_add_tail(&child->node, &parent->children);
738 up_write(&pci_bus_sem);
742 EXPORT_SYMBOL(pci_add_new_bus);
745 * If it's a bridge, configure it and scan the bus behind it.
746 * For CardBus bridges, we don't scan behind as the devices will
747 * be handled by the bridge driver itself.
749 * We need to process bridges in two passes -- first we scan those
750 * already configured by the BIOS and after we are done with all of
751 * them, we proceed to assigning numbers to the remaining buses in
752 * order to avoid overlaps between old and new bus numbers.
754 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
756 struct pci_bus *child;
757 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
760 u8 primary, secondary, subordinate;
763 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
764 primary = buses & 0xFF;
765 secondary = (buses >> 8) & 0xFF;
766 subordinate = (buses >> 16) & 0xFF;
768 dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
769 secondary, subordinate, pass);
771 if (!primary && (primary != bus->number) && secondary && subordinate) {
772 dev_warn(&dev->dev, "Primary bus is hard wired to 0\n");
773 primary = bus->number;
776 /* Check if setup is sensible at all */
778 (primary != bus->number || secondary <= bus->number ||
779 secondary > subordinate || subordinate > bus->busn_res.end)) {
780 dev_info(&dev->dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
781 secondary, subordinate);
785 /* Disable MasterAbortMode during probing to avoid reporting
786 of bus errors (in some architectures) */
787 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
788 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
789 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
791 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
792 !is_cardbus && !broken) {
795 * Bus already configured by firmware, process it in the first
796 * pass and just note the configuration.
802 * The bus might already exist for two reasons: Either we are
803 * rescanning the bus or the bus is reachable through more than
804 * one bridge. The second case can happen with the i450NX
807 child = pci_find_bus(pci_domain_nr(bus), secondary);
809 child = pci_add_new_bus(bus, dev, secondary);
812 child->primary = primary;
813 pci_bus_insert_busn_res(child, secondary, subordinate);
814 child->bridge_ctl = bctl;
817 cmax = pci_scan_child_bus(child);
818 if (cmax > subordinate)
819 dev_warn(&dev->dev, "bridge has subordinate %02x but max busn %02x\n",
821 /* subordinate should equal child->busn_res.end */
822 if (subordinate > max)
826 * We need to assign a number to this bus which we always
827 * do in the second pass.
830 if (pcibios_assign_all_busses() || broken || is_cardbus)
831 /* Temporarily disable forwarding of the
832 configuration cycles on all bridges in
833 this bus segment to avoid possible
834 conflicts in the second pass between two
835 bridges programmed with overlapping
837 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
842 if (max >= bus->busn_res.end) {
843 dev_warn(&dev->dev, "can't allocate child bus %02x from %pR\n",
844 max, &bus->busn_res);
849 pci_write_config_word(dev, PCI_STATUS, 0xffff);
851 /* The bus will already exist if we are rescanning */
852 child = pci_find_bus(pci_domain_nr(bus), max+1);
854 child = pci_add_new_bus(bus, dev, max+1);
857 pci_bus_insert_busn_res(child, max+1,
861 buses = (buses & 0xff000000)
862 | ((unsigned int)(child->primary) << 0)
863 | ((unsigned int)(child->busn_res.start) << 8)
864 | ((unsigned int)(child->busn_res.end) << 16);
867 * yenta.c forces a secondary latency timer of 176.
868 * Copy that behaviour here.
871 buses &= ~0xff000000;
872 buses |= CARDBUS_LATENCY_TIMER << 24;
876 * We need to blast all three values with a single write.
878 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
881 child->bridge_ctl = bctl;
882 max = pci_scan_child_bus(child);
885 * For CardBus bridges, we leave 4 bus numbers
886 * as cards with a PCI-to-PCI bridge can be
889 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
890 struct pci_bus *parent = bus;
891 if (pci_find_bus(pci_domain_nr(bus),
894 while (parent->parent) {
895 if ((!pcibios_assign_all_busses()) &&
896 (parent->busn_res.end > max) &&
897 (parent->busn_res.end <= max+i)) {
900 parent = parent->parent;
904 * Often, there are two cardbus bridges
905 * -- try to leave one valid bus number
915 * Set the subordinate bus number to its real value.
917 if (max > bus->busn_res.end) {
918 dev_warn(&dev->dev, "max busn %02x is outside %pR\n",
919 max, &bus->busn_res);
920 max = bus->busn_res.end;
922 pci_bus_update_busn_res_end(child, max);
923 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
927 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
928 pci_domain_nr(bus), child->number);
930 /* Has only triggered on CardBus, fixup is in yenta_socket */
931 while (bus->parent) {
932 if ((child->busn_res.end > bus->busn_res.end) ||
933 (child->number > bus->busn_res.end) ||
934 (child->number < bus->number) ||
935 (child->busn_res.end < bus->number)) {
936 dev_info(&child->dev, "%pR %s hidden behind%s bridge %s %pR\n",
938 (bus->number > child->busn_res.end &&
939 bus->busn_res.end < child->number) ?
940 "wholly" : "partially",
941 bus->self->transparent ? " transparent" : "",
949 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
953 EXPORT_SYMBOL(pci_scan_bridge);
956 * Read interrupt line and base address registers.
957 * The architecture-dependent code can tweak these, of course.
959 static void pci_read_irq(struct pci_dev *dev)
963 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
966 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
970 void set_pcie_port_type(struct pci_dev *pdev)
975 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
978 pdev->pcie_cap = pos;
979 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
980 pdev->pcie_flags_reg = reg16;
981 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
982 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
985 void set_pcie_hotplug_bridge(struct pci_dev *pdev)
989 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32);
990 if (reg32 & PCI_EXP_SLTCAP_HPC)
991 pdev->is_hotplug_bridge = 1;
995 * pci_ext_cfg_is_aliased - is ext config space just an alias of std config?
998 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
999 * when forwarding a type1 configuration request the bridge must check that
1000 * the extended register address field is zero. The bridge is not permitted
1001 * to forward the transactions and must handle it as an Unsupported Request.
1002 * Some bridges do not follow this rule and simply drop the extended register
1003 * bits, resulting in the standard config space being aliased, every 256
1004 * bytes across the entire configuration space. Test for this condition by
1005 * comparing the first dword of each potential alias to the vendor/device ID.
1007 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1008 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1010 static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
1012 #ifdef CONFIG_PCI_QUIRKS
1016 pci_read_config_dword(dev, PCI_VENDOR_ID, &header);
1018 for (pos = PCI_CFG_SPACE_SIZE;
1019 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
1020 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL
1032 * pci_cfg_space_size - get the configuration space size of the PCI device.
1035 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1036 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1037 * access it. Maybe we don't have a way to generate extended config space
1038 * accesses, or the device is behind a reverse Express bridge. So we try
1039 * reading the dword at 0x100 which must either be 0 or a valid extended
1040 * capability header.
1042 static int pci_cfg_space_size_ext(struct pci_dev *dev)
1045 int pos = PCI_CFG_SPACE_SIZE;
1047 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1049 if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
1052 return PCI_CFG_SPACE_EXP_SIZE;
1055 return PCI_CFG_SPACE_SIZE;
1058 int pci_cfg_space_size(struct pci_dev *dev)
1064 class = dev->class >> 8;
1065 if (class == PCI_CLASS_BRIDGE_HOST)
1066 return pci_cfg_space_size_ext(dev);
1068 if (!pci_is_pcie(dev)) {
1069 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1073 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1074 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
1078 return pci_cfg_space_size_ext(dev);
1081 return PCI_CFG_SPACE_SIZE;
1084 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1087 * pci_setup_device - fill in class and map information of a device
1088 * @dev: the device structure to fill
1090 * Initialize the device structure with information about the device's
1091 * vendor,class,memory and IO-space addresses,IRQ lines etc.
1092 * Called at initialisation of the PCI subsystem and by CardBus services.
1093 * Returns 0 on success and negative if unknown type of device (not normal,
1094 * bridge or CardBus).
1096 int pci_setup_device(struct pci_dev *dev)
1100 struct pci_slot *slot;
1102 struct pci_bus_region region;
1103 struct resource *res;
1105 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
1108 dev->sysdata = dev->bus->sysdata;
1109 dev->dev.parent = dev->bus->bridge;
1110 dev->dev.bus = &pci_bus_type;
1111 dev->hdr_type = hdr_type & 0x7f;
1112 dev->multifunction = !!(hdr_type & 0x80);
1113 dev->error_state = pci_channel_io_normal;
1114 set_pcie_port_type(dev);
1116 list_for_each_entry(slot, &dev->bus->slots, list)
1117 if (PCI_SLOT(dev->devfn) == slot->number)
1120 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1121 set this higher, assuming the system even supports it. */
1122 dev->dma_mask = 0xffffffff;
1124 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1125 dev->bus->number, PCI_SLOT(dev->devfn),
1126 PCI_FUNC(dev->devfn));
1128 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
1129 dev->revision = class & 0xff;
1130 dev->class = class >> 8; /* upper 3 bytes */
1132 dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %02x class %#08x\n",
1133 dev->vendor, dev->device, dev->hdr_type, dev->class);
1135 /* need to have dev->class ready */
1136 dev->cfg_size = pci_cfg_space_size(dev);
1138 /* "Unknown power state" */
1139 dev->current_state = PCI_UNKNOWN;
1141 /* Early fixups, before probing the BARs */
1142 pci_fixup_device(pci_fixup_early, dev);
1143 /* device class may be changed after fixup */
1144 class = dev->class >> 8;
1146 switch (dev->hdr_type) { /* header type */
1147 case PCI_HEADER_TYPE_NORMAL: /* standard header */
1148 if (class == PCI_CLASS_BRIDGE_PCI)
1151 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1152 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1153 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
1156 * Do the ugly legacy mode stuff here rather than broken chip
1157 * quirk code. Legacy mode ATA controllers have fixed
1158 * addresses. These are not always echoed in BAR0-3, and
1159 * BAR0-3 in a few cases contain junk!
1161 if (class == PCI_CLASS_STORAGE_IDE) {
1163 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1164 if ((progif & 1) == 0) {
1165 region.start = 0x1F0;
1167 res = &dev->resource[0];
1168 res->flags = LEGACY_IO_RESOURCE;
1169 pcibios_bus_to_resource(dev->bus, res, ®ion);
1170 dev_info(&dev->dev, "legacy IDE quirk: reg 0x10: %pR\n",
1172 region.start = 0x3F6;
1174 res = &dev->resource[1];
1175 res->flags = LEGACY_IO_RESOURCE;
1176 pcibios_bus_to_resource(dev->bus, res, ®ion);
1177 dev_info(&dev->dev, "legacy IDE quirk: reg 0x14: %pR\n",
1180 if ((progif & 4) == 0) {
1181 region.start = 0x170;
1183 res = &dev->resource[2];
1184 res->flags = LEGACY_IO_RESOURCE;
1185 pcibios_bus_to_resource(dev->bus, res, ®ion);
1186 dev_info(&dev->dev, "legacy IDE quirk: reg 0x18: %pR\n",
1188 region.start = 0x376;
1190 res = &dev->resource[3];
1191 res->flags = LEGACY_IO_RESOURCE;
1192 pcibios_bus_to_resource(dev->bus, res, ®ion);
1193 dev_info(&dev->dev, "legacy IDE quirk: reg 0x1c: %pR\n",
1199 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1200 if (class != PCI_CLASS_BRIDGE_PCI)
1202 /* The PCI-to-PCI bridge spec requires that subtractive
1203 decoding (i.e. transparent) bridge must have programming
1204 interface code of 0x01. */
1206 dev->transparent = ((dev->class & 0xff) == 1);
1207 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1208 set_pcie_hotplug_bridge(dev);
1209 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1211 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1212 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1216 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1217 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1220 pci_read_bases(dev, 1, 0);
1221 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1222 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1225 default: /* unknown header */
1226 dev_err(&dev->dev, "unknown header type %02x, ignoring device\n",
1231 dev_err(&dev->dev, "ignoring class %#08x (doesn't match header type %02x)\n",
1232 dev->class, dev->hdr_type);
1233 dev->class = PCI_CLASS_NOT_DEFINED;
1236 /* We found a fine healthy device, go go go... */
1240 static struct hpp_type0 pci_default_type0 = {
1242 .cache_line_size = 8,
1243 .latency_timer = 0x40,
1248 static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp)
1250 u16 pci_cmd, pci_bctl;
1253 hpp = &pci_default_type0;
1255 if (hpp->revision > 1) {
1257 "PCI settings rev %d not supported; using defaults\n",
1259 hpp = &pci_default_type0;
1262 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size);
1263 pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp->latency_timer);
1264 pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
1265 if (hpp->enable_serr)
1266 pci_cmd |= PCI_COMMAND_SERR;
1267 if (hpp->enable_perr)
1268 pci_cmd |= PCI_COMMAND_PARITY;
1269 pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
1271 /* Program bridge control value */
1272 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1273 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER,
1274 hpp->latency_timer);
1275 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl);
1276 if (hpp->enable_serr)
1277 pci_bctl |= PCI_BRIDGE_CTL_SERR;
1278 if (hpp->enable_perr)
1279 pci_bctl |= PCI_BRIDGE_CTL_PARITY;
1280 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl);
1284 static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp)
1287 dev_warn(&dev->dev, "PCI-X settings not supported\n");
1290 static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
1298 if (hpp->revision > 1) {
1299 dev_warn(&dev->dev, "PCIe settings rev %d not supported\n",
1305 * Don't allow _HPX to change MPS or MRRS settings. We manage
1306 * those to make sure they're consistent with the rest of the
1309 hpp->pci_exp_devctl_and |= PCI_EXP_DEVCTL_PAYLOAD |
1310 PCI_EXP_DEVCTL_READRQ;
1311 hpp->pci_exp_devctl_or &= ~(PCI_EXP_DEVCTL_PAYLOAD |
1312 PCI_EXP_DEVCTL_READRQ);
1314 /* Initialize Device Control Register */
1315 pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
1316 ~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or);
1318 /* Initialize Link Control Register */
1319 if (dev->subordinate)
1320 pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL,
1321 ~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or);
1323 /* Find Advanced Error Reporting Enhanced Capability */
1324 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
1328 /* Initialize Uncorrectable Error Mask Register */
1329 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, ®32);
1330 reg32 = (reg32 & hpp->unc_err_mask_and) | hpp->unc_err_mask_or;
1331 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32);
1333 /* Initialize Uncorrectable Error Severity Register */
1334 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, ®32);
1335 reg32 = (reg32 & hpp->unc_err_sever_and) | hpp->unc_err_sever_or;
1336 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32);
1338 /* Initialize Correctable Error Mask Register */
1339 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®32);
1340 reg32 = (reg32 & hpp->cor_err_mask_and) | hpp->cor_err_mask_or;
1341 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32);
1343 /* Initialize Advanced Error Capabilities and Control Register */
1344 pci_read_config_dword(dev, pos + PCI_ERR_CAP, ®32);
1345 reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or;
1346 pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32);
1349 * FIXME: The following two registers are not supported yet.
1351 * o Secondary Uncorrectable Error Severity Register
1352 * o Secondary Uncorrectable Error Mask Register
1356 static void pci_configure_device(struct pci_dev *dev)
1358 struct hotplug_params hpp;
1361 if (system_state == SYSTEM_BOOTING)
1364 memset(&hpp, 0, sizeof(hpp));
1365 ret = pci_get_hp_params(dev, &hpp);
1369 program_hpp_type2(dev, hpp.t2);
1370 program_hpp_type1(dev, hpp.t1);
1371 program_hpp_type0(dev, hpp.t0);
1374 static void pci_release_capabilities(struct pci_dev *dev)
1376 pci_vpd_release(dev);
1377 pci_iov_release(dev);
1378 pci_free_cap_save_buffers(dev);
1382 * pci_release_dev - free a pci device structure when all users of it are finished.
1383 * @dev: device that's been disconnected
1385 * Will be called only by the device core when all users of this pci device are
1388 static void pci_release_dev(struct device *dev)
1390 struct pci_dev *pci_dev;
1392 pci_dev = to_pci_dev(dev);
1393 pci_release_capabilities(pci_dev);
1394 pci_release_of_node(pci_dev);
1395 pcibios_release_device(pci_dev);
1396 pci_bus_put(pci_dev->bus);
1397 kfree(pci_dev->driver_override);
1401 struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
1403 struct pci_dev *dev;
1405 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
1409 INIT_LIST_HEAD(&dev->bus_list);
1410 dev->dev.type = &pci_dev_type;
1411 dev->bus = pci_bus_get(bus);
1415 EXPORT_SYMBOL(pci_alloc_dev);
1417 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
1422 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1425 /* some broken boards return 0 or ~0 if a slot is empty: */
1426 if (*l == 0xffffffff || *l == 0x00000000 ||
1427 *l == 0x0000ffff || *l == 0xffff0000)
1430 /* Configuration request Retry Status */
1431 while (*l == 0xffff0001) {
1437 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1439 /* Card hasn't responded in 60 seconds? Must be stuck. */
1440 if (delay > crs_timeout) {
1441 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not responding\n",
1442 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
1450 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
1453 * Read the config data for a PCI device, sanity-check it
1454 * and fill in the dev structure...
1456 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
1458 struct pci_dev *dev;
1461 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
1464 dev = pci_alloc_dev(bus);
1469 dev->vendor = l & 0xffff;
1470 dev->device = (l >> 16) & 0xffff;
1472 pci_set_of_node(dev);
1474 if (pci_setup_device(dev)) {
1475 pci_bus_put(dev->bus);
1483 static void pci_init_capabilities(struct pci_dev *dev)
1485 /* MSI/MSI-X list */
1486 pci_msi_init_pci_dev(dev);
1488 /* Buffers for saving PCIe and PCI-X capabilities */
1489 pci_allocate_cap_save_buffers(dev);
1491 /* Power Management */
1494 /* Vital Product Data */
1495 pci_vpd_pci22_init(dev);
1497 /* Alternative Routing-ID Forwarding */
1498 pci_configure_ari(dev);
1500 /* Single Root I/O Virtualization */
1503 /* Enable ACS P2P upstream forwarding */
1504 pci_enable_acs(dev);
1507 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
1511 pci_configure_device(dev);
1513 device_initialize(&dev->dev);
1514 dev->dev.release = pci_release_dev;
1516 set_dev_node(&dev->dev, pcibus_to_node(bus));
1517 dev->dev.dma_mask = &dev->dma_mask;
1518 dev->dev.dma_parms = &dev->dma_parms;
1519 dev->dev.coherent_dma_mask = 0xffffffffull;
1521 pci_set_dma_max_seg_size(dev, 65536);
1522 pci_set_dma_seg_boundary(dev, 0xffffffff);
1524 /* Fix up broken headers */
1525 pci_fixup_device(pci_fixup_header, dev);
1527 /* moved out from quirk header fixup code */
1528 pci_reassigndev_resource_alignment(dev);
1530 /* Clear the state_saved flag. */
1531 dev->state_saved = false;
1533 /* Initialize various capabilities */
1534 pci_init_capabilities(dev);
1537 * Add the device to our list of discovered devices
1538 * and the bus list for fixup functions, etc.
1540 down_write(&pci_bus_sem);
1541 list_add_tail(&dev->bus_list, &bus->devices);
1542 up_write(&pci_bus_sem);
1544 ret = pcibios_add_device(dev);
1547 /* Notifier could use PCI capabilities */
1548 dev->match_driver = false;
1549 ret = device_add(&dev->dev);
1553 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
1555 struct pci_dev *dev;
1557 dev = pci_get_slot(bus, devfn);
1563 dev = pci_scan_device(bus, devfn);
1567 pci_device_add(dev, bus);
1571 EXPORT_SYMBOL(pci_scan_single_device);
1573 static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn)
1579 if (pci_ari_enabled(bus)) {
1582 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1586 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
1587 next_fn = PCI_ARI_CAP_NFN(cap);
1589 return 0; /* protect against malformed list */
1594 /* dev may be NULL for non-contiguous multifunction devices */
1595 if (!dev || dev->multifunction)
1596 return (fn + 1) % 8;
1601 static int only_one_child(struct pci_bus *bus)
1603 struct pci_dev *parent = bus->self;
1605 if (!parent || !pci_is_pcie(parent))
1607 if (pci_pcie_type(parent) == PCI_EXP_TYPE_ROOT_PORT)
1609 if (pci_pcie_type(parent) == PCI_EXP_TYPE_DOWNSTREAM &&
1610 !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
1616 * pci_scan_slot - scan a PCI slot on a bus for devices.
1617 * @bus: PCI bus to scan
1618 * @devfn: slot number to scan (must have zero function.)
1620 * Scan a PCI slot on the specified PCI bus for devices, adding
1621 * discovered devices to the @bus->devices list. New devices
1622 * will not have is_added set.
1624 * Returns the number of new devices found.
1626 int pci_scan_slot(struct pci_bus *bus, int devfn)
1628 unsigned fn, nr = 0;
1629 struct pci_dev *dev;
1631 if (only_one_child(bus) && (devfn > 0))
1632 return 0; /* Already scanned the entire slot */
1634 dev = pci_scan_single_device(bus, devfn);
1640 for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) {
1641 dev = pci_scan_single_device(bus, devfn + fn);
1645 dev->multifunction = 1;
1649 /* only one slot has pcie device */
1650 if (bus->self && nr)
1651 pcie_aspm_init_link_state(bus->self);
1655 EXPORT_SYMBOL(pci_scan_slot);
1657 static int pcie_find_smpss(struct pci_dev *dev, void *data)
1661 if (!pci_is_pcie(dev))
1665 * We don't have a way to change MPS settings on devices that have
1666 * drivers attached. A hot-added device might support only the minimum
1667 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
1668 * where devices may be hot-added, we limit the fabric MPS to 128 so
1669 * hot-added devices will work correctly.
1671 * However, if we hot-add a device to a slot directly below a Root
1672 * Port, it's impossible for there to be other existing devices below
1673 * the port. We don't limit the MPS in this case because we can
1674 * reconfigure MPS on both the Root Port and the hot-added device,
1675 * and there are no other devices involved.
1677 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
1679 if (dev->is_hotplug_bridge &&
1680 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
1683 if (*smpss > dev->pcie_mpss)
1684 *smpss = dev->pcie_mpss;
1689 static void pcie_write_mps(struct pci_dev *dev, int mps)
1693 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
1694 mps = 128 << dev->pcie_mpss;
1696 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
1698 /* For "Performance", the assumption is made that
1699 * downstream communication will never be larger than
1700 * the MRRS. So, the MPS only needs to be configured
1701 * for the upstream communication. This being the case,
1702 * walk from the top down and set the MPS of the child
1703 * to that of the parent bus.
1705 * Configure the device MPS with the smaller of the
1706 * device MPSS or the bridge MPS (which is assumed to be
1707 * properly configured at this point to the largest
1708 * allowable MPS based on its parent bus).
1710 mps = min(mps, pcie_get_mps(dev->bus->self));
1713 rc = pcie_set_mps(dev, mps);
1715 dev_err(&dev->dev, "Failed attempting to set the MPS\n");
1718 static void pcie_write_mrrs(struct pci_dev *dev)
1722 /* In the "safe" case, do not configure the MRRS. There appear to be
1723 * issues with setting MRRS to 0 on a number of devices.
1725 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
1728 /* For Max performance, the MRRS must be set to the largest supported
1729 * value. However, it cannot be configured larger than the MPS the
1730 * device or the bus can support. This should already be properly
1731 * configured by a prior call to pcie_write_mps.
1733 mrrs = pcie_get_mps(dev);
1735 /* MRRS is a R/W register. Invalid values can be written, but a
1736 * subsequent read will verify if the value is acceptable or not.
1737 * If the MRRS value provided is not acceptable (e.g., too large),
1738 * shrink the value until it is acceptable to the HW.
1740 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
1741 rc = pcie_set_readrq(dev, mrrs);
1745 dev_warn(&dev->dev, "Failed attempting to set the MRRS\n");
1750 dev_err(&dev->dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
1753 static void pcie_bus_detect_mps(struct pci_dev *dev)
1755 struct pci_dev *bridge = dev->bus->self;
1761 mps = pcie_get_mps(dev);
1762 p_mps = pcie_get_mps(bridge);
1765 dev_warn(&dev->dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1766 mps, pci_name(bridge), p_mps);
1769 static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
1773 if (!pci_is_pcie(dev))
1776 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
1777 pcie_bus_detect_mps(dev);
1781 mps = 128 << *(u8 *)data;
1782 orig_mps = pcie_get_mps(dev);
1784 pcie_write_mps(dev, mps);
1785 pcie_write_mrrs(dev);
1787 dev_info(&dev->dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
1788 pcie_get_mps(dev), 128 << dev->pcie_mpss,
1789 orig_mps, pcie_get_readrq(dev));
1794 /* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down,
1795 * parents then children fashion. If this changes, then this code will not
1798 void pcie_bus_configure_settings(struct pci_bus *bus)
1805 if (!pci_is_pcie(bus->self))
1808 /* FIXME - Peer to peer DMA is possible, though the endpoint would need
1809 * to be aware of the MPS of the destination. To work around this,
1810 * simply force the MPS of the entire system to the smallest possible.
1812 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
1815 if (pcie_bus_config == PCIE_BUS_SAFE) {
1816 smpss = bus->self->pcie_mpss;
1818 pcie_find_smpss(bus->self, &smpss);
1819 pci_walk_bus(bus, pcie_find_smpss, &smpss);
1822 pcie_bus_configure_set(bus->self, &smpss);
1823 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
1825 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
1827 unsigned int pci_scan_child_bus(struct pci_bus *bus)
1829 unsigned int devfn, pass, max = bus->busn_res.start;
1830 struct pci_dev *dev;
1832 dev_dbg(&bus->dev, "scanning bus\n");
1834 /* Go find them, Rover! */
1835 for (devfn = 0; devfn < 0x100; devfn += 8)
1836 pci_scan_slot(bus, devfn);
1838 /* Reserve buses for SR-IOV capability. */
1839 max += pci_iov_bus_range(bus);
1842 * After performing arch-dependent fixup of the bus, look behind
1843 * all PCI-to-PCI bridges on this bus.
1845 if (!bus->is_added) {
1846 dev_dbg(&bus->dev, "fixups for bus\n");
1847 pcibios_fixup_bus(bus);
1851 for (pass = 0; pass < 2; pass++)
1852 list_for_each_entry(dev, &bus->devices, bus_list) {
1853 if (pci_is_bridge(dev))
1854 max = pci_scan_bridge(bus, dev, max, pass);
1858 * We've scanned the bus and so we know all about what's on
1859 * the other side of any bridges that may be on this bus plus
1862 * Return how far we've got finding sub-buses.
1864 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
1867 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1870 * pcibios_root_bridge_prepare - Platform-specific host bridge setup.
1871 * @bridge: Host bridge to set up.
1873 * Default empty implementation. Replace with an architecture-specific setup
1874 * routine, if necessary.
1876 int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
1881 void __weak pcibios_add_bus(struct pci_bus *bus)
1885 void __weak pcibios_remove_bus(struct pci_bus *bus)
1889 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
1890 struct pci_ops *ops, void *sysdata, struct list_head *resources)
1893 struct pci_host_bridge *bridge;
1894 struct pci_bus *b, *b2;
1895 struct pci_host_bridge_window *window, *n;
1896 struct resource *res;
1897 resource_size_t offset;
1901 b = pci_alloc_bus();
1905 b->sysdata = sysdata;
1907 b->number = b->busn_res.start = bus;
1908 b2 = pci_find_bus(pci_domain_nr(b), bus);
1910 /* If we already got to this bus through a different bridge, ignore it */
1911 dev_dbg(&b2->dev, "bus already known\n");
1915 bridge = pci_alloc_host_bridge(b);
1919 bridge->dev.parent = parent;
1920 bridge->dev.release = pci_release_host_bridge_dev;
1921 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(b), bus);
1922 error = pcibios_root_bridge_prepare(bridge);
1928 error = device_register(&bridge->dev);
1930 put_device(&bridge->dev);
1933 b->bridge = get_device(&bridge->dev);
1934 device_enable_async_suspend(b->bridge);
1935 pci_set_bus_of_node(b);
1938 set_dev_node(b->bridge, pcibus_to_node(b));
1940 b->dev.class = &pcibus_class;
1941 b->dev.parent = b->bridge;
1942 dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus);
1943 error = device_register(&b->dev);
1945 goto class_dev_reg_err;
1949 /* Create legacy_io and legacy_mem files for this bus */
1950 pci_create_legacy_files(b);
1953 dev_info(parent, "PCI host bridge to bus %s\n", dev_name(&b->dev));
1955 printk(KERN_INFO "PCI host bridge to bus %s\n", dev_name(&b->dev));
1957 /* Add initial resources to the bus */
1958 list_for_each_entry_safe(window, n, resources, list) {
1959 list_move_tail(&window->list, &bridge->windows);
1961 offset = window->offset;
1962 if (res->flags & IORESOURCE_BUS)
1963 pci_bus_insert_busn_res(b, bus, res->end);
1965 pci_bus_add_resource(b, res, 0);
1967 if (resource_type(res) == IORESOURCE_IO)
1968 fmt = " (bus address [%#06llx-%#06llx])";
1970 fmt = " (bus address [%#010llx-%#010llx])";
1971 snprintf(bus_addr, sizeof(bus_addr), fmt,
1972 (unsigned long long) (res->start - offset),
1973 (unsigned long long) (res->end - offset));
1976 dev_info(&b->dev, "root bus resource %pR%s\n", res, bus_addr);
1979 down_write(&pci_bus_sem);
1980 list_add_tail(&b->node, &pci_root_buses);
1981 up_write(&pci_bus_sem);
1986 put_device(&bridge->dev);
1987 device_unregister(&bridge->dev);
1993 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
1995 struct resource *res = &b->busn_res;
1996 struct resource *parent_res, *conflict;
2000 res->flags = IORESOURCE_BUS;
2002 if (!pci_is_root_bus(b))
2003 parent_res = &b->parent->busn_res;
2005 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
2006 res->flags |= IORESOURCE_PCI_FIXED;
2009 conflict = request_resource_conflict(parent_res, res);
2012 dev_printk(KERN_DEBUG, &b->dev,
2013 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
2014 res, pci_is_root_bus(b) ? "domain " : "",
2015 parent_res, conflict->name, conflict);
2017 return conflict == NULL;
2020 int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
2022 struct resource *res = &b->busn_res;
2023 struct resource old_res = *res;
2024 resource_size_t size;
2027 if (res->start > bus_max)
2030 size = bus_max - res->start + 1;
2031 ret = adjust_resource(res, res->start, size);
2032 dev_printk(KERN_DEBUG, &b->dev,
2033 "busn_res: %pR end %s updated to %02x\n",
2034 &old_res, ret ? "can not be" : "is", bus_max);
2036 if (!ret && !res->parent)
2037 pci_bus_insert_busn_res(b, res->start, res->end);
2042 void pci_bus_release_busn_res(struct pci_bus *b)
2044 struct resource *res = &b->busn_res;
2047 if (!res->flags || !res->parent)
2050 ret = release_resource(res);
2051 dev_printk(KERN_DEBUG, &b->dev,
2052 "busn_res: %pR %s released\n",
2053 res, ret ? "can not be" : "is");
2056 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
2057 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2059 struct pci_host_bridge_window *window;
2064 list_for_each_entry(window, resources, list)
2065 if (window->res->flags & IORESOURCE_BUS) {
2070 b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
2076 "No busn resource found for root bus, will use [bus %02x-ff]\n",
2078 pci_bus_insert_busn_res(b, bus, 255);
2081 max = pci_scan_child_bus(b);
2084 pci_bus_update_busn_res_end(b, max);
2086 pci_bus_add_devices(b);
2089 EXPORT_SYMBOL(pci_scan_root_bus);
2091 /* Deprecated; use pci_scan_root_bus() instead */
2092 struct pci_bus *pci_scan_bus_parented(struct device *parent,
2093 int bus, struct pci_ops *ops, void *sysdata)
2095 LIST_HEAD(resources);
2098 pci_add_resource(&resources, &ioport_resource);
2099 pci_add_resource(&resources, &iomem_resource);
2100 pci_add_resource(&resources, &busn_resource);
2101 b = pci_create_root_bus(parent, bus, ops, sysdata, &resources);
2103 pci_scan_child_bus(b);
2105 pci_free_resource_list(&resources);
2108 EXPORT_SYMBOL(pci_scan_bus_parented);
2110 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
2113 LIST_HEAD(resources);
2116 pci_add_resource(&resources, &ioport_resource);
2117 pci_add_resource(&resources, &iomem_resource);
2118 pci_add_resource(&resources, &busn_resource);
2119 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
2121 pci_scan_child_bus(b);
2122 pci_bus_add_devices(b);
2124 pci_free_resource_list(&resources);
2128 EXPORT_SYMBOL(pci_scan_bus);
2131 * pci_rescan_bus_bridge_resize - scan a PCI bus for devices.
2132 * @bridge: PCI bridge for the bus to scan
2134 * Scan a PCI bus and child buses for new devices, add them,
2135 * and enable them, resizing bridge mmio/io resource if necessary
2136 * and possible. The caller must ensure the child devices are already
2137 * removed for resizing to occur.
2139 * Returns the max number of subordinate bus discovered.
2141 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
2144 struct pci_bus *bus = bridge->subordinate;
2146 max = pci_scan_child_bus(bus);
2148 pci_assign_unassigned_bridge_resources(bridge);
2150 pci_bus_add_devices(bus);
2156 * pci_rescan_bus - scan a PCI bus for devices.
2157 * @bus: PCI bus to scan
2159 * Scan a PCI bus and child buses for new devices, adds them,
2162 * Returns the max number of subordinate bus discovered.
2164 unsigned int pci_rescan_bus(struct pci_bus *bus)
2168 max = pci_scan_child_bus(bus);
2169 pci_assign_unassigned_bus_resources(bus);
2170 pci_bus_add_devices(bus);
2174 EXPORT_SYMBOL_GPL(pci_rescan_bus);
2177 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
2178 * routines should always be executed under this mutex.
2180 static DEFINE_MUTEX(pci_rescan_remove_lock);
2182 void pci_lock_rescan_remove(void)
2184 mutex_lock(&pci_rescan_remove_lock);
2186 EXPORT_SYMBOL_GPL(pci_lock_rescan_remove);
2188 void pci_unlock_rescan_remove(void)
2190 mutex_unlock(&pci_rescan_remove_lock);
2192 EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove);
2194 static int __init pci_sort_bf_cmp(const struct device *d_a,
2195 const struct device *d_b)
2197 const struct pci_dev *a = to_pci_dev(d_a);
2198 const struct pci_dev *b = to_pci_dev(d_b);
2200 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
2201 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
2203 if (a->bus->number < b->bus->number) return -1;
2204 else if (a->bus->number > b->bus->number) return 1;
2206 if (a->devfn < b->devfn) return -1;
2207 else if (a->devfn > b->devfn) return 1;
2212 void __init pci_sort_breadthfirst(void)
2214 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);