1 // SPDX-License-Identifier: GPL-2.0-only
3 * Perf support for the Statistical Profiling Extension, introduced as
6 * Copyright (C) 2016 ARM Limited
8 * Author: Will Deacon <will.deacon@arm.com>
11 #define PMUNAME "arm_spe"
12 #define DRVNAME PMUNAME "_pmu"
13 #define pr_fmt(fmt) DRVNAME ": " fmt
15 #include <linux/bitops.h>
16 #include <linux/bug.h>
17 #include <linux/capability.h>
18 #include <linux/cpuhotplug.h>
19 #include <linux/cpumask.h>
20 #include <linux/device.h>
21 #include <linux/errno.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
24 #include <linux/kernel.h>
25 #include <linux/list.h>
26 #include <linux/module.h>
27 #include <linux/of_address.h>
28 #include <linux/of_device.h>
29 #include <linux/perf_event.h>
30 #include <linux/perf/arm_pmu.h>
31 #include <linux/platform_device.h>
32 #include <linux/printk.h>
33 #include <linux/slab.h>
34 #include <linux/smp.h>
35 #include <linux/vmalloc.h>
37 #include <asm/barrier.h>
38 #include <asm/cpufeature.h>
40 #include <asm/sysreg.h>
42 #define ARM_SPE_BUF_PAD_BYTE 0
44 struct arm_spe_pmu_buf {
52 struct platform_device *pdev;
53 cpumask_t supported_cpus;
54 struct hlist_node hotplug_node;
61 #define SPE_PMU_FEAT_FILT_EVT (1UL << 0)
62 #define SPE_PMU_FEAT_FILT_TYP (1UL << 1)
63 #define SPE_PMU_FEAT_FILT_LAT (1UL << 2)
64 #define SPE_PMU_FEAT_ARCH_INST (1UL << 3)
65 #define SPE_PMU_FEAT_LDS (1UL << 4)
66 #define SPE_PMU_FEAT_ERND (1UL << 5)
67 #define SPE_PMU_FEAT_DEV_PROBED (1UL << 63)
72 struct perf_output_handle __percpu *handle;
75 #define to_spe_pmu(p) (container_of(p, struct arm_spe_pmu, pmu))
77 /* Convert a free-running index from perf into an SPE buffer offset */
78 #define PERF_IDX2OFF(idx, buf) ((idx) % ((buf)->nr_pages << PAGE_SHIFT))
80 /* Keep track of our dynamic hotplug state */
81 static enum cpuhp_state arm_spe_pmu_online;
83 enum arm_spe_pmu_buf_fault_action {
84 SPE_PMU_BUF_FAULT_ACT_SPURIOUS,
85 SPE_PMU_BUF_FAULT_ACT_FATAL,
86 SPE_PMU_BUF_FAULT_ACT_OK,
89 /* This sysfs gunk was really good fun to write. */
90 enum arm_spe_pmu_capabilities {
91 SPE_PMU_CAP_ARCH_INST = 0,
94 SPE_PMU_CAP_CNT_SZ = SPE_PMU_CAP_FEAT_MAX,
98 static int arm_spe_pmu_feat_caps[SPE_PMU_CAP_FEAT_MAX] = {
99 [SPE_PMU_CAP_ARCH_INST] = SPE_PMU_FEAT_ARCH_INST,
100 [SPE_PMU_CAP_ERND] = SPE_PMU_FEAT_ERND,
103 static u32 arm_spe_pmu_cap_get(struct arm_spe_pmu *spe_pmu, int cap)
105 if (cap < SPE_PMU_CAP_FEAT_MAX)
106 return !!(spe_pmu->features & arm_spe_pmu_feat_caps[cap]);
109 case SPE_PMU_CAP_CNT_SZ:
110 return spe_pmu->counter_sz;
111 case SPE_PMU_CAP_MIN_IVAL:
112 return spe_pmu->min_period;
114 WARN(1, "unknown cap %d\n", cap);
120 static ssize_t arm_spe_pmu_cap_show(struct device *dev,
121 struct device_attribute *attr,
124 struct arm_spe_pmu *spe_pmu = dev_get_drvdata(dev);
125 struct dev_ext_attribute *ea =
126 container_of(attr, struct dev_ext_attribute, attr);
127 int cap = (long)ea->var;
129 return sysfs_emit(buf, "%u\n", arm_spe_pmu_cap_get(spe_pmu, cap));
132 #define SPE_EXT_ATTR_ENTRY(_name, _func, _var) \
133 &((struct dev_ext_attribute[]) { \
134 { __ATTR(_name, S_IRUGO, _func, NULL), (void *)_var } \
137 #define SPE_CAP_EXT_ATTR_ENTRY(_name, _var) \
138 SPE_EXT_ATTR_ENTRY(_name, arm_spe_pmu_cap_show, _var)
140 static struct attribute *arm_spe_pmu_cap_attr[] = {
141 SPE_CAP_EXT_ATTR_ENTRY(arch_inst, SPE_PMU_CAP_ARCH_INST),
142 SPE_CAP_EXT_ATTR_ENTRY(ernd, SPE_PMU_CAP_ERND),
143 SPE_CAP_EXT_ATTR_ENTRY(count_size, SPE_PMU_CAP_CNT_SZ),
144 SPE_CAP_EXT_ATTR_ENTRY(min_interval, SPE_PMU_CAP_MIN_IVAL),
148 static const struct attribute_group arm_spe_pmu_cap_group = {
150 .attrs = arm_spe_pmu_cap_attr,
154 #define ATTR_CFG_FLD_ts_enable_CFG config /* PMSCR_EL1.TS */
155 #define ATTR_CFG_FLD_ts_enable_LO 0
156 #define ATTR_CFG_FLD_ts_enable_HI 0
157 #define ATTR_CFG_FLD_pa_enable_CFG config /* PMSCR_EL1.PA */
158 #define ATTR_CFG_FLD_pa_enable_LO 1
159 #define ATTR_CFG_FLD_pa_enable_HI 1
160 #define ATTR_CFG_FLD_pct_enable_CFG config /* PMSCR_EL1.PCT */
161 #define ATTR_CFG_FLD_pct_enable_LO 2
162 #define ATTR_CFG_FLD_pct_enable_HI 2
163 #define ATTR_CFG_FLD_jitter_CFG config /* PMSIRR_EL1.RND */
164 #define ATTR_CFG_FLD_jitter_LO 16
165 #define ATTR_CFG_FLD_jitter_HI 16
166 #define ATTR_CFG_FLD_branch_filter_CFG config /* PMSFCR_EL1.B */
167 #define ATTR_CFG_FLD_branch_filter_LO 32
168 #define ATTR_CFG_FLD_branch_filter_HI 32
169 #define ATTR_CFG_FLD_load_filter_CFG config /* PMSFCR_EL1.LD */
170 #define ATTR_CFG_FLD_load_filter_LO 33
171 #define ATTR_CFG_FLD_load_filter_HI 33
172 #define ATTR_CFG_FLD_store_filter_CFG config /* PMSFCR_EL1.ST */
173 #define ATTR_CFG_FLD_store_filter_LO 34
174 #define ATTR_CFG_FLD_store_filter_HI 34
176 #define ATTR_CFG_FLD_event_filter_CFG config1 /* PMSEVFR_EL1 */
177 #define ATTR_CFG_FLD_event_filter_LO 0
178 #define ATTR_CFG_FLD_event_filter_HI 63
180 #define ATTR_CFG_FLD_min_latency_CFG config2 /* PMSLATFR_EL1.MINLAT */
181 #define ATTR_CFG_FLD_min_latency_LO 0
182 #define ATTR_CFG_FLD_min_latency_HI 11
184 /* Why does everything I do descend into this? */
185 #define __GEN_PMU_FORMAT_ATTR(cfg, lo, hi) \
186 (lo) == (hi) ? #cfg ":" #lo "\n" : #cfg ":" #lo "-" #hi
188 #define _GEN_PMU_FORMAT_ATTR(cfg, lo, hi) \
189 __GEN_PMU_FORMAT_ATTR(cfg, lo, hi)
191 #define GEN_PMU_FORMAT_ATTR(name) \
192 PMU_FORMAT_ATTR(name, \
193 _GEN_PMU_FORMAT_ATTR(ATTR_CFG_FLD_##name##_CFG, \
194 ATTR_CFG_FLD_##name##_LO, \
195 ATTR_CFG_FLD_##name##_HI))
197 #define _ATTR_CFG_GET_FLD(attr, cfg, lo, hi) \
198 ((((attr)->cfg) >> lo) & GENMASK(hi - lo, 0))
200 #define ATTR_CFG_GET_FLD(attr, name) \
201 _ATTR_CFG_GET_FLD(attr, \
202 ATTR_CFG_FLD_##name##_CFG, \
203 ATTR_CFG_FLD_##name##_LO, \
204 ATTR_CFG_FLD_##name##_HI)
206 GEN_PMU_FORMAT_ATTR(ts_enable);
207 GEN_PMU_FORMAT_ATTR(pa_enable);
208 GEN_PMU_FORMAT_ATTR(pct_enable);
209 GEN_PMU_FORMAT_ATTR(jitter);
210 GEN_PMU_FORMAT_ATTR(branch_filter);
211 GEN_PMU_FORMAT_ATTR(load_filter);
212 GEN_PMU_FORMAT_ATTR(store_filter);
213 GEN_PMU_FORMAT_ATTR(event_filter);
214 GEN_PMU_FORMAT_ATTR(min_latency);
216 static struct attribute *arm_spe_pmu_formats_attr[] = {
217 &format_attr_ts_enable.attr,
218 &format_attr_pa_enable.attr,
219 &format_attr_pct_enable.attr,
220 &format_attr_jitter.attr,
221 &format_attr_branch_filter.attr,
222 &format_attr_load_filter.attr,
223 &format_attr_store_filter.attr,
224 &format_attr_event_filter.attr,
225 &format_attr_min_latency.attr,
229 static const struct attribute_group arm_spe_pmu_format_group = {
231 .attrs = arm_spe_pmu_formats_attr,
234 static ssize_t arm_spe_pmu_get_attr_cpumask(struct device *dev,
235 struct device_attribute *attr,
238 struct arm_spe_pmu *spe_pmu = dev_get_drvdata(dev);
240 return cpumap_print_to_pagebuf(true, buf, &spe_pmu->supported_cpus);
242 static DEVICE_ATTR(cpumask, S_IRUGO, arm_spe_pmu_get_attr_cpumask, NULL);
244 static struct attribute *arm_spe_pmu_attrs[] = {
245 &dev_attr_cpumask.attr,
249 static const struct attribute_group arm_spe_pmu_group = {
250 .attrs = arm_spe_pmu_attrs,
253 static const struct attribute_group *arm_spe_pmu_attr_groups[] = {
255 &arm_spe_pmu_cap_group,
256 &arm_spe_pmu_format_group,
260 /* Convert between user ABI and register values */
261 static u64 arm_spe_event_to_pmscr(struct perf_event *event)
263 struct perf_event_attr *attr = &event->attr;
266 reg |= ATTR_CFG_GET_FLD(attr, ts_enable) << SYS_PMSCR_EL1_TS_SHIFT;
267 reg |= ATTR_CFG_GET_FLD(attr, pa_enable) << SYS_PMSCR_EL1_PA_SHIFT;
268 reg |= ATTR_CFG_GET_FLD(attr, pct_enable) << SYS_PMSCR_EL1_PCT_SHIFT;
270 if (!attr->exclude_user)
271 reg |= BIT(SYS_PMSCR_EL1_E0SPE_SHIFT);
273 if (!attr->exclude_kernel)
274 reg |= BIT(SYS_PMSCR_EL1_E1SPE_SHIFT);
276 if (IS_ENABLED(CONFIG_PID_IN_CONTEXTIDR) && perfmon_capable())
277 reg |= BIT(SYS_PMSCR_EL1_CX_SHIFT);
282 static void arm_spe_event_sanitise_period(struct perf_event *event)
284 struct arm_spe_pmu *spe_pmu = to_spe_pmu(event->pmu);
285 u64 period = event->hw.sample_period;
286 u64 max_period = SYS_PMSIRR_EL1_INTERVAL_MASK
287 << SYS_PMSIRR_EL1_INTERVAL_SHIFT;
289 if (period < spe_pmu->min_period)
290 period = spe_pmu->min_period;
291 else if (period > max_period)
294 period &= max_period;
296 event->hw.sample_period = period;
299 static u64 arm_spe_event_to_pmsirr(struct perf_event *event)
301 struct perf_event_attr *attr = &event->attr;
304 arm_spe_event_sanitise_period(event);
306 reg |= ATTR_CFG_GET_FLD(attr, jitter) << SYS_PMSIRR_EL1_RND_SHIFT;
307 reg |= event->hw.sample_period;
312 static u64 arm_spe_event_to_pmsfcr(struct perf_event *event)
314 struct perf_event_attr *attr = &event->attr;
317 reg |= ATTR_CFG_GET_FLD(attr, load_filter) << SYS_PMSFCR_EL1_LD_SHIFT;
318 reg |= ATTR_CFG_GET_FLD(attr, store_filter) << SYS_PMSFCR_EL1_ST_SHIFT;
319 reg |= ATTR_CFG_GET_FLD(attr, branch_filter) << SYS_PMSFCR_EL1_B_SHIFT;
322 reg |= BIT(SYS_PMSFCR_EL1_FT_SHIFT);
324 if (ATTR_CFG_GET_FLD(attr, event_filter))
325 reg |= BIT(SYS_PMSFCR_EL1_FE_SHIFT);
327 if (ATTR_CFG_GET_FLD(attr, min_latency))
328 reg |= BIT(SYS_PMSFCR_EL1_FL_SHIFT);
333 static u64 arm_spe_event_to_pmsevfr(struct perf_event *event)
335 struct perf_event_attr *attr = &event->attr;
336 return ATTR_CFG_GET_FLD(attr, event_filter);
339 static u64 arm_spe_event_to_pmslatfr(struct perf_event *event)
341 struct perf_event_attr *attr = &event->attr;
342 return ATTR_CFG_GET_FLD(attr, min_latency)
343 << SYS_PMSLATFR_EL1_MINLAT_SHIFT;
346 static void arm_spe_pmu_pad_buf(struct perf_output_handle *handle, int len)
348 struct arm_spe_pmu_buf *buf = perf_get_aux(handle);
349 u64 head = PERF_IDX2OFF(handle->head, buf);
351 memset(buf->base + head, ARM_SPE_BUF_PAD_BYTE, len);
353 perf_aux_output_skip(handle, len);
356 static u64 arm_spe_pmu_next_snapshot_off(struct perf_output_handle *handle)
358 struct arm_spe_pmu_buf *buf = perf_get_aux(handle);
359 struct arm_spe_pmu *spe_pmu = to_spe_pmu(handle->event->pmu);
360 u64 head = PERF_IDX2OFF(handle->head, buf);
361 u64 limit = buf->nr_pages * PAGE_SIZE;
364 * The trace format isn't parseable in reverse, so clamp
365 * the limit to half of the buffer size in snapshot mode
366 * so that the worst case is half a buffer of records, as
367 * opposed to a single record.
369 if (head < limit >> 1)
373 * If we're within max_record_sz of the limit, we must
374 * pad, move the head index and recompute the limit.
376 if (limit - head < spe_pmu->max_record_sz) {
377 arm_spe_pmu_pad_buf(handle, limit - head);
378 handle->head = PERF_IDX2OFF(limit, buf);
379 limit = ((buf->nr_pages * PAGE_SIZE) >> 1) + handle->head;
385 static u64 __arm_spe_pmu_next_off(struct perf_output_handle *handle)
387 struct arm_spe_pmu *spe_pmu = to_spe_pmu(handle->event->pmu);
388 struct arm_spe_pmu_buf *buf = perf_get_aux(handle);
389 const u64 bufsize = buf->nr_pages * PAGE_SIZE;
391 u64 head, tail, wakeup;
394 * The head can be misaligned for two reasons:
396 * 1. The hardware left PMBPTR pointing to the first byte after
397 * a record when generating a buffer management event.
399 * 2. We used perf_aux_output_skip to consume handle->size bytes
400 * and CIRC_SPACE was used to compute the size, which always
401 * leaves one entry free.
403 * Deal with this by padding to the next alignment boundary and
404 * moving the head index. If we run out of buffer space, we'll
405 * reduce handle->size to zero and end up reporting truncation.
407 head = PERF_IDX2OFF(handle->head, buf);
408 if (!IS_ALIGNED(head, spe_pmu->align)) {
409 unsigned long delta = roundup(head, spe_pmu->align) - head;
411 delta = min(delta, handle->size);
412 arm_spe_pmu_pad_buf(handle, delta);
413 head = PERF_IDX2OFF(handle->head, buf);
416 /* If we've run out of free space, then nothing more to do */
420 /* Compute the tail and wakeup indices now that we've aligned head */
421 tail = PERF_IDX2OFF(handle->head + handle->size, buf);
422 wakeup = PERF_IDX2OFF(handle->wakeup, buf);
425 * Avoid clobbering unconsumed data. We know we have space, so
426 * if we see head == tail we know that the buffer is empty. If
427 * head > tail, then there's nothing to clobber prior to
431 limit = round_down(tail, PAGE_SIZE);
434 * Wakeup may be arbitrarily far into the future. If it's not in
435 * the current generation, either we'll wrap before hitting it,
436 * or it's in the past and has been handled already.
438 * If there's a wakeup before we wrap, arrange to be woken up by
439 * the page boundary following it. Keep the tail boundary if
442 if (handle->wakeup < (handle->head + handle->size) && head <= wakeup)
443 limit = min(limit, round_up(wakeup, PAGE_SIZE));
448 arm_spe_pmu_pad_buf(handle, handle->size);
450 perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
451 perf_aux_output_end(handle, 0);
455 static u64 arm_spe_pmu_next_off(struct perf_output_handle *handle)
457 struct arm_spe_pmu_buf *buf = perf_get_aux(handle);
458 struct arm_spe_pmu *spe_pmu = to_spe_pmu(handle->event->pmu);
459 u64 limit = __arm_spe_pmu_next_off(handle);
460 u64 head = PERF_IDX2OFF(handle->head, buf);
463 * If the head has come too close to the end of the buffer,
464 * then pad to the end and recompute the limit.
466 if (limit && (limit - head < spe_pmu->max_record_sz)) {
467 arm_spe_pmu_pad_buf(handle, limit - head);
468 limit = __arm_spe_pmu_next_off(handle);
474 static void arm_spe_perf_aux_output_begin(struct perf_output_handle *handle,
475 struct perf_event *event)
478 struct arm_spe_pmu_buf *buf;
480 /* Start a new aux session */
481 buf = perf_aux_output_begin(handle, event);
483 event->hw.state |= PERF_HES_STOPPED;
485 * We still need to clear the limit pointer, since the
486 * profiler might only be disabled by virtue of a fault.
489 goto out_write_limit;
492 limit = buf->snapshot ? arm_spe_pmu_next_snapshot_off(handle)
493 : arm_spe_pmu_next_off(handle);
495 limit |= BIT(SYS_PMBLIMITR_EL1_E_SHIFT);
497 limit += (u64)buf->base;
498 base = (u64)buf->base + PERF_IDX2OFF(handle->head, buf);
499 write_sysreg_s(base, SYS_PMBPTR_EL1);
502 write_sysreg_s(limit, SYS_PMBLIMITR_EL1);
505 static void arm_spe_perf_aux_output_end(struct perf_output_handle *handle)
507 struct arm_spe_pmu_buf *buf = perf_get_aux(handle);
510 offset = read_sysreg_s(SYS_PMBPTR_EL1) - (u64)buf->base;
511 size = offset - PERF_IDX2OFF(handle->head, buf);
514 handle->head = offset;
516 perf_aux_output_end(handle, size);
519 static void arm_spe_pmu_disable_and_drain_local(void)
521 /* Disable profiling at EL0 and EL1 */
522 write_sysreg_s(0, SYS_PMSCR_EL1);
525 /* Drain any buffered data */
529 /* Disable the profiling buffer */
530 write_sysreg_s(0, SYS_PMBLIMITR_EL1);
535 static enum arm_spe_pmu_buf_fault_action
536 arm_spe_pmu_buf_get_fault_act(struct perf_output_handle *handle)
540 enum arm_spe_pmu_buf_fault_action ret;
543 * Ensure new profiling data is visible to the CPU and any external
544 * aborts have been resolved.
549 /* Ensure hardware updates to PMBPTR_EL1 are visible */
552 /* Service required? */
553 pmbsr = read_sysreg_s(SYS_PMBSR_EL1);
554 if (!(pmbsr & BIT(SYS_PMBSR_EL1_S_SHIFT)))
555 return SPE_PMU_BUF_FAULT_ACT_SPURIOUS;
558 * If we've lost data, disable profiling and also set the PARTIAL
559 * flag to indicate that the last record is corrupted.
561 if (pmbsr & BIT(SYS_PMBSR_EL1_DL_SHIFT))
562 perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED |
563 PERF_AUX_FLAG_PARTIAL);
565 /* Report collisions to userspace so that it can up the period */
566 if (pmbsr & BIT(SYS_PMBSR_EL1_COLL_SHIFT))
567 perf_aux_output_flag(handle, PERF_AUX_FLAG_COLLISION);
569 /* We only expect buffer management events */
570 switch (pmbsr & (SYS_PMBSR_EL1_EC_MASK << SYS_PMBSR_EL1_EC_SHIFT)) {
571 case SYS_PMBSR_EL1_EC_BUF:
574 case SYS_PMBSR_EL1_EC_FAULT_S1:
575 case SYS_PMBSR_EL1_EC_FAULT_S2:
576 err_str = "Unexpected buffer fault";
579 err_str = "Unknown error code";
583 /* Buffer management event */
585 (SYS_PMBSR_EL1_BUF_BSC_MASK << SYS_PMBSR_EL1_BUF_BSC_SHIFT)) {
586 case SYS_PMBSR_EL1_BUF_BSC_FULL:
587 ret = SPE_PMU_BUF_FAULT_ACT_OK;
590 err_str = "Unknown buffer status code";
594 pr_err_ratelimited("%s on CPU %d [PMBSR=0x%016llx, PMBPTR=0x%016llx, PMBLIMITR=0x%016llx]\n",
595 err_str, smp_processor_id(), pmbsr,
596 read_sysreg_s(SYS_PMBPTR_EL1),
597 read_sysreg_s(SYS_PMBLIMITR_EL1));
598 ret = SPE_PMU_BUF_FAULT_ACT_FATAL;
601 arm_spe_perf_aux_output_end(handle);
605 static irqreturn_t arm_spe_pmu_irq_handler(int irq, void *dev)
607 struct perf_output_handle *handle = dev;
608 struct perf_event *event = handle->event;
609 enum arm_spe_pmu_buf_fault_action act;
611 if (!perf_get_aux(handle))
614 act = arm_spe_pmu_buf_get_fault_act(handle);
615 if (act == SPE_PMU_BUF_FAULT_ACT_SPURIOUS)
619 * Ensure perf callbacks have completed, which may disable the
620 * profiling buffer in response to a TRUNCATION flag.
625 case SPE_PMU_BUF_FAULT_ACT_FATAL:
627 * If a fatal exception occurred then leaving the profiling
628 * buffer enabled is a recipe waiting to happen. Since
629 * fatal faults don't always imply truncation, make sure
630 * that the profiling buffer is disabled explicitly before
631 * clearing the syndrome register.
633 arm_spe_pmu_disable_and_drain_local();
635 case SPE_PMU_BUF_FAULT_ACT_OK:
637 * We handled the fault (the buffer was full), so resume
638 * profiling as long as we didn't detect truncation.
639 * PMBPTR might be misaligned, but we'll burn that bridge
642 if (!(handle->aux_flags & PERF_AUX_FLAG_TRUNCATED)) {
643 arm_spe_perf_aux_output_begin(handle, event);
647 case SPE_PMU_BUF_FAULT_ACT_SPURIOUS:
648 /* We've seen you before, but GCC has the memory of a sieve. */
652 /* The buffer pointers are now sane, so resume profiling. */
653 write_sysreg_s(0, SYS_PMBSR_EL1);
657 static u64 arm_spe_pmsevfr_res0(u16 pmsver)
660 case ID_AA64DFR0_PMSVER_8_2:
661 return SYS_PMSEVFR_EL1_RES0_8_2;
662 case ID_AA64DFR0_PMSVER_8_3:
663 /* Return the highest version we support in default */
665 return SYS_PMSEVFR_EL1_RES0_8_3;
670 static int arm_spe_pmu_event_init(struct perf_event *event)
673 struct perf_event_attr *attr = &event->attr;
674 struct arm_spe_pmu *spe_pmu = to_spe_pmu(event->pmu);
676 /* This is, of course, deeply driver-specific */
677 if (attr->type != event->pmu->type)
680 if (event->cpu >= 0 &&
681 !cpumask_test_cpu(event->cpu, &spe_pmu->supported_cpus))
684 if (arm_spe_event_to_pmsevfr(event) & arm_spe_pmsevfr_res0(spe_pmu->pmsver))
687 if (attr->exclude_idle)
691 * Feedback-directed frequency throttling doesn't work when we
692 * have a buffer of samples. We'd need to manually count the
693 * samples in the buffer when it fills up and adjust the event
694 * count to reflect that. Instead, just force the user to specify
700 reg = arm_spe_event_to_pmsfcr(event);
701 if ((reg & BIT(SYS_PMSFCR_EL1_FE_SHIFT)) &&
702 !(spe_pmu->features & SPE_PMU_FEAT_FILT_EVT))
705 if ((reg & BIT(SYS_PMSFCR_EL1_FT_SHIFT)) &&
706 !(spe_pmu->features & SPE_PMU_FEAT_FILT_TYP))
709 if ((reg & BIT(SYS_PMSFCR_EL1_FL_SHIFT)) &&
710 !(spe_pmu->features & SPE_PMU_FEAT_FILT_LAT))
713 reg = arm_spe_event_to_pmscr(event);
714 if (!perfmon_capable() &&
715 (reg & (BIT(SYS_PMSCR_EL1_PA_SHIFT) |
716 BIT(SYS_PMSCR_EL1_CX_SHIFT) |
717 BIT(SYS_PMSCR_EL1_PCT_SHIFT))))
723 static void arm_spe_pmu_start(struct perf_event *event, int flags)
726 struct arm_spe_pmu *spe_pmu = to_spe_pmu(event->pmu);
727 struct hw_perf_event *hwc = &event->hw;
728 struct perf_output_handle *handle = this_cpu_ptr(spe_pmu->handle);
731 arm_spe_perf_aux_output_begin(handle, event);
735 reg = arm_spe_event_to_pmsfcr(event);
736 write_sysreg_s(reg, SYS_PMSFCR_EL1);
738 reg = arm_spe_event_to_pmsevfr(event);
739 write_sysreg_s(reg, SYS_PMSEVFR_EL1);
741 reg = arm_spe_event_to_pmslatfr(event);
742 write_sysreg_s(reg, SYS_PMSLATFR_EL1);
744 if (flags & PERF_EF_RELOAD) {
745 reg = arm_spe_event_to_pmsirr(event);
746 write_sysreg_s(reg, SYS_PMSIRR_EL1);
748 reg = local64_read(&hwc->period_left);
749 write_sysreg_s(reg, SYS_PMSICR_EL1);
752 reg = arm_spe_event_to_pmscr(event);
754 write_sysreg_s(reg, SYS_PMSCR_EL1);
757 static void arm_spe_pmu_stop(struct perf_event *event, int flags)
759 struct arm_spe_pmu *spe_pmu = to_spe_pmu(event->pmu);
760 struct hw_perf_event *hwc = &event->hw;
761 struct perf_output_handle *handle = this_cpu_ptr(spe_pmu->handle);
763 /* If we're already stopped, then nothing to do */
764 if (hwc->state & PERF_HES_STOPPED)
767 /* Stop all trace generation */
768 arm_spe_pmu_disable_and_drain_local();
770 if (flags & PERF_EF_UPDATE) {
772 * If there's a fault pending then ensure we contain it
773 * to this buffer, since we might be on the context-switch
776 if (perf_get_aux(handle)) {
777 enum arm_spe_pmu_buf_fault_action act;
779 act = arm_spe_pmu_buf_get_fault_act(handle);
780 if (act == SPE_PMU_BUF_FAULT_ACT_SPURIOUS)
781 arm_spe_perf_aux_output_end(handle);
783 write_sysreg_s(0, SYS_PMBSR_EL1);
787 * This may also contain ECOUNT, but nobody else should
788 * be looking at period_left, since we forbid frequency
791 local64_set(&hwc->period_left, read_sysreg_s(SYS_PMSICR_EL1));
792 hwc->state |= PERF_HES_UPTODATE;
795 hwc->state |= PERF_HES_STOPPED;
798 static int arm_spe_pmu_add(struct perf_event *event, int flags)
801 struct arm_spe_pmu *spe_pmu = to_spe_pmu(event->pmu);
802 struct hw_perf_event *hwc = &event->hw;
803 int cpu = event->cpu == -1 ? smp_processor_id() : event->cpu;
805 if (!cpumask_test_cpu(cpu, &spe_pmu->supported_cpus))
808 hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
810 if (flags & PERF_EF_START) {
811 arm_spe_pmu_start(event, PERF_EF_RELOAD);
812 if (hwc->state & PERF_HES_STOPPED)
819 static void arm_spe_pmu_del(struct perf_event *event, int flags)
821 arm_spe_pmu_stop(event, PERF_EF_UPDATE);
824 static void arm_spe_pmu_read(struct perf_event *event)
828 static void *arm_spe_pmu_setup_aux(struct perf_event *event, void **pages,
829 int nr_pages, bool snapshot)
831 int i, cpu = event->cpu;
832 struct page **pglist;
833 struct arm_spe_pmu_buf *buf;
835 /* We need at least two pages for this to work. */
840 * We require an even number of pages for snapshot mode, so that
841 * we can effectively treat the buffer as consisting of two equal
842 * parts and give userspace a fighting chance of getting some
843 * useful data out of it.
845 if (snapshot && (nr_pages & 1))
849 cpu = raw_smp_processor_id();
851 buf = kzalloc_node(sizeof(*buf), GFP_KERNEL, cpu_to_node(cpu));
855 pglist = kcalloc(nr_pages, sizeof(*pglist), GFP_KERNEL);
859 for (i = 0; i < nr_pages; ++i)
860 pglist[i] = virt_to_page(pages[i]);
862 buf->base = vmap(pglist, nr_pages, VM_MAP, PAGE_KERNEL);
864 goto out_free_pglist;
866 buf->nr_pages = nr_pages;
867 buf->snapshot = snapshot;
879 static void arm_spe_pmu_free_aux(void *aux)
881 struct arm_spe_pmu_buf *buf = aux;
887 /* Initialisation and teardown functions */
888 static int arm_spe_pmu_perf_init(struct arm_spe_pmu *spe_pmu)
890 static atomic_t pmu_idx = ATOMIC_INIT(-1);
894 struct device *dev = &spe_pmu->pdev->dev;
896 spe_pmu->pmu = (struct pmu) {
897 .module = THIS_MODULE,
898 .capabilities = PERF_PMU_CAP_EXCLUSIVE | PERF_PMU_CAP_ITRACE,
899 .attr_groups = arm_spe_pmu_attr_groups,
901 * We hitch a ride on the software context here, so that
902 * we can support per-task profiling (which is not possible
903 * with the invalid context as it doesn't get sched callbacks).
904 * This requires that userspace either uses a dummy event for
905 * perf_event_open, since the aux buffer is not setup until
906 * a subsequent mmap, or creates the profiling event in a
907 * disabled state and explicitly PERF_EVENT_IOC_ENABLEs it
908 * once the buffer has been created.
910 .task_ctx_nr = perf_sw_context,
911 .event_init = arm_spe_pmu_event_init,
912 .add = arm_spe_pmu_add,
913 .del = arm_spe_pmu_del,
914 .start = arm_spe_pmu_start,
915 .stop = arm_spe_pmu_stop,
916 .read = arm_spe_pmu_read,
917 .setup_aux = arm_spe_pmu_setup_aux,
918 .free_aux = arm_spe_pmu_free_aux,
921 idx = atomic_inc_return(&pmu_idx);
922 name = devm_kasprintf(dev, GFP_KERNEL, "%s_%d", PMUNAME, idx);
924 dev_err(dev, "failed to allocate name for pmu %d\n", idx);
928 return perf_pmu_register(&spe_pmu->pmu, name, -1);
931 static void arm_spe_pmu_perf_destroy(struct arm_spe_pmu *spe_pmu)
933 perf_pmu_unregister(&spe_pmu->pmu);
936 static void __arm_spe_pmu_dev_probe(void *info)
940 struct arm_spe_pmu *spe_pmu = info;
941 struct device *dev = &spe_pmu->pdev->dev;
943 fld = cpuid_feature_extract_unsigned_field(read_cpuid(ID_AA64DFR0_EL1),
944 ID_AA64DFR0_PMSVER_SHIFT);
947 "unsupported ID_AA64DFR0_EL1.PMSVer [%d] on CPU %d\n",
948 fld, smp_processor_id());
951 spe_pmu->pmsver = (u16)fld;
953 /* Read PMBIDR first to determine whether or not we have access */
954 reg = read_sysreg_s(SYS_PMBIDR_EL1);
955 if (reg & BIT(SYS_PMBIDR_EL1_P_SHIFT)) {
957 "profiling buffer owned by higher exception level\n");
961 /* Minimum alignment. If it's out-of-range, then fail the probe */
962 fld = reg >> SYS_PMBIDR_EL1_ALIGN_SHIFT & SYS_PMBIDR_EL1_ALIGN_MASK;
963 spe_pmu->align = 1 << fld;
964 if (spe_pmu->align > SZ_2K) {
965 dev_err(dev, "unsupported PMBIDR.Align [%d] on CPU %d\n",
966 fld, smp_processor_id());
970 /* It's now safe to read PMSIDR and figure out what we've got */
971 reg = read_sysreg_s(SYS_PMSIDR_EL1);
972 if (reg & BIT(SYS_PMSIDR_EL1_FE_SHIFT))
973 spe_pmu->features |= SPE_PMU_FEAT_FILT_EVT;
975 if (reg & BIT(SYS_PMSIDR_EL1_FT_SHIFT))
976 spe_pmu->features |= SPE_PMU_FEAT_FILT_TYP;
978 if (reg & BIT(SYS_PMSIDR_EL1_FL_SHIFT))
979 spe_pmu->features |= SPE_PMU_FEAT_FILT_LAT;
981 if (reg & BIT(SYS_PMSIDR_EL1_ARCHINST_SHIFT))
982 spe_pmu->features |= SPE_PMU_FEAT_ARCH_INST;
984 if (reg & BIT(SYS_PMSIDR_EL1_LDS_SHIFT))
985 spe_pmu->features |= SPE_PMU_FEAT_LDS;
987 if (reg & BIT(SYS_PMSIDR_EL1_ERND_SHIFT))
988 spe_pmu->features |= SPE_PMU_FEAT_ERND;
990 /* This field has a spaced out encoding, so just use a look-up */
991 fld = reg >> SYS_PMSIDR_EL1_INTERVAL_SHIFT & SYS_PMSIDR_EL1_INTERVAL_MASK;
994 spe_pmu->min_period = 256;
997 spe_pmu->min_period = 512;
1000 spe_pmu->min_period = 768;
1003 spe_pmu->min_period = 1024;
1006 spe_pmu->min_period = 1536;
1009 spe_pmu->min_period = 2048;
1012 spe_pmu->min_period = 3072;
1015 dev_warn(dev, "unknown PMSIDR_EL1.Interval [%d]; assuming 8\n",
1019 spe_pmu->min_period = 4096;
1022 /* Maximum record size. If it's out-of-range, then fail the probe */
1023 fld = reg >> SYS_PMSIDR_EL1_MAXSIZE_SHIFT & SYS_PMSIDR_EL1_MAXSIZE_MASK;
1024 spe_pmu->max_record_sz = 1 << fld;
1025 if (spe_pmu->max_record_sz > SZ_2K || spe_pmu->max_record_sz < 16) {
1026 dev_err(dev, "unsupported PMSIDR_EL1.MaxSize [%d] on CPU %d\n",
1027 fld, smp_processor_id());
1031 fld = reg >> SYS_PMSIDR_EL1_COUNTSIZE_SHIFT & SYS_PMSIDR_EL1_COUNTSIZE_MASK;
1034 dev_warn(dev, "unknown PMSIDR_EL1.CountSize [%d]; assuming 2\n",
1038 spe_pmu->counter_sz = 12;
1042 "probed for CPUs %*pbl [max_record_sz %u, align %u, features 0x%llx]\n",
1043 cpumask_pr_args(&spe_pmu->supported_cpus),
1044 spe_pmu->max_record_sz, spe_pmu->align, spe_pmu->features);
1046 spe_pmu->features |= SPE_PMU_FEAT_DEV_PROBED;
1050 static void __arm_spe_pmu_reset_local(void)
1053 * This is probably overkill, as we have no idea where we're
1054 * draining any buffered data to...
1056 arm_spe_pmu_disable_and_drain_local();
1058 /* Reset the buffer base pointer */
1059 write_sysreg_s(0, SYS_PMBPTR_EL1);
1062 /* Clear any pending management interrupts */
1063 write_sysreg_s(0, SYS_PMBSR_EL1);
1067 static void __arm_spe_pmu_setup_one(void *info)
1069 struct arm_spe_pmu *spe_pmu = info;
1071 __arm_spe_pmu_reset_local();
1072 enable_percpu_irq(spe_pmu->irq, IRQ_TYPE_NONE);
1075 static void __arm_spe_pmu_stop_one(void *info)
1077 struct arm_spe_pmu *spe_pmu = info;
1079 disable_percpu_irq(spe_pmu->irq);
1080 __arm_spe_pmu_reset_local();
1083 static int arm_spe_pmu_cpu_startup(unsigned int cpu, struct hlist_node *node)
1085 struct arm_spe_pmu *spe_pmu;
1087 spe_pmu = hlist_entry_safe(node, struct arm_spe_pmu, hotplug_node);
1088 if (!cpumask_test_cpu(cpu, &spe_pmu->supported_cpus))
1091 __arm_spe_pmu_setup_one(spe_pmu);
1095 static int arm_spe_pmu_cpu_teardown(unsigned int cpu, struct hlist_node *node)
1097 struct arm_spe_pmu *spe_pmu;
1099 spe_pmu = hlist_entry_safe(node, struct arm_spe_pmu, hotplug_node);
1100 if (!cpumask_test_cpu(cpu, &spe_pmu->supported_cpus))
1103 __arm_spe_pmu_stop_one(spe_pmu);
1107 static int arm_spe_pmu_dev_init(struct arm_spe_pmu *spe_pmu)
1110 cpumask_t *mask = &spe_pmu->supported_cpus;
1112 /* Make sure we probe the hardware on a relevant CPU */
1113 ret = smp_call_function_any(mask, __arm_spe_pmu_dev_probe, spe_pmu, 1);
1114 if (ret || !(spe_pmu->features & SPE_PMU_FEAT_DEV_PROBED))
1117 /* Request our PPIs (note that the IRQ is still disabled) */
1118 ret = request_percpu_irq(spe_pmu->irq, arm_spe_pmu_irq_handler, DRVNAME,
1124 * Register our hotplug notifier now so we don't miss any events.
1125 * This will enable the IRQ for any supported CPUs that are already
1128 ret = cpuhp_state_add_instance(arm_spe_pmu_online,
1129 &spe_pmu->hotplug_node);
1131 free_percpu_irq(spe_pmu->irq, spe_pmu->handle);
1136 static void arm_spe_pmu_dev_teardown(struct arm_spe_pmu *spe_pmu)
1138 cpuhp_state_remove_instance(arm_spe_pmu_online, &spe_pmu->hotplug_node);
1139 free_percpu_irq(spe_pmu->irq, spe_pmu->handle);
1142 /* Driver and device probing */
1143 static int arm_spe_pmu_irq_probe(struct arm_spe_pmu *spe_pmu)
1145 struct platform_device *pdev = spe_pmu->pdev;
1146 int irq = platform_get_irq(pdev, 0);
1151 if (!irq_is_percpu(irq)) {
1152 dev_err(&pdev->dev, "expected PPI but got SPI (%d)\n", irq);
1156 if (irq_get_percpu_devid_partition(irq, &spe_pmu->supported_cpus)) {
1157 dev_err(&pdev->dev, "failed to get PPI partition (%d)\n", irq);
1165 static const struct of_device_id arm_spe_pmu_of_match[] = {
1166 { .compatible = "arm,statistical-profiling-extension-v1", .data = (void *)1 },
1169 MODULE_DEVICE_TABLE(of, arm_spe_pmu_of_match);
1171 static const struct platform_device_id arm_spe_match[] = {
1172 { ARMV8_SPE_PDEV_NAME, 0},
1175 MODULE_DEVICE_TABLE(platform, arm_spe_match);
1177 static int arm_spe_pmu_device_probe(struct platform_device *pdev)
1180 struct arm_spe_pmu *spe_pmu;
1181 struct device *dev = &pdev->dev;
1184 * If kernelspace is unmapped when running at EL0, then the SPE
1185 * buffer will fault and prematurely terminate the AUX session.
1187 if (arm64_kernel_unmapped_at_el0()) {
1188 dev_warn_once(dev, "profiling buffer inaccessible. Try passing \"kpti=off\" on the kernel command line\n");
1192 spe_pmu = devm_kzalloc(dev, sizeof(*spe_pmu), GFP_KERNEL);
1194 dev_err(dev, "failed to allocate spe_pmu\n");
1198 spe_pmu->handle = alloc_percpu(typeof(*spe_pmu->handle));
1199 if (!spe_pmu->handle)
1202 spe_pmu->pdev = pdev;
1203 platform_set_drvdata(pdev, spe_pmu);
1205 ret = arm_spe_pmu_irq_probe(spe_pmu);
1207 goto out_free_handle;
1209 ret = arm_spe_pmu_dev_init(spe_pmu);
1211 goto out_free_handle;
1213 ret = arm_spe_pmu_perf_init(spe_pmu);
1215 goto out_teardown_dev;
1220 arm_spe_pmu_dev_teardown(spe_pmu);
1222 free_percpu(spe_pmu->handle);
1226 static int arm_spe_pmu_device_remove(struct platform_device *pdev)
1228 struct arm_spe_pmu *spe_pmu = platform_get_drvdata(pdev);
1230 arm_spe_pmu_perf_destroy(spe_pmu);
1231 arm_spe_pmu_dev_teardown(spe_pmu);
1232 free_percpu(spe_pmu->handle);
1236 static struct platform_driver arm_spe_pmu_driver = {
1237 .id_table = arm_spe_match,
1240 .of_match_table = of_match_ptr(arm_spe_pmu_of_match),
1241 .suppress_bind_attrs = true,
1243 .probe = arm_spe_pmu_device_probe,
1244 .remove = arm_spe_pmu_device_remove,
1247 static int __init arm_spe_pmu_init(void)
1251 ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, DRVNAME,
1252 arm_spe_pmu_cpu_startup,
1253 arm_spe_pmu_cpu_teardown);
1256 arm_spe_pmu_online = ret;
1258 ret = platform_driver_register(&arm_spe_pmu_driver);
1260 cpuhp_remove_multi_state(arm_spe_pmu_online);
1265 static void __exit arm_spe_pmu_exit(void)
1267 platform_driver_unregister(&arm_spe_pmu_driver);
1268 cpuhp_remove_multi_state(arm_spe_pmu_online);
1271 module_init(arm_spe_pmu_init);
1272 module_exit(arm_spe_pmu_exit);
1274 MODULE_DESCRIPTION("Perf driver for the ARMv8.2 Statistical Profiling Extension");
1275 MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>");
1276 MODULE_LICENSE("GPL v2");