drivers/phy/marvell/phy-berlin-sata.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Marvell Berlin SATA PHY driver
   4  *
   5  * Copyright (C) 2014 Marvell Technology Group Ltd.
   6  *
   7  * Antoine Ténart <antoine.tenart@free-electrons.com>
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/module.h>
  12 #include <linux/phy/phy.h>
  13 #include <linux/io.h>
  14 #include <linux/platform_device.h>
  15
  16 #define HOST_VSA_ADDR           0x0
  17 #define HOST_VSA_DATA           0x4
  18 #define PORT_SCR_CTL            0x2c
  19 #define PORT_VSR_ADDR           0x78
  20 #define PORT_VSR_DATA           0x7c
  21
  22 #define CONTROL_REGISTER        0x0
  23 #define MBUS_SIZE_CONTROL       0x4
  24
  25 #define POWER_DOWN_PHY0                 BIT(6)
  26 #define POWER_DOWN_PHY1                 BIT(14)
  27 #define MBUS_WRITE_REQUEST_SIZE_128     (BIT(2) << 16)
  28 #define MBUS_READ_REQUEST_SIZE_128      (BIT(2) << 19)
  29
  30 #define BG2_PHY_BASE            0x080
  31 #define BG2Q_PHY_BASE           0x200
  32
  33 /* register 0x01 */
  34 #define REF_FREF_SEL_25         BIT(0)
  35 #define PHY_MODE_SATA           (0x0 << 5)
  36
  37 /* register 0x02 */
  38 #define USE_MAX_PLL_RATE        BIT(12)
  39
  40 /* register 0x23 */
  41 #define DATA_BIT_WIDTH_10       (0x0 << 10)
  42 #define DATA_BIT_WIDTH_20       (0x1 << 10)
  43 #define DATA_BIT_WIDTH_40       (0x2 << 10)
  44
  45 /* register 0x25 */
  46 #define PHY_GEN_MAX_1_5         (0x0 << 10)
  47 #define PHY_GEN_MAX_3_0         (0x1 << 10)
  48 #define PHY_GEN_MAX_6_0         (0x2 << 10)
  49
  50 struct phy_berlin_desc {
  51         struct phy      *phy;
  52         u32             power_bit;
  53         unsigned        index;
  54 };
  55
  56 struct phy_berlin_priv {
  57         void __iomem            *base;
  58         spinlock_t              lock;
  59         struct clk              *clk;
  60         struct phy_berlin_desc  **phys;
  61         unsigned                nphys;
  62         u32                     phy_base;
  63 };
  64
  65 static inline void phy_berlin_sata_reg_setbits(void __iomem *ctrl_reg,
  66                                u32 phy_base, u32 reg, u32 mask, u32 val)
  67 {
  68         u32 regval;
  69
  70         /* select register */
  71         writel(phy_base + reg, ctrl_reg + PORT_VSR_ADDR);
  72
  73         /* set bits */
  74         regval = readl(ctrl_reg + PORT_VSR_DATA);
  75         regval &= ~mask;
  76         regval |= val;
  77         writel(regval, ctrl_reg + PORT_VSR_DATA);
  78 }
  79
  80 static int phy_berlin_sata_power_on(struct phy *phy)
  81 {
  82         struct phy_berlin_desc *desc = phy_get_drvdata(phy);
  83         struct phy_berlin_priv *priv = dev_get_drvdata(phy->dev.parent);
  84         void __iomem *ctrl_reg = priv->base + 0x60 + (desc->index * 0x80);
  85         u32 regval;
  86
  87         clk_prepare_enable(priv->clk);
  88
  89         spin_lock(&priv->lock);
  90
  91         /* Power on PHY */
  92         writel(CONTROL_REGISTER, priv->base + HOST_VSA_ADDR);
  93         regval = readl(priv->base + HOST_VSA_DATA);
  94         regval &= ~desc->power_bit;
  95         writel(regval, priv->base + HOST_VSA_DATA);
  96
  97         /* Configure MBus */
  98         writel(MBUS_SIZE_CONTROL, priv->base + HOST_VSA_ADDR);
  99         regval = readl(priv->base + HOST_VSA_DATA);
 100         regval |= MBUS_WRITE_REQUEST_SIZE_128 | MBUS_READ_REQUEST_SIZE_128;
 101         writel(regval, priv->base + HOST_VSA_DATA);
 102
 103         /* set PHY mode and ref freq to 25 MHz */
 104         phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x01,
 105                                     0x00ff, REF_FREF_SEL_25 | PHY_MODE_SATA);
 106
 107         /* set PHY up to 6 Gbps */
 108         phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x25,
 109                                     0x0c00, PHY_GEN_MAX_6_0);
 110
 111         /* set 40 bits width */
 112         phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x23,
 113                                     0x0c00, DATA_BIT_WIDTH_40);
 114
 115         /* use max pll rate */
 116         phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x02,
 117                                     0x0000, USE_MAX_PLL_RATE);
 118
 119         /* set Gen3 controller speed */
 120         regval = readl(ctrl_reg + PORT_SCR_CTL);
 121         regval &= ~GENMASK(7, 4);
 122         regval |= 0x30;
 123         writel(regval, ctrl_reg + PORT_SCR_CTL);
 124
 125         spin_unlock(&priv->lock);
 126
 127         clk_disable_unprepare(priv->clk);
 128
 129         return 0;
 130 }
 131
 132 static int phy_berlin_sata_power_off(struct phy *phy)
 133 {
 134         struct phy_berlin_desc *desc = phy_get_drvdata(phy);
 135         struct phy_berlin_priv *priv = dev_get_drvdata(phy->dev.parent);
 136         u32 regval;
 137
 138         clk_prepare_enable(priv->clk);
 139
 140         spin_lock(&priv->lock);
 141
 142         /* Power down PHY */
 143         writel(CONTROL_REGISTER, priv->base + HOST_VSA_ADDR);
 144         regval = readl(priv->base + HOST_VSA_DATA);
 145         regval |= desc->power_bit;
 146         writel(regval, priv->base + HOST_VSA_DATA);
 147
 148         spin_unlock(&priv->lock);
 149
 150         clk_disable_unprepare(priv->clk);
 151
 152         return 0;
 153 }
 154
 155 static struct phy *phy_berlin_sata_phy_xlate(struct device *dev,
 156                                              struct of_phandle_args *args)
 157 {
 158         struct phy_berlin_priv *priv = dev_get_drvdata(dev);
 159         int i;
 160
 161         if (WARN_ON(args->args[0] >= priv->nphys))
 162                 return ERR_PTR(-ENODEV);
 163
 164         for (i = 0; i < priv->nphys; i++) {
 165                 if (priv->phys[i]->index == args->args[0])
 166                         break;
 167         }
 168
 169         if (i == priv->nphys)
 170                 return ERR_PTR(-ENODEV);
 171
 172         return priv->phys[i]->phy;
 173 }
 174
 175 static const struct phy_ops phy_berlin_sata_ops = {
 176         .power_on       = phy_berlin_sata_power_on,
 177         .power_off      = phy_berlin_sata_power_off,
 178         .owner          = THIS_MODULE,
 179 };
 180
 181 static u32 phy_berlin_power_down_bits[] = {
 182         POWER_DOWN_PHY0,
 183         POWER_DOWN_PHY1,
 184 };
 185
 186 static int phy_berlin_sata_probe(struct platform_device *pdev)
 187 {
 188         struct device *dev = &pdev->dev;
 189         struct device_node *child;
 190         struct phy *phy;
 191         struct phy_provider *phy_provider;
 192         struct phy_berlin_priv *priv;
 193         struct resource *res;
 194         int ret, i = 0;
 195         u32 phy_id;
 196
 197         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 198         if (!priv)
 199                 return -ENOMEM;
 200
 201         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 202         if (!res)
 203                 return -EINVAL;
 204
 205         priv->base = devm_ioremap(dev, res->start, resource_size(res));
 206         if (!priv->base)
 207                 return -ENOMEM;
 208
 209         priv->clk = devm_clk_get(dev, NULL);
 210         if (IS_ERR(priv->clk))
 211                 return PTR_ERR(priv->clk);
 212
 213         priv->nphys = of_get_child_count(dev->of_node);
 214         if (priv->nphys == 0)
 215                 return -ENODEV;
 216
 217         priv->phys = devm_kcalloc(dev, priv->nphys, sizeof(*priv->phys),
 218                                   GFP_KERNEL);
 219         if (!priv->phys)
 220                 return -ENOMEM;
 221
 222         if (of_device_is_compatible(dev->of_node, "marvell,berlin2-sata-phy"))
 223                 priv->phy_base = BG2_PHY_BASE;
 224         else
 225                 priv->phy_base = BG2Q_PHY_BASE;
 226
 227         dev_set_drvdata(dev, priv);
 228         spin_lock_init(&priv->lock);
 229
 230         for_each_available_child_of_node(dev->of_node, child) {
 231                 struct phy_berlin_desc *phy_desc;
 232
 233                 if (of_property_read_u32(child, "reg", &phy_id)) {
 234                         dev_err(dev, "missing reg property in node %pOFn\n",
 235                                 child);
 236                         ret = -EINVAL;
 237                         goto put_child;
 238                 }
 239
 240                 if (phy_id >= ARRAY_SIZE(phy_berlin_power_down_bits)) {
 241                         dev_err(dev, "invalid reg in node %pOFn\n", child);
 242                         ret = -EINVAL;
 243                         goto put_child;
 244                 }
 245
 246                 phy_desc = devm_kzalloc(dev, sizeof(*phy_desc), GFP_KERNEL);
 247                 if (!phy_desc) {
 248                         ret = -ENOMEM;
 249                         goto put_child;
 250                 }
 251
 252                 phy = devm_phy_create(dev, NULL, &phy_berlin_sata_ops);
 253                 if (IS_ERR(phy)) {
 254                         dev_err(dev, "failed to create PHY %d\n", phy_id);
 255                         ret = PTR_ERR(phy);
 256                         goto put_child;
 257                 }
 258
 259                 phy_desc->phy = phy;
 260                 phy_desc->power_bit = phy_berlin_power_down_bits[phy_id];
 261                 phy_desc->index = phy_id;
 262                 phy_set_drvdata(phy, phy_desc);
 263
 264                 priv->phys[i++] = phy_desc;
 265
 266                 /* Make sure the PHY is off */
 267                 phy_berlin_sata_power_off(phy);
 268         }
 269
 270         phy_provider =
 271                 devm_of_phy_provider_register(dev, phy_berlin_sata_phy_xlate);
 272         return PTR_ERR_OR_ZERO(phy_provider);
 273 put_child:
 274         of_node_put(child);
 275         return ret;
 276 }
 277
 278 static const struct of_device_id phy_berlin_sata_of_match[] = {
 279         { .compatible = "marvell,berlin2-sata-phy" },
 280         { .compatible = "marvell,berlin2q-sata-phy" },
 281         { },
 282 };
 283 MODULE_DEVICE_TABLE(of, phy_berlin_sata_of_match);
 284
 285 static struct platform_driver phy_berlin_sata_driver = {
 286         .probe  = phy_berlin_sata_probe,
 287         .driver = {
 288                 .name           = "phy-berlin-sata",
 289                 .of_match_table = phy_berlin_sata_of_match,
 290         },
 291 };
 292 module_platform_driver(phy_berlin_sata_driver);
 293
 294 MODULE_DESCRIPTION("Marvell Berlin SATA PHY driver");
 295 MODULE_AUTHOR("Antoine Ténart <antoine.tenart@free-electrons.com>");
 296 MODULE_LICENSE("GPL v2");