drivers/phy/phy-qcom-ufs-qmp-v3.c

   1 /*
   2  * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  */
  14
  15 #include "phy-qcom-ufs-qmp-v3.h"
  16
  17 #define UFS_PHY_NAME "ufs_phy_qmp_v3"
  18
  19 static
  20 int ufs_qcom_phy_qmp_v3_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy,
  21                                         bool is_rate_B)
  22 {
  23         int err;
  24         int tbl_size_A, tbl_size_B;
  25         struct ufs_qcom_phy_calibration *tbl_A, *tbl_B;
  26         u8 major = ufs_qcom_phy->host_ctrl_rev_major;
  27         u16 minor = ufs_qcom_phy->host_ctrl_rev_minor;
  28         u16 step = ufs_qcom_phy->host_ctrl_rev_step;
  29
  30         tbl_size_B = ARRAY_SIZE(phy_cal_table_rate_B);
  31         tbl_B = phy_cal_table_rate_B;
  32
  33         if ((major == 0x3) && (minor == 0x000) && (step == 0x0000)) {
  34                 tbl_A = phy_cal_table_rate_A_3_0_0;
  35                 tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A_3_0_0);
  36         } else if ((major == 0x3) && (minor == 0x001) && (step == 0x0000)) {
  37                 tbl_A = phy_cal_table_rate_A_3_1_0;
  38                 tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A_3_1_0);
  39         } else {
  40                 dev_err(ufs_qcom_phy->dev,
  41                         "%s: Unknown UFS-PHY version (major 0x%x minor 0x%x step 0x%x), no calibration values\n",
  42                         __func__, major, minor, step);
  43                 err = -ENODEV;
  44                 goto out;
  45         }
  46
  47         err = ufs_qcom_phy_calibrate(ufs_qcom_phy,
  48                                      tbl_A, tbl_size_A,
  49                                      tbl_B, tbl_size_B,
  50                                      is_rate_B);
  51
  52         if (err)
  53                 dev_err(ufs_qcom_phy->dev,
  54                         "%s: ufs_qcom_phy_calibrate() failed %d\n",
  55                         __func__, err);
  56
  57 out:
  58         return err;
  59 }
  60
  61 static int ufs_qcom_phy_qmp_v3_init(struct phy *generic_phy)
  62 {
  63         struct ufs_qcom_phy_qmp_v3 *phy = phy_get_drvdata(generic_phy);
  64         struct ufs_qcom_phy *phy_common = &phy->common_cfg;
  65         int err;
  66
  67         err = ufs_qcom_phy_init_clks(generic_phy, phy_common);
  68         if (err) {
  69                 dev_err(phy_common->dev, "%s: ufs_qcom_phy_init_clks() failed %d\n",
  70                         __func__, err);
  71                 goto out;
  72         }
  73
  74         err = ufs_qcom_phy_init_vregulators(generic_phy, phy_common);
  75         if (err) {
  76                 dev_err(phy_common->dev, "%s: ufs_qcom_phy_init_vregulators() failed %d\n",
  77                         __func__, err);
  78                 goto out;
  79         }
  80
  81 out:
  82         return err;
  83 }
  84
  85 static
  86 void ufs_qcom_phy_qmp_v3_power_control(struct ufs_qcom_phy *phy,
  87                                          bool power_ctrl)
  88 {
  89         if (!power_ctrl) {
  90                 /* apply analog power collapse */
  91                 writel_relaxed(0x0, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL);
  92                 /*
  93                  * Make sure that PHY knows its analog rail is going to be
  94                  * powered OFF.
  95                  */
  96                 mb();
  97         } else {
  98                 /* bring PHY out of analog power collapse */
  99                 writel_relaxed(0x1, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL);
 100
 101                 /*
 102                  * Before any transactions involving PHY, ensure PHY knows
 103                  * that it's analog rail is powered ON.
 104                  */
 105                 mb();
 106         }
 107 }
 108
 109 static inline
 110 void ufs_qcom_phy_qmp_v3_set_tx_lane_enable(struct ufs_qcom_phy *phy, u32 val)
 111 {
 112         /*
 113          * v3 PHY does not have TX_LANE_ENABLE register.
 114          * Implement this function so as not to propagate error to caller.
 115          */
 116 }
 117
 118 static
 119 void ufs_qcom_phy_qmp_v3_ctrl_rx_linecfg(struct ufs_qcom_phy *phy, bool ctrl)
 120 {
 121         u32 temp;
 122
 123         temp = readl_relaxed(phy->mmio + UFS_PHY_LINECFG_DISABLE);
 124
 125         if (ctrl) /* enable RX LineCfg */
 126                 temp &= ~UFS_PHY_RX_LINECFG_DISABLE_BIT;
 127         else /* disable RX LineCfg */
 128                 temp |= UFS_PHY_RX_LINECFG_DISABLE_BIT;
 129
 130         writel_relaxed(temp, phy->mmio + UFS_PHY_LINECFG_DISABLE);
 131         /* make sure that RX LineCfg config applied before we return */
 132         mb();
 133 }
 134
 135 static inline void ufs_qcom_phy_qmp_v3_start_serdes(struct ufs_qcom_phy *phy)
 136 {
 137         u32 tmp;
 138
 139         tmp = readl_relaxed(phy->mmio + UFS_PHY_PHY_START);
 140         tmp &= ~MASK_SERDES_START;
 141         tmp |= (1 << OFFSET_SERDES_START);
 142         writel_relaxed(tmp, phy->mmio + UFS_PHY_PHY_START);
 143         /* Ensure register value is committed */
 144         mb();
 145 }
 146
 147 static int ufs_qcom_phy_qmp_v3_is_pcs_ready(struct ufs_qcom_phy *phy_common)
 148 {
 149         int err = 0;
 150         u32 val;
 151
 152         err = readl_poll_timeout(phy_common->mmio + UFS_PHY_PCS_READY_STATUS,
 153                 val, (val & MASK_PCS_READY), 10, 1000000);
 154         if (err) {
 155                 dev_err(phy_common->dev, "%s: poll for pcs failed err = %d\n",
 156                         __func__, err);
 157                 goto out;
 158         }
 159
 160 out:
 161         return err;
 162 }
 163
 164 static
 165 int ufs_qcom_phy_qmp_v3_configure_lpm(struct ufs_qcom_phy *ufs_qcom_phy,
 166                                         bool enable)
 167 {
 168         int err = 0;
 169         int tbl_size;
 170         struct ufs_qcom_phy_calibration *tbl = NULL;
 171
 172         /* The default low power mode configuration is SVS2 */
 173         if (enable) {
 174                 tbl_size = ARRAY_SIZE(phy_cal_table_svs2_enable);
 175                 tbl = phy_cal_table_svs2_enable;
 176         } else {
 177                 tbl_size = ARRAY_SIZE(phy_cal_table_svs2_disable);
 178                 tbl = phy_cal_table_svs2_disable;
 179         }
 180
 181         if (!tbl) {
 182                 dev_err(ufs_qcom_phy->dev, "%s: tbl for SVS2 %s is NULL",
 183                         __func__, enable ? "enable" : "disable");
 184                 err = -EINVAL;
 185                 goto out;
 186         }
 187
 188         ufs_qcom_phy_write_tbl(ufs_qcom_phy, tbl, tbl_size);
 189
 190         /* flush buffered writes */
 191         mb();
 192
 193 out:
 194         return err;
 195 }
 196
 197 static void ufs_qcom_phy_qmp_v3_dbg_register_dump(struct ufs_qcom_phy *phy)
 198 {
 199         ufs_qcom_phy_dump_regs(phy, COM_BASE, COM_SIZE,
 200                                         "PHY QSERDES COM Registers ");
 201         ufs_qcom_phy_dump_regs(phy, PHY_BASE, PHY_SIZE,
 202                                         "PHY Registers ");
 203         ufs_qcom_phy_dump_regs(phy, RX_BASE(0), RX_SIZE,
 204                                         "PHY RX0 Registers ");
 205         ufs_qcom_phy_dump_regs(phy, TX_BASE(0), TX_SIZE,
 206                                         "PHY TX0 Registers ");
 207         ufs_qcom_phy_dump_regs(phy, RX_BASE(1), RX_SIZE,
 208                                         "PHY RX1 Registers ");
 209         ufs_qcom_phy_dump_regs(phy, TX_BASE(1), TX_SIZE,
 210                                         "PHY TX1 Registers ");
 211 }
 212
 213 struct phy_ops ufs_qcom_phy_qmp_v3_phy_ops = {
 214         .init           = ufs_qcom_phy_qmp_v3_init,
 215         .exit           = ufs_qcom_phy_exit,
 216         .power_on       = ufs_qcom_phy_power_on,
 217         .power_off      = ufs_qcom_phy_power_off,
 218         .owner          = THIS_MODULE,
 219 };
 220
 221 struct ufs_qcom_phy_specific_ops phy_v3_ops = {
 222         .calibrate_phy          = ufs_qcom_phy_qmp_v3_phy_calibrate,
 223         .start_serdes           = ufs_qcom_phy_qmp_v3_start_serdes,
 224         .is_physical_coding_sublayer_ready = ufs_qcom_phy_qmp_v3_is_pcs_ready,
 225         .set_tx_lane_enable     = ufs_qcom_phy_qmp_v3_set_tx_lane_enable,
 226         .ctrl_rx_linecfg        = ufs_qcom_phy_qmp_v3_ctrl_rx_linecfg,
 227         .power_control          = ufs_qcom_phy_qmp_v3_power_control,
 228         .configure_lpm          = ufs_qcom_phy_qmp_v3_configure_lpm,
 229         .dbg_register_dump      = ufs_qcom_phy_qmp_v3_dbg_register_dump,
 230 };
 231
 232 static int ufs_qcom_phy_qmp_v3_probe(struct platform_device *pdev)
 233 {
 234         struct device *dev = &pdev->dev;
 235         struct phy *generic_phy;
 236         struct ufs_qcom_phy_qmp_v3 *phy;
 237         int err = 0;
 238
 239         phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
 240         if (!phy) {
 241                 err = -ENOMEM;
 242                 goto out;
 243         }
 244
 245         generic_phy = ufs_qcom_phy_generic_probe(pdev, &phy->common_cfg,
 246                                 &ufs_qcom_phy_qmp_v3_phy_ops, &phy_v3_ops);
 247
 248         if (!generic_phy) {
 249                 dev_err(dev, "%s: ufs_qcom_phy_generic_probe() failed\n",
 250                         __func__);
 251                 err = -EIO;
 252                 goto out;
 253         }
 254
 255         phy_set_drvdata(generic_phy, phy);
 256
 257         strlcpy(phy->common_cfg.name, UFS_PHY_NAME,
 258                 sizeof(phy->common_cfg.name));
 259
 260 out:
 261         return err;
 262 }
 263
 264 static int ufs_qcom_phy_qmp_v3_remove(struct platform_device *pdev)
 265 {
 266         struct device *dev = &pdev->dev;
 267         struct phy *generic_phy = to_phy(dev);
 268         struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
 269         int err = 0;
 270
 271         err = ufs_qcom_phy_remove(generic_phy, ufs_qcom_phy);
 272         if (err)
 273                 dev_err(dev, "%s: ufs_qcom_phy_remove failed = %d\n",
 274                         __func__, err);
 275
 276         return err;
 277 }
 278
 279 static const struct of_device_id ufs_qcom_phy_qmp_v3_of_match[] = {
 280         {.compatible = "qcom,ufs-phy-qmp-v3"},
 281         {},
 282 };
 283 MODULE_DEVICE_TABLE(of, ufs_qcom_phy_qmp_v3_of_match);
 284
 285 static struct platform_driver ufs_qcom_phy_qmp_v3_driver = {
 286         .probe = ufs_qcom_phy_qmp_v3_probe,
 287         .remove = ufs_qcom_phy_qmp_v3_remove,
 288         .driver = {
 289                 .of_match_table = ufs_qcom_phy_qmp_v3_of_match,
 290                 .name = "ufs_qcom_phy_qmp_v3",
 291                 .owner = THIS_MODULE,
 292         },
 293 };
 294
 295 module_platform_driver(ufs_qcom_phy_qmp_v3_driver);
 296
 297 MODULE_DESCRIPTION("Universal Flash Storage (UFS) QCOM PHY QMP v3");
 298 MODULE_LICENSE("GPL v2");