drivers/phy/phy-qcom-ufs-qmp-v3.h

   1 /*
   2  * Copyright (c) 2013-2017, The Linux Foundation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  */
  14
  15 #ifndef UFS_QCOM_PHY_QMP_V3_H_
  16 #define UFS_QCOM_PHY_QMP_V3_H_
  17
  18 #include "phy-qcom-ufs-i.h"
  19
  20 /* QCOM UFS PHY control registers */
  21 #define COM_BASE        0x000
  22 #define COM_SIZE        0x18C
  23 #define PHY_BASE        0xC00
  24 #define PHY_SIZE        0x1DC
  25 #define TX_BASE(n)      (0x400 + (0x400 * n))
  26 #define TX_SIZE         0x128
  27 #define RX_BASE(n)      (0x600 + (0x400 * n))
  28 #define RX_SIZE         0x1FC
  29 #define COM_OFF(x)      (COM_BASE + x)
  30 #define PHY_OFF(x)      (PHY_BASE + x)
  31 #define TX_OFF(n, x)    (TX_BASE(n) + x)
  32 #define RX_OFF(n, x)    (RX_BASE(n) + x)
  33
  34 /* UFS PHY QSERDES COM registers */
  35 #define QSERDES_COM_ATB_SEL1                    COM_OFF(0x00)
  36 #define QSERDES_COM_ATB_SEL2                    COM_OFF(0x04)
  37 #define QSERDES_COM_FREQ_UPDATE                 COM_OFF(0x08)
  38 #define QSERDES_COM_BG_TIMER                    COM_OFF(0x0C)
  39 #define QSERDES_COM_SSC_EN_CENTER               COM_OFF(0x10)
  40 #define QSERDES_COM_SSC_ADJ_PER1                COM_OFF(0x14)
  41 #define QSERDES_COM_SSC_ADJ_PER2                COM_OFF(0x18)
  42 #define QSERDES_COM_SSC_PER1                    COM_OFF(0x1C)
  43 #define QSERDES_COM_SSC_PER2                    COM_OFF(0x20)
  44 #define QSERDES_COM_SSC_STEP_SIZE1              COM_OFF(0x24)
  45 #define QSERDES_COM_SSC_STEP_SIZE2              COM_OFF(0x28)
  46 #define QSERDES_COM_POST_DIV                    COM_OFF(0x2C)
  47 #define QSERDES_COM_POST_DIV_MUX                COM_OFF(0x30)
  48 #define QSERDES_COM_BIAS_EN_CLKBUFLR_EN         COM_OFF(0x34)
  49 #define QSERDES_COM_CLK_ENABLE1                 COM_OFF(0x38)
  50 #define QSERDES_COM_SYS_CLK_CTRL                COM_OFF(0x3C)
  51 #define QSERDES_COM_SYSCLK_BUF_ENABLE           COM_OFF(0x40)
  52 #define QSERDES_COM_PLL_EN                      COM_OFF(0x44)
  53 #define QSERDES_COM_PLL_IVCO                    COM_OFF(0x48)
  54 #define QSERDES_COM_CMN_IETRIM                  COM_OFF(0x4C)
  55 #define QSERDES_COM_CMN_IPTRIM                  COM_OFF(0x50)
  56 #define QSERDES_COM_EP_CLOCK_DETECT_CTR         COM_OFF(0x54)
  57 #define QSERDES_COM_SYSCLK_DET_COMP_STATUS      COM_OFF(0x58)
  58 #define QSERDES_COM_CLK_EP_DIV                  COM_OFF(0x5C)
  59 #define QSERDES_COM_CP_CTRL_MODE0               COM_OFF(0x60)
  60 #define QSERDES_COM_CP_CTRL_MODE1               COM_OFF(0x64)
  61 #define QSERDES_COM_PLL_RCTRL_MODE0             COM_OFF(0x68)
  62 #define QSERDES_COM_PLL_RCTRL_MODE1             COM_OFF(0x6C)
  63 #define QSERDES_COM_PLL_CCTRL_MODE0             COM_OFF(0x70)
  64 #define QSERDES_COM_PLL_CCTRL_MODE1             COM_OFF(0x74)
  65 #define QSERDES_COM_PLL_CNTRL                   COM_OFF(0x78)
  66 #define SERDES_COM_BIAS_EN_CTRL_BY_PSM          COM_OFF(0x7C)
  67 #define QSERDES_COM_SYSCLK_EN_SEL               COM_OFF(0x80)
  68 #define QSERDES_COM_CML_SYSCLK_SEL              COM_OFF(0x84)
  69 #define QSERDES_COM_RESETSM_CNTRL               COM_OFF(0x88)
  70 #define QSERDES_COM_RESETSM_CNTRL2              COM_OFF(0x8C)
  71 #define QSERDES_COM_LOCK_CMP_EN                 COM_OFF(0x90)
  72 #define QSERDES_COM_LOCK_CMP_CFG                COM_OFF(0x94)
  73 #define QSERDES_COM_LOCK_CMP1_MODE0             COM_OFF(0x98)
  74 #define QSERDES_COM_LOCK_CMP2_MODE0             COM_OFF(0x9C)
  75 #define QSERDES_COM_LOCK_CMP3_MODE0             COM_OFF(0xA0)
  76 #define QSERDES_COM_LOCK_CMP1_MODE1             COM_OFF(0xA4)
  77 #define QSERDES_COM_LOCK_CMP2_MODE1             COM_OFF(0xA8)
  78 #define QSERDES_COM_LOCK_CMP3_MODE1             COM_OFF(0xAC)
  79 #define QSERDES_COM_DEC_START_MODE0             COM_OFF(0xB0)
  80 #define QSERDES_COM_DEC_START_MODE1             COM_OFF(0xB4)
  81 #define QSERDES_COM_DIV_FRAC_START1_MODE0       COM_OFF(0xB8)
  82 #define QSERDES_COM_DIV_FRAC_START2_MODE0       COM_OFF(0xBC)
  83 #define QSERDES_COM_DIV_FRAC_START3_MODE0       COM_OFF(0xC0)
  84 #define QSERDES_COM_DIV_FRAC_START1_MODE1       COM_OFF(0xC4)
  85 #define QSERDES_COM_DIV_FRAC_START2_MODE1       COM_OFF(0xC8)
  86 #define QSERDES_COM_DIV_FRAC_START3_MODE1       COM_OFF(0xCC)
  87 #define QSERDES_COM_INTEGLOOP_INITVAL           COM_OFF(0xD0)
  88 #define QSERDES_COM_INTEGLOOP_EN                COM_OFF(0xD4)
  89 #define QSERDES_COM_INTEGLOOP_GAIN0_MODE0       COM_OFF(0xD8)
  90 #define QSERDES_COM_INTEGLOOP_GAIN1_MODE0       COM_OFF(0xDC)
  91 #define QSERDES_COM_INTEGLOOP_GAIN0_MODE1       COM_OFF(0xE0)
  92 #define QSERDES_COM_INTEGLOOP_GAIN1_MODE1       COM_OFF(0xE4)
  93 #define QSERDES_COM_VCOCAL_DEADMAN_CTRL         COM_OFF(0xE8)
  94 #define QSERDES_COM_VCO_TUNE_CTRL               COM_OFF(0xEC)
  95 #define QSERDES_COM_VCO_TUNE_MAP                COM_OFF(0xF0)
  96 #define QSERDES_COM_VCO_TUNE1_MODE0             COM_OFF(0xF4)
  97 #define QSERDES_COM_VCO_TUNE2_MODE0             COM_OFF(0xF8)
  98 #define QSERDES_COM_VCO_TUNE1_MODE1             COM_OFF(0xFC)
  99 #define QSERDES_COM_VCO_TUNE2_MODE1             COM_OFF(0x100)
 100 #define QSERDES_COM_VCO_TUNE_INITVAL1           COM_OFF(0x104)
 101 #define QSERDES_COM_VCO_TUNE_INITVAL2           COM_OFF(0x108)
 102 #define QSERDES_COM_VCO_TUNE_MINVAL1            COM_OFF(0x10C)
 103 #define QSERDES_COM_VCO_TUNE_MINVAL2            COM_OFF(0x110)
 104 #define QSERDES_COM_VCO_TUNE_MAXVAL1            COM_OFF(0x114)
 105 #define QSERDES_COM_VCO_TUNE_MAXVAL2            COM_OFF(0x118)
 106 #define QSERDES_COM_VCO_TUNE_TIMER1             COM_OFF(0x11C)
 107 #define QSERDES_COM_VCO_TUNE_TIMER2             COM_OFF(0x120)
 108 #define QSERDES_COM_CMN_STATUS                  COM_OFF(0x124)
 109 #define QSERDES_COM_RESET_SM_STATUS             COM_OFF(0x128)
 110 #define QSERDES_COM_RESTRIM_CODE_STATUS         COM_OFF(0x12C)
 111 #define QSERDES_COM_PLLCAL_CODE1_STATUS         COM_OFF(0x130)
 112 #define QSERDES_COM_PLLCAL_CODE2_STATUS         COM_OFF(0x134)
 113 #define QSERDES_COM_CLK_SELECT                  COM_OFF(0x138)
 114 #define QSERDES_COM_HSCLK_SEL                   COM_OFF(0x13C)
 115 #define QSERDES_COM_INTEGLOOP_BINCODE_STATUS    COM_OFF(0x140)
 116 #define QSERDES_COM_PLL_ANALOG                  COM_OFF(0x144)
 117 #define QSERDES_COM_CORECLK_DIV_MODE0           COM_OFF(0x148)
 118 #define QSERDES_COM_CORECLK_DIV_MODE1           COM_OFF(0x14C)
 119 #define QSERDES_COM_SW_RESET                    COM_OFF(0x150)
 120 #define QSERDES_COM_CORE_CLK_EN                 COM_OFF(0x154)
 121 #define QSERDES_COM_C_READY_STATUS              COM_OFF(0x158)
 122 #define QSERDES_COM_CMN_CONFIG                  COM_OFF(0x15C)
 123 #define QSERDES_COM_CMN_RATE_OVERRIDE           COM_OFF(0x160)
 124 #define QSERDES_COM_SVS_MODE_CLK_SEL            COM_OFF(0x164)
 125 #define QSERDES_COM_DEBUG_BUS0                  COM_OFF(0x168)
 126 #define QSERDES_COM_DEBUG_BUS1                  COM_OFF(0x16C)
 127 #define QSERDES_COM_DEBUG_BUS2                  COM_OFF(0x170)
 128 #define QSERDES_COM_DEBUG_BUS3                  COM_OFF(0x174)
 129 #define QSERDES_COM_DEBUG_BUS_SEL               COM_OFF(0x178)
 130 #define QSERDES_COM_CMN_MISC1                   COM_OFF(0x17C)
 131 #define QSERDES_COM_CMN_MISC2                   COM_OFF(0x180)
 132 #define QSERDES_COM_CMN_MODE                    COM_OFF(0x184)
 133 #define QSERDES_COM_CMN_VREG_SEL                COM_OFF(0x188)
 134
 135 /* UFS PHY registers */
 136 #define UFS_PHY_PHY_START                       PHY_OFF(0x00)
 137 #define UFS_PHY_POWER_DOWN_CONTROL              PHY_OFF(0x04)
 138 #define UFS_PHY_TIMER_20US_CORECLK_STEPS_MSB    PHY_OFF(0x08)
 139 #define UFS_PHY_TIMER_20US_CORECLK_STEPS_LSB    PHY_OFF(0x0C)
 140 #define UFS_PHY_TX_LARGE_AMP_DRV_LVL            PHY_OFF(0x2C)
 141 #define UFS_PHY_TX_SMALL_AMP_DRV_LVL            PHY_OFF(0x34)
 142 #define UFS_PHY_LINECFG_DISABLE                 PHY_OFF(0x130)
 143 #define UFS_PHY_RX_SYM_RESYNC_CTRL              PHY_OFF(0x134)
 144 #define UFS_PHY_RX_MIN_HIBERN8_TIME             PHY_OFF(0x138)
 145 #define UFS_PHY_RX_SIGDET_CTRL1                 PHY_OFF(0x13C)
 146 #define UFS_PHY_RX_SIGDET_CTRL2                 PHY_OFF(0x140)
 147 #define UFS_PHY_RX_PWM_GEAR_BAND                PHY_OFF(0x14C)
 148 #define UFS_PHY_PCS_READY_STATUS                PHY_OFF(0x160)
 149 #define UFS_PHY_TX_MID_TERM_CTRL1               PHY_OFF(0x1BC)
 150 #define UFS_PHY_MULTI_LANE_CTRL1                PHY_OFF(0x1C4)
 151
 152 /* UFS PHY TX registers */
 153 #define QSERDES_TX0_TRANSCEIVER_BIAS_EN         TX_OFF(0, 0x5C)
 154 #define QSERDES_TX0_LANE_MODE_1                 TX_OFF(0, 0x8C)
 155 #define QSERDES_TX0_LANE_MODE_2                 TX_OFF(0, 0x90)
 156 #define QSERDES_TX0_LANE_MODE_3                 TX_OFF(0, 0x94)
 157
 158 #define QSERDES_TX1_LANE_MODE_1                 TX_OFF(1, 0x8C)
 159
 160
 161 /* UFS PHY RX registers */
 162 #define QSERDES_RX0_UCDR_SVS_SO_GAIN_HALF               RX_OFF(0, 0x24)
 163 #define QSERDES_RX0_UCDR_SVS_SO_GAIN_QUARTER            RX_OFF(0, 0x28)
 164 #define QSERDES_RX0_UCDR_SVS_SO_GAIN                    RX_OFF(0, 0x2C)
 165 #define QSERDES_RX0_UCDR_FASTLOCK_FO_GAIN               RX_OFF(0, 0x30)
 166 #define QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE       RX_OFF(0, 0x34)
 167 #define QSERDES_RX0_UCDR_FASTLOCK_COUNT_LOW             RX_OFF(0, 0x3C)
 168 #define QSERDES_RX0_UCDR_PI_CONTROLS                    RX_OFF(0, 0x44)
 169 #define QSERDES_RX0_RX_TERM_BW                          RX_OFF(0, 0x7C)
 170 #define QSERDES_RX0_RX_EQ_GAIN2_LSB                     RX_OFF(0, 0xC8)
 171 #define QSERDES_RX0_RX_EQ_GAIN2_MSB                     RX_OFF(0, 0xCC)
 172 #define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL1               RX_OFF(0, 0xD0)
 173 #define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2               RX_OFF(0, 0xD4)
 174 #define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3               RX_OFF(0, 0xD8)
 175 #define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4               RX_OFF(0, 0xDC)
 176 #define QSERDES_RX0_SIGDET_CNTRL                        RX_OFF(0, 0x104)
 177 #define QSERDES_RX0_SIGDET_LVL                          RX_OFF(0, 0x108)
 178 #define QSERDES_RX0_SIGDET_DEGLITCH_CNTRL               RX_OFF(0, 0x10C)
 179 #define QSERDES_RX0_RX_INTERFACE_MODE                   RX_OFF(0, 0x11C)
 180
 181 #define QSERDES_RX1_UCDR_SVS_SO_GAIN_HALF               RX_OFF(1, 0x24)
 182 #define QSERDES_RX1_UCDR_SVS_SO_GAIN_QUARTER            RX_OFF(1, 0x28)
 183 #define QSERDES_RX1_UCDR_SVS_SO_GAIN                    RX_OFF(1, 0x2C)
 184 #define QSERDES_RX1_UCDR_FASTLOCK_FO_GAIN               RX_OFF(1, 0x30)
 185 #define QSERDES_RX1_UCDR_SO_SATURATION_AND_ENABLE       RX_OFF(1, 0x34)
 186 #define QSERDES_RX1_UCDR_FASTLOCK_COUNT_LOW             RX_OFF(1, 0x3C)
 187 #define QSERDES_RX1_UCDR_PI_CONTROLS                    RX_OFF(1, 0x44)
 188 #define QSERDES_RX1_RX_TERM_BW                          RX_OFF(1, 0x7C)
 189 #define QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL2               RX_OFF(1, 0xD4)
 190 #define QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL3               RX_OFF(1, 0xD8)
 191 #define QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL4               RX_OFF(1, 0xDC)
 192 #define QSERDES_RX1_SIGDET_CNTRL                        RX_OFF(1, 0x104)
 193 #define QSERDES_RX1_SIGDET_LVL                          RX_OFF(1, 0x108)
 194 #define QSERDES_RX1_SIGDET_DEGLITCH_CNTRL               RX_OFF(1, 0x10C)
 195 #define QSERDES_RX1_RX_INTERFACE_MODE                   RX_OFF(1, 0x11C)
 196
 197 #define UFS_PHY_RX_LINECFG_DISABLE_BIT          BIT(1)
 198
 199 /*
 200  * This structure represents the v3 specific phy.
 201  * common_cfg MUST remain the first field in this structure
 202  * in case extra fields are added. This way, when calling
 203  * get_ufs_qcom_phy() of generic phy, we can extract the
 204  * common phy structure (struct ufs_qcom_phy) out of it
 205  * regardless of the relevant specific phy.
 206  */
 207 struct ufs_qcom_phy_qmp_v3 {
 208         struct ufs_qcom_phy common_cfg;
 209 };
 210
 211 static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_3_0_0[] = {
 212         UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01),
 213         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CMN_CONFIG, 0x06),
 214         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL, 0xD5),
 215         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CLK_SELECT, 0x30),
 216         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYS_CLK_CTRL, 0x02),
 217         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
 218         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BG_TIMER, 0x0A),
 219         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_HSCLK_SEL, 0x00),
 220         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP_EN, 0x01),
 221         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
 222         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORE_CLK_EN, 0x00),
 223         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x04),
 224         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
 225         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IVCO, 0x0F),
 226         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_INITVAL1, 0xFF),
 227         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
 228         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE0, 0x82),
 229         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE0, 0x08),
 230         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 231         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE0, 0x34),
 232         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x3F),
 233         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 234         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE1_MODE0, 0xCB),
 235         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE2_MODE0, 0x01),
 236         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE0, 0xFF),
 237         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE0, 0x0C),
 238         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE1, 0x98),
 239         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE1, 0x08),
 240         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
 241         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE1, 0x34),
 242         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x3F),
 243         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
 244         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE1_MODE1, 0xB2),
 245         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
 246         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
 247         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE1, 0x0F),
 248         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_LANE_MODE_1, 0x06),
 249         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_SIGDET_LVL, 0x24),
 250         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_SIGDET_CNTRL, 0x0F),
 251         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x1E),
 252         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_INTERFACE_MODE, 0x40),
 253         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FASTLOCK_FO_GAIN, 0x0B),
 254         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_TERM_BW, 0x5B),
 255         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x06),
 256         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
 257         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1D),
 258         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SVS_SO_GAIN_HALF, 0x04),
 259         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
 260         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SVS_SO_GAIN, 0x04),
 261         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x4B),
 262         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_PI_CONTROLS, 0x81),
 263         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FASTLOCK_COUNT_LOW, 0x80),
 264         UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL2, 0x6E),
 265         UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_DRV_LVL, 0x0A),
 266         UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_SMALL_AMP_DRV_LVL, 0x02),
 267         UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SYM_RESYNC_CTRL, 0x03),
 268         UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_MIN_HIBERN8_TIME, 0x9A), /* 8 us */
 269 };
 270
 271 static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_3_1_0[] = {
 272         UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01),
 273         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CMN_CONFIG, 0x06),
 274         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL, 0xD5),
 275         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL, 0x20),
 276         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CLK_SELECT, 0x30),
 277         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYS_CLK_CTRL, 0x02),
 278         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
 279         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BG_TIMER, 0x0A),
 280         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_HSCLK_SEL, 0x00),
 281         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP_EN, 0x01),
 282         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
 283         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORE_CLK_EN, 0x00),
 284         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x04),
 285         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
 286         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IVCO, 0x0F),
 287         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_INITVAL1, 0xFF),
 288         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
 289         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE0, 0x82),
 290         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE0, 0x06),
 291         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 292         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE0, 0x36),
 293         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x3F),
 294         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 295         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE1_MODE0, 0xDA),
 296         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE2_MODE0, 0x01),
 297         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE0, 0xFF),
 298         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE0, 0x0C),
 299         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE1, 0x98),
 300         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE1, 0x06),
 301         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
 302         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE1, 0x36),
 303         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x3F),
 304         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
 305         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE1_MODE1, 0xC1),
 306         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
 307         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
 308         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE1, 0x0F),
 309         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_LANE_MODE_1, 0x06),
 310         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_SIGDET_LVL, 0x24),
 311         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_SIGDET_CNTRL, 0x0F),
 312         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x1E),
 313         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_INTERFACE_MODE, 0x40),
 314         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FASTLOCK_FO_GAIN, 0x0B),
 315         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_TERM_BW, 0x5B),
 316         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x06),
 317         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
 318         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1D),
 319         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SVS_SO_GAIN_HALF, 0x04),
 320         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
 321         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SVS_SO_GAIN, 0x04),
 322         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x4B),
 323         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_PI_CONTROLS, 0x81),
 324         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FASTLOCK_COUNT_LOW, 0x80),
 325         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_LANE_MODE_1, 0x06),
 326         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_SIGDET_LVL, 0x24),
 327         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_SIGDET_CNTRL, 0x0F),
 328         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_SIGDET_DEGLITCH_CNTRL, 0x1E),
 329         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_INTERFACE_MODE, 0x40),
 330         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FASTLOCK_FO_GAIN, 0x0B),
 331         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_TERM_BW, 0x5B),
 332         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL2, 0x06),
 333         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL3, 0x04),
 334         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL4, 0x1D),
 335         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_SVS_SO_GAIN_HALF, 0x04),
 336         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
 337         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_SVS_SO_GAIN, 0x04),
 338         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_SO_SATURATION_AND_ENABLE, 0x4B),
 339         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_PI_CONTROLS, 0x81),
 340         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FASTLOCK_COUNT_LOW, 0x80),
 341         UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_MULTI_LANE_CTRL1, 0x02),
 342         UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL2, 0x6E),
 343         UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_DRV_LVL, 0x0A),
 344         UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_SMALL_AMP_DRV_LVL, 0x02),
 345         UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SYM_RESYNC_CTRL, 0x03),
 346         UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_MID_TERM_CTRL1, 0x43),
 347         UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL1, 0x0F),
 348         UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_MIN_HIBERN8_TIME, 0x9A), /* 8 us */
 349 };
 350
 351 static struct ufs_qcom_phy_calibration phy_cal_table_rate_B[] = {
 352         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x44),
 353 };
 354
 355 static struct ufs_qcom_phy_calibration phy_cal_table_svs2_enable[] = {
 356         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORECLK_DIV_MODE0, 0x14),
 357         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORECLK_DIV_MODE1, 0x14),
 358         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SVS_MODE_CLK_SEL, 0x0a),
 359         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x7e),
 360         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 361         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE0, 0x7f),
 362         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE0, 0x06),
 363         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x7e),
 364         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
 365         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE1, 0x99),
 366         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE1, 0x07),
 367         UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TIMER_20US_CORECLK_STEPS_MSB, 0x0b),
 368         UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TIMER_20US_CORECLK_STEPS_LSB, 0x66),
 369 };
 370
 371 static struct ufs_qcom_phy_calibration phy_cal_table_svs2_disable[] = {
 372         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORECLK_DIV_MODE0, 0x0a),
 373         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
 374         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
 375         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 376         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 377         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
 378         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
 379         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
 380         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
 381         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
 382         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
 383         UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
 384         UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TIMER_20US_CORECLK_STEPS_LSB, 0xcc),
 385 };
 386
 387 #endif