drivers/phy/phy-ti-pipe3.c

   1 /*
   2  * phy-ti-pipe3 - PIPE3 PHY driver.
   3  *
   4  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * Author: Kishon Vijay Abraham I <kishon@ti.com>
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  */
  18
  19 #include <linux/module.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/slab.h>
  22 #include <linux/phy/phy.h>
  23 #include <linux/of.h>
  24 #include <linux/clk.h>
  25 #include <linux/err.h>
  26 #include <linux/io.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/delay.h>
  29 #include <linux/phy/omap_control_phy.h>
  30 #include <linux/of_platform.h>
  31 #include <linux/spinlock.h>
  32
  33 #define PLL_STATUS              0x00000004
  34 #define PLL_GO                  0x00000008
  35 #define PLL_CONFIGURATION1      0x0000000C
  36 #define PLL_CONFIGURATION2      0x00000010
  37 #define PLL_CONFIGURATION3      0x00000014
  38 #define PLL_CONFIGURATION4      0x00000020
  39
  40 #define PLL_REGM_MASK           0x001FFE00
  41 #define PLL_REGM_SHIFT          0x9
  42 #define PLL_REGM_F_MASK         0x0003FFFF
  43 #define PLL_REGM_F_SHIFT        0x0
  44 #define PLL_REGN_MASK           0x000001FE
  45 #define PLL_REGN_SHIFT          0x1
  46 #define PLL_SELFREQDCO_MASK     0x0000000E
  47 #define PLL_SELFREQDCO_SHIFT    0x1
  48 #define PLL_SD_MASK             0x0003FC00
  49 #define PLL_SD_SHIFT            10
  50 #define SET_PLL_GO              0x1
  51 #define PLL_LDOPWDN             BIT(15)
  52 #define PLL_TICOPWDN            BIT(16)
  53 #define PLL_LOCK                0x2
  54 #define PLL_IDLE                0x1
  55
  56 /*
  57  * This is an Empirical value that works, need to confirm the actual
  58  * value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status
  59  * to be correctly reflected in the PIPE3PHY_PLL_STATUS register.
  60  */
  61 #define PLL_IDLE_TIME   100     /* in milliseconds */
  62 #define PLL_LOCK_TIME   100     /* in milliseconds */
  63
  64 struct pipe3_dpll_params {
  65         u16     m;
  66         u8      n;
  67         u8      freq:3;
  68         u8      sd;
  69         u32     mf;
  70 };
  71
  72 struct pipe3_dpll_map {
  73         unsigned long rate;
  74         struct pipe3_dpll_params params;
  75 };
  76
  77 struct ti_pipe3 {
  78         void __iomem            *pll_ctrl_base;
  79         struct device           *dev;
  80         struct device           *control_dev;
  81         struct clk              *wkupclk;
  82         struct clk              *sys_clk;
  83         struct clk              *refclk;
  84         struct clk              *div_clk;
  85         struct pipe3_dpll_map   *dpll_map;
  86         bool                    enabled;
  87         spinlock_t              lock;   /* serialize clock enable/disable */
  88 };
  89
  90 static struct pipe3_dpll_map dpll_map_usb[] = {
  91         {12000000, {1250, 5, 4, 20, 0} },       /* 12 MHz */
  92         {16800000, {3125, 20, 4, 20, 0} },      /* 16.8 MHz */
  93         {19200000, {1172, 8, 4, 20, 65537} },   /* 19.2 MHz */
  94         {20000000, {1000, 7, 4, 10, 0} },       /* 20 MHz */
  95         {26000000, {1250, 12, 4, 20, 0} },      /* 26 MHz */
  96         {38400000, {3125, 47, 4, 20, 92843} },  /* 38.4 MHz */
  97         { },                                    /* Terminator */
  98 };
  99
 100 static struct pipe3_dpll_map dpll_map_sata[] = {
 101         {12000000, {1000, 7, 4, 6, 0} },        /* 12 MHz */
 102         {16800000, {714, 7, 4, 6, 0} },         /* 16.8 MHz */
 103         {19200000, {625, 7, 4, 6, 0} },         /* 19.2 MHz */
 104         {20000000, {600, 7, 4, 6, 0} },         /* 20 MHz */
 105         {26000000, {461, 7, 4, 6, 0} },         /* 26 MHz */
 106         {38400000, {312, 7, 4, 6, 0} },         /* 38.4 MHz */
 107         { },                                    /* Terminator */
 108 };
 109
 110 static inline u32 ti_pipe3_readl(void __iomem *addr, unsigned offset)
 111 {
 112         return __raw_readl(addr + offset);
 113 }
 114
 115 static inline void ti_pipe3_writel(void __iomem *addr, unsigned offset,
 116         u32 data)
 117 {
 118         __raw_writel(data, addr + offset);
 119 }
 120
 121 static struct pipe3_dpll_params *ti_pipe3_get_dpll_params(struct ti_pipe3 *phy)
 122 {
 123         unsigned long rate;
 124         struct pipe3_dpll_map *dpll_map = phy->dpll_map;
 125
 126         rate = clk_get_rate(phy->sys_clk);
 127
 128         for (; dpll_map->rate; dpll_map++) {
 129                 if (rate == dpll_map->rate)
 130                         return &dpll_map->params;
 131         }
 132
 133         dev_err(phy->dev, "No DPLL configuration for %lu Hz SYS CLK\n", rate);
 134
 135         return NULL;
 136 }
 137
 138 static int ti_pipe3_power_off(struct phy *x)
 139 {
 140         struct ti_pipe3 *phy = phy_get_drvdata(x);
 141
 142         omap_control_phy_power(phy->control_dev, 0);
 143
 144         return 0;
 145 }
 146
 147 static int ti_pipe3_power_on(struct phy *x)
 148 {
 149         struct ti_pipe3 *phy = phy_get_drvdata(x);
 150
 151         omap_control_phy_power(phy->control_dev, 1);
 152
 153         return 0;
 154 }
 155
 156 static int ti_pipe3_dpll_wait_lock(struct ti_pipe3 *phy)
 157 {
 158         u32             val;
 159         unsigned long   timeout;
 160
 161         timeout = jiffies + msecs_to_jiffies(PLL_LOCK_TIME);
 162         do {
 163                 cpu_relax();
 164                 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
 165                 if (val & PLL_LOCK)
 166                         break;
 167         } while (!time_after(jiffies, timeout));
 168
 169         if (!(val & PLL_LOCK)) {
 170                 dev_err(phy->dev, "DPLL failed to lock\n");
 171                 return -EBUSY;
 172         }
 173
 174         return 0;
 175 }
 176
 177 static int ti_pipe3_dpll_program(struct ti_pipe3 *phy)
 178 {
 179         u32                     val;
 180         struct pipe3_dpll_params *dpll_params;
 181
 182         dpll_params = ti_pipe3_get_dpll_params(phy);
 183         if (!dpll_params)
 184                 return -EINVAL;
 185
 186         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
 187         val &= ~PLL_REGN_MASK;
 188         val |= dpll_params->n << PLL_REGN_SHIFT;
 189         ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
 190
 191         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
 192         val &= ~PLL_SELFREQDCO_MASK;
 193         val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
 194         ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
 195
 196         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
 197         val &= ~PLL_REGM_MASK;
 198         val |= dpll_params->m << PLL_REGM_SHIFT;
 199         ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
 200
 201         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4);
 202         val &= ~PLL_REGM_F_MASK;
 203         val |= dpll_params->mf << PLL_REGM_F_SHIFT;
 204         ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val);
 205
 206         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3);
 207         val &= ~PLL_SD_MASK;
 208         val |= dpll_params->sd << PLL_SD_SHIFT;
 209         ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val);
 210
 211         ti_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO);
 212
 213         return ti_pipe3_dpll_wait_lock(phy);
 214 }
 215
 216 static int ti_pipe3_init(struct phy *x)
 217 {
 218         struct ti_pipe3 *phy = phy_get_drvdata(x);
 219         u32 val;
 220         int ret = 0;
 221
 222         /*
 223          * Set pcie_pcs register to 0x96 for proper functioning of phy
 224          * as recommended in AM572x TRM SPRUHZ6, section 18.5.2.2, table
 225          * 18-1804.
 226          */
 227         if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie")) {
 228                 omap_control_pcie_pcs(phy->control_dev, 0x96);
 229                 return 0;
 230         }
 231
 232         /* Bring it out of IDLE if it is IDLE */
 233         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
 234         if (val & PLL_IDLE) {
 235                 val &= ~PLL_IDLE;
 236                 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
 237                 ret = ti_pipe3_dpll_wait_lock(phy);
 238         }
 239
 240         /* Program the DPLL only if not locked */
 241         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
 242         if (!(val & PLL_LOCK))
 243                 if (ti_pipe3_dpll_program(phy))
 244                         return -EINVAL;
 245
 246         return ret;
 247 }
 248
 249 static int ti_pipe3_exit(struct phy *x)
 250 {
 251         struct ti_pipe3 *phy = phy_get_drvdata(x);
 252         u32 val;
 253         unsigned long timeout;
 254
 255         /* SATA DPLL can't be powered down due to Errata i783 and PCIe
 256          * does not have internal DPLL
 257          */
 258         if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-sata") ||
 259             of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie"))
 260                 return 0;
 261
 262         /* Put DPLL in IDLE mode */
 263         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
 264         val |= PLL_IDLE;
 265         ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
 266
 267         /* wait for LDO and Oscillator to power down */
 268         timeout = jiffies + msecs_to_jiffies(PLL_IDLE_TIME);
 269         do {
 270                 cpu_relax();
 271                 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
 272                 if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))
 273                         break;
 274         } while (!time_after(jiffies, timeout));
 275
 276         if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) {
 277                 dev_err(phy->dev, "Failed to power down: PLL_STATUS 0x%x\n",
 278                         val);
 279                 return -EBUSY;
 280         }
 281
 282         return 0;
 283 }
 284 static struct phy_ops ops = {
 285         .init           = ti_pipe3_init,
 286         .exit           = ti_pipe3_exit,
 287         .power_on       = ti_pipe3_power_on,
 288         .power_off      = ti_pipe3_power_off,
 289         .owner          = THIS_MODULE,
 290 };
 291
 292 #ifdef CONFIG_OF
 293 static const struct of_device_id ti_pipe3_id_table[];
 294 #endif
 295
 296 static int ti_pipe3_probe(struct platform_device *pdev)
 297 {
 298         struct ti_pipe3 *phy;
 299         struct phy *generic_phy;
 300         struct phy_provider *phy_provider;
 301         struct resource *res;
 302         struct device_node *node = pdev->dev.of_node;
 303         struct device_node *control_node;
 304         struct platform_device *control_pdev;
 305         const struct of_device_id *match;
 306         struct clk *clk;
 307
 308         phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
 309         if (!phy)
 310                 return -ENOMEM;
 311
 312         phy->dev                = &pdev->dev;
 313         spin_lock_init(&phy->lock);
 314
 315         if (!of_device_is_compatible(node, "ti,phy-pipe3-pcie")) {
 316                 match = of_match_device(of_match_ptr(ti_pipe3_id_table),
 317                                         &pdev->dev);
 318                 if (!match)
 319                         return -EINVAL;
 320
 321                 phy->dpll_map = (struct pipe3_dpll_map *)match->data;
 322                 if (!phy->dpll_map) {
 323                         dev_err(&pdev->dev, "no DPLL data\n");
 324                         return -EINVAL;
 325                 }
 326
 327                 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 328                                                    "pll_ctrl");
 329                 phy->pll_ctrl_base = devm_ioremap_resource(&pdev->dev, res);
 330                 if (IS_ERR(phy->pll_ctrl_base))
 331                         return PTR_ERR(phy->pll_ctrl_base);
 332
 333                 phy->sys_clk = devm_clk_get(phy->dev, "sysclk");
 334                 if (IS_ERR(phy->sys_clk)) {
 335                         dev_err(&pdev->dev, "unable to get sysclk\n");
 336                         return -EINVAL;
 337                 }
 338         }
 339
 340         if (!of_device_is_compatible(node, "ti,phy-pipe3-sata")) {
 341                 phy->wkupclk = devm_clk_get(phy->dev, "wkupclk");
 342                 if (IS_ERR(phy->wkupclk)) {
 343                         dev_err(&pdev->dev, "unable to get wkupclk\n");
 344                         return PTR_ERR(phy->wkupclk);
 345                 }
 346
 347                 phy->refclk = devm_clk_get(phy->dev, "refclk");
 348                 if (IS_ERR(phy->refclk)) {
 349                         dev_err(&pdev->dev, "unable to get refclk\n");
 350                         return PTR_ERR(phy->refclk);
 351                 }
 352         } else {
 353                 phy->wkupclk = ERR_PTR(-ENODEV);
 354                 phy->refclk = ERR_PTR(-ENODEV);
 355         }
 356
 357         if (of_device_is_compatible(node, "ti,phy-pipe3-pcie")) {
 358
 359                 clk = devm_clk_get(phy->dev, "dpll_ref");
 360                 if (IS_ERR(clk)) {
 361                         dev_err(&pdev->dev, "unable to get dpll ref clk\n");
 362                         return PTR_ERR(clk);
 363                 }
 364                 clk_set_rate(clk, 1500000000);
 365
 366                 clk = devm_clk_get(phy->dev, "dpll_ref_m2");
 367                 if (IS_ERR(clk)) {
 368                         dev_err(&pdev->dev, "unable to get dpll ref m2 clk\n");
 369                         return PTR_ERR(clk);
 370                 }
 371                 clk_set_rate(clk, 100000000);
 372
 373                 clk = devm_clk_get(phy->dev, "phy-div");
 374                 if (IS_ERR(clk)) {
 375                         dev_err(&pdev->dev, "unable to get phy-div clk\n");
 376                         return PTR_ERR(clk);
 377                 }
 378                 clk_set_rate(clk, 100000000);
 379
 380                 phy->div_clk = devm_clk_get(phy->dev, "div-clk");
 381                 if (IS_ERR(phy->div_clk)) {
 382                         dev_err(&pdev->dev, "unable to get div-clk\n");
 383                         return PTR_ERR(phy->div_clk);
 384                 }
 385         } else {
 386                 phy->div_clk = ERR_PTR(-ENODEV);
 387         }
 388
 389         control_node = of_parse_phandle(node, "ctrl-module", 0);
 390         if (!control_node) {
 391                 dev_err(&pdev->dev, "Failed to get control device phandle\n");
 392                 return -EINVAL;
 393         }
 394
 395         control_pdev = of_find_device_by_node(control_node);
 396         if (!control_pdev) {
 397                 dev_err(&pdev->dev, "Failed to get control device\n");
 398                 return -EINVAL;
 399         }
 400
 401         phy->control_dev = &control_pdev->dev;
 402
 403         omap_control_phy_power(phy->control_dev, 0);
 404
 405         platform_set_drvdata(pdev, phy);
 406         pm_runtime_enable(phy->dev);
 407
 408         generic_phy = devm_phy_create(phy->dev, NULL, &ops);
 409         if (IS_ERR(generic_phy))
 410                 return PTR_ERR(generic_phy);
 411
 412         phy_set_drvdata(generic_phy, phy);
 413         phy_provider = devm_of_phy_provider_register(phy->dev,
 414                         of_phy_simple_xlate);
 415         if (IS_ERR(phy_provider))
 416                 return PTR_ERR(phy_provider);
 417
 418         pm_runtime_get(&pdev->dev);
 419
 420         return 0;
 421 }
 422
 423 static int ti_pipe3_remove(struct platform_device *pdev)
 424 {
 425         if (!pm_runtime_suspended(&pdev->dev))
 426                 pm_runtime_put(&pdev->dev);
 427         pm_runtime_disable(&pdev->dev);
 428
 429         return 0;
 430 }
 431
 432 #ifdef CONFIG_PM
 433
 434 static int ti_pipe3_enable_clocks(struct ti_pipe3 *phy)
 435 {
 436         int ret = 0;
 437         unsigned long flags;
 438
 439         spin_lock_irqsave(&phy->lock, flags);
 440         if (phy->enabled)
 441                 goto err1;
 442
 443         if (!IS_ERR(phy->refclk)) {
 444                 ret = clk_prepare_enable(phy->refclk);
 445                 if (ret) {
 446                         dev_err(phy->dev, "Failed to enable refclk %d\n", ret);
 447                         goto err1;
 448                 }
 449         }
 450
 451         if (!IS_ERR(phy->wkupclk)) {
 452                 ret = clk_prepare_enable(phy->wkupclk);
 453                 if (ret) {
 454                         dev_err(phy->dev, "Failed to enable wkupclk %d\n", ret);
 455                         goto err2;
 456                 }
 457         }
 458
 459         if (!IS_ERR(phy->div_clk)) {
 460                 ret = clk_prepare_enable(phy->div_clk);
 461                 if (ret) {
 462                         dev_err(phy->dev, "Failed to enable div_clk %d\n", ret);
 463                         goto err3;
 464                 }
 465         }
 466
 467         phy->enabled = true;
 468         spin_unlock_irqrestore(&phy->lock, flags);
 469         return 0;
 470
 471 err3:
 472         if (!IS_ERR(phy->wkupclk))
 473                 clk_disable_unprepare(phy->wkupclk);
 474
 475 err2:
 476         if (!IS_ERR(phy->refclk))
 477                 clk_disable_unprepare(phy->refclk);
 478
 479 err1:
 480         spin_unlock_irqrestore(&phy->lock, flags);
 481         return ret;
 482 }
 483
 484 static void ti_pipe3_disable_clocks(struct ti_pipe3 *phy)
 485 {
 486         unsigned long flags;
 487
 488         spin_lock_irqsave(&phy->lock, flags);
 489         if (!phy->enabled) {
 490                 spin_unlock_irqrestore(&phy->lock, flags);
 491                 return;
 492         }
 493
 494         if (!IS_ERR(phy->wkupclk))
 495                 clk_disable_unprepare(phy->wkupclk);
 496         if (!IS_ERR(phy->refclk))
 497                 clk_disable_unprepare(phy->refclk);
 498         if (!IS_ERR(phy->div_clk))
 499                 clk_disable_unprepare(phy->div_clk);
 500         phy->enabled = false;
 501         spin_unlock_irqrestore(&phy->lock, flags);
 502 }
 503
 504 static int ti_pipe3_runtime_suspend(struct device *dev)
 505 {
 506         struct ti_pipe3 *phy = dev_get_drvdata(dev);
 507
 508         ti_pipe3_disable_clocks(phy);
 509         return 0;
 510 }
 511
 512 static int ti_pipe3_runtime_resume(struct device *dev)
 513 {
 514         struct ti_pipe3 *phy = dev_get_drvdata(dev);
 515         int ret = 0;
 516
 517         ret = ti_pipe3_enable_clocks(phy);
 518         return ret;
 519 }
 520
 521 static int ti_pipe3_suspend(struct device *dev)
 522 {
 523         struct ti_pipe3 *phy = dev_get_drvdata(dev);
 524
 525         ti_pipe3_disable_clocks(phy);
 526         return 0;
 527 }
 528
 529 static int ti_pipe3_resume(struct device *dev)
 530 {
 531         struct ti_pipe3 *phy = dev_get_drvdata(dev);
 532         int ret;
 533
 534         ret = ti_pipe3_enable_clocks(phy);
 535         if (ret)
 536                 return ret;
 537
 538         pm_runtime_disable(dev);
 539         pm_runtime_set_active(dev);
 540         pm_runtime_enable(dev);
 541         return 0;
 542 }
 543 #endif
 544
 545 static const struct dev_pm_ops ti_pipe3_pm_ops = {
 546         SET_RUNTIME_PM_OPS(ti_pipe3_runtime_suspend,
 547                            ti_pipe3_runtime_resume, NULL)
 548         SET_SYSTEM_SLEEP_PM_OPS(ti_pipe3_suspend, ti_pipe3_resume)
 549 };
 550
 551 #ifdef CONFIG_OF
 552 static const struct of_device_id ti_pipe3_id_table[] = {
 553         {
 554                 .compatible = "ti,phy-usb3",
 555                 .data = dpll_map_usb,
 556         },
 557         {
 558                 .compatible = "ti,omap-usb3",
 559                 .data = dpll_map_usb,
 560         },
 561         {
 562                 .compatible = "ti,phy-pipe3-sata",
 563                 .data = dpll_map_sata,
 564         },
 565         {
 566                 .compatible = "ti,phy-pipe3-pcie",
 567         },
 568         {}
 569 };
 570 MODULE_DEVICE_TABLE(of, ti_pipe3_id_table);
 571 #endif
 572
 573 static struct platform_driver ti_pipe3_driver = {
 574         .probe          = ti_pipe3_probe,
 575         .remove         = ti_pipe3_remove,
 576         .driver         = {
 577                 .name   = "ti-pipe3",
 578                 .pm     = &ti_pipe3_pm_ops,
 579                 .of_match_table = of_match_ptr(ti_pipe3_id_table),
 580         },
 581 };
 582
 583 module_platform_driver(ti_pipe3_driver);
 584
 585 MODULE_ALIAS("platform: ti_pipe3");
 586 MODULE_AUTHOR("Texas Instruments Inc.");
 587 MODULE_DESCRIPTION("TI PIPE3 phy driver");
 588 MODULE_LICENSE("GPL v2");