drivers/phy/phy-ti-pipe3.c

   1 /*
   2  * phy-ti-pipe3 - PIPE3 PHY driver.
   3  *
   4  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * Author: Kishon Vijay Abraham I <kishon@ti.com>
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  */
  18
  19 #include <linux/module.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/slab.h>
  22 #include <linux/phy/phy.h>
  23 #include <linux/of.h>
  24 #include <linux/clk.h>
  25 #include <linux/err.h>
  26 #include <linux/io.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/delay.h>
  29 #include <linux/phy/omap_control_phy.h>
  30 #include <linux/of_platform.h>
  31
  32 #define PLL_STATUS              0x00000004
  33 #define PLL_GO                  0x00000008
  34 #define PLL_CONFIGURATION1      0x0000000C
  35 #define PLL_CONFIGURATION2      0x00000010
  36 #define PLL_CONFIGURATION3      0x00000014
  37 #define PLL_CONFIGURATION4      0x00000020
  38
  39 #define PLL_REGM_MASK           0x001FFE00
  40 #define PLL_REGM_SHIFT          0x9
  41 #define PLL_REGM_F_MASK         0x0003FFFF
  42 #define PLL_REGM_F_SHIFT        0x0
  43 #define PLL_REGN_MASK           0x000001FE
  44 #define PLL_REGN_SHIFT          0x1
  45 #define PLL_SELFREQDCO_MASK     0x0000000E
  46 #define PLL_SELFREQDCO_SHIFT    0x1
  47 #define PLL_SD_MASK             0x0003FC00
  48 #define PLL_SD_SHIFT            10
  49 #define SET_PLL_GO              0x1
  50 #define PLL_LDOPWDN             BIT(15)
  51 #define PLL_TICOPWDN            BIT(16)
  52 #define PLL_LOCK                0x2
  53 #define PLL_IDLE                0x1
  54
  55 /*
  56  * This is an Empirical value that works, need to confirm the actual
  57  * value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status
  58  * to be correctly reflected in the PIPE3PHY_PLL_STATUS register.
  59  */
  60 #define PLL_IDLE_TIME   100     /* in milliseconds */
  61 #define PLL_LOCK_TIME   100     /* in milliseconds */
  62
  63 struct pipe3_dpll_params {
  64         u16     m;
  65         u8      n;
  66         u8      freq:3;
  67         u8      sd;
  68         u32     mf;
  69 };
  70
  71 struct pipe3_dpll_map {
  72         unsigned long rate;
  73         struct pipe3_dpll_params params;
  74 };
  75
  76 struct ti_pipe3 {
  77         void __iomem            *pll_ctrl_base;
  78         struct device           *dev;
  79         struct device           *control_dev;
  80         struct clk              *wkupclk;
  81         struct clk              *sys_clk;
  82         struct clk              *refclk;
  83         struct clk              *div_clk;
  84         struct pipe3_dpll_map   *dpll_map;
  85 };
  86
  87 static struct pipe3_dpll_map dpll_map_usb[] = {
  88         {12000000, {1250, 5, 4, 20, 0} },       /* 12 MHz */
  89         {16800000, {3125, 20, 4, 20, 0} },      /* 16.8 MHz */
  90         {19200000, {1172, 8, 4, 20, 65537} },   /* 19.2 MHz */
  91         {20000000, {1000, 7, 4, 10, 0} },       /* 20 MHz */
  92         {26000000, {1250, 12, 4, 20, 0} },      /* 26 MHz */
  93         {38400000, {3125, 47, 4, 20, 92843} },  /* 38.4 MHz */
  94         { },                                    /* Terminator */
  95 };
  96
  97 static struct pipe3_dpll_map dpll_map_sata[] = {
  98         {12000000, {1000, 7, 4, 6, 0} },        /* 12 MHz */
  99         {16800000, {714, 7, 4, 6, 0} },         /* 16.8 MHz */
 100         {19200000, {625, 7, 4, 6, 0} },         /* 19.2 MHz */
 101         {20000000, {600, 7, 4, 6, 0} },         /* 20 MHz */
 102         {26000000, {461, 7, 4, 6, 0} },         /* 26 MHz */
 103         {38400000, {312, 7, 4, 6, 0} },         /* 38.4 MHz */
 104         { },                                    /* Terminator */
 105 };
 106
 107 static inline u32 ti_pipe3_readl(void __iomem *addr, unsigned offset)
 108 {
 109         return __raw_readl(addr + offset);
 110 }
 111
 112 static inline void ti_pipe3_writel(void __iomem *addr, unsigned offset,
 113         u32 data)
 114 {
 115         __raw_writel(data, addr + offset);
 116 }
 117
 118 static struct pipe3_dpll_params *ti_pipe3_get_dpll_params(struct ti_pipe3 *phy)
 119 {
 120         unsigned long rate;
 121         struct pipe3_dpll_map *dpll_map = phy->dpll_map;
 122
 123         rate = clk_get_rate(phy->sys_clk);
 124
 125         for (; dpll_map->rate; dpll_map++) {
 126                 if (rate == dpll_map->rate)
 127                         return &dpll_map->params;
 128         }
 129
 130         dev_err(phy->dev, "No DPLL configuration for %lu Hz SYS CLK\n", rate);
 131
 132         return NULL;
 133 }
 134
 135 static int ti_pipe3_power_off(struct phy *x)
 136 {
 137         struct ti_pipe3 *phy = phy_get_drvdata(x);
 138
 139         omap_control_phy_power(phy->control_dev, 0);
 140
 141         return 0;
 142 }
 143
 144 static int ti_pipe3_power_on(struct phy *x)
 145 {
 146         struct ti_pipe3 *phy = phy_get_drvdata(x);
 147
 148         omap_control_phy_power(phy->control_dev, 1);
 149
 150         return 0;
 151 }
 152
 153 static int ti_pipe3_dpll_wait_lock(struct ti_pipe3 *phy)
 154 {
 155         u32             val;
 156         unsigned long   timeout;
 157
 158         timeout = jiffies + msecs_to_jiffies(PLL_LOCK_TIME);
 159         do {
 160                 cpu_relax();
 161                 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
 162                 if (val & PLL_LOCK)
 163                         break;
 164         } while (!time_after(jiffies, timeout));
 165
 166         if (!(val & PLL_LOCK)) {
 167                 dev_err(phy->dev, "DPLL failed to lock\n");
 168                 return -EBUSY;
 169         }
 170
 171         return 0;
 172 }
 173
 174 static int ti_pipe3_dpll_program(struct ti_pipe3 *phy)
 175 {
 176         u32                     val;
 177         struct pipe3_dpll_params *dpll_params;
 178
 179         dpll_params = ti_pipe3_get_dpll_params(phy);
 180         if (!dpll_params)
 181                 return -EINVAL;
 182
 183         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
 184         val &= ~PLL_REGN_MASK;
 185         val |= dpll_params->n << PLL_REGN_SHIFT;
 186         ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
 187
 188         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
 189         val &= ~PLL_SELFREQDCO_MASK;
 190         val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
 191         ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
 192
 193         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
 194         val &= ~PLL_REGM_MASK;
 195         val |= dpll_params->m << PLL_REGM_SHIFT;
 196         ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
 197
 198         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4);
 199         val &= ~PLL_REGM_F_MASK;
 200         val |= dpll_params->mf << PLL_REGM_F_SHIFT;
 201         ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val);
 202
 203         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3);
 204         val &= ~PLL_SD_MASK;
 205         val |= dpll_params->sd << PLL_SD_SHIFT;
 206         ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val);
 207
 208         ti_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO);
 209
 210         return ti_pipe3_dpll_wait_lock(phy);
 211 }
 212
 213 static int ti_pipe3_init(struct phy *x)
 214 {
 215         struct ti_pipe3 *phy = phy_get_drvdata(x);
 216         u32 val;
 217         int ret = 0;
 218
 219         /*
 220          * Set pcie_pcs register to 0x96 for proper functioning of phy
 221          * as recommended in AM572x TRM SPRUHZ6, section 18.5.2.2, table
 222          * 18-1804.
 223          */
 224         if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie")) {
 225                 omap_control_pcie_pcs(phy->control_dev, 0x96);
 226                 return 0;
 227         }
 228
 229         /* Bring it out of IDLE if it is IDLE */
 230         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
 231         if (val & PLL_IDLE) {
 232                 val &= ~PLL_IDLE;
 233                 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
 234                 ret = ti_pipe3_dpll_wait_lock(phy);
 235         }
 236
 237         /* Program the DPLL only if not locked */
 238         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
 239         if (!(val & PLL_LOCK))
 240                 if (ti_pipe3_dpll_program(phy))
 241                         return -EINVAL;
 242
 243         return ret;
 244 }
 245
 246 static int ti_pipe3_exit(struct phy *x)
 247 {
 248         struct ti_pipe3 *phy = phy_get_drvdata(x);
 249         u32 val;
 250         unsigned long timeout;
 251
 252         /* SATA DPLL can't be powered down due to Errata i783 and PCIe
 253          * does not have internal DPLL
 254          */
 255         if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-sata") ||
 256             of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie"))
 257                 return 0;
 258
 259         /* Put DPLL in IDLE mode */
 260         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
 261         val |= PLL_IDLE;
 262         ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
 263
 264         /* wait for LDO and Oscillator to power down */
 265         timeout = jiffies + msecs_to_jiffies(PLL_IDLE_TIME);
 266         do {
 267                 cpu_relax();
 268                 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
 269                 if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))
 270                         break;
 271         } while (!time_after(jiffies, timeout));
 272
 273         if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) {
 274                 dev_err(phy->dev, "Failed to power down: PLL_STATUS 0x%x\n",
 275                         val);
 276                 return -EBUSY;
 277         }
 278
 279         return 0;
 280 }
 281 static struct phy_ops ops = {
 282         .init           = ti_pipe3_init,
 283         .exit           = ti_pipe3_exit,
 284         .power_on       = ti_pipe3_power_on,
 285         .power_off      = ti_pipe3_power_off,
 286         .owner          = THIS_MODULE,
 287 };
 288
 289 #ifdef CONFIG_OF
 290 static const struct of_device_id ti_pipe3_id_table[];
 291 #endif
 292
 293 static int ti_pipe3_probe(struct platform_device *pdev)
 294 {
 295         struct ti_pipe3 *phy;
 296         struct phy *generic_phy;
 297         struct phy_provider *phy_provider;
 298         struct resource *res;
 299         struct device_node *node = pdev->dev.of_node;
 300         struct device_node *control_node;
 301         struct platform_device *control_pdev;
 302         const struct of_device_id *match;
 303         struct clk *clk;
 304
 305         phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
 306         if (!phy)
 307                 return -ENOMEM;
 308
 309         phy->dev                = &pdev->dev;
 310
 311         if (!of_device_is_compatible(node, "ti,phy-pipe3-pcie")) {
 312                 match = of_match_device(of_match_ptr(ti_pipe3_id_table),
 313                                         &pdev->dev);
 314                 if (!match)
 315                         return -EINVAL;
 316
 317                 phy->dpll_map = (struct pipe3_dpll_map *)match->data;
 318                 if (!phy->dpll_map) {
 319                         dev_err(&pdev->dev, "no DPLL data\n");
 320                         return -EINVAL;
 321                 }
 322
 323                 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 324                                                    "pll_ctrl");
 325                 phy->pll_ctrl_base = devm_ioremap_resource(&pdev->dev, res);
 326                 if (IS_ERR(phy->pll_ctrl_base))
 327                         return PTR_ERR(phy->pll_ctrl_base);
 328
 329                 phy->sys_clk = devm_clk_get(phy->dev, "sysclk");
 330                 if (IS_ERR(phy->sys_clk)) {
 331                         dev_err(&pdev->dev, "unable to get sysclk\n");
 332                         return -EINVAL;
 333                 }
 334         }
 335
 336         if (!of_device_is_compatible(node, "ti,phy-pipe3-sata")) {
 337                 phy->wkupclk = devm_clk_get(phy->dev, "wkupclk");
 338                 if (IS_ERR(phy->wkupclk)) {
 339                         dev_err(&pdev->dev, "unable to get wkupclk\n");
 340                         return PTR_ERR(phy->wkupclk);
 341                 }
 342
 343                 phy->refclk = devm_clk_get(phy->dev, "refclk");
 344                 if (IS_ERR(phy->refclk)) {
 345                         dev_err(&pdev->dev, "unable to get refclk\n");
 346                         return PTR_ERR(phy->refclk);
 347                 }
 348         } else {
 349                 phy->wkupclk = ERR_PTR(-ENODEV);
 350                 phy->refclk = ERR_PTR(-ENODEV);
 351         }
 352
 353         if (of_device_is_compatible(node, "ti,phy-pipe3-pcie")) {
 354
 355                 clk = devm_clk_get(phy->dev, "dpll_ref");
 356                 if (IS_ERR(clk)) {
 357                         dev_err(&pdev->dev, "unable to get dpll ref clk\n");
 358                         return PTR_ERR(clk);
 359                 }
 360                 clk_set_rate(clk, 1500000000);
 361
 362                 clk = devm_clk_get(phy->dev, "dpll_ref_m2");
 363                 if (IS_ERR(clk)) {
 364                         dev_err(&pdev->dev, "unable to get dpll ref m2 clk\n");
 365                         return PTR_ERR(clk);
 366                 }
 367                 clk_set_rate(clk, 100000000);
 368
 369                 clk = devm_clk_get(phy->dev, "phy-div");
 370                 if (IS_ERR(clk)) {
 371                         dev_err(&pdev->dev, "unable to get phy-div clk\n");
 372                         return PTR_ERR(clk);
 373                 }
 374                 clk_set_rate(clk, 100000000);
 375
 376                 phy->div_clk = devm_clk_get(phy->dev, "div-clk");
 377                 if (IS_ERR(phy->div_clk)) {
 378                         dev_err(&pdev->dev, "unable to get div-clk\n");
 379                         return PTR_ERR(phy->div_clk);
 380                 }
 381         } else {
 382                 phy->div_clk = ERR_PTR(-ENODEV);
 383         }
 384
 385         control_node = of_parse_phandle(node, "ctrl-module", 0);
 386         if (!control_node) {
 387                 dev_err(&pdev->dev, "Failed to get control device phandle\n");
 388                 return -EINVAL;
 389         }
 390
 391         control_pdev = of_find_device_by_node(control_node);
 392         if (!control_pdev) {
 393                 dev_err(&pdev->dev, "Failed to get control device\n");
 394                 return -EINVAL;
 395         }
 396
 397         phy->control_dev = &control_pdev->dev;
 398
 399         omap_control_phy_power(phy->control_dev, 0);
 400
 401         platform_set_drvdata(pdev, phy);
 402         pm_runtime_enable(phy->dev);
 403
 404         generic_phy = devm_phy_create(phy->dev, NULL, &ops);
 405         if (IS_ERR(generic_phy))
 406                 return PTR_ERR(generic_phy);
 407
 408         phy_set_drvdata(generic_phy, phy);
 409         phy_provider = devm_of_phy_provider_register(phy->dev,
 410                         of_phy_simple_xlate);
 411         if (IS_ERR(phy_provider))
 412                 return PTR_ERR(phy_provider);
 413
 414         pm_runtime_get(&pdev->dev);
 415
 416         return 0;
 417 }
 418
 419 static int ti_pipe3_remove(struct platform_device *pdev)
 420 {
 421         if (!pm_runtime_suspended(&pdev->dev))
 422                 pm_runtime_put(&pdev->dev);
 423         pm_runtime_disable(&pdev->dev);
 424
 425         return 0;
 426 }
 427
 428 #ifdef CONFIG_PM
 429
 430 static int ti_pipe3_runtime_suspend(struct device *dev)
 431 {
 432         struct ti_pipe3 *phy = dev_get_drvdata(dev);
 433
 434         if (!IS_ERR(phy->wkupclk))
 435                 clk_disable_unprepare(phy->wkupclk);
 436         if (!IS_ERR(phy->refclk))
 437                 clk_disable_unprepare(phy->refclk);
 438         if (!IS_ERR(phy->div_clk))
 439                 clk_disable_unprepare(phy->div_clk);
 440
 441         return 0;
 442 }
 443
 444 static int ti_pipe3_runtime_resume(struct device *dev)
 445 {
 446         u32 ret = 0;
 447         struct ti_pipe3 *phy = dev_get_drvdata(dev);
 448
 449         if (!IS_ERR(phy->refclk)) {
 450                 ret = clk_prepare_enable(phy->refclk);
 451                 if (ret) {
 452                         dev_err(phy->dev, "Failed to enable refclk %d\n", ret);
 453                         goto err1;
 454                 }
 455         }
 456
 457         if (!IS_ERR(phy->wkupclk)) {
 458                 ret = clk_prepare_enable(phy->wkupclk);
 459                 if (ret) {
 460                         dev_err(phy->dev, "Failed to enable wkupclk %d\n", ret);
 461                         goto err2;
 462                 }
 463         }
 464
 465         if (!IS_ERR(phy->div_clk)) {
 466                 ret = clk_prepare_enable(phy->div_clk);
 467                 if (ret) {
 468                         dev_err(phy->dev, "Failed to enable div_clk %d\n", ret);
 469                         goto err3;
 470                 }
 471         }
 472         return 0;
 473
 474 err3:
 475         if (!IS_ERR(phy->wkupclk))
 476                 clk_disable_unprepare(phy->wkupclk);
 477
 478 err2:
 479         if (!IS_ERR(phy->refclk))
 480                 clk_disable_unprepare(phy->refclk);
 481
 482 err1:
 483         return ret;
 484 }
 485
 486 static const struct dev_pm_ops ti_pipe3_pm_ops = {
 487         SET_RUNTIME_PM_OPS(ti_pipe3_runtime_suspend,
 488                            ti_pipe3_runtime_resume, NULL)
 489 };
 490
 491 #define DEV_PM_OPS     (&ti_pipe3_pm_ops)
 492 #else
 493 #define DEV_PM_OPS     NULL
 494 #endif
 495
 496 #ifdef CONFIG_OF
 497 static const struct of_device_id ti_pipe3_id_table[] = {
 498         {
 499                 .compatible = "ti,phy-usb3",
 500                 .data = dpll_map_usb,
 501         },
 502         {
 503                 .compatible = "ti,omap-usb3",
 504                 .data = dpll_map_usb,
 505         },
 506         {
 507                 .compatible = "ti,phy-pipe3-sata",
 508                 .data = dpll_map_sata,
 509         },
 510         {
 511                 .compatible = "ti,phy-pipe3-pcie",
 512         },
 513         {}
 514 };
 515 MODULE_DEVICE_TABLE(of, ti_pipe3_id_table);
 516 #endif
 517
 518 static struct platform_driver ti_pipe3_driver = {
 519         .probe          = ti_pipe3_probe,
 520         .remove         = ti_pipe3_remove,
 521         .driver         = {
 522                 .name   = "ti-pipe3",
 523                 .pm     = DEV_PM_OPS,
 524                 .of_match_table = of_match_ptr(ti_pipe3_id_table),
 525         },
 526 };
 527
 528 module_platform_driver(ti_pipe3_driver);
 529
 530 MODULE_ALIAS("platform: ti_pipe3");
 531 MODULE_AUTHOR("Texas Instruments Inc.");
 532 MODULE_DESCRIPTION("TI PIPE3 phy driver");
 533 MODULE_LICENSE("GPL v2");