2 * Pinctrl GPIO driver for Intel Baytrail
3 * Copyright (c) 2012-2013, Intel Corporation.
5 * Author: Mathias Nyman <mathias.nyman@linux.intel.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/init.h>
25 #include <linux/types.h>
26 #include <linux/bitops.h>
27 #include <linux/interrupt.h>
28 #include <linux/gpio.h>
29 #include <linux/acpi.h>
30 #include <linux/platform_device.h>
31 #include <linux/seq_file.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/pinctrl/pinctrl.h>
36 /* memory mapped register offsets */
37 #define BYT_CONF0_REG 0x000
38 #define BYT_CONF1_REG 0x004
39 #define BYT_VAL_REG 0x008
40 #define BYT_DFT_REG 0x00c
41 #define BYT_INT_STAT_REG 0x800
43 /* BYT_CONF0_REG register bits */
44 #define BYT_IODEN BIT(31)
45 #define BYT_DIRECT_IRQ_EN BIT(27)
46 #define BYT_TRIG_NEG BIT(26)
47 #define BYT_TRIG_POS BIT(25)
48 #define BYT_TRIG_LVL BIT(24)
49 #define BYT_PULL_STR_SHIFT 9
50 #define BYT_PULL_STR_MASK (3 << BYT_PULL_STR_SHIFT)
51 #define BYT_PULL_STR_2K (0 << BYT_PULL_STR_SHIFT)
52 #define BYT_PULL_STR_10K (1 << BYT_PULL_STR_SHIFT)
53 #define BYT_PULL_STR_20K (2 << BYT_PULL_STR_SHIFT)
54 #define BYT_PULL_STR_40K (3 << BYT_PULL_STR_SHIFT)
55 #define BYT_PULL_ASSIGN_SHIFT 7
56 #define BYT_PULL_ASSIGN_MASK (3 << BYT_PULL_ASSIGN_SHIFT)
57 #define BYT_PULL_ASSIGN_UP (1 << BYT_PULL_ASSIGN_SHIFT)
58 #define BYT_PULL_ASSIGN_DOWN (2 << BYT_PULL_ASSIGN_SHIFT)
59 #define BYT_PIN_MUX 0x07
61 /* BYT_VAL_REG register bits */
62 #define BYT_INPUT_EN BIT(2) /* 0: input enabled (active low)*/
63 #define BYT_OUTPUT_EN BIT(1) /* 0: output enabled (active low)*/
64 #define BYT_LEVEL BIT(0)
66 #define BYT_DIR_MASK (BIT(1) | BIT(2))
67 #define BYT_TRIG_MASK (BIT(26) | BIT(25) | BIT(24))
69 #define BYT_NGPIO_SCORE 102
70 #define BYT_NGPIO_NCORE 28
71 #define BYT_NGPIO_SUS 44
73 #define BYT_SCORE_ACPI_UID "1"
74 #define BYT_NCORE_ACPI_UID "2"
75 #define BYT_SUS_ACPI_UID "3"
78 * Baytrail gpio controller consist of three separate sub-controllers called
79 * SCORE, NCORE and SUS. The sub-controllers are identified by their acpi UID.
81 * GPIO numbering is _not_ ordered meaning that gpio # 0 in ACPI namespace does
82 * _not_ correspond to the first gpio register at controller's gpio base.
83 * There is no logic or pattern in mapping gpio numbers to registers (pads) so
84 * each sub-controller needs to have its own mapping table
87 /* score_pins[gpio_nr] = pad_nr */
89 static unsigned const score_pins[BYT_NGPIO_SCORE] = {
90 85, 89, 93, 96, 99, 102, 98, 101, 34, 37,
91 36, 38, 39, 35, 40, 84, 62, 61, 64, 59,
92 54, 56, 60, 55, 63, 57, 51, 50, 53, 47,
93 52, 49, 48, 43, 46, 41, 45, 42, 58, 44,
94 95, 105, 70, 68, 67, 66, 69, 71, 65, 72,
95 86, 90, 88, 92, 103, 77, 79, 83, 78, 81,
96 80, 82, 13, 12, 15, 14, 17, 18, 19, 16,
97 2, 1, 0, 4, 6, 7, 9, 8, 33, 32,
98 31, 30, 29, 27, 25, 28, 26, 23, 21, 20,
99 24, 22, 5, 3, 10, 11, 106, 87, 91, 104,
103 static unsigned const ncore_pins[BYT_NGPIO_NCORE] = {
104 19, 18, 17, 20, 21, 22, 24, 25, 23, 16,
105 14, 15, 12, 26, 27, 1, 4, 8, 11, 0,
106 3, 6, 10, 13, 2, 5, 9, 7,
109 static unsigned const sus_pins[BYT_NGPIO_SUS] = {
110 29, 33, 30, 31, 32, 34, 36, 35, 38, 37,
111 18, 7, 11, 20, 17, 1, 8, 10, 19, 12,
112 0, 2, 23, 39, 28, 27, 22, 21, 24, 25,
113 26, 51, 56, 54, 49, 55, 48, 57, 50, 58,
117 static struct pinctrl_gpio_range byt_ranges[] = {
119 .name = BYT_SCORE_ACPI_UID, /* match with acpi _UID in probe */
120 .npins = BYT_NGPIO_SCORE,
124 .name = BYT_NCORE_ACPI_UID,
125 .npins = BYT_NGPIO_NCORE,
129 .name = BYT_SUS_ACPI_UID,
130 .npins = BYT_NGPIO_SUS,
138 struct gpio_chip chip;
139 struct platform_device *pdev;
141 void __iomem *reg_base;
142 struct pinctrl_gpio_range *range;
145 #define to_byt_gpio(c) container_of(c, struct byt_gpio, chip)
147 static void __iomem *byt_gpio_reg(struct gpio_chip *chip, unsigned offset,
150 struct byt_gpio *vg = to_byt_gpio(chip);
153 if (reg == BYT_INT_STAT_REG)
154 reg_offset = (offset / 32) * 4;
156 reg_offset = vg->range->pins[offset] * 16;
158 return vg->reg_base + reg_offset + reg;
161 static void byt_gpio_clear_triggering(struct byt_gpio *vg, unsigned offset)
163 void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG);
167 spin_lock_irqsave(&vg->lock, flags);
169 value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
171 spin_unlock_irqrestore(&vg->lock, flags);
174 static u32 byt_get_gpio_mux(struct byt_gpio *vg, unsigned offset)
176 /* SCORE pin 92-93 */
177 if (!strcmp(vg->range->name, BYT_SCORE_ACPI_UID) &&
178 offset >= 92 && offset <= 93)
182 if (!strcmp(vg->range->name, BYT_SUS_ACPI_UID) &&
183 offset >= 11 && offset <= 21)
189 static int byt_gpio_request(struct gpio_chip *chip, unsigned offset)
191 struct byt_gpio *vg = to_byt_gpio(chip);
192 void __iomem *reg = byt_gpio_reg(chip, offset, BYT_CONF0_REG);
196 * In most cases, func pin mux 000 means GPIO function.
197 * But, some pins may have func pin mux 001 represents
200 * Because there are devices out there where some pins were not
201 * configured correctly we allow changing the mux value from
202 * request (but print out warning about that).
204 value = readl(reg) & BYT_PIN_MUX;
205 gpio_mux = byt_get_gpio_mux(vg, offset);
206 if (WARN_ON(gpio_mux != value)) {
209 spin_lock_irqsave(&vg->lock, flags);
210 value = readl(reg) & ~BYT_PIN_MUX;
213 spin_unlock_irqrestore(&vg->lock, flags);
215 dev_warn(&vg->pdev->dev,
216 "pin %u forcibly re-configured as GPIO\n", offset);
219 pm_runtime_get(&vg->pdev->dev);
224 static void byt_gpio_free(struct gpio_chip *chip, unsigned offset)
226 struct byt_gpio *vg = to_byt_gpio(chip);
228 byt_gpio_clear_triggering(vg, offset);
229 pm_runtime_put(&vg->pdev->dev);
232 static int byt_irq_type(struct irq_data *d, unsigned type)
234 struct byt_gpio *vg = to_byt_gpio(irq_data_get_irq_chip_data(d));
235 u32 offset = irqd_to_hwirq(d);
238 void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG);
240 if (offset >= vg->chip.ngpio)
243 spin_lock_irqsave(&vg->lock, flags);
246 WARN(value & BYT_DIRECT_IRQ_EN,
247 "Bad pad config for io mode, force direct_irq_en bit clearing");
249 /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits
250 * are used to indicate high and low level triggering
252 value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG |
257 if (type & IRQ_TYPE_EDGE_BOTH)
258 __irq_set_handler_locked(d->irq, handle_edge_irq);
259 else if (type & IRQ_TYPE_LEVEL_MASK)
260 __irq_set_handler_locked(d->irq, handle_level_irq);
262 spin_unlock_irqrestore(&vg->lock, flags);
267 static int byt_gpio_get(struct gpio_chip *chip, unsigned offset)
269 void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
270 return readl(reg) & BYT_LEVEL;
273 static void byt_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
275 struct byt_gpio *vg = to_byt_gpio(chip);
276 void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
280 spin_lock_irqsave(&vg->lock, flags);
282 old_val = readl(reg);
285 writel(old_val | BYT_LEVEL, reg);
287 writel(old_val & ~BYT_LEVEL, reg);
289 spin_unlock_irqrestore(&vg->lock, flags);
292 static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
294 struct byt_gpio *vg = to_byt_gpio(chip);
295 void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
299 spin_lock_irqsave(&vg->lock, flags);
301 value = readl(reg) | BYT_DIR_MASK;
302 value &= ~BYT_INPUT_EN; /* active low */
305 spin_unlock_irqrestore(&vg->lock, flags);
310 static int byt_gpio_direction_output(struct gpio_chip *chip,
311 unsigned gpio, int value)
313 struct byt_gpio *vg = to_byt_gpio(chip);
314 void __iomem *conf_reg = byt_gpio_reg(chip, gpio, BYT_CONF0_REG);
315 void __iomem *reg = byt_gpio_reg(chip, gpio, BYT_VAL_REG);
319 spin_lock_irqsave(&vg->lock, flags);
322 * Before making any direction modifications, do a check if gpio
323 * is set for direct IRQ. On baytrail, setting GPIO to output does
324 * not make sense, so let's at least warn the caller before they shoot
325 * themselves in the foot.
327 WARN(readl(conf_reg) & BYT_DIRECT_IRQ_EN,
328 "Potential Error: Setting GPIO with direct_irq_en to output");
330 reg_val = readl(reg) | BYT_DIR_MASK;
331 reg_val &= ~(BYT_OUTPUT_EN | BYT_INPUT_EN);
334 writel(reg_val | BYT_LEVEL, reg);
336 writel(reg_val & ~BYT_LEVEL, reg);
338 spin_unlock_irqrestore(&vg->lock, flags);
343 static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
345 struct byt_gpio *vg = to_byt_gpio(chip);
348 u32 conf0, val, offs;
350 spin_lock_irqsave(&vg->lock, flags);
352 for (i = 0; i < vg->chip.ngpio; i++) {
353 const char *pull_str = NULL;
354 const char *pull = NULL;
356 offs = vg->range->pins[i] * 16;
357 conf0 = readl(vg->reg_base + offs + BYT_CONF0_REG);
358 val = readl(vg->reg_base + offs + BYT_VAL_REG);
360 label = gpiochip_is_requested(chip, i);
362 label = "Unrequested";
364 switch (conf0 & BYT_PULL_ASSIGN_MASK) {
365 case BYT_PULL_ASSIGN_UP:
368 case BYT_PULL_ASSIGN_DOWN:
373 switch (conf0 & BYT_PULL_STR_MASK) {
374 case BYT_PULL_STR_2K:
377 case BYT_PULL_STR_10K:
380 case BYT_PULL_STR_20K:
383 case BYT_PULL_STR_40K:
389 " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s",
392 val & BYT_INPUT_EN ? " " : "in",
393 val & BYT_OUTPUT_EN ? " " : "out",
394 val & BYT_LEVEL ? "hi" : "lo",
395 vg->range->pins[i], offs,
397 conf0 & BYT_TRIG_NEG ? " fall" : " ",
398 conf0 & BYT_TRIG_POS ? " rise" : " ",
399 conf0 & BYT_TRIG_LVL ? " level" : " ");
401 if (pull && pull_str)
402 seq_printf(s, " %-4s %-3s", pull, pull_str);
406 if (conf0 & BYT_IODEN)
407 seq_puts(s, " open-drain");
411 spin_unlock_irqrestore(&vg->lock, flags);
414 static void byt_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
416 struct irq_data *data = irq_desc_get_irq_data(desc);
417 struct byt_gpio *vg = to_byt_gpio(irq_desc_get_handler_data(desc));
418 struct irq_chip *chip = irq_data_get_irq_chip(data);
421 unsigned long pending;
424 /* check from GPIO controller which pin triggered the interrupt */
425 for (base = 0; base < vg->chip.ngpio; base += 32) {
426 reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG);
427 pending = readl(reg);
428 for_each_set_bit(pin, &pending, 32) {
429 virq = irq_find_mapping(vg->chip.irqdomain, base + pin);
430 generic_handle_irq(virq);
436 static void byt_irq_ack(struct irq_data *d)
438 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
439 struct byt_gpio *vg = to_byt_gpio(gc);
440 unsigned offset = irqd_to_hwirq(d);
443 reg = byt_gpio_reg(&vg->chip, offset, BYT_INT_STAT_REG);
444 writel(BIT(offset % 32), reg);
447 static void byt_irq_unmask(struct irq_data *d)
449 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
450 struct byt_gpio *vg = to_byt_gpio(gc);
451 unsigned offset = irqd_to_hwirq(d);
456 spin_lock_irqsave(&vg->lock, flags);
458 reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG);
461 switch (irqd_get_trigger_type(d)) {
462 case IRQ_TYPE_LEVEL_HIGH:
463 value |= BYT_TRIG_LVL;
464 case IRQ_TYPE_EDGE_RISING:
465 value |= BYT_TRIG_POS;
467 case IRQ_TYPE_LEVEL_LOW:
468 value |= BYT_TRIG_LVL;
469 case IRQ_TYPE_EDGE_FALLING:
470 value |= BYT_TRIG_NEG;
472 case IRQ_TYPE_EDGE_BOTH:
473 value |= (BYT_TRIG_NEG | BYT_TRIG_POS);
479 spin_unlock_irqrestore(&vg->lock, flags);
482 static void byt_irq_mask(struct irq_data *d)
484 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
485 struct byt_gpio *vg = to_byt_gpio(gc);
487 byt_gpio_clear_triggering(vg, irqd_to_hwirq(d));
490 static struct irq_chip byt_irqchip = {
492 .irq_ack = byt_irq_ack,
493 .irq_mask = byt_irq_mask,
494 .irq_unmask = byt_irq_unmask,
495 .irq_set_type = byt_irq_type,
496 .flags = IRQCHIP_SKIP_SET_WAKE,
499 static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
506 * Clear interrupt triggers for all pins that are GPIOs and
507 * do not use direct IRQ mode. This will prevent spurious
508 * interrupts from misconfigured pins.
510 for (i = 0; i < vg->chip.ngpio; i++) {
511 value = readl(byt_gpio_reg(&vg->chip, i, BYT_CONF0_REG));
512 if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i) &&
513 !(value & BYT_DIRECT_IRQ_EN)) {
514 byt_gpio_clear_triggering(vg, i);
515 dev_dbg(&vg->pdev->dev, "disabling GPIO %d\n", i);
519 /* clear interrupt status trigger registers */
520 for (base = 0; base < vg->chip.ngpio; base += 32) {
521 reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG);
522 writel(0xffffffff, reg);
523 /* make sure trigger bits are cleared, if not then a pin
524 might be misconfigured in bios */
527 dev_err(&vg->pdev->dev,
528 "GPIO interrupt error, pins misconfigured\n");
532 static int byt_gpio_probe(struct platform_device *pdev)
535 struct gpio_chip *gc;
536 struct resource *mem_rc, *irq_rc;
537 struct device *dev = &pdev->dev;
538 struct acpi_device *acpi_dev;
539 struct pinctrl_gpio_range *range;
540 acpi_handle handle = ACPI_HANDLE(dev);
543 if (acpi_bus_get_device(handle, &acpi_dev))
546 vg = devm_kzalloc(dev, sizeof(struct byt_gpio), GFP_KERNEL);
548 dev_err(&pdev->dev, "can't allocate byt_gpio chip data\n");
552 for (range = byt_ranges; range->name; range++) {
553 if (!strcmp(acpi_dev->pnp.unique_id, range->name)) {
554 vg->chip.ngpio = range->npins;
560 if (!vg->chip.ngpio || !vg->range)
564 platform_set_drvdata(pdev, vg);
566 mem_rc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
567 vg->reg_base = devm_ioremap_resource(dev, mem_rc);
568 if (IS_ERR(vg->reg_base))
569 return PTR_ERR(vg->reg_base);
571 spin_lock_init(&vg->lock);
574 gc->label = dev_name(&pdev->dev);
575 gc->owner = THIS_MODULE;
576 gc->request = byt_gpio_request;
577 gc->free = byt_gpio_free;
578 gc->direction_input = byt_gpio_direction_input;
579 gc->direction_output = byt_gpio_direction_output;
580 gc->get = byt_gpio_get;
581 gc->set = byt_gpio_set;
582 gc->dbg_show = byt_gpio_dbg_show;
584 gc->can_sleep = false;
587 ret = gpiochip_add(gc);
589 dev_err(&pdev->dev, "failed adding byt-gpio chip\n");
593 /* set up interrupts */
594 irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
595 if (irq_rc && irq_rc->start) {
596 byt_gpio_irq_init_hw(vg);
597 ret = gpiochip_irqchip_add(gc, &byt_irqchip, 0,
598 handle_simple_irq, IRQ_TYPE_NONE);
600 dev_err(dev, "failed to add irqchip\n");
605 gpiochip_set_chained_irqchip(gc, &byt_irqchip,
606 (unsigned)irq_rc->start,
607 byt_gpio_irq_handler);
610 pm_runtime_enable(dev);
615 static int byt_gpio_runtime_suspend(struct device *dev)
620 static int byt_gpio_runtime_resume(struct device *dev)
625 static const struct dev_pm_ops byt_gpio_pm_ops = {
626 .runtime_suspend = byt_gpio_runtime_suspend,
627 .runtime_resume = byt_gpio_runtime_resume,
630 static const struct acpi_device_id byt_gpio_acpi_match[] = {
635 MODULE_DEVICE_TABLE(acpi, byt_gpio_acpi_match);
637 static int byt_gpio_remove(struct platform_device *pdev)
639 struct byt_gpio *vg = platform_get_drvdata(pdev);
641 pm_runtime_disable(&pdev->dev);
642 gpiochip_remove(&vg->chip);
647 static struct platform_driver byt_gpio_driver = {
648 .probe = byt_gpio_probe,
649 .remove = byt_gpio_remove,
652 .pm = &byt_gpio_pm_ops,
653 .acpi_match_table = ACPI_PTR(byt_gpio_acpi_match),
657 static int __init byt_gpio_init(void)
659 return platform_driver_register(&byt_gpio_driver);
661 subsys_initcall(byt_gpio_init);
663 static void __exit byt_gpio_exit(void)
665 platform_driver_unregister(&byt_gpio_driver);
667 module_exit(byt_gpio_exit);