1 // SPDX-License-Identifier: GPL-2.0
3 * Cherryview/Braswell pinctrl driver
5 * Copyright (C) 2014, Intel Corporation
6 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
8 * This driver is based on the original Cherryview GPIO driver by
9 * Ning Li <ning.li@intel.com>
10 * Alan Cox <alan@linux.intel.com>
13 #include <linux/acpi.h>
14 #include <linux/dmi.h>
15 #include <linux/gpio/driver.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/types.h>
21 #include <linux/pinctrl/pinctrl.h>
22 #include <linux/pinctrl/pinmux.h>
23 #include <linux/pinctrl/pinconf.h>
24 #include <linux/pinctrl/pinconf-generic.h>
26 #include "pinctrl-intel.h"
28 #define CHV_INTSTAT 0x300
29 #define CHV_INTMASK 0x380
31 #define FAMILY_PAD_REGS_OFF 0x4400
32 #define FAMILY_PAD_REGS_SIZE 0x400
33 #define MAX_FAMILY_PAD_GPIO_NO 15
34 #define GPIO_REGS_SIZE 8
36 #define CHV_PADCTRL0 0x000
37 #define CHV_PADCTRL0_INTSEL_SHIFT 28
38 #define CHV_PADCTRL0_INTSEL_MASK (0xf << CHV_PADCTRL0_INTSEL_SHIFT)
39 #define CHV_PADCTRL0_TERM_UP BIT(23)
40 #define CHV_PADCTRL0_TERM_SHIFT 20
41 #define CHV_PADCTRL0_TERM_MASK (7 << CHV_PADCTRL0_TERM_SHIFT)
42 #define CHV_PADCTRL0_TERM_20K 1
43 #define CHV_PADCTRL0_TERM_5K 2
44 #define CHV_PADCTRL0_TERM_1K 4
45 #define CHV_PADCTRL0_PMODE_SHIFT 16
46 #define CHV_PADCTRL0_PMODE_MASK (0xf << CHV_PADCTRL0_PMODE_SHIFT)
47 #define CHV_PADCTRL0_GPIOEN BIT(15)
48 #define CHV_PADCTRL0_GPIOCFG_SHIFT 8
49 #define CHV_PADCTRL0_GPIOCFG_MASK (7 << CHV_PADCTRL0_GPIOCFG_SHIFT)
50 #define CHV_PADCTRL0_GPIOCFG_GPIO 0
51 #define CHV_PADCTRL0_GPIOCFG_GPO 1
52 #define CHV_PADCTRL0_GPIOCFG_GPI 2
53 #define CHV_PADCTRL0_GPIOCFG_HIZ 3
54 #define CHV_PADCTRL0_GPIOTXSTATE BIT(1)
55 #define CHV_PADCTRL0_GPIORXSTATE BIT(0)
57 #define CHV_PADCTRL1 0x004
58 #define CHV_PADCTRL1_CFGLOCK BIT(31)
59 #define CHV_PADCTRL1_INVRXTX_SHIFT 4
60 #define CHV_PADCTRL1_INVRXTX_MASK (0xf << CHV_PADCTRL1_INVRXTX_SHIFT)
61 #define CHV_PADCTRL1_INVRXTX_TXENABLE (2 << CHV_PADCTRL1_INVRXTX_SHIFT)
62 #define CHV_PADCTRL1_ODEN BIT(3)
63 #define CHV_PADCTRL1_INVRXTX_RXDATA (4 << CHV_PADCTRL1_INVRXTX_SHIFT)
64 #define CHV_PADCTRL1_INTWAKECFG_MASK 7
65 #define CHV_PADCTRL1_INTWAKECFG_FALLING 1
66 #define CHV_PADCTRL1_INTWAKECFG_RISING 2
67 #define CHV_PADCTRL1_INTWAKECFG_BOTH 3
68 #define CHV_PADCTRL1_INTWAKECFG_LEVEL 4
71 * struct chv_alternate_function - A per group or per pin alternate function
72 * @pin: Pin number (only used in per pin configs)
73 * @mode: Mode the pin should be set in
74 * @invert_oe: Invert OE for this pin
76 struct chv_alternate_function {
83 * struct chv_pincgroup - describes a CHV pin group
84 * @name: Name of the group
85 * @pins: An array of pins in this group
86 * @npins: Number of pins in this group
87 * @altfunc: Alternate function applied to all pins in this group
88 * @overrides: Alternate function override per pin or %NULL if not used
89 * @noverrides: Number of per pin alternate function overrides if
94 const unsigned int *pins;
96 struct chv_alternate_function altfunc;
97 const struct chv_alternate_function *overrides;
102 * struct chv_gpio_pinrange - A range of pins that can be used as GPIOs
103 * @base: Start pin number
104 * @npins: Number of pins in this range
106 struct chv_gpio_pinrange {
112 * struct chv_community - A community specific configuration
113 * @uid: ACPI _UID used to match the community
114 * @pins: All pins in this community
115 * @npins: Number of pins
116 * @groups: All groups in this community
117 * @ngroups: Number of groups
118 * @functions: All functions in this community
119 * @nfunctions: Number of functions
120 * @gpio_ranges: An array of GPIO ranges in this community
121 * @ngpio_ranges: Number of GPIO ranges
122 * @nirqs: Total number of IRQs this community can generate
123 * @acpi_space_id: An address space ID for ACPI OpRegion handler
125 struct chv_community {
127 const struct pinctrl_pin_desc *pins;
129 const struct chv_pingroup *groups;
131 const struct intel_function *functions;
133 const struct chv_gpio_pinrange *gpio_ranges;
136 acpi_adr_space_type acpi_space_id;
139 struct chv_pin_context {
145 * struct chv_pinctrl - CHV pinctrl private structure
146 * @dev: Pointer to the parent device
147 * @pctldesc: Pin controller description
148 * @pctldev: Pointer to the pin controller device
149 * @chip: GPIO chip in this pin controller
150 * @regs: MMIO registers
151 * @intr_lines: Stores mapping between 16 HW interrupt wires and GPIO
152 * offset (in GPIO number space)
153 * @community: Community this pinctrl instance represents
154 * @saved_intmask: Interrupt mask saved for system sleep
155 * @saved_pin_context: Pointer to a context of the pins saved for system sleep
157 * The first group in @groups is expected to contain all pins that can be
162 struct pinctrl_desc pctldesc;
163 struct pinctrl_dev *pctldev;
164 struct gpio_chip chip;
166 unsigned intr_lines[16];
167 const struct chv_community *community;
169 struct chv_pin_context *saved_pin_context;
172 #define ALTERNATE_FUNCTION(p, m, i) \
179 #define PIN_GROUP_WITH_ALT(n, p, m, i) \
183 .npins = ARRAY_SIZE((p)), \
184 .altfunc.mode = (m), \
185 .altfunc.invert_oe = (i), \
188 #define PIN_GROUP_WITH_OVERRIDE(n, p, m, i, o) \
192 .npins = ARRAY_SIZE((p)), \
193 .altfunc.mode = (m), \
194 .altfunc.invert_oe = (i), \
196 .noverrides = ARRAY_SIZE((o)), \
199 #define GPIO_PINRANGE(start, end) \
202 .npins = (end) - (start) + 1, \
205 static const struct pinctrl_pin_desc southwest_pins[] = {
206 PINCTRL_PIN(0, "FST_SPI_D2"),
207 PINCTRL_PIN(1, "FST_SPI_D0"),
208 PINCTRL_PIN(2, "FST_SPI_CLK"),
209 PINCTRL_PIN(3, "FST_SPI_D3"),
210 PINCTRL_PIN(4, "FST_SPI_CS1_B"),
211 PINCTRL_PIN(5, "FST_SPI_D1"),
212 PINCTRL_PIN(6, "FST_SPI_CS0_B"),
213 PINCTRL_PIN(7, "FST_SPI_CS2_B"),
215 PINCTRL_PIN(15, "UART1_RTS_B"),
216 PINCTRL_PIN(16, "UART1_RXD"),
217 PINCTRL_PIN(17, "UART2_RXD"),
218 PINCTRL_PIN(18, "UART1_CTS_B"),
219 PINCTRL_PIN(19, "UART2_RTS_B"),
220 PINCTRL_PIN(20, "UART1_TXD"),
221 PINCTRL_PIN(21, "UART2_TXD"),
222 PINCTRL_PIN(22, "UART2_CTS_B"),
224 PINCTRL_PIN(30, "MF_HDA_CLK"),
225 PINCTRL_PIN(31, "MF_HDA_RSTB"),
226 PINCTRL_PIN(32, "MF_HDA_SDIO"),
227 PINCTRL_PIN(33, "MF_HDA_SDO"),
228 PINCTRL_PIN(34, "MF_HDA_DOCKRSTB"),
229 PINCTRL_PIN(35, "MF_HDA_SYNC"),
230 PINCTRL_PIN(36, "MF_HDA_SDI1"),
231 PINCTRL_PIN(37, "MF_HDA_DOCKENB"),
233 PINCTRL_PIN(45, "I2C5_SDA"),
234 PINCTRL_PIN(46, "I2C4_SDA"),
235 PINCTRL_PIN(47, "I2C6_SDA"),
236 PINCTRL_PIN(48, "I2C5_SCL"),
237 PINCTRL_PIN(49, "I2C_NFC_SDA"),
238 PINCTRL_PIN(50, "I2C4_SCL"),
239 PINCTRL_PIN(51, "I2C6_SCL"),
240 PINCTRL_PIN(52, "I2C_NFC_SCL"),
242 PINCTRL_PIN(60, "I2C1_SDA"),
243 PINCTRL_PIN(61, "I2C0_SDA"),
244 PINCTRL_PIN(62, "I2C2_SDA"),
245 PINCTRL_PIN(63, "I2C1_SCL"),
246 PINCTRL_PIN(64, "I2C3_SDA"),
247 PINCTRL_PIN(65, "I2C0_SCL"),
248 PINCTRL_PIN(66, "I2C2_SCL"),
249 PINCTRL_PIN(67, "I2C3_SCL"),
251 PINCTRL_PIN(75, "SATA_GP0"),
252 PINCTRL_PIN(76, "SATA_GP1"),
253 PINCTRL_PIN(77, "SATA_LEDN"),
254 PINCTRL_PIN(78, "SATA_GP2"),
255 PINCTRL_PIN(79, "MF_SMB_ALERTB"),
256 PINCTRL_PIN(80, "SATA_GP3"),
257 PINCTRL_PIN(81, "MF_SMB_CLK"),
258 PINCTRL_PIN(82, "MF_SMB_DATA"),
260 PINCTRL_PIN(90, "PCIE_CLKREQ0B"),
261 PINCTRL_PIN(91, "PCIE_CLKREQ1B"),
262 PINCTRL_PIN(92, "GP_SSP_2_CLK"),
263 PINCTRL_PIN(93, "PCIE_CLKREQ2B"),
264 PINCTRL_PIN(94, "GP_SSP_2_RXD"),
265 PINCTRL_PIN(95, "PCIE_CLKREQ3B"),
266 PINCTRL_PIN(96, "GP_SSP_2_FS"),
267 PINCTRL_PIN(97, "GP_SSP_2_TXD"),
270 static const unsigned southwest_uart0_pins[] = { 16, 20 };
271 static const unsigned southwest_uart1_pins[] = { 15, 16, 18, 20 };
272 static const unsigned southwest_uart2_pins[] = { 17, 19, 21, 22 };
273 static const unsigned southwest_i2c0_pins[] = { 61, 65 };
274 static const unsigned southwest_hda_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37 };
275 static const unsigned southwest_lpe_pins[] = {
276 30, 31, 32, 33, 34, 35, 36, 37, 92, 94, 96, 97,
278 static const unsigned southwest_i2c1_pins[] = { 60, 63 };
279 static const unsigned southwest_i2c2_pins[] = { 62, 66 };
280 static const unsigned southwest_i2c3_pins[] = { 64, 67 };
281 static const unsigned southwest_i2c4_pins[] = { 46, 50 };
282 static const unsigned southwest_i2c5_pins[] = { 45, 48 };
283 static const unsigned southwest_i2c6_pins[] = { 47, 51 };
284 static const unsigned southwest_i2c_nfc_pins[] = { 49, 52 };
285 static const unsigned southwest_spi3_pins[] = { 76, 79, 80, 81, 82 };
287 /* LPE I2S TXD pins need to have invert_oe set */
288 static const struct chv_alternate_function southwest_lpe_altfuncs[] = {
289 ALTERNATE_FUNCTION(30, 1, true),
290 ALTERNATE_FUNCTION(34, 1, true),
291 ALTERNATE_FUNCTION(97, 1, true),
295 * Two spi3 chipselects are available in different mode than the main spi3
296 * functionality, which is using mode 1.
298 static const struct chv_alternate_function southwest_spi3_altfuncs[] = {
299 ALTERNATE_FUNCTION(76, 3, false),
300 ALTERNATE_FUNCTION(80, 3, false),
303 static const struct chv_pingroup southwest_groups[] = {
304 PIN_GROUP_WITH_ALT("uart0_grp", southwest_uart0_pins, 2, false),
305 PIN_GROUP_WITH_ALT("uart1_grp", southwest_uart1_pins, 1, false),
306 PIN_GROUP_WITH_ALT("uart2_grp", southwest_uart2_pins, 1, false),
307 PIN_GROUP_WITH_ALT("hda_grp", southwest_hda_pins, 2, false),
308 PIN_GROUP_WITH_ALT("i2c0_grp", southwest_i2c0_pins, 1, true),
309 PIN_GROUP_WITH_ALT("i2c1_grp", southwest_i2c1_pins, 1, true),
310 PIN_GROUP_WITH_ALT("i2c2_grp", southwest_i2c2_pins, 1, true),
311 PIN_GROUP_WITH_ALT("i2c3_grp", southwest_i2c3_pins, 1, true),
312 PIN_GROUP_WITH_ALT("i2c4_grp", southwest_i2c4_pins, 1, true),
313 PIN_GROUP_WITH_ALT("i2c5_grp", southwest_i2c5_pins, 1, true),
314 PIN_GROUP_WITH_ALT("i2c6_grp", southwest_i2c6_pins, 1, true),
315 PIN_GROUP_WITH_ALT("i2c_nfc_grp", southwest_i2c_nfc_pins, 2, true),
317 PIN_GROUP_WITH_OVERRIDE("lpe_grp", southwest_lpe_pins, 1, false,
318 southwest_lpe_altfuncs),
319 PIN_GROUP_WITH_OVERRIDE("spi3_grp", southwest_spi3_pins, 2, false,
320 southwest_spi3_altfuncs),
323 static const char * const southwest_uart0_groups[] = { "uart0_grp" };
324 static const char * const southwest_uart1_groups[] = { "uart1_grp" };
325 static const char * const southwest_uart2_groups[] = { "uart2_grp" };
326 static const char * const southwest_hda_groups[] = { "hda_grp" };
327 static const char * const southwest_lpe_groups[] = { "lpe_grp" };
328 static const char * const southwest_i2c0_groups[] = { "i2c0_grp" };
329 static const char * const southwest_i2c1_groups[] = { "i2c1_grp" };
330 static const char * const southwest_i2c2_groups[] = { "i2c2_grp" };
331 static const char * const southwest_i2c3_groups[] = { "i2c3_grp" };
332 static const char * const southwest_i2c4_groups[] = { "i2c4_grp" };
333 static const char * const southwest_i2c5_groups[] = { "i2c5_grp" };
334 static const char * const southwest_i2c6_groups[] = { "i2c6_grp" };
335 static const char * const southwest_i2c_nfc_groups[] = { "i2c_nfc_grp" };
336 static const char * const southwest_spi3_groups[] = { "spi3_grp" };
339 * Only do pinmuxing for certain LPSS devices for now. Rest of the pins are
340 * enabled only as GPIOs.
342 static const struct intel_function southwest_functions[] = {
343 FUNCTION("uart0", southwest_uart0_groups),
344 FUNCTION("uart1", southwest_uart1_groups),
345 FUNCTION("uart2", southwest_uart2_groups),
346 FUNCTION("hda", southwest_hda_groups),
347 FUNCTION("lpe", southwest_lpe_groups),
348 FUNCTION("i2c0", southwest_i2c0_groups),
349 FUNCTION("i2c1", southwest_i2c1_groups),
350 FUNCTION("i2c2", southwest_i2c2_groups),
351 FUNCTION("i2c3", southwest_i2c3_groups),
352 FUNCTION("i2c4", southwest_i2c4_groups),
353 FUNCTION("i2c5", southwest_i2c5_groups),
354 FUNCTION("i2c6", southwest_i2c6_groups),
355 FUNCTION("i2c_nfc", southwest_i2c_nfc_groups),
356 FUNCTION("spi3", southwest_spi3_groups),
359 static const struct chv_gpio_pinrange southwest_gpio_ranges[] = {
361 GPIO_PINRANGE(15, 22),
362 GPIO_PINRANGE(30, 37),
363 GPIO_PINRANGE(45, 52),
364 GPIO_PINRANGE(60, 67),
365 GPIO_PINRANGE(75, 82),
366 GPIO_PINRANGE(90, 97),
369 static const struct chv_community southwest_community = {
371 .pins = southwest_pins,
372 .npins = ARRAY_SIZE(southwest_pins),
373 .groups = southwest_groups,
374 .ngroups = ARRAY_SIZE(southwest_groups),
375 .functions = southwest_functions,
376 .nfunctions = ARRAY_SIZE(southwest_functions),
377 .gpio_ranges = southwest_gpio_ranges,
378 .ngpio_ranges = ARRAY_SIZE(southwest_gpio_ranges),
380 * Southwest community can benerate GPIO interrupts only for the
381 * first 8 interrupts. The upper half (8-15) can only be used to
385 .acpi_space_id = 0x91,
388 static const struct pinctrl_pin_desc north_pins[] = {
389 PINCTRL_PIN(0, "GPIO_DFX_0"),
390 PINCTRL_PIN(1, "GPIO_DFX_3"),
391 PINCTRL_PIN(2, "GPIO_DFX_7"),
392 PINCTRL_PIN(3, "GPIO_DFX_1"),
393 PINCTRL_PIN(4, "GPIO_DFX_5"),
394 PINCTRL_PIN(5, "GPIO_DFX_4"),
395 PINCTRL_PIN(6, "GPIO_DFX_8"),
396 PINCTRL_PIN(7, "GPIO_DFX_2"),
397 PINCTRL_PIN(8, "GPIO_DFX_6"),
399 PINCTRL_PIN(15, "GPIO_SUS0"),
400 PINCTRL_PIN(16, "SEC_GPIO_SUS10"),
401 PINCTRL_PIN(17, "GPIO_SUS3"),
402 PINCTRL_PIN(18, "GPIO_SUS7"),
403 PINCTRL_PIN(19, "GPIO_SUS1"),
404 PINCTRL_PIN(20, "GPIO_SUS5"),
405 PINCTRL_PIN(21, "SEC_GPIO_SUS11"),
406 PINCTRL_PIN(22, "GPIO_SUS4"),
407 PINCTRL_PIN(23, "SEC_GPIO_SUS8"),
408 PINCTRL_PIN(24, "GPIO_SUS2"),
409 PINCTRL_PIN(25, "GPIO_SUS6"),
410 PINCTRL_PIN(26, "CX_PREQ_B"),
411 PINCTRL_PIN(27, "SEC_GPIO_SUS9"),
413 PINCTRL_PIN(30, "TRST_B"),
414 PINCTRL_PIN(31, "TCK"),
415 PINCTRL_PIN(32, "PROCHOT_B"),
416 PINCTRL_PIN(33, "SVIDO_DATA"),
417 PINCTRL_PIN(34, "TMS"),
418 PINCTRL_PIN(35, "CX_PRDY_B_2"),
419 PINCTRL_PIN(36, "TDO_2"),
420 PINCTRL_PIN(37, "CX_PRDY_B"),
421 PINCTRL_PIN(38, "SVIDO_ALERT_B"),
422 PINCTRL_PIN(39, "TDO"),
423 PINCTRL_PIN(40, "SVIDO_CLK"),
424 PINCTRL_PIN(41, "TDI"),
426 PINCTRL_PIN(45, "GP_CAMERASB_05"),
427 PINCTRL_PIN(46, "GP_CAMERASB_02"),
428 PINCTRL_PIN(47, "GP_CAMERASB_08"),
429 PINCTRL_PIN(48, "GP_CAMERASB_00"),
430 PINCTRL_PIN(49, "GP_CAMERASB_06"),
431 PINCTRL_PIN(50, "GP_CAMERASB_10"),
432 PINCTRL_PIN(51, "GP_CAMERASB_03"),
433 PINCTRL_PIN(52, "GP_CAMERASB_09"),
434 PINCTRL_PIN(53, "GP_CAMERASB_01"),
435 PINCTRL_PIN(54, "GP_CAMERASB_07"),
436 PINCTRL_PIN(55, "GP_CAMERASB_11"),
437 PINCTRL_PIN(56, "GP_CAMERASB_04"),
439 PINCTRL_PIN(60, "PANEL0_BKLTEN"),
440 PINCTRL_PIN(61, "HV_DDI0_HPD"),
441 PINCTRL_PIN(62, "HV_DDI2_DDC_SDA"),
442 PINCTRL_PIN(63, "PANEL1_BKLTCTL"),
443 PINCTRL_PIN(64, "HV_DDI1_HPD"),
444 PINCTRL_PIN(65, "PANEL0_BKLTCTL"),
445 PINCTRL_PIN(66, "HV_DDI0_DDC_SDA"),
446 PINCTRL_PIN(67, "HV_DDI2_DDC_SCL"),
447 PINCTRL_PIN(68, "HV_DDI2_HPD"),
448 PINCTRL_PIN(69, "PANEL1_VDDEN"),
449 PINCTRL_PIN(70, "PANEL1_BKLTEN"),
450 PINCTRL_PIN(71, "HV_DDI0_DDC_SCL"),
451 PINCTRL_PIN(72, "PANEL0_VDDEN"),
454 static const struct chv_gpio_pinrange north_gpio_ranges[] = {
456 GPIO_PINRANGE(15, 27),
457 GPIO_PINRANGE(30, 41),
458 GPIO_PINRANGE(45, 56),
459 GPIO_PINRANGE(60, 72),
462 static const struct chv_community north_community = {
465 .npins = ARRAY_SIZE(north_pins),
466 .gpio_ranges = north_gpio_ranges,
467 .ngpio_ranges = ARRAY_SIZE(north_gpio_ranges),
469 * North community can generate GPIO interrupts only for the first
470 * 8 interrupts. The upper half (8-15) can only be used to trigger
474 .acpi_space_id = 0x92,
477 static const struct pinctrl_pin_desc east_pins[] = {
478 PINCTRL_PIN(0, "PMU_SLP_S3_B"),
479 PINCTRL_PIN(1, "PMU_BATLOW_B"),
480 PINCTRL_PIN(2, "SUS_STAT_B"),
481 PINCTRL_PIN(3, "PMU_SLP_S0IX_B"),
482 PINCTRL_PIN(4, "PMU_AC_PRESENT"),
483 PINCTRL_PIN(5, "PMU_PLTRST_B"),
484 PINCTRL_PIN(6, "PMU_SUSCLK"),
485 PINCTRL_PIN(7, "PMU_SLP_LAN_B"),
486 PINCTRL_PIN(8, "PMU_PWRBTN_B"),
487 PINCTRL_PIN(9, "PMU_SLP_S4_B"),
488 PINCTRL_PIN(10, "PMU_WAKE_B"),
489 PINCTRL_PIN(11, "PMU_WAKE_LAN_B"),
491 PINCTRL_PIN(15, "MF_ISH_GPIO_3"),
492 PINCTRL_PIN(16, "MF_ISH_GPIO_7"),
493 PINCTRL_PIN(17, "MF_ISH_I2C1_SCL"),
494 PINCTRL_PIN(18, "MF_ISH_GPIO_1"),
495 PINCTRL_PIN(19, "MF_ISH_GPIO_5"),
496 PINCTRL_PIN(20, "MF_ISH_GPIO_9"),
497 PINCTRL_PIN(21, "MF_ISH_GPIO_0"),
498 PINCTRL_PIN(22, "MF_ISH_GPIO_4"),
499 PINCTRL_PIN(23, "MF_ISH_GPIO_8"),
500 PINCTRL_PIN(24, "MF_ISH_GPIO_2"),
501 PINCTRL_PIN(25, "MF_ISH_GPIO_6"),
502 PINCTRL_PIN(26, "MF_ISH_I2C1_SDA"),
505 static const struct chv_gpio_pinrange east_gpio_ranges[] = {
506 GPIO_PINRANGE(0, 11),
507 GPIO_PINRANGE(15, 26),
510 static const struct chv_community east_community = {
513 .npins = ARRAY_SIZE(east_pins),
514 .gpio_ranges = east_gpio_ranges,
515 .ngpio_ranges = ARRAY_SIZE(east_gpio_ranges),
517 .acpi_space_id = 0x93,
520 static const struct pinctrl_pin_desc southeast_pins[] = {
521 PINCTRL_PIN(0, "MF_PLT_CLK0"),
522 PINCTRL_PIN(1, "PWM1"),
523 PINCTRL_PIN(2, "MF_PLT_CLK1"),
524 PINCTRL_PIN(3, "MF_PLT_CLK4"),
525 PINCTRL_PIN(4, "MF_PLT_CLK3"),
526 PINCTRL_PIN(5, "PWM0"),
527 PINCTRL_PIN(6, "MF_PLT_CLK5"),
528 PINCTRL_PIN(7, "MF_PLT_CLK2"),
530 PINCTRL_PIN(15, "SDMMC2_D3_CD_B"),
531 PINCTRL_PIN(16, "SDMMC1_CLK"),
532 PINCTRL_PIN(17, "SDMMC1_D0"),
533 PINCTRL_PIN(18, "SDMMC2_D1"),
534 PINCTRL_PIN(19, "SDMMC2_CLK"),
535 PINCTRL_PIN(20, "SDMMC1_D2"),
536 PINCTRL_PIN(21, "SDMMC2_D2"),
537 PINCTRL_PIN(22, "SDMMC2_CMD"),
538 PINCTRL_PIN(23, "SDMMC1_CMD"),
539 PINCTRL_PIN(24, "SDMMC1_D1"),
540 PINCTRL_PIN(25, "SDMMC2_D0"),
541 PINCTRL_PIN(26, "SDMMC1_D3_CD_B"),
543 PINCTRL_PIN(30, "SDMMC3_D1"),
544 PINCTRL_PIN(31, "SDMMC3_CLK"),
545 PINCTRL_PIN(32, "SDMMC3_D3"),
546 PINCTRL_PIN(33, "SDMMC3_D2"),
547 PINCTRL_PIN(34, "SDMMC3_CMD"),
548 PINCTRL_PIN(35, "SDMMC3_D0"),
550 PINCTRL_PIN(45, "MF_LPC_AD2"),
551 PINCTRL_PIN(46, "LPC_CLKRUNB"),
552 PINCTRL_PIN(47, "MF_LPC_AD0"),
553 PINCTRL_PIN(48, "LPC_FRAMEB"),
554 PINCTRL_PIN(49, "MF_LPC_CLKOUT1"),
555 PINCTRL_PIN(50, "MF_LPC_AD3"),
556 PINCTRL_PIN(51, "MF_LPC_CLKOUT0"),
557 PINCTRL_PIN(52, "MF_LPC_AD1"),
559 PINCTRL_PIN(60, "SPI1_MISO"),
560 PINCTRL_PIN(61, "SPI1_CSO_B"),
561 PINCTRL_PIN(62, "SPI1_CLK"),
562 PINCTRL_PIN(63, "MMC1_D6"),
563 PINCTRL_PIN(64, "SPI1_MOSI"),
564 PINCTRL_PIN(65, "MMC1_D5"),
565 PINCTRL_PIN(66, "SPI1_CS1_B"),
566 PINCTRL_PIN(67, "MMC1_D4_SD_WE"),
567 PINCTRL_PIN(68, "MMC1_D7"),
568 PINCTRL_PIN(69, "MMC1_RCLK"),
570 PINCTRL_PIN(75, "USB_OC1_B"),
571 PINCTRL_PIN(76, "PMU_RESETBUTTON_B"),
572 PINCTRL_PIN(77, "GPIO_ALERT"),
573 PINCTRL_PIN(78, "SDMMC3_PWR_EN_B"),
574 PINCTRL_PIN(79, "ILB_SERIRQ"),
575 PINCTRL_PIN(80, "USB_OC0_B"),
576 PINCTRL_PIN(81, "SDMMC3_CD_B"),
577 PINCTRL_PIN(82, "SPKR"),
578 PINCTRL_PIN(83, "SUSPWRDNACK"),
579 PINCTRL_PIN(84, "SPARE_PIN"),
580 PINCTRL_PIN(85, "SDMMC3_1P8_EN"),
583 static const unsigned southeast_pwm0_pins[] = { 5 };
584 static const unsigned southeast_pwm1_pins[] = { 1 };
585 static const unsigned southeast_sdmmc1_pins[] = {
586 16, 17, 20, 23, 24, 26, 63, 65, 67, 68, 69,
588 static const unsigned southeast_sdmmc2_pins[] = { 15, 18, 19, 21, 22, 25 };
589 static const unsigned southeast_sdmmc3_pins[] = {
590 30, 31, 32, 33, 34, 35, 78, 81, 85,
592 static const unsigned southeast_spi1_pins[] = { 60, 61, 62, 64, 66 };
593 static const unsigned southeast_spi2_pins[] = { 2, 3, 4, 6, 7 };
595 static const struct chv_pingroup southeast_groups[] = {
596 PIN_GROUP_WITH_ALT("pwm0_grp", southeast_pwm0_pins, 1, false),
597 PIN_GROUP_WITH_ALT("pwm1_grp", southeast_pwm1_pins, 1, false),
598 PIN_GROUP_WITH_ALT("sdmmc1_grp", southeast_sdmmc1_pins, 1, false),
599 PIN_GROUP_WITH_ALT("sdmmc2_grp", southeast_sdmmc2_pins, 1, false),
600 PIN_GROUP_WITH_ALT("sdmmc3_grp", southeast_sdmmc3_pins, 1, false),
601 PIN_GROUP_WITH_ALT("spi1_grp", southeast_spi1_pins, 1, false),
602 PIN_GROUP_WITH_ALT("spi2_grp", southeast_spi2_pins, 4, false),
605 static const char * const southeast_pwm0_groups[] = { "pwm0_grp" };
606 static const char * const southeast_pwm1_groups[] = { "pwm1_grp" };
607 static const char * const southeast_sdmmc1_groups[] = { "sdmmc1_grp" };
608 static const char * const southeast_sdmmc2_groups[] = { "sdmmc2_grp" };
609 static const char * const southeast_sdmmc3_groups[] = { "sdmmc3_grp" };
610 static const char * const southeast_spi1_groups[] = { "spi1_grp" };
611 static const char * const southeast_spi2_groups[] = { "spi2_grp" };
613 static const struct intel_function southeast_functions[] = {
614 FUNCTION("pwm0", southeast_pwm0_groups),
615 FUNCTION("pwm1", southeast_pwm1_groups),
616 FUNCTION("sdmmc1", southeast_sdmmc1_groups),
617 FUNCTION("sdmmc2", southeast_sdmmc2_groups),
618 FUNCTION("sdmmc3", southeast_sdmmc3_groups),
619 FUNCTION("spi1", southeast_spi1_groups),
620 FUNCTION("spi2", southeast_spi2_groups),
623 static const struct chv_gpio_pinrange southeast_gpio_ranges[] = {
625 GPIO_PINRANGE(15, 26),
626 GPIO_PINRANGE(30, 35),
627 GPIO_PINRANGE(45, 52),
628 GPIO_PINRANGE(60, 69),
629 GPIO_PINRANGE(75, 85),
632 static const struct chv_community southeast_community = {
634 .pins = southeast_pins,
635 .npins = ARRAY_SIZE(southeast_pins),
636 .groups = southeast_groups,
637 .ngroups = ARRAY_SIZE(southeast_groups),
638 .functions = southeast_functions,
639 .nfunctions = ARRAY_SIZE(southeast_functions),
640 .gpio_ranges = southeast_gpio_ranges,
641 .ngpio_ranges = ARRAY_SIZE(southeast_gpio_ranges),
643 .acpi_space_id = 0x94,
646 static const struct chv_community *chv_communities[] = {
647 &southwest_community,
650 &southeast_community,
654 * Lock to serialize register accesses
656 * Due to a silicon issue, a shared lock must be used to prevent
657 * concurrent accesses across the 4 GPIO controllers.
659 * See Intel Atom Z8000 Processor Series Specification Update (Rev. 005),
660 * errata #CHT34, for further information.
662 static DEFINE_RAW_SPINLOCK(chv_lock);
664 static void __iomem *chv_padreg(struct chv_pinctrl *pctrl, unsigned int offset,
667 unsigned int family_no = offset / MAX_FAMILY_PAD_GPIO_NO;
668 unsigned int pad_no = offset % MAX_FAMILY_PAD_GPIO_NO;
670 offset = FAMILY_PAD_REGS_OFF + FAMILY_PAD_REGS_SIZE * family_no +
671 GPIO_REGS_SIZE * pad_no;
673 return pctrl->regs + offset + reg;
676 static void chv_writel(u32 value, void __iomem *reg)
679 /* simple readback to confirm the bus transferring done */
683 /* When Pad Cfg is locked, driver can only change GPIOTXState or GPIORXState */
684 static bool chv_pad_locked(struct chv_pinctrl *pctrl, unsigned int offset)
688 reg = chv_padreg(pctrl, offset, CHV_PADCTRL1);
689 return readl(reg) & CHV_PADCTRL1_CFGLOCK;
692 static int chv_get_groups_count(struct pinctrl_dev *pctldev)
694 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
696 return pctrl->community->ngroups;
699 static const char *chv_get_group_name(struct pinctrl_dev *pctldev,
702 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
704 return pctrl->community->groups[group].name;
707 static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
708 const unsigned int **pins, unsigned int *npins)
710 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
712 *pins = pctrl->community->groups[group].pins;
713 *npins = pctrl->community->groups[group].npins;
717 static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
720 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
725 raw_spin_lock_irqsave(&chv_lock, flags);
727 ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
728 ctrl1 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL1));
729 locked = chv_pad_locked(pctrl, offset);
731 raw_spin_unlock_irqrestore(&chv_lock, flags);
733 if (ctrl0 & CHV_PADCTRL0_GPIOEN) {
734 seq_puts(s, "GPIO ");
738 mode = ctrl0 & CHV_PADCTRL0_PMODE_MASK;
739 mode >>= CHV_PADCTRL0_PMODE_SHIFT;
741 seq_printf(s, "mode %d ", mode);
744 seq_printf(s, "0x%08x 0x%08x", ctrl0, ctrl1);
747 seq_puts(s, " [LOCKED]");
750 static const struct pinctrl_ops chv_pinctrl_ops = {
751 .get_groups_count = chv_get_groups_count,
752 .get_group_name = chv_get_group_name,
753 .get_group_pins = chv_get_group_pins,
754 .pin_dbg_show = chv_pin_dbg_show,
757 static int chv_get_functions_count(struct pinctrl_dev *pctldev)
759 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
761 return pctrl->community->nfunctions;
764 static const char *chv_get_function_name(struct pinctrl_dev *pctldev,
765 unsigned int function)
767 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
769 return pctrl->community->functions[function].name;
772 static int chv_get_function_groups(struct pinctrl_dev *pctldev,
773 unsigned int function,
774 const char * const **groups,
775 unsigned int * const ngroups)
777 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
779 *groups = pctrl->community->functions[function].groups;
780 *ngroups = pctrl->community->functions[function].ngroups;
784 static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev,
785 unsigned int function, unsigned int group)
787 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
788 const struct chv_pingroup *grp;
792 grp = &pctrl->community->groups[group];
794 raw_spin_lock_irqsave(&chv_lock, flags);
796 /* Check first that the pad is not locked */
797 for (i = 0; i < grp->npins; i++) {
798 if (chv_pad_locked(pctrl, grp->pins[i])) {
799 dev_warn(pctrl->dev, "unable to set mode for locked pin %u\n",
801 raw_spin_unlock_irqrestore(&chv_lock, flags);
806 for (i = 0; i < grp->npins; i++) {
807 const struct chv_alternate_function *altfunc = &grp->altfunc;
808 int pin = grp->pins[i];
812 /* Check if there is pin-specific config */
813 if (grp->overrides) {
816 for (j = 0; j < grp->noverrides; j++) {
817 if (grp->overrides[j].pin == pin) {
818 altfunc = &grp->overrides[j];
824 reg = chv_padreg(pctrl, pin, CHV_PADCTRL0);
826 /* Disable GPIO mode */
827 value &= ~CHV_PADCTRL0_GPIOEN;
828 /* Set to desired mode */
829 value &= ~CHV_PADCTRL0_PMODE_MASK;
830 value |= altfunc->mode << CHV_PADCTRL0_PMODE_SHIFT;
831 chv_writel(value, reg);
833 /* Update for invert_oe */
834 reg = chv_padreg(pctrl, pin, CHV_PADCTRL1);
835 value = readl(reg) & ~CHV_PADCTRL1_INVRXTX_MASK;
836 if (altfunc->invert_oe)
837 value |= CHV_PADCTRL1_INVRXTX_TXENABLE;
838 chv_writel(value, reg);
840 dev_dbg(pctrl->dev, "configured pin %u mode %u OE %sinverted\n",
841 pin, altfunc->mode, altfunc->invert_oe ? "" : "not ");
844 raw_spin_unlock_irqrestore(&chv_lock, flags);
849 static void chv_gpio_clear_triggering(struct chv_pinctrl *pctrl,
855 reg = chv_padreg(pctrl, offset, CHV_PADCTRL1);
857 value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
858 value &= ~CHV_PADCTRL1_INVRXTX_MASK;
859 chv_writel(value, reg);
862 static int chv_gpio_request_enable(struct pinctrl_dev *pctldev,
863 struct pinctrl_gpio_range *range,
866 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
871 raw_spin_lock_irqsave(&chv_lock, flags);
873 if (chv_pad_locked(pctrl, offset)) {
874 value = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
875 if (!(value & CHV_PADCTRL0_GPIOEN)) {
876 /* Locked so cannot enable */
877 raw_spin_unlock_irqrestore(&chv_lock, flags);
883 /* Reset the interrupt mapping */
884 for (i = 0; i < ARRAY_SIZE(pctrl->intr_lines); i++) {
885 if (pctrl->intr_lines[i] == offset) {
886 pctrl->intr_lines[i] = 0;
891 /* Disable interrupt generation */
892 chv_gpio_clear_triggering(pctrl, offset);
894 reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
898 * If the pin is in HiZ mode (both TX and RX buffers are
899 * disabled) we turn it to be input now.
901 if ((value & CHV_PADCTRL0_GPIOCFG_MASK) ==
902 (CHV_PADCTRL0_GPIOCFG_HIZ << CHV_PADCTRL0_GPIOCFG_SHIFT)) {
903 value &= ~CHV_PADCTRL0_GPIOCFG_MASK;
904 value |= CHV_PADCTRL0_GPIOCFG_GPI <<
905 CHV_PADCTRL0_GPIOCFG_SHIFT;
908 /* Switch to a GPIO mode */
909 value |= CHV_PADCTRL0_GPIOEN;
910 chv_writel(value, reg);
913 raw_spin_unlock_irqrestore(&chv_lock, flags);
918 static void chv_gpio_disable_free(struct pinctrl_dev *pctldev,
919 struct pinctrl_gpio_range *range,
922 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
927 raw_spin_lock_irqsave(&chv_lock, flags);
929 reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
930 value = readl(reg) & ~CHV_PADCTRL0_GPIOEN;
931 chv_writel(value, reg);
933 raw_spin_unlock_irqrestore(&chv_lock, flags);
936 static int chv_gpio_set_direction(struct pinctrl_dev *pctldev,
937 struct pinctrl_gpio_range *range,
938 unsigned int offset, bool input)
940 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
941 void __iomem *reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
945 raw_spin_lock_irqsave(&chv_lock, flags);
947 ctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIOCFG_MASK;
949 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT;
951 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPO << CHV_PADCTRL0_GPIOCFG_SHIFT;
952 chv_writel(ctrl0, reg);
954 raw_spin_unlock_irqrestore(&chv_lock, flags);
959 static const struct pinmux_ops chv_pinmux_ops = {
960 .get_functions_count = chv_get_functions_count,
961 .get_function_name = chv_get_function_name,
962 .get_function_groups = chv_get_function_groups,
963 .set_mux = chv_pinmux_set_mux,
964 .gpio_request_enable = chv_gpio_request_enable,
965 .gpio_disable_free = chv_gpio_disable_free,
966 .gpio_set_direction = chv_gpio_set_direction,
969 static int chv_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
970 unsigned long *config)
972 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
973 enum pin_config_param param = pinconf_to_config_param(*config);
979 raw_spin_lock_irqsave(&chv_lock, flags);
980 ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
981 ctrl1 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1));
982 raw_spin_unlock_irqrestore(&chv_lock, flags);
984 term = (ctrl0 & CHV_PADCTRL0_TERM_MASK) >> CHV_PADCTRL0_TERM_SHIFT;
987 case PIN_CONFIG_BIAS_DISABLE:
992 case PIN_CONFIG_BIAS_PULL_UP:
993 if (!(ctrl0 & CHV_PADCTRL0_TERM_UP))
997 case CHV_PADCTRL0_TERM_20K:
1000 case CHV_PADCTRL0_TERM_5K:
1003 case CHV_PADCTRL0_TERM_1K:
1010 case PIN_CONFIG_BIAS_PULL_DOWN:
1011 if (!term || (ctrl0 & CHV_PADCTRL0_TERM_UP))
1015 case CHV_PADCTRL0_TERM_20K:
1018 case CHV_PADCTRL0_TERM_5K:
1025 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1026 if (!(ctrl1 & CHV_PADCTRL1_ODEN))
1030 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: {
1033 cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
1034 cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
1035 if (cfg != CHV_PADCTRL0_GPIOCFG_HIZ)
1045 *config = pinconf_to_config_packed(param, arg);
1049 static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned int pin,
1050 enum pin_config_param param, u32 arg)
1052 void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL0);
1053 unsigned long flags;
1056 raw_spin_lock_irqsave(&chv_lock, flags);
1060 case PIN_CONFIG_BIAS_DISABLE:
1061 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
1064 case PIN_CONFIG_BIAS_PULL_UP:
1065 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
1069 /* For 1k there is only pull up */
1070 pull = CHV_PADCTRL0_TERM_1K << CHV_PADCTRL0_TERM_SHIFT;
1073 pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT;
1076 pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
1079 raw_spin_unlock_irqrestore(&chv_lock, flags);
1083 ctrl0 |= CHV_PADCTRL0_TERM_UP | pull;
1086 case PIN_CONFIG_BIAS_PULL_DOWN:
1087 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
1091 pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT;
1094 pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
1097 raw_spin_unlock_irqrestore(&chv_lock, flags);
1105 raw_spin_unlock_irqrestore(&chv_lock, flags);
1109 chv_writel(ctrl0, reg);
1110 raw_spin_unlock_irqrestore(&chv_lock, flags);
1115 static int chv_config_set_oden(struct chv_pinctrl *pctrl, unsigned int pin,
1118 void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL1);
1119 unsigned long flags;
1122 raw_spin_lock_irqsave(&chv_lock, flags);
1126 ctrl1 |= CHV_PADCTRL1_ODEN;
1128 ctrl1 &= ~CHV_PADCTRL1_ODEN;
1130 chv_writel(ctrl1, reg);
1131 raw_spin_unlock_irqrestore(&chv_lock, flags);
1136 static int chv_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
1137 unsigned long *configs, unsigned int nconfigs)
1139 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
1140 enum pin_config_param param;
1144 if (chv_pad_locked(pctrl, pin))
1147 for (i = 0; i < nconfigs; i++) {
1148 param = pinconf_to_config_param(configs[i]);
1149 arg = pinconf_to_config_argument(configs[i]);
1152 case PIN_CONFIG_BIAS_DISABLE:
1153 case PIN_CONFIG_BIAS_PULL_UP:
1154 case PIN_CONFIG_BIAS_PULL_DOWN:
1155 ret = chv_config_set_pull(pctrl, pin, param, arg);
1160 case PIN_CONFIG_DRIVE_PUSH_PULL:
1161 ret = chv_config_set_oden(pctrl, pin, false);
1166 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1167 ret = chv_config_set_oden(pctrl, pin, true);
1176 dev_dbg(pctrl->dev, "pin %d set config %d arg %u\n", pin,
1183 static int chv_config_group_get(struct pinctrl_dev *pctldev,
1185 unsigned long *config)
1187 const unsigned int *pins;
1191 ret = chv_get_group_pins(pctldev, group, &pins, &npins);
1195 ret = chv_config_get(pctldev, pins[0], config);
1202 static int chv_config_group_set(struct pinctrl_dev *pctldev,
1203 unsigned int group, unsigned long *configs,
1204 unsigned int num_configs)
1206 const unsigned int *pins;
1210 ret = chv_get_group_pins(pctldev, group, &pins, &npins);
1214 for (i = 0; i < npins; i++) {
1215 ret = chv_config_set(pctldev, pins[i], configs, num_configs);
1223 static const struct pinconf_ops chv_pinconf_ops = {
1225 .pin_config_set = chv_config_set,
1226 .pin_config_get = chv_config_get,
1227 .pin_config_group_get = chv_config_group_get,
1228 .pin_config_group_set = chv_config_group_set,
1231 static struct pinctrl_desc chv_pinctrl_desc = {
1232 .pctlops = &chv_pinctrl_ops,
1233 .pmxops = &chv_pinmux_ops,
1234 .confops = &chv_pinconf_ops,
1235 .owner = THIS_MODULE,
1238 static int chv_gpio_get(struct gpio_chip *chip, unsigned int offset)
1240 struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
1241 unsigned long flags;
1244 raw_spin_lock_irqsave(&chv_lock, flags);
1245 ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
1246 raw_spin_unlock_irqrestore(&chv_lock, flags);
1248 cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
1249 cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
1251 if (cfg == CHV_PADCTRL0_GPIOCFG_GPO)
1252 return !!(ctrl0 & CHV_PADCTRL0_GPIOTXSTATE);
1253 return !!(ctrl0 & CHV_PADCTRL0_GPIORXSTATE);
1256 static void chv_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
1258 struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
1259 unsigned long flags;
1263 raw_spin_lock_irqsave(&chv_lock, flags);
1265 reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
1269 ctrl0 |= CHV_PADCTRL0_GPIOTXSTATE;
1271 ctrl0 &= ~CHV_PADCTRL0_GPIOTXSTATE;
1273 chv_writel(ctrl0, reg);
1275 raw_spin_unlock_irqrestore(&chv_lock, flags);
1278 static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
1280 struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
1281 u32 ctrl0, direction;
1282 unsigned long flags;
1284 raw_spin_lock_irqsave(&chv_lock, flags);
1285 ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
1286 raw_spin_unlock_irqrestore(&chv_lock, flags);
1288 direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
1289 direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
1291 return direction != CHV_PADCTRL0_GPIOCFG_GPO;
1294 static int chv_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
1296 return pinctrl_gpio_direction_input(chip->base + offset);
1299 static int chv_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
1302 chv_gpio_set(chip, offset, value);
1303 return pinctrl_gpio_direction_output(chip->base + offset);
1306 static const struct gpio_chip chv_gpio_chip = {
1307 .owner = THIS_MODULE,
1308 .request = gpiochip_generic_request,
1309 .free = gpiochip_generic_free,
1310 .get_direction = chv_gpio_get_direction,
1311 .direction_input = chv_gpio_direction_input,
1312 .direction_output = chv_gpio_direction_output,
1313 .get = chv_gpio_get,
1314 .set = chv_gpio_set,
1317 static void chv_gpio_irq_ack(struct irq_data *d)
1319 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1320 struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1321 int pin = irqd_to_hwirq(d);
1324 raw_spin_lock(&chv_lock);
1326 intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1327 intr_line &= CHV_PADCTRL0_INTSEL_MASK;
1328 intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
1329 chv_writel(BIT(intr_line), pctrl->regs + CHV_INTSTAT);
1331 raw_spin_unlock(&chv_lock);
1334 static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
1336 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1337 struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1338 int pin = irqd_to_hwirq(d);
1339 u32 value, intr_line;
1340 unsigned long flags;
1342 raw_spin_lock_irqsave(&chv_lock, flags);
1344 intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1345 intr_line &= CHV_PADCTRL0_INTSEL_MASK;
1346 intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
1348 value = readl(pctrl->regs + CHV_INTMASK);
1350 value &= ~BIT(intr_line);
1352 value |= BIT(intr_line);
1353 chv_writel(value, pctrl->regs + CHV_INTMASK);
1355 raw_spin_unlock_irqrestore(&chv_lock, flags);
1358 static void chv_gpio_irq_mask(struct irq_data *d)
1360 chv_gpio_irq_mask_unmask(d, true);
1363 static void chv_gpio_irq_unmask(struct irq_data *d)
1365 chv_gpio_irq_mask_unmask(d, false);
1368 static unsigned chv_gpio_irq_startup(struct irq_data *d)
1371 * Check if the interrupt has been requested with 0 as triggering
1372 * type. In that case it is assumed that the current values
1373 * programmed to the hardware are used (e.g BIOS configured
1376 * In that case ->irq_set_type() will never be called so we need to
1377 * read back the values from hardware now, set correct flow handler
1378 * and update mappings before the interrupt is being used.
1380 if (irqd_get_trigger_type(d) == IRQ_TYPE_NONE) {
1381 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1382 struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1383 unsigned int pin = irqd_to_hwirq(d);
1384 irq_flow_handler_t handler;
1385 unsigned long flags;
1388 raw_spin_lock_irqsave(&chv_lock, flags);
1389 intsel = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1390 intsel &= CHV_PADCTRL0_INTSEL_MASK;
1391 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
1393 value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1));
1394 if (value & CHV_PADCTRL1_INTWAKECFG_LEVEL)
1395 handler = handle_level_irq;
1397 handler = handle_edge_irq;
1399 if (!pctrl->intr_lines[intsel]) {
1400 irq_set_handler_locked(d, handler);
1401 pctrl->intr_lines[intsel] = pin;
1403 raw_spin_unlock_irqrestore(&chv_lock, flags);
1406 chv_gpio_irq_unmask(d);
1410 static int chv_gpio_irq_type(struct irq_data *d, unsigned int type)
1412 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1413 struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1414 unsigned int pin = irqd_to_hwirq(d);
1415 unsigned long flags;
1418 raw_spin_lock_irqsave(&chv_lock, flags);
1421 * Pins which can be used as shared interrupt are configured in
1422 * BIOS. Driver trusts BIOS configurations and assigns different
1423 * handler according to the irq type.
1425 * Driver needs to save the mapping between each pin and
1426 * its interrupt line.
1427 * 1. If the pin cfg is locked in BIOS:
1428 * Trust BIOS has programmed IntWakeCfg bits correctly,
1429 * driver just needs to save the mapping.
1430 * 2. If the pin cfg is not locked in BIOS:
1431 * Driver programs the IntWakeCfg bits and save the mapping.
1433 if (!chv_pad_locked(pctrl, pin)) {
1434 void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL1);
1437 value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
1438 value &= ~CHV_PADCTRL1_INVRXTX_MASK;
1440 if (type & IRQ_TYPE_EDGE_BOTH) {
1441 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
1442 value |= CHV_PADCTRL1_INTWAKECFG_BOTH;
1443 else if (type & IRQ_TYPE_EDGE_RISING)
1444 value |= CHV_PADCTRL1_INTWAKECFG_RISING;
1445 else if (type & IRQ_TYPE_EDGE_FALLING)
1446 value |= CHV_PADCTRL1_INTWAKECFG_FALLING;
1447 } else if (type & IRQ_TYPE_LEVEL_MASK) {
1448 value |= CHV_PADCTRL1_INTWAKECFG_LEVEL;
1449 if (type & IRQ_TYPE_LEVEL_LOW)
1450 value |= CHV_PADCTRL1_INVRXTX_RXDATA;
1453 chv_writel(value, reg);
1456 value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1457 value &= CHV_PADCTRL0_INTSEL_MASK;
1458 value >>= CHV_PADCTRL0_INTSEL_SHIFT;
1460 pctrl->intr_lines[value] = pin;
1462 if (type & IRQ_TYPE_EDGE_BOTH)
1463 irq_set_handler_locked(d, handle_edge_irq);
1464 else if (type & IRQ_TYPE_LEVEL_MASK)
1465 irq_set_handler_locked(d, handle_level_irq);
1467 raw_spin_unlock_irqrestore(&chv_lock, flags);
1472 static struct irq_chip chv_gpio_irqchip = {
1474 .irq_startup = chv_gpio_irq_startup,
1475 .irq_ack = chv_gpio_irq_ack,
1476 .irq_mask = chv_gpio_irq_mask,
1477 .irq_unmask = chv_gpio_irq_unmask,
1478 .irq_set_type = chv_gpio_irq_type,
1479 .flags = IRQCHIP_SKIP_SET_WAKE,
1482 static void chv_gpio_irq_handler(struct irq_desc *desc)
1484 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
1485 struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1486 struct irq_chip *chip = irq_desc_get_chip(desc);
1487 unsigned long pending;
1490 chained_irq_enter(chip, desc);
1492 pending = readl(pctrl->regs + CHV_INTSTAT);
1493 for_each_set_bit(intr_line, &pending, pctrl->community->nirqs) {
1494 unsigned irq, offset;
1496 offset = pctrl->intr_lines[intr_line];
1497 irq = irq_find_mapping(gc->irq.domain, offset);
1498 generic_handle_irq(irq);
1501 chained_irq_exit(chip, desc);
1505 * Certain machines seem to hardcode Linux IRQ numbers in their ACPI
1506 * tables. Since we leave GPIOs that are not capable of generating
1507 * interrupts out of the irqdomain the numbering will be different and
1508 * cause devices using the hardcoded IRQ numbers fail. In order not to
1509 * break such machines we will only mask pins from irqdomain if the machine
1510 * is not listed below.
1512 static const struct dmi_system_id chv_no_valid_mask[] = {
1513 /* See https://bugzilla.kernel.org/show_bug.cgi?id=194945 */
1515 .ident = "Intel_Strago based Chromebooks (All models)",
1517 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
1518 DMI_MATCH(DMI_PRODUCT_FAMILY, "Intel_Strago"),
1519 DMI_MATCH(DMI_BOARD_VERSION, "1.0"),
1523 .ident = "HP Chromebook 11 G5 (Setzer)",
1525 DMI_MATCH(DMI_SYS_VENDOR, "HP"),
1526 DMI_MATCH(DMI_PRODUCT_NAME, "Setzer"),
1527 DMI_MATCH(DMI_BOARD_VERSION, "1.0"),
1531 .ident = "Acer Chromebook R11 (Cyan)",
1533 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
1534 DMI_MATCH(DMI_PRODUCT_NAME, "Cyan"),
1535 DMI_MATCH(DMI_BOARD_VERSION, "1.0"),
1539 .ident = "Samsung Chromebook 3 (Celes)",
1541 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
1542 DMI_MATCH(DMI_PRODUCT_NAME, "Celes"),
1543 DMI_MATCH(DMI_BOARD_VERSION, "1.0"),
1549 static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)
1551 const struct chv_gpio_pinrange *range;
1552 struct gpio_chip *chip = &pctrl->chip;
1553 bool need_valid_mask = !dmi_check_system(chv_no_valid_mask);
1554 const struct chv_community *community = pctrl->community;
1555 int ret, i, irq_base;
1557 *chip = chv_gpio_chip;
1559 chip->ngpio = community->pins[community->npins - 1].number + 1;
1560 chip->label = dev_name(pctrl->dev);
1561 chip->parent = pctrl->dev;
1563 chip->irq.need_valid_mask = need_valid_mask;
1565 ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl);
1567 dev_err(pctrl->dev, "Failed to register gpiochip\n");
1571 for (i = 0; i < community->ngpio_ranges; i++) {
1572 range = &community->gpio_ranges[i];
1573 ret = gpiochip_add_pin_range(chip, dev_name(pctrl->dev),
1574 range->base, range->base,
1577 dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1582 /* Do not add GPIOs that can only generate GPEs to the IRQ domain */
1583 for (i = 0; i < community->npins; i++) {
1584 const struct pinctrl_pin_desc *desc;
1587 desc = &community->pins[i];
1589 intsel = readl(chv_padreg(pctrl, desc->number, CHV_PADCTRL0));
1590 intsel &= CHV_PADCTRL0_INTSEL_MASK;
1591 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
1593 if (need_valid_mask && intsel >= community->nirqs)
1594 clear_bit(i, chip->irq.valid_mask);
1598 * The same set of machines in chv_no_valid_mask[] have incorrectly
1599 * configured GPIOs that generate spurious interrupts so we use
1600 * this same list to apply another quirk for them.
1602 * See also https://bugzilla.kernel.org/show_bug.cgi?id=197953.
1604 if (!need_valid_mask) {
1606 * Mask all interrupts the community is able to generate
1607 * but leave the ones that can only generate GPEs unmasked.
1609 chv_writel(GENMASK(31, pctrl->community->nirqs),
1610 pctrl->regs + CHV_INTMASK);
1613 /* Clear all interrupts */
1614 chv_writel(0xffff, pctrl->regs + CHV_INTSTAT);
1616 if (!need_valid_mask) {
1617 irq_base = devm_irq_alloc_descs(pctrl->dev, -1, 0,
1618 community->npins, NUMA_NO_NODE);
1620 dev_err(pctrl->dev, "Failed to allocate IRQ numbers\n");
1625 ret = gpiochip_irqchip_add(chip, &chv_gpio_irqchip, 0,
1626 handle_bad_irq, IRQ_TYPE_NONE);
1628 dev_err(pctrl->dev, "failed to add IRQ chip\n");
1632 if (!need_valid_mask) {
1633 for (i = 0; i < community->ngpio_ranges; i++) {
1634 range = &community->gpio_ranges[i];
1636 irq_domain_associate_many(chip->irq.domain, irq_base,
1637 range->base, range->npins);
1638 irq_base += range->npins;
1642 gpiochip_set_chained_irqchip(chip, &chv_gpio_irqchip, irq,
1643 chv_gpio_irq_handler);
1647 static acpi_status chv_pinctrl_mmio_access_handler(u32 function,
1648 acpi_physical_address address, u32 bits, u64 *value,
1649 void *handler_context, void *region_context)
1651 struct chv_pinctrl *pctrl = region_context;
1652 unsigned long flags;
1653 acpi_status ret = AE_OK;
1655 raw_spin_lock_irqsave(&chv_lock, flags);
1657 if (function == ACPI_WRITE)
1658 chv_writel((u32)(*value), pctrl->regs + (u32)address);
1659 else if (function == ACPI_READ)
1660 *value = readl(pctrl->regs + (u32)address);
1662 ret = AE_BAD_PARAMETER;
1664 raw_spin_unlock_irqrestore(&chv_lock, flags);
1669 static int chv_pinctrl_probe(struct platform_device *pdev)
1671 struct chv_pinctrl *pctrl;
1672 struct acpi_device *adev;
1673 struct resource *res;
1677 adev = ACPI_COMPANION(&pdev->dev);
1681 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1685 for (i = 0; i < ARRAY_SIZE(chv_communities); i++)
1686 if (!strcmp(adev->pnp.unique_id, chv_communities[i]->uid)) {
1687 pctrl->community = chv_communities[i];
1690 if (i == ARRAY_SIZE(chv_communities))
1693 pctrl->dev = &pdev->dev;
1695 #ifdef CONFIG_PM_SLEEP
1696 pctrl->saved_pin_context = devm_kcalloc(pctrl->dev,
1697 pctrl->community->npins, sizeof(*pctrl->saved_pin_context),
1699 if (!pctrl->saved_pin_context)
1703 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1704 pctrl->regs = devm_ioremap_resource(&pdev->dev, res);
1705 if (IS_ERR(pctrl->regs))
1706 return PTR_ERR(pctrl->regs);
1708 irq = platform_get_irq(pdev, 0);
1710 dev_err(&pdev->dev, "failed to get interrupt number\n");
1714 pctrl->pctldesc = chv_pinctrl_desc;
1715 pctrl->pctldesc.name = dev_name(&pdev->dev);
1716 pctrl->pctldesc.pins = pctrl->community->pins;
1717 pctrl->pctldesc.npins = pctrl->community->npins;
1719 pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc,
1721 if (IS_ERR(pctrl->pctldev)) {
1722 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1723 return PTR_ERR(pctrl->pctldev);
1726 ret = chv_gpio_probe(pctrl, irq);
1730 status = acpi_install_address_space_handler(adev->handle,
1731 pctrl->community->acpi_space_id,
1732 chv_pinctrl_mmio_access_handler,
1734 if (ACPI_FAILURE(status))
1735 dev_err(&pdev->dev, "failed to install ACPI addr space handler\n");
1737 platform_set_drvdata(pdev, pctrl);
1742 static int chv_pinctrl_remove(struct platform_device *pdev)
1744 struct chv_pinctrl *pctrl = platform_get_drvdata(pdev);
1746 acpi_remove_address_space_handler(ACPI_COMPANION(&pdev->dev),
1747 pctrl->community->acpi_space_id,
1748 chv_pinctrl_mmio_access_handler);
1753 #ifdef CONFIG_PM_SLEEP
1754 static int chv_pinctrl_suspend_noirq(struct device *dev)
1756 struct chv_pinctrl *pctrl = dev_get_drvdata(dev);
1757 unsigned long flags;
1760 raw_spin_lock_irqsave(&chv_lock, flags);
1762 pctrl->saved_intmask = readl(pctrl->regs + CHV_INTMASK);
1764 for (i = 0; i < pctrl->community->npins; i++) {
1765 const struct pinctrl_pin_desc *desc;
1766 struct chv_pin_context *ctx;
1769 desc = &pctrl->community->pins[i];
1770 if (chv_pad_locked(pctrl, desc->number))
1773 ctx = &pctrl->saved_pin_context[i];
1775 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0);
1776 ctx->padctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE;
1778 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1);
1779 ctx->padctrl1 = readl(reg);
1782 raw_spin_unlock_irqrestore(&chv_lock, flags);
1787 static int chv_pinctrl_resume_noirq(struct device *dev)
1789 struct chv_pinctrl *pctrl = dev_get_drvdata(dev);
1790 unsigned long flags;
1793 raw_spin_lock_irqsave(&chv_lock, flags);
1796 * Mask all interrupts before restoring per-pin configuration
1797 * registers because we don't know in which state BIOS left them
1798 * upon exiting suspend.
1800 chv_writel(0, pctrl->regs + CHV_INTMASK);
1802 for (i = 0; i < pctrl->community->npins; i++) {
1803 const struct pinctrl_pin_desc *desc;
1804 const struct chv_pin_context *ctx;
1808 desc = &pctrl->community->pins[i];
1809 if (chv_pad_locked(pctrl, desc->number))
1812 ctx = &pctrl->saved_pin_context[i];
1814 /* Only restore if our saved state differs from the current */
1815 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0);
1816 val = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE;
1817 if (ctx->padctrl0 != val) {
1818 chv_writel(ctx->padctrl0, reg);
1819 dev_dbg(pctrl->dev, "restored pin %2u ctrl0 0x%08x\n",
1820 desc->number, readl(reg));
1823 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1);
1825 if (ctx->padctrl1 != val) {
1826 chv_writel(ctx->padctrl1, reg);
1827 dev_dbg(pctrl->dev, "restored pin %2u ctrl1 0x%08x\n",
1828 desc->number, readl(reg));
1833 * Now that all pins are restored to known state, we can restore
1834 * the interrupt mask register as well.
1836 chv_writel(0xffff, pctrl->regs + CHV_INTSTAT);
1837 chv_writel(pctrl->saved_intmask, pctrl->regs + CHV_INTMASK);
1839 raw_spin_unlock_irqrestore(&chv_lock, flags);
1845 static const struct dev_pm_ops chv_pinctrl_pm_ops = {
1846 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(chv_pinctrl_suspend_noirq,
1847 chv_pinctrl_resume_noirq)
1850 static const struct acpi_device_id chv_pinctrl_acpi_match[] = {
1854 MODULE_DEVICE_TABLE(acpi, chv_pinctrl_acpi_match);
1856 static struct platform_driver chv_pinctrl_driver = {
1857 .probe = chv_pinctrl_probe,
1858 .remove = chv_pinctrl_remove,
1860 .name = "cherryview-pinctrl",
1861 .pm = &chv_pinctrl_pm_ops,
1862 .acpi_match_table = chv_pinctrl_acpi_match,
1866 static int __init chv_pinctrl_init(void)
1868 return platform_driver_register(&chv_pinctrl_driver);
1870 subsys_initcall(chv_pinctrl_init);
1872 static void __exit chv_pinctrl_exit(void)
1874 platform_driver_unregister(&chv_pinctrl_driver);
1876 module_exit(chv_pinctrl_exit);
1878 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1879 MODULE_DESCRIPTION("Intel Cherryview/Braswell pinctrl driver");
1880 MODULE_LICENSE("GPL v2");