1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2014,2015 AMD Corporation.
6 * Authors: Ken Xue <Ken.Xue@amd.com>
7 * Wu, Jeff <Jeff.Wu@amd.com>
11 #include <linux/err.h>
12 #include <linux/bug.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/spinlock.h>
16 #include <linux/compiler.h>
17 #include <linux/types.h>
18 #include <linux/errno.h>
19 #include <linux/log2.h>
21 #include <linux/gpio/driver.h>
22 #include <linux/slab.h>
23 #include <linux/platform_device.h>
24 #include <linux/mutex.h>
25 #include <linux/acpi.h>
26 #include <linux/seq_file.h>
27 #include <linux/interrupt.h>
28 #include <linux/list.h>
29 #include <linux/bitops.h>
30 #include <linux/pinctrl/pinconf.h>
31 #include <linux/pinctrl/pinconf-generic.h>
32 #include <linux/pinctrl/pinmux.h>
33 #include <linux/suspend.h>
36 #include "pinctrl-utils.h"
37 #include "pinctrl-amd.h"
39 static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
43 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
45 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
46 pin_reg = readl(gpio_dev->base + offset * 4);
47 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
49 if (pin_reg & BIT(OUTPUT_ENABLE_OFF))
50 return GPIO_LINE_DIRECTION_OUT;
52 return GPIO_LINE_DIRECTION_IN;
55 static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
59 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
61 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
62 pin_reg = readl(gpio_dev->base + offset * 4);
63 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF);
64 writel(pin_reg, gpio_dev->base + offset * 4);
65 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
70 static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
75 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
77 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
78 pin_reg = readl(gpio_dev->base + offset * 4);
79 pin_reg |= BIT(OUTPUT_ENABLE_OFF);
81 pin_reg |= BIT(OUTPUT_VALUE_OFF);
83 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
84 writel(pin_reg, gpio_dev->base + offset * 4);
85 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
90 static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset)
94 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
96 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
97 pin_reg = readl(gpio_dev->base + offset * 4);
98 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
100 return !!(pin_reg & BIT(PIN_STS_OFF));
103 static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value)
107 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
109 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
110 pin_reg = readl(gpio_dev->base + offset * 4);
112 pin_reg |= BIT(OUTPUT_VALUE_OFF);
114 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
115 writel(pin_reg, gpio_dev->base + offset * 4);
116 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
119 static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
126 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
128 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
130 /* Use special handling for Pin0 debounce */
131 pin_reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
132 if (pin_reg & INTERNAL_GPIO0_DEBOUNCE)
135 pin_reg = readl(gpio_dev->base + offset * 4);
138 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
139 pin_reg &= ~DB_TMR_OUT_MASK;
141 Debounce Debounce Timer Max
142 TmrLarge TmrOutUnit Unit Debounce
144 0 0 61 usec (2 RtcClk) 976 usec
145 0 1 244 usec (8 RtcClk) 3.9 msec
146 1 0 15.6 msec (512 RtcClk) 250 msec
147 1 1 62.5 msec (2048 RtcClk) 1 sec
152 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
153 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
154 } else if (debounce < 976) {
155 time = debounce / 61;
156 pin_reg |= time & DB_TMR_OUT_MASK;
157 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
158 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
159 } else if (debounce < 3900) {
160 time = debounce / 244;
161 pin_reg |= time & DB_TMR_OUT_MASK;
162 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
163 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
164 } else if (debounce < 250000) {
165 time = debounce / 15625;
166 pin_reg |= time & DB_TMR_OUT_MASK;
167 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
168 pin_reg |= BIT(DB_TMR_LARGE_OFF);
169 } else if (debounce < 1000000) {
170 time = debounce / 62500;
171 pin_reg |= time & DB_TMR_OUT_MASK;
172 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
173 pin_reg |= BIT(DB_TMR_LARGE_OFF);
175 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
179 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
180 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
181 pin_reg &= ~DB_TMR_OUT_MASK;
182 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
184 writel(pin_reg, gpio_dev->base + offset * 4);
185 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
190 static int amd_gpio_set_config(struct gpio_chip *gc, unsigned offset,
191 unsigned long config)
195 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
198 debounce = pinconf_to_config_argument(config);
199 return amd_gpio_set_debounce(gc, offset, debounce);
202 #ifdef CONFIG_DEBUG_FS
203 static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
208 unsigned int bank, i, pin_num;
209 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
216 char *interrupt_mask;
225 char debounce_value[40];
226 char *debounce_enable;
229 seq_printf(s, "WAKE_INT_MASTER_REG: 0x%08x\n", readl(gpio_dev->base + WAKE_INT_MASTER_REG));
230 for (bank = 0; bank < gpio_dev->hwbank_num; bank++) {
231 unsigned int time = 0;
232 unsigned int unit = 0;
237 pin_num = AMD_GPIO_PINS_BANK0;
241 pin_num = AMD_GPIO_PINS_BANK1 + i;
245 pin_num = AMD_GPIO_PINS_BANK2 + i;
249 pin_num = AMD_GPIO_PINS_BANK3 + i;
252 /* Illegal bank number, ignore */
255 seq_printf(s, "GPIO bank%d\n", bank);
256 seq_puts(s, "gpio\t int|active|trigger|S0i3| S3|S4/S5| Z|wake|pull| orient| debounce|reg\n");
257 for (; i < pin_num; i++) {
258 seq_printf(s, "#%d\t", i);
259 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
260 pin_reg = readl(gpio_dev->base + i * 4);
261 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
263 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) {
264 u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) &
267 if (level == ACTIVE_LEVEL_HIGH)
269 else if (level == ACTIVE_LEVEL_LOW)
271 else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) &&
272 level == ACTIVE_LEVEL_BOTH)
277 if (pin_reg & BIT(LEVEL_TRIG_OFF))
278 level_trig = "level";
280 level_trig = " edge";
282 if (pin_reg & BIT(INTERRUPT_MASK_OFF))
283 interrupt_mask = "😛";
285 interrupt_mask = "😷";
287 if (pin_reg & BIT(INTERRUPT_STS_OFF))
292 seq_printf(s, "%s %s| %s| %s|",
298 seq_puts(s, " ∅| | |");
300 if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3))
304 seq_printf(s, " %s| ", wake_cntrl0);
306 if (pin_reg & BIT(WAKE_CNTRL_OFF_S3))
310 seq_printf(s, "%s|", wake_cntrl1);
312 if (pin_reg & BIT(WAKE_CNTRL_OFF_S4))
316 seq_printf(s, " %s|", wake_cntrl2);
318 if (pin_reg & BIT(WAKECNTRL_Z_OFF))
322 seq_printf(s, "%s|", wake_cntrlz);
324 if (pin_reg & BIT(WAKE_STS_OFF))
328 seq_printf(s, " %s|", wake_sts);
330 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) {
331 if (pin_reg & BIT(PULL_UP_SEL_OFF))
335 seq_printf(s, "%s ↑|",
337 } else if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) {
343 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) {
345 if (pin_reg & BIT(OUTPUT_VALUE_OFF))
351 if (pin_reg & BIT(PIN_STS_OFF))
356 seq_printf(s, "%s %s|", pin_sts, orientation);
358 db_cntrl = (DB_CNTRl_MASK << DB_CNTRL_OFF) & pin_reg;
360 tmr_out_unit = pin_reg & BIT(DB_TMR_OUT_UNIT_OFF);
361 tmr_large = pin_reg & BIT(DB_TMR_LARGE_OFF);
362 time = pin_reg & DB_TMR_OUT_MASK;
374 if ((DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF) == db_cntrl)
375 debounce_enable = "b";
376 else if ((DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF) == db_cntrl)
377 debounce_enable = "↓";
379 debounce_enable = "↑";
380 snprintf(debounce_value, sizeof(debounce_value), "%06u", time * unit);
381 seq_printf(s, "%s (🕑 %sus)|", debounce_enable, debounce_value);
385 seq_printf(s, "0x%x\n", pin_reg);
390 #define amd_gpio_dbg_show NULL
393 static void amd_gpio_irq_enable(struct irq_data *d)
397 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
398 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
400 gpiochip_enable_irq(gc, d->hwirq);
402 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
403 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
404 pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
405 pin_reg |= BIT(INTERRUPT_MASK_OFF);
406 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
407 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
410 static void amd_gpio_irq_disable(struct irq_data *d)
414 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
415 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
417 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
418 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
419 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF);
420 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
421 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
422 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
424 gpiochip_disable_irq(gc, d->hwirq);
427 static void amd_gpio_irq_mask(struct irq_data *d)
431 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
432 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
434 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
435 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
436 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
437 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
438 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
441 static void amd_gpio_irq_unmask(struct irq_data *d)
445 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
446 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
448 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
449 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
450 pin_reg |= BIT(INTERRUPT_MASK_OFF);
451 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
452 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
455 static int amd_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
459 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
460 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
461 u32 wake_mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3);
464 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
465 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
468 pin_reg |= wake_mask;
470 pin_reg &= ~wake_mask;
472 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
473 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
476 err = enable_irq_wake(gpio_dev->irq);
478 err = disable_irq_wake(gpio_dev->irq);
481 dev_err(&gpio_dev->pdev->dev, "failed to %s wake-up interrupt\n",
482 on ? "enable" : "disable");
487 static void amd_gpio_irq_eoi(struct irq_data *d)
491 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
492 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
494 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
495 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
497 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
498 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
501 static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
504 u32 pin_reg, pin_reg_irq_en, mask;
506 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
507 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
509 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
510 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
512 switch (type & IRQ_TYPE_SENSE_MASK) {
513 case IRQ_TYPE_EDGE_RISING:
514 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
515 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
516 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
517 irq_set_handler_locked(d, handle_edge_irq);
520 case IRQ_TYPE_EDGE_FALLING:
521 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
522 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
523 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
524 irq_set_handler_locked(d, handle_edge_irq);
527 case IRQ_TYPE_EDGE_BOTH:
528 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
529 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
530 pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF;
531 irq_set_handler_locked(d, handle_edge_irq);
534 case IRQ_TYPE_LEVEL_HIGH:
535 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
536 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
537 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
538 irq_set_handler_locked(d, handle_level_irq);
541 case IRQ_TYPE_LEVEL_LOW:
542 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
543 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
544 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
545 irq_set_handler_locked(d, handle_level_irq);
552 dev_err(&gpio_dev->pdev->dev, "Invalid type value\n");
556 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF;
558 * If WAKE_INT_MASTER_REG.MaskStsEn is set, a software write to the
559 * debounce registers of any GPIO will block wake/interrupt status
560 * generation for *all* GPIOs for a length of time that depends on
561 * WAKE_INT_MASTER_REG.MaskStsLength[11:0]. During this period the
562 * INTERRUPT_ENABLE bit will read as 0.
564 * We temporarily enable irq for the GPIO whose configuration is
565 * changing, and then wait for it to read back as 1 to know when
566 * debounce has settled and then disable the irq again.
567 * We do this polling with the spinlock held to ensure other GPIO
568 * access routines do not read an incorrect value for the irq enable
569 * bit of other GPIOs. We keep the GPIO masked while polling to avoid
570 * spurious irqs, and disable the irq again after polling.
572 mask = BIT(INTERRUPT_ENABLE_OFF);
573 pin_reg_irq_en = pin_reg;
574 pin_reg_irq_en |= mask;
575 pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF);
576 writel(pin_reg_irq_en, gpio_dev->base + (d->hwirq)*4);
577 while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask)
579 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
580 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
585 static void amd_irq_ack(struct irq_data *d)
588 * based on HW design,there is no need to ack HW
589 * before handle current irq. But this routine is
590 * necessary for handle_edge_irq
594 static const struct irq_chip amd_gpio_irqchip = {
596 .irq_ack = amd_irq_ack,
597 .irq_enable = amd_gpio_irq_enable,
598 .irq_disable = amd_gpio_irq_disable,
599 .irq_mask = amd_gpio_irq_mask,
600 .irq_unmask = amd_gpio_irq_unmask,
601 .irq_set_wake = amd_gpio_irq_set_wake,
602 .irq_eoi = amd_gpio_irq_eoi,
603 .irq_set_type = amd_gpio_irq_set_type,
605 * We need to set IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND so that a wake event
606 * also generates an IRQ. We need the IRQ so the irq_handler can clear
607 * the wake event. Otherwise the wake event will never clear and
608 * prevent the system from suspending.
610 .flags = IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND | IRQCHIP_IMMUTABLE,
611 GPIOCHIP_IRQ_RESOURCE_HELPERS,
614 #define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF))
616 static bool do_amd_gpio_irq_handler(int irq, void *dev_id)
618 struct amd_gpio *gpio_dev = dev_id;
619 struct gpio_chip *gc = &gpio_dev->gc;
620 unsigned int i, irqnr;
627 /* Read the wake status */
628 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
629 status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1);
631 status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0);
632 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
634 /* Bit 0-45 contain the relevant status bits */
635 status &= (1ULL << 46) - 1;
636 regs = gpio_dev->base;
637 for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) {
638 if (!(status & mask))
642 /* Each status bit covers four pins */
643 for (i = 0; i < 4; i++) {
644 regval = readl(regs + i);
646 if (regval & PIN_IRQ_PENDING)
647 pm_pr_dbg("GPIO %d is active: 0x%x",
650 /* caused wake on resume context for shared IRQ */
651 if (irq < 0 && (regval & BIT(WAKE_STS_OFF)))
654 if (!(regval & PIN_IRQ_PENDING) ||
655 !(regval & BIT(INTERRUPT_MASK_OFF)))
657 generic_handle_domain_irq_safe(gc->irq.domain, irqnr + i);
660 * We must read the pin register again, in case the
661 * value was changed while executing
662 * generic_handle_domain_irq() above.
663 * If the line is not an irq, disable it in order to
664 * avoid a system hang caused by an interrupt storm.
666 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
667 regval = readl(regs + i);
668 if (!gpiochip_line_is_irq(gc, irqnr + i)) {
669 regval &= ~BIT(INTERRUPT_MASK_OFF);
670 dev_dbg(&gpio_dev->pdev->dev,
671 "Disabling spurious GPIO IRQ %d\n",
676 writel(regval, regs + i);
677 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
680 /* did not cause wake on resume context for shared IRQ */
684 /* Signal EOI to the GPIO unit */
685 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
686 regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
688 writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG);
689 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
694 static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id)
696 return IRQ_RETVAL(do_amd_gpio_irq_handler(irq, dev_id));
699 static bool __maybe_unused amd_gpio_check_wake(void *dev_id)
701 return do_amd_gpio_irq_handler(-1, dev_id);
704 static int amd_get_groups_count(struct pinctrl_dev *pctldev)
706 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
708 return gpio_dev->ngroups;
711 static const char *amd_get_group_name(struct pinctrl_dev *pctldev,
714 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
716 return gpio_dev->groups[group].name;
719 static int amd_get_group_pins(struct pinctrl_dev *pctldev,
721 const unsigned **pins,
724 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
726 *pins = gpio_dev->groups[group].pins;
727 *num_pins = gpio_dev->groups[group].npins;
731 static const struct pinctrl_ops amd_pinctrl_ops = {
732 .get_groups_count = amd_get_groups_count,
733 .get_group_name = amd_get_group_name,
734 .get_group_pins = amd_get_group_pins,
736 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
737 .dt_free_map = pinctrl_utils_free_map,
741 static int amd_pinconf_get(struct pinctrl_dev *pctldev,
743 unsigned long *config)
748 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
749 enum pin_config_param param = pinconf_to_config_param(*config);
751 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
752 pin_reg = readl(gpio_dev->base + pin*4);
753 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
755 case PIN_CONFIG_INPUT_DEBOUNCE:
756 arg = pin_reg & DB_TMR_OUT_MASK;
759 case PIN_CONFIG_BIAS_PULL_DOWN:
760 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0);
763 case PIN_CONFIG_BIAS_PULL_UP:
764 arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1));
767 case PIN_CONFIG_DRIVE_STRENGTH:
768 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK;
772 dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n",
777 *config = pinconf_to_config_packed(param, arg);
782 static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
783 unsigned long *configs, unsigned num_configs)
790 enum pin_config_param param;
791 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
793 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
794 for (i = 0; i < num_configs; i++) {
795 param = pinconf_to_config_param(configs[i]);
796 arg = pinconf_to_config_argument(configs[i]);
797 pin_reg = readl(gpio_dev->base + pin*4);
800 case PIN_CONFIG_INPUT_DEBOUNCE:
801 pin_reg &= ~DB_TMR_OUT_MASK;
802 pin_reg |= arg & DB_TMR_OUT_MASK;
805 case PIN_CONFIG_BIAS_PULL_DOWN:
806 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF);
807 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF;
810 case PIN_CONFIG_BIAS_PULL_UP:
811 pin_reg &= ~BIT(PULL_UP_SEL_OFF);
812 pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF;
813 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF);
814 pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF;
817 case PIN_CONFIG_DRIVE_STRENGTH:
818 pin_reg &= ~(DRV_STRENGTH_SEL_MASK
819 << DRV_STRENGTH_SEL_OFF);
820 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK)
821 << DRV_STRENGTH_SEL_OFF;
825 dev_err(&gpio_dev->pdev->dev,
826 "Invalid config param %04x\n", param);
830 writel(pin_reg, gpio_dev->base + pin*4);
832 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
837 static int amd_pinconf_group_get(struct pinctrl_dev *pctldev,
839 unsigned long *config)
841 const unsigned *pins;
845 ret = amd_get_group_pins(pctldev, group, &pins, &npins);
849 if (amd_pinconf_get(pctldev, pins[0], config))
855 static int amd_pinconf_group_set(struct pinctrl_dev *pctldev,
856 unsigned group, unsigned long *configs,
857 unsigned num_configs)
859 const unsigned *pins;
863 ret = amd_get_group_pins(pctldev, group, &pins, &npins);
866 for (i = 0; i < npins; i++) {
867 if (amd_pinconf_set(pctldev, pins[i], configs, num_configs))
873 static const struct pinconf_ops amd_pinconf_ops = {
874 .pin_config_get = amd_pinconf_get,
875 .pin_config_set = amd_pinconf_set,
876 .pin_config_group_get = amd_pinconf_group_get,
877 .pin_config_group_set = amd_pinconf_group_set,
880 #ifdef CONFIG_PM_SLEEP
881 static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin)
883 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin);
889 * Only restore the pin if it is actually in use by the kernel (or
892 if (pd->mux_owner || pd->gpio_owner ||
893 gpiochip_line_is_irq(&gpio_dev->gc, pin))
899 static int amd_gpio_suspend(struct device *dev)
901 struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
902 struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
906 for (i = 0; i < desc->npins; i++) {
907 int pin = desc->pins[i].number;
909 if (!amd_gpio_should_save(gpio_dev, pin))
912 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
913 gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin * 4) & ~PIN_IRQ_PENDING;
914 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
920 static int amd_gpio_resume(struct device *dev)
922 struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
923 struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
927 for (i = 0; i < desc->npins; i++) {
928 int pin = desc->pins[i].number;
930 if (!amd_gpio_should_save(gpio_dev, pin))
933 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
934 gpio_dev->saved_regs[i] |= readl(gpio_dev->base + pin * 4) & PIN_IRQ_PENDING;
935 writel(gpio_dev->saved_regs[i], gpio_dev->base + pin * 4);
936 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
942 static const struct dev_pm_ops amd_gpio_pm_ops = {
943 SET_LATE_SYSTEM_SLEEP_PM_OPS(amd_gpio_suspend,
948 static int amd_get_functions_count(struct pinctrl_dev *pctldev)
950 return ARRAY_SIZE(pmx_functions);
953 static const char *amd_get_fname(struct pinctrl_dev *pctrldev, unsigned int selector)
955 return pmx_functions[selector].name;
958 static int amd_get_groups(struct pinctrl_dev *pctrldev, unsigned int selector,
959 const char * const **groups,
960 unsigned int * const num_groups)
962 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctrldev);
964 if (!gpio_dev->iomux_base) {
965 dev_err(&gpio_dev->pdev->dev, "iomux function %d group not supported\n", selector);
969 *groups = pmx_functions[selector].groups;
970 *num_groups = pmx_functions[selector].ngroups;
974 static int amd_set_mux(struct pinctrl_dev *pctrldev, unsigned int function, unsigned int group)
976 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctrldev);
977 struct device *dev = &gpio_dev->pdev->dev;
981 if (!gpio_dev->iomux_base)
984 for (index = 0; index < NSELECTS; index++) {
985 if (strcmp(gpio_dev->groups[group].name, pmx_functions[function].groups[index]))
988 if (readb(gpio_dev->iomux_base + pmx_functions[function].index) ==
990 dev_err(dev, "IOMUX_GPIO 0x%x not present or supported\n",
991 pmx_functions[function].index);
995 writeb(index, gpio_dev->iomux_base + pmx_functions[function].index);
997 if (index != (readb(gpio_dev->iomux_base + pmx_functions[function].index) &
999 dev_err(dev, "IOMUX_GPIO 0x%x not present or supported\n",
1000 pmx_functions[function].index);
1004 for (ind = 0; ind < gpio_dev->groups[group].npins; ind++) {
1005 if (strncmp(gpio_dev->groups[group].name, "IMX_F", strlen("IMX_F")))
1008 pd = pin_desc_get(gpio_dev->pctrl, gpio_dev->groups[group].pins[ind]);
1009 pd->mux_owner = gpio_dev->groups[group].name;
1017 static const struct pinmux_ops amd_pmxops = {
1018 .get_functions_count = amd_get_functions_count,
1019 .get_function_name = amd_get_fname,
1020 .get_function_groups = amd_get_groups,
1021 .set_mux = amd_set_mux,
1024 static struct pinctrl_desc amd_pinctrl_desc = {
1025 .pins = kerncz_pins,
1026 .npins = ARRAY_SIZE(kerncz_pins),
1027 .pctlops = &amd_pinctrl_ops,
1028 .pmxops = &amd_pmxops,
1029 .confops = &amd_pinconf_ops,
1030 .owner = THIS_MODULE,
1033 static void amd_get_iomux_res(struct amd_gpio *gpio_dev)
1035 struct pinctrl_desc *desc = &amd_pinctrl_desc;
1036 struct device *dev = &gpio_dev->pdev->dev;
1039 index = device_property_match_string(dev, "pinctrl-resource-names", "iomux");
1041 dev_dbg(dev, "iomux not supported\n");
1045 gpio_dev->iomux_base = devm_platform_ioremap_resource(gpio_dev->pdev, index);
1046 if (IS_ERR(gpio_dev->iomux_base)) {
1047 dev_dbg(dev, "iomux not supported %d io resource\n", index);
1054 desc->pmxops = NULL;
1057 static int amd_gpio_probe(struct platform_device *pdev)
1060 struct resource *res;
1061 struct amd_gpio *gpio_dev;
1062 struct gpio_irq_chip *girq;
1064 gpio_dev = devm_kzalloc(&pdev->dev,
1065 sizeof(struct amd_gpio), GFP_KERNEL);
1069 raw_spin_lock_init(&gpio_dev->lock);
1071 gpio_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1072 if (IS_ERR(gpio_dev->base)) {
1073 dev_err(&pdev->dev, "Failed to get gpio io resource.\n");
1074 return PTR_ERR(gpio_dev->base);
1077 gpio_dev->irq = platform_get_irq(pdev, 0);
1078 if (gpio_dev->irq < 0)
1079 return gpio_dev->irq;
1081 #ifdef CONFIG_PM_SLEEP
1082 gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins,
1083 sizeof(*gpio_dev->saved_regs),
1085 if (!gpio_dev->saved_regs)
1089 gpio_dev->pdev = pdev;
1090 gpio_dev->gc.get_direction = amd_gpio_get_direction;
1091 gpio_dev->gc.direction_input = amd_gpio_direction_input;
1092 gpio_dev->gc.direction_output = amd_gpio_direction_output;
1093 gpio_dev->gc.get = amd_gpio_get_value;
1094 gpio_dev->gc.set = amd_gpio_set_value;
1095 gpio_dev->gc.set_config = amd_gpio_set_config;
1096 gpio_dev->gc.dbg_show = amd_gpio_dbg_show;
1098 gpio_dev->gc.base = -1;
1099 gpio_dev->gc.label = pdev->name;
1100 gpio_dev->gc.owner = THIS_MODULE;
1101 gpio_dev->gc.parent = &pdev->dev;
1102 gpio_dev->gc.ngpio = resource_size(res) / 4;
1104 gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64;
1105 gpio_dev->groups = kerncz_groups;
1106 gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups);
1108 amd_pinctrl_desc.name = dev_name(&pdev->dev);
1109 amd_get_iomux_res(gpio_dev);
1110 gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc,
1112 if (IS_ERR(gpio_dev->pctrl)) {
1113 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
1114 return PTR_ERR(gpio_dev->pctrl);
1117 girq = &gpio_dev->gc.irq;
1118 gpio_irq_chip_set_chip(girq, &amd_gpio_irqchip);
1119 /* This will let us handle the parent IRQ in the driver */
1120 girq->parent_handler = NULL;
1121 girq->num_parents = 0;
1122 girq->parents = NULL;
1123 girq->default_type = IRQ_TYPE_NONE;
1124 girq->handler = handle_simple_irq;
1126 ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev);
1130 ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev),
1131 0, 0, gpio_dev->gc.ngpio);
1133 dev_err(&pdev->dev, "Failed to add pin range\n");
1137 ret = devm_request_irq(&pdev->dev, gpio_dev->irq, amd_gpio_irq_handler,
1138 IRQF_SHARED, KBUILD_MODNAME, gpio_dev);
1142 platform_set_drvdata(pdev, gpio_dev);
1143 acpi_register_wakeup_handler(gpio_dev->irq, amd_gpio_check_wake, gpio_dev);
1145 dev_dbg(&pdev->dev, "amd gpio driver loaded\n");
1149 gpiochip_remove(&gpio_dev->gc);
1154 static int amd_gpio_remove(struct platform_device *pdev)
1156 struct amd_gpio *gpio_dev;
1158 gpio_dev = platform_get_drvdata(pdev);
1160 gpiochip_remove(&gpio_dev->gc);
1161 acpi_unregister_wakeup_handler(amd_gpio_check_wake, gpio_dev);
1167 static const struct acpi_device_id amd_gpio_acpi_match[] = {
1173 MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match);
1176 static struct platform_driver amd_gpio_driver = {
1179 .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match),
1180 #ifdef CONFIG_PM_SLEEP
1181 .pm = &amd_gpio_pm_ops,
1184 .probe = amd_gpio_probe,
1185 .remove = amd_gpio_remove,
1188 module_platform_driver(amd_gpio_driver);
1190 MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>");
1191 MODULE_DESCRIPTION("AMD GPIO pinctrl driver");