1 // SPDX-License-Identifier: GPL-2.0-only
3 * Apple SoC pinctrl+GPIO+external IRQ driver
5 * Copyright (C) The Asahi Linux Contributors
6 * Copyright (C) 2020 Corellium LLC
8 * Based on: pinctrl-pistachio.c
9 * Copyright (C) 2014 Imagination Technologies Ltd.
10 * Copyright (C) 2014 Google, Inc.
13 #include <dt-bindings/pinctrl/apple.h>
14 #include <linux/bits.h>
15 #include <linux/gpio/driver.h>
16 #include <linux/interrupt.h>
17 #include <linux/irq.h>
18 #include <linux/module.h>
20 #include <linux/of_irq.h>
21 #include <linux/pinctrl/pinctrl.h>
22 #include <linux/pinctrl/pinmux.h>
23 #include <linux/platform_device.h>
24 #include <linux/regmap.h>
26 #include "pinctrl-utils.h"
30 struct apple_gpio_pinctrl {
32 struct pinctrl_dev *pctldev;
37 struct pinctrl_desc pinctrl_desc;
38 struct gpio_chip gpio_chip;
39 struct irq_chip irq_chip;
43 #define REG_GPIO(x) (4 * (x))
44 #define REG_GPIOx_DATA BIT(0)
45 #define REG_GPIOx_MODE GENMASK(3, 1)
46 #define REG_GPIOx_OUT 1
47 #define REG_GPIOx_IN_IRQ_HI 2
48 #define REG_GPIOx_IN_IRQ_LO 3
49 #define REG_GPIOx_IN_IRQ_UP 4
50 #define REG_GPIOx_IN_IRQ_DN 5
51 #define REG_GPIOx_IN_IRQ_ANY 6
52 #define REG_GPIOx_IN_IRQ_OFF 7
53 #define REG_GPIOx_PERIPH GENMASK(6, 5)
54 #define REG_GPIOx_PULL GENMASK(8, 7)
55 #define REG_GPIOx_PULL_OFF 0
56 #define REG_GPIOx_PULL_DOWN 1
57 #define REG_GPIOx_PULL_UP_STRONG 2
58 #define REG_GPIOx_PULL_UP 3
59 #define REG_GPIOx_INPUT_ENABLE BIT(9)
60 #define REG_GPIOx_DRIVE_STRENGTH0 GENMASK(11, 10)
61 #define REG_GPIOx_SCHMITT BIT(15)
62 #define REG_GPIOx_GRP GENMASK(18, 16)
63 #define REG_GPIOx_LOCK BIT(21)
64 #define REG_GPIOx_DRIVE_STRENGTH1 GENMASK(23, 22)
65 #define REG_IRQ(g, x) (0x800 + 0x40 * (g) + 4 * ((x) >> 5))
67 struct regmap_config regmap_config = {
71 .cache_type = REGCACHE_FLAT,
72 .max_register = 512 * sizeof(u32),
73 .num_reg_defaults_raw = 512,
74 .use_relaxed_mmio = true,
77 /* No locking needed to mask/unmask IRQs as the interrupt mode is per pin-register. */
78 static void apple_gpio_set_reg(struct apple_gpio_pinctrl *pctl,
79 unsigned int pin, u32 mask, u32 value)
81 regmap_update_bits(pctl->map, REG_GPIO(pin), mask, value);
84 static u32 apple_gpio_get_reg(struct apple_gpio_pinctrl *pctl,
90 ret = regmap_read(pctl->map, REG_GPIO(pin), &val);
97 /* Pin controller functions */
99 static int apple_gpio_dt_node_to_map(struct pinctrl_dev *pctldev,
100 struct device_node *node,
101 struct pinctrl_map **map,
104 unsigned reserved_maps;
105 struct apple_gpio_pinctrl *pctl;
106 u32 pinfunc, pin, func;
107 int num_pins, i, ret;
108 const char *group_name;
109 const char *function_name;
115 pctl = pinctrl_dev_get_drvdata(pctldev);
117 ret = of_property_count_u32_elems(node, "pinmux");
120 "missing or empty pinmux property in node %pOFn.\n",
122 return ret ? ret : -EINVAL;
127 ret = pinctrl_utils_reserve_map(pctldev, map, &reserved_maps, num_maps, num_pins);
131 for (i = 0; i < num_pins; i++) {
132 ret = of_property_read_u32_index(node, "pinmux", i, &pinfunc);
136 pin = APPLE_PIN(pinfunc);
137 func = APPLE_FUNC(pinfunc);
139 if (func >= pinmux_generic_get_function_count(pctldev)) {
144 group_name = pinctrl_generic_get_group_name(pctldev, pin);
145 function_name = pinmux_generic_get_function_name(pctl->pctldev, func);
146 ret = pinctrl_utils_add_map_mux(pctl->pctldev, map,
147 &reserved_maps, num_maps,
148 group_name, function_name);
155 pinctrl_utils_free_map(pctldev, *map, *num_maps);
160 static const struct pinctrl_ops apple_gpio_pinctrl_ops = {
161 .get_groups_count = pinctrl_generic_get_group_count,
162 .get_group_name = pinctrl_generic_get_group_name,
163 .get_group_pins = pinctrl_generic_get_group_pins,
164 .dt_node_to_map = apple_gpio_dt_node_to_map,
165 .dt_free_map = pinctrl_utils_free_map,
168 /* Pin multiplexer functions */
170 static int apple_gpio_pinmux_set(struct pinctrl_dev *pctldev, unsigned func,
173 struct apple_gpio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
176 pctl, group, REG_GPIOx_PERIPH | REG_GPIOx_INPUT_ENABLE,
177 FIELD_PREP(REG_GPIOx_PERIPH, func) | REG_GPIOx_INPUT_ENABLE);
182 static const struct pinmux_ops apple_gpio_pinmux_ops = {
183 .get_functions_count = pinmux_generic_get_function_count,
184 .get_function_name = pinmux_generic_get_function_name,
185 .get_function_groups = pinmux_generic_get_function_groups,
186 .set_mux = apple_gpio_pinmux_set,
190 /* GPIO chip functions */
192 static int apple_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
194 struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);
195 unsigned int reg = apple_gpio_get_reg(pctl, offset);
197 if (FIELD_GET(REG_GPIOx_MODE, reg) == REG_GPIOx_OUT)
198 return GPIO_LINE_DIRECTION_OUT;
199 return GPIO_LINE_DIRECTION_IN;
202 static int apple_gpio_get(struct gpio_chip *chip, unsigned offset)
204 struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);
205 unsigned int reg = apple_gpio_get_reg(pctl, offset);
208 * If this is an input GPIO, read the actual value (not the
209 * cached regmap value)
211 if (FIELD_GET(REG_GPIOx_MODE, reg) != REG_GPIOx_OUT)
212 reg = readl_relaxed(pctl->base + REG_GPIO(offset));
214 return !!(reg & REG_GPIOx_DATA);
217 static void apple_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
219 struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);
221 apple_gpio_set_reg(pctl, offset, REG_GPIOx_DATA, value ? REG_GPIOx_DATA : 0);
224 static int apple_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
226 struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);
228 apple_gpio_set_reg(pctl, offset,
229 REG_GPIOx_PERIPH | REG_GPIOx_MODE | REG_GPIOx_DATA |
230 REG_GPIOx_INPUT_ENABLE,
231 FIELD_PREP(REG_GPIOx_MODE, REG_GPIOx_IN_IRQ_OFF) |
232 REG_GPIOx_INPUT_ENABLE);
236 static int apple_gpio_direction_output(struct gpio_chip *chip,
237 unsigned int offset, int value)
239 struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);
241 apple_gpio_set_reg(pctl, offset,
242 REG_GPIOx_PERIPH | REG_GPIOx_MODE | REG_GPIOx_DATA,
243 FIELD_PREP(REG_GPIOx_MODE, REG_GPIOx_OUT) |
244 (value ? REG_GPIOx_DATA : 0));
248 /* IRQ chip functions */
250 static void apple_gpio_irq_ack(struct irq_data *data)
252 struct apple_gpio_pinctrl *pctl = gpiochip_get_data(irq_data_get_irq_chip_data(data));
253 unsigned int irqgrp = FIELD_GET(REG_GPIOx_GRP, apple_gpio_get_reg(pctl, data->hwirq));
255 writel(BIT(data->hwirq % 32), pctl->base + REG_IRQ(irqgrp, data->hwirq));
258 static unsigned int apple_gpio_irq_type(unsigned int type)
260 switch (type & IRQ_TYPE_SENSE_MASK) {
261 case IRQ_TYPE_EDGE_RISING:
262 return REG_GPIOx_IN_IRQ_UP;
263 case IRQ_TYPE_EDGE_FALLING:
264 return REG_GPIOx_IN_IRQ_DN;
265 case IRQ_TYPE_EDGE_BOTH:
266 return REG_GPIOx_IN_IRQ_ANY;
267 case IRQ_TYPE_LEVEL_HIGH:
268 return REG_GPIOx_IN_IRQ_HI;
269 case IRQ_TYPE_LEVEL_LOW:
270 return REG_GPIOx_IN_IRQ_LO;
272 return REG_GPIOx_IN_IRQ_OFF;
276 static void apple_gpio_irq_mask(struct irq_data *data)
278 struct apple_gpio_pinctrl *pctl = gpiochip_get_data(irq_data_get_irq_chip_data(data));
280 apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_MODE,
281 FIELD_PREP(REG_GPIOx_MODE, REG_GPIOx_IN_IRQ_OFF));
284 static void apple_gpio_irq_unmask(struct irq_data *data)
286 struct apple_gpio_pinctrl *pctl = gpiochip_get_data(irq_data_get_irq_chip_data(data));
287 unsigned int irqtype = apple_gpio_irq_type(irqd_get_trigger_type(data));
289 apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_MODE,
290 FIELD_PREP(REG_GPIOx_MODE, irqtype));
293 static unsigned int apple_gpio_irq_startup(struct irq_data *data)
295 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
296 struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);
298 apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_GRP,
299 FIELD_PREP(REG_GPIOx_GRP, 0));
301 apple_gpio_direction_input(chip, data->hwirq);
302 apple_gpio_irq_unmask(data);
307 static int apple_gpio_irq_set_type(struct irq_data *data, unsigned int type)
309 struct apple_gpio_pinctrl *pctl = gpiochip_get_data(irq_data_get_irq_chip_data(data));
310 unsigned int irqtype = apple_gpio_irq_type(type);
312 if (irqtype == REG_GPIOx_IN_IRQ_OFF)
315 apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_MODE,
316 FIELD_PREP(REG_GPIOx_MODE, irqtype));
318 if (type & IRQ_TYPE_LEVEL_MASK)
319 irq_set_handler_locked(data, handle_level_irq);
321 irq_set_handler_locked(data, handle_edge_irq);
325 static void apple_gpio_irq_handler(struct irq_desc *desc)
327 struct irq_chip *chip = irq_desc_get_chip(desc);
328 u8 *grpp = irq_desc_get_handler_data(desc);
329 struct apple_gpio_pinctrl *pctl;
330 unsigned int pinh, pinl;
331 unsigned long pending;
332 struct gpio_chip *gc;
334 pctl = container_of(grpp - *grpp, typeof(*pctl), irqgrps[0]);
335 gc = &pctl->gpio_chip;
337 chained_irq_enter(chip, desc);
338 for (pinh = 0; pinh < gc->ngpio; pinh += 32) {
339 pending = readl_relaxed(pctl->base + REG_IRQ(*grpp, pinh));
340 for_each_set_bit(pinl, &pending, 32)
341 generic_handle_domain_irq(gc->irq.domain, pinh + pinl);
343 chained_irq_exit(chip, desc);
346 static struct irq_chip apple_gpio_irqchip = {
347 .name = "Apple-GPIO",
348 .irq_startup = apple_gpio_irq_startup,
349 .irq_ack = apple_gpio_irq_ack,
350 .irq_mask = apple_gpio_irq_mask,
351 .irq_unmask = apple_gpio_irq_unmask,
352 .irq_set_type = apple_gpio_irq_set_type,
355 /* Probe & register */
357 static int apple_gpio_register(struct apple_gpio_pinctrl *pctl)
359 struct gpio_irq_chip *girq = &pctl->gpio_chip.irq;
360 void **irq_data = NULL;
363 pctl->irq_chip = apple_gpio_irqchip;
365 pctl->gpio_chip.label = dev_name(pctl->dev);
366 pctl->gpio_chip.request = gpiochip_generic_request;
367 pctl->gpio_chip.free = gpiochip_generic_free;
368 pctl->gpio_chip.get_direction = apple_gpio_get_direction;
369 pctl->gpio_chip.direction_input = apple_gpio_direction_input;
370 pctl->gpio_chip.direction_output = apple_gpio_direction_output;
371 pctl->gpio_chip.get = apple_gpio_get;
372 pctl->gpio_chip.set = apple_gpio_set;
373 pctl->gpio_chip.base = -1;
374 pctl->gpio_chip.ngpio = pctl->pinctrl_desc.npins;
375 pctl->gpio_chip.parent = pctl->dev;
377 if (girq->num_parents) {
380 girq->chip = &pctl->irq_chip;
381 girq->parent_handler = apple_gpio_irq_handler;
383 girq->parents = kmalloc_array(girq->num_parents,
384 sizeof(*girq->parents),
386 irq_data = kmalloc_array(girq->num_parents, sizeof(*irq_data),
388 if (!girq->parents || !irq_data) {
390 goto out_free_irq_data;
393 for (i = 0; i < girq->num_parents; i++) {
394 ret = platform_get_irq(to_platform_device(pctl->dev), i);
396 goto out_free_irq_data;
398 girq->parents[i] = ret;
399 pctl->irqgrps[i] = i;
400 irq_data[i] = &pctl->irqgrps[i];
403 girq->parent_handler_data_array = irq_data;
404 girq->per_parent_data = true;
405 girq->default_type = IRQ_TYPE_NONE;
406 girq->handler = handle_level_irq;
409 ret = devm_gpiochip_add_data(pctl->dev, &pctl->gpio_chip, pctl);
412 kfree(girq->parents);
418 static int apple_gpio_pinctrl_probe(struct platform_device *pdev)
420 struct apple_gpio_pinctrl *pctl;
421 struct pinctrl_pin_desc *pins;
423 const char **pin_names;
424 unsigned int *pin_nums;
425 static const char* pinmux_functions[] = {
426 "gpio", "periph1", "periph2", "periph3"
428 unsigned int i, nirqs = 0;
431 if (of_property_read_bool(pdev->dev.of_node, "interrupt-controller")) {
432 res = platform_irq_count(pdev);
437 pctl = devm_kzalloc(&pdev->dev, struct_size(pctl, irqgrps, nirqs),
441 pctl->dev = &pdev->dev;
442 pctl->gpio_chip.irq.num_parents = nirqs;
443 dev_set_drvdata(&pdev->dev, pctl);
445 if (of_property_read_u32(pdev->dev.of_node, "apple,npins", &npins))
446 return dev_err_probe(&pdev->dev, -EINVAL,
447 "apple,npins property not found\n");
449 pins = devm_kmalloc_array(&pdev->dev, npins, sizeof(pins[0]),
451 pin_names = devm_kmalloc_array(&pdev->dev, npins, sizeof(pin_names[0]),
453 pin_nums = devm_kmalloc_array(&pdev->dev, npins, sizeof(pin_nums[0]),
455 if (!pins || !pin_names || !pin_nums)
458 pctl->base = devm_platform_ioremap_resource(pdev, 0);
459 if (IS_ERR(pctl->base))
460 return PTR_ERR(pctl->base);
462 pctl->map = devm_regmap_init_mmio(&pdev->dev, pctl->base, ®map_config);
463 if (IS_ERR(pctl->map))
464 return dev_err_probe(&pdev->dev, PTR_ERR(pctl->map),
465 "Failed to create regmap\n");
467 for (i = 0; i < npins; i++) {
469 pins[i].name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "PIN%u", i);
470 pins[i].drv_data = pctl;
471 pin_names[i] = pins[i].name;
475 pctl->pinctrl_desc.name = dev_name(pctl->dev);
476 pctl->pinctrl_desc.pins = pins;
477 pctl->pinctrl_desc.npins = npins;
478 pctl->pinctrl_desc.pctlops = &apple_gpio_pinctrl_ops;
479 pctl->pinctrl_desc.pmxops = &apple_gpio_pinmux_ops;
481 pctl->pctldev = devm_pinctrl_register(&pdev->dev, &pctl->pinctrl_desc, pctl);
482 if (IS_ERR(pctl->pctldev))
483 return dev_err_probe(&pdev->dev, PTR_ERR(pctl->pctldev),
484 "Failed to register pinctrl device.\n");
486 for (i = 0; i < npins; i++) {
487 res = pinctrl_generic_add_group(pctl->pctldev, pins[i].name,
488 pin_nums + i, 1, pctl);
490 return dev_err_probe(pctl->dev, res,
491 "Failed to register group");
494 for (i = 0; i < ARRAY_SIZE(pinmux_functions); ++i) {
495 res = pinmux_generic_add_function(pctl->pctldev, pinmux_functions[i],
496 pin_names, npins, pctl);
498 return dev_err_probe(pctl->dev, res,
499 "Failed to register function.");
502 return apple_gpio_register(pctl);
505 static const struct of_device_id apple_gpio_pinctrl_of_match[] = {
506 { .compatible = "apple,pinctrl", },
510 static struct platform_driver apple_gpio_pinctrl_driver = {
512 .name = "apple-gpio-pinctrl",
513 .of_match_table = apple_gpio_pinctrl_of_match,
514 .suppress_bind_attrs = true,
516 .probe = apple_gpio_pinctrl_probe,
518 module_platform_driver(apple_gpio_pinctrl_driver);
520 MODULE_DESCRIPTION("Apple pinctrl/GPIO driver");
521 MODULE_AUTHOR("Stan Skowronek <stan@corellium.com>");
522 MODULE_AUTHOR("Joey Gouly <joey.gouly@arm.com>");
523 MODULE_LICENSE("GPL v2");