2 * Generic GPIO driver for logic cells found in the Nomadik SoC
4 * Copyright (C) 2008,2009 STMicroelectronics
5 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
6 * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
7 * Copyright (C) 2011 Linus Walleij <linus.walleij@linaro.org>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/device.h>
17 #include <linux/platform_device.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
21 #include <linux/gpio.h>
22 #include <linux/spinlock.h>
23 #include <linux/interrupt.h>
24 #include <linux/irq.h>
25 #include <linux/irqdomain.h>
26 #include <linux/slab.h>
27 #include <linux/pinctrl/pinctrl.h>
29 #include <asm/mach/irq.h>
31 #include <plat/pincfg.h>
32 #include <plat/gpio-nomadik.h>
34 #include "pinctrl-nomadik.h"
37 * The GPIO module in the Nomadik family of Systems-on-Chip is an
38 * AMBA device, managing 32 pins and alternate functions. The logic block
39 * is currently used in the Nomadik and ux500.
41 * Symbols in this file are called "nmk_gpio" for "nomadik gpio"
44 #define NMK_GPIO_PER_CHIP 32
46 struct nmk_gpio_chip {
47 struct gpio_chip chip;
48 struct irq_domain *domain;
52 unsigned int parent_irq;
53 int secondary_parent_irq;
54 u32 (*get_secondary_status)(unsigned int bank);
55 void (*set_ioforce)(bool enable);
58 /* Keep track of configured edges */
72 struct pinctrl_dev *pctl;
73 const struct nmk_pinctrl_soc_data *soc;
76 static struct nmk_gpio_chip *
77 nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)];
79 static DEFINE_SPINLOCK(nmk_gpio_slpm_lock);
81 #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips)
83 static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,
84 unsigned offset, int gpio_mode)
86 u32 bit = 1 << offset;
89 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit;
90 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit;
91 if (gpio_mode & NMK_GPIO_ALT_A)
93 if (gpio_mode & NMK_GPIO_ALT_B)
95 writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
96 writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
99 static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip,
100 unsigned offset, enum nmk_gpio_slpm mode)
102 u32 bit = 1 << offset;
105 slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC);
106 if (mode == NMK_GPIO_SLPM_NOCHANGE)
110 writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);
113 static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,
114 unsigned offset, enum nmk_gpio_pull pull)
116 u32 bit = 1 << offset;
119 pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);
120 if (pull == NMK_GPIO_PULL_NONE) {
122 nmk_chip->pull_up &= ~bit;
127 writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);
129 if (pull == NMK_GPIO_PULL_UP) {
130 nmk_chip->pull_up |= bit;
131 writel(bit, nmk_chip->addr + NMK_GPIO_DATS);
132 } else if (pull == NMK_GPIO_PULL_DOWN) {
133 nmk_chip->pull_up &= ~bit;
134 writel(bit, nmk_chip->addr + NMK_GPIO_DATC);
138 static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip,
139 unsigned offset, bool lowemi)
141 u32 bit = BIT(offset);
142 bool enabled = nmk_chip->lowemi & bit;
144 if (lowemi == enabled)
148 nmk_chip->lowemi |= bit;
150 nmk_chip->lowemi &= ~bit;
152 writel_relaxed(nmk_chip->lowemi,
153 nmk_chip->addr + NMK_GPIO_LOWEMI);
156 static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
159 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
162 static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip,
163 unsigned offset, int val)
166 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS);
168 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC);
171 static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
172 unsigned offset, int val)
174 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS);
175 __nmk_gpio_set_output(nmk_chip, offset, val);
178 static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,
179 unsigned offset, int gpio_mode,
182 u32 rwimsc = nmk_chip->rwimsc;
183 u32 fwimsc = nmk_chip->fwimsc;
185 if (glitch && nmk_chip->set_ioforce) {
186 u32 bit = BIT(offset);
188 /* Prevent spurious wakeups */
189 writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);
190 writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);
192 nmk_chip->set_ioforce(true);
195 __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode);
197 if (glitch && nmk_chip->set_ioforce) {
198 nmk_chip->set_ioforce(false);
200 writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);
201 writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);
206 nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset)
208 u32 falling = nmk_chip->fimsc & BIT(offset);
209 u32 rising = nmk_chip->rimsc & BIT(offset);
210 int gpio = nmk_chip->chip.base + offset;
211 int irq = NOMADIK_GPIO_TO_IRQ(gpio);
212 struct irq_data *d = irq_get_irq_data(irq);
214 if (!rising && !falling)
217 if (!d || !irqd_irq_disabled(d))
221 nmk_chip->rimsc &= ~BIT(offset);
222 writel_relaxed(nmk_chip->rimsc,
223 nmk_chip->addr + NMK_GPIO_RIMSC);
227 nmk_chip->fimsc &= ~BIT(offset);
228 writel_relaxed(nmk_chip->fimsc,
229 nmk_chip->addr + NMK_GPIO_FIMSC);
232 dev_dbg(nmk_chip->chip.dev, "%d: clearing interrupt mask\n", gpio);
235 static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
236 pin_cfg_t cfg, bool sleep, unsigned int *slpmregs)
238 static const char *afnames[] = {
239 [NMK_GPIO_ALT_GPIO] = "GPIO",
240 [NMK_GPIO_ALT_A] = "A",
241 [NMK_GPIO_ALT_B] = "B",
242 [NMK_GPIO_ALT_C] = "C"
244 static const char *pullnames[] = {
245 [NMK_GPIO_PULL_NONE] = "none",
246 [NMK_GPIO_PULL_UP] = "up",
247 [NMK_GPIO_PULL_DOWN] = "down",
248 [3] /* illegal */ = "??"
250 static const char *slpmnames[] = {
251 [NMK_GPIO_SLPM_INPUT] = "input/wakeup",
252 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup",
255 int pin = PIN_NUM(cfg);
256 int pull = PIN_PULL(cfg);
257 int af = PIN_ALT(cfg);
258 int slpm = PIN_SLPM(cfg);
259 int output = PIN_DIR(cfg);
260 int val = PIN_VAL(cfg);
261 bool glitch = af == NMK_GPIO_ALT_C;
263 dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: af %s, pull %s, slpm %s (%s%s)\n",
264 pin, cfg, afnames[af], pullnames[pull], slpmnames[slpm],
265 output ? "output " : "input",
266 output ? (val ? "high" : "low") : "");
269 int slpm_pull = PIN_SLPM_PULL(cfg);
270 int slpm_output = PIN_SLPM_DIR(cfg);
271 int slpm_val = PIN_SLPM_VAL(cfg);
273 af = NMK_GPIO_ALT_GPIO;
276 * The SLPM_* values are normal values + 1 to allow zero to
277 * mean "same as normal".
280 pull = slpm_pull - 1;
282 output = slpm_output - 1;
286 dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n",
288 slpm_pull ? pullnames[pull] : "same",
289 slpm_output ? (output ? "output" : "input") : "same",
290 slpm_val ? (val ? "high" : "low") : "same");
294 __nmk_gpio_make_output(nmk_chip, offset, val);
296 __nmk_gpio_make_input(nmk_chip, offset);
297 __nmk_gpio_set_pull(nmk_chip, offset, pull);
300 __nmk_gpio_set_lowemi(nmk_chip, offset, PIN_LOWEMI(cfg));
303 * If the pin is switching to altfunc, and there was an interrupt
304 * installed on it which has been lazy disabled, actually mask the
305 * interrupt to prevent spurious interrupts that would occur while the
306 * pin is under control of the peripheral. Only SKE does this.
308 if (af != NMK_GPIO_ALT_GPIO)
309 nmk_gpio_disable_lazy_irq(nmk_chip, offset);
312 * If we've backed up the SLPM registers (glitch workaround), modify
313 * the backups since they will be restored.
316 if (slpm == NMK_GPIO_SLPM_NOCHANGE)
317 slpmregs[nmk_chip->bank] |= BIT(offset);
319 slpmregs[nmk_chip->bank] &= ~BIT(offset);
321 __nmk_gpio_set_slpm(nmk_chip, offset, slpm);
323 __nmk_gpio_set_mode_safe(nmk_chip, offset, af, glitch);
327 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
328 * - Save SLPM registers
329 * - Set SLPM=0 for the IOs you want to switch and others to 1
330 * - Configure the GPIO registers for the IOs that are being switched
332 * - Modify the AFLSA/B registers for the IOs that are being switched
334 * - Restore SLPM registers
335 * - Any spurious wake up event during switch sequence to be ignored and
338 static void nmk_gpio_glitch_slpm_init(unsigned int *slpm)
342 for (i = 0; i < NUM_BANKS; i++) {
343 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
344 unsigned int temp = slpm[i];
349 clk_enable(chip->clk);
351 slpm[i] = readl(chip->addr + NMK_GPIO_SLPC);
352 writel(temp, chip->addr + NMK_GPIO_SLPC);
356 static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm)
360 for (i = 0; i < NUM_BANKS; i++) {
361 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
366 writel(slpm[i], chip->addr + NMK_GPIO_SLPC);
368 clk_disable(chip->clk);
372 static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep)
374 static unsigned int slpm[NUM_BANKS];
380 for (i = 0; i < num; i++) {
381 if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) {
387 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
390 memset(slpm, 0xff, sizeof(slpm));
392 for (i = 0; i < num; i++) {
393 int pin = PIN_NUM(cfgs[i]);
394 int offset = pin % NMK_GPIO_PER_CHIP;
396 if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C)
397 slpm[pin / NMK_GPIO_PER_CHIP] &= ~BIT(offset);
400 nmk_gpio_glitch_slpm_init(slpm);
403 for (i = 0; i < num; i++) {
404 struct nmk_gpio_chip *nmk_chip;
405 int pin = PIN_NUM(cfgs[i]);
407 nmk_chip = nmk_gpio_chips[pin / NMK_GPIO_PER_CHIP];
413 clk_enable(nmk_chip->clk);
414 spin_lock(&nmk_chip->lock);
415 __nmk_config_pin(nmk_chip, pin % NMK_GPIO_PER_CHIP,
416 cfgs[i], sleep, glitch ? slpm : NULL);
417 spin_unlock(&nmk_chip->lock);
418 clk_disable(nmk_chip->clk);
422 nmk_gpio_glitch_slpm_restore(slpm);
424 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
430 * nmk_config_pin - configure a pin's mux attributes
431 * @cfg: pin confguration
433 * Configures a pin's mode (alternate function or GPIO), its pull up status,
434 * and its sleep mode based on the specified configuration. The @cfg is
435 * usually one of the SoC specific macros defined in mach/<soc>-pins.h. These
436 * are constructed using, and can be further enhanced with, the macros in
439 * If a pin's mode is set to GPIO, it is configured as an input to avoid
440 * side-effects. The gpio can be manipulated later using standard GPIO API
443 int nmk_config_pin(pin_cfg_t cfg, bool sleep)
445 return __nmk_config_pins(&cfg, 1, sleep);
447 EXPORT_SYMBOL(nmk_config_pin);
450 * nmk_config_pins - configure several pins at once
451 * @cfgs: array of pin configurations
452 * @num: number of elments in the array
454 * Configures several pins using nmk_config_pin(). Refer to that function for
455 * further information.
457 int nmk_config_pins(pin_cfg_t *cfgs, int num)
459 return __nmk_config_pins(cfgs, num, false);
461 EXPORT_SYMBOL(nmk_config_pins);
463 int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num)
465 return __nmk_config_pins(cfgs, num, true);
467 EXPORT_SYMBOL(nmk_config_pins_sleep);
470 * nmk_gpio_set_slpm() - configure the sleep mode of a pin
472 * @mode: NMK_GPIO_SLPM_INPUT or NMK_GPIO_SLPM_NOCHANGE,
474 * This register is actually in the pinmux layer, not the GPIO block itself.
475 * The GPIO1B_SLPM register defines the GPIO mode when SLEEP/DEEP-SLEEP
476 * mode is entered (i.e. when signal IOFORCE is HIGH by the platform code).
477 * Each GPIO can be configured to be forced into GPIO mode when IOFORCE is
478 * HIGH, overriding the normal setting defined by GPIO_AFSELx registers.
479 * When IOFORCE returns LOW (by software, after SLEEP/DEEP-SLEEP exit),
480 * the GPIOs return to the normal setting defined by GPIO_AFSELx registers.
482 * If @mode is NMK_GPIO_SLPM_INPUT, the corresponding GPIO is switched to GPIO
483 * mode when signal IOFORCE is HIGH (i.e. when SLEEP/DEEP-SLEEP mode is
484 * entered) regardless of the altfunction selected. Also wake-up detection is
487 * If @mode is NMK_GPIO_SLPM_NOCHANGE, the corresponding GPIO remains
488 * controlled by NMK_GPIO_DATC, NMK_GPIO_DATS, NMK_GPIO_DIR, NMK_GPIO_PDIS
489 * (for altfunction GPIO) or respective on-chip peripherals (for other
490 * altfuncs) when IOFORCE is HIGH. Also wake-up detection DISABLED.
492 * Note that enable_irq_wake() will automatically enable wakeup detection.
494 int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode)
496 struct nmk_gpio_chip *nmk_chip;
499 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
503 clk_enable(nmk_chip->clk);
504 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
505 spin_lock(&nmk_chip->lock);
507 __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP, mode);
509 spin_unlock(&nmk_chip->lock);
510 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
511 clk_disable(nmk_chip->clk);
517 * nmk_gpio_set_pull() - enable/disable pull up/down on a gpio
519 * @pull: one of NMK_GPIO_PULL_DOWN, NMK_GPIO_PULL_UP, and NMK_GPIO_PULL_NONE
521 * Enables/disables pull up/down on a specified pin. This only takes effect if
522 * the pin is configured as an input (either explicitly or by the alternate
525 * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is
526 * configured as an input. Otherwise, due to the way the controller registers
527 * work, this function will change the value output on the pin.
529 int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull)
531 struct nmk_gpio_chip *nmk_chip;
534 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
538 clk_enable(nmk_chip->clk);
539 spin_lock_irqsave(&nmk_chip->lock, flags);
540 __nmk_gpio_set_pull(nmk_chip, gpio % NMK_GPIO_PER_CHIP, pull);
541 spin_unlock_irqrestore(&nmk_chip->lock, flags);
542 clk_disable(nmk_chip->clk);
549 * nmk_gpio_set_mode() - set the mux mode of a gpio pin
551 * @gpio_mode: one of NMK_GPIO_ALT_GPIO, NMK_GPIO_ALT_A,
552 * NMK_GPIO_ALT_B, and NMK_GPIO_ALT_C
554 * Sets the mode of the specified pin to one of the alternate functions or
557 int nmk_gpio_set_mode(int gpio, int gpio_mode)
559 struct nmk_gpio_chip *nmk_chip;
562 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
566 clk_enable(nmk_chip->clk);
567 spin_lock_irqsave(&nmk_chip->lock, flags);
568 __nmk_gpio_set_mode(nmk_chip, gpio % NMK_GPIO_PER_CHIP, gpio_mode);
569 spin_unlock_irqrestore(&nmk_chip->lock, flags);
570 clk_disable(nmk_chip->clk);
574 EXPORT_SYMBOL(nmk_gpio_set_mode);
576 int nmk_gpio_get_mode(int gpio)
578 struct nmk_gpio_chip *nmk_chip;
579 u32 afunc, bfunc, bit;
581 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
585 bit = 1 << (gpio % NMK_GPIO_PER_CHIP);
587 clk_enable(nmk_chip->clk);
589 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit;
590 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit;
592 clk_disable(nmk_chip->clk);
594 return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0);
596 EXPORT_SYMBOL(nmk_gpio_get_mode);
600 static inline int nmk_gpio_get_bitmask(int gpio)
602 return 1 << (gpio % NMK_GPIO_PER_CHIP);
605 static void nmk_gpio_irq_ack(struct irq_data *d)
607 struct nmk_gpio_chip *nmk_chip;
609 nmk_chip = irq_data_get_irq_chip_data(d);
613 clk_enable(nmk_chip->clk);
614 writel(nmk_gpio_get_bitmask(d->hwirq), nmk_chip->addr + NMK_GPIO_IC);
615 clk_disable(nmk_chip->clk);
618 enum nmk_gpio_irq_type {
623 static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
624 int gpio, enum nmk_gpio_irq_type which,
627 u32 bitmask = nmk_gpio_get_bitmask(gpio);
633 if (which == NORMAL) {
634 rimscreg = NMK_GPIO_RIMSC;
635 fimscreg = NMK_GPIO_FIMSC;
636 rimscval = &nmk_chip->rimsc;
637 fimscval = &nmk_chip->fimsc;
639 rimscreg = NMK_GPIO_RWIMSC;
640 fimscreg = NMK_GPIO_FWIMSC;
641 rimscval = &nmk_chip->rwimsc;
642 fimscval = &nmk_chip->fwimsc;
645 /* we must individually set/clear the two edges */
646 if (nmk_chip->edge_rising & bitmask) {
648 *rimscval |= bitmask;
650 *rimscval &= ~bitmask;
651 writel(*rimscval, nmk_chip->addr + rimscreg);
653 if (nmk_chip->edge_falling & bitmask) {
655 *fimscval |= bitmask;
657 *fimscval &= ~bitmask;
658 writel(*fimscval, nmk_chip->addr + fimscreg);
662 static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
666 * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is
667 * disabled, since setting SLPM to 1 increases power consumption, and
668 * wakeup is anyhow controlled by the RIMSC and FIMSC registers.
670 if (nmk_chip->sleepmode && on) {
671 __nmk_gpio_set_slpm(nmk_chip, gpio % nmk_chip->chip.base,
672 NMK_GPIO_SLPM_WAKEUP_ENABLE);
675 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on);
678 static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable)
680 struct nmk_gpio_chip *nmk_chip;
684 nmk_chip = irq_data_get_irq_chip_data(d);
685 bitmask = nmk_gpio_get_bitmask(d->hwirq);
689 clk_enable(nmk_chip->clk);
690 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
691 spin_lock(&nmk_chip->lock);
693 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable);
695 if (!(nmk_chip->real_wake & bitmask))
696 __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable);
698 spin_unlock(&nmk_chip->lock);
699 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
700 clk_disable(nmk_chip->clk);
705 static void nmk_gpio_irq_mask(struct irq_data *d)
707 nmk_gpio_irq_maskunmask(d, false);
710 static void nmk_gpio_irq_unmask(struct irq_data *d)
712 nmk_gpio_irq_maskunmask(d, true);
715 static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
717 struct nmk_gpio_chip *nmk_chip;
721 nmk_chip = irq_data_get_irq_chip_data(d);
724 bitmask = nmk_gpio_get_bitmask(d->hwirq);
726 clk_enable(nmk_chip->clk);
727 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
728 spin_lock(&nmk_chip->lock);
730 if (irqd_irq_disabled(d))
731 __nmk_gpio_set_wake(nmk_chip, d->hwirq, on);
734 nmk_chip->real_wake |= bitmask;
736 nmk_chip->real_wake &= ~bitmask;
738 spin_unlock(&nmk_chip->lock);
739 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
740 clk_disable(nmk_chip->clk);
745 static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
747 bool enabled = !irqd_irq_disabled(d);
748 bool wake = irqd_is_wakeup_set(d);
749 struct nmk_gpio_chip *nmk_chip;
753 nmk_chip = irq_data_get_irq_chip_data(d);
754 bitmask = nmk_gpio_get_bitmask(d->hwirq);
757 if (type & IRQ_TYPE_LEVEL_HIGH)
759 if (type & IRQ_TYPE_LEVEL_LOW)
762 clk_enable(nmk_chip->clk);
763 spin_lock_irqsave(&nmk_chip->lock, flags);
766 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false);
769 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false);
771 nmk_chip->edge_rising &= ~bitmask;
772 if (type & IRQ_TYPE_EDGE_RISING)
773 nmk_chip->edge_rising |= bitmask;
775 nmk_chip->edge_falling &= ~bitmask;
776 if (type & IRQ_TYPE_EDGE_FALLING)
777 nmk_chip->edge_falling |= bitmask;
780 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true);
783 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true);
785 spin_unlock_irqrestore(&nmk_chip->lock, flags);
786 clk_disable(nmk_chip->clk);
791 static unsigned int nmk_gpio_irq_startup(struct irq_data *d)
793 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
795 clk_enable(nmk_chip->clk);
796 nmk_gpio_irq_unmask(d);
800 static void nmk_gpio_irq_shutdown(struct irq_data *d)
802 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
804 nmk_gpio_irq_mask(d);
805 clk_disable(nmk_chip->clk);
808 static struct irq_chip nmk_gpio_irq_chip = {
809 .name = "Nomadik-GPIO",
810 .irq_ack = nmk_gpio_irq_ack,
811 .irq_mask = nmk_gpio_irq_mask,
812 .irq_unmask = nmk_gpio_irq_unmask,
813 .irq_set_type = nmk_gpio_irq_set_type,
814 .irq_set_wake = nmk_gpio_irq_set_wake,
815 .irq_startup = nmk_gpio_irq_startup,
816 .irq_shutdown = nmk_gpio_irq_shutdown,
819 static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
822 struct nmk_gpio_chip *nmk_chip;
823 struct irq_chip *host_chip = irq_get_chip(irq);
824 unsigned int first_irq;
826 chained_irq_enter(host_chip, desc);
828 nmk_chip = irq_get_handler_data(irq);
829 first_irq = nmk_chip->domain->revmap_data.legacy.first_irq;
831 int bit = __ffs(status);
833 generic_handle_irq(first_irq + bit);
837 chained_irq_exit(host_chip, desc);
840 static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
842 struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
845 clk_enable(nmk_chip->clk);
846 status = readl(nmk_chip->addr + NMK_GPIO_IS);
847 clk_disable(nmk_chip->clk);
849 __nmk_gpio_irq_handler(irq, desc, status);
852 static void nmk_gpio_secondary_irq_handler(unsigned int irq,
853 struct irq_desc *desc)
855 struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
856 u32 status = nmk_chip->get_secondary_status(nmk_chip->bank);
858 __nmk_gpio_irq_handler(irq, desc, status);
861 static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip)
863 irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler);
864 irq_set_handler_data(nmk_chip->parent_irq, nmk_chip);
866 if (nmk_chip->secondary_parent_irq >= 0) {
867 irq_set_chained_handler(nmk_chip->secondary_parent_irq,
868 nmk_gpio_secondary_irq_handler);
869 irq_set_handler_data(nmk_chip->secondary_parent_irq, nmk_chip);
876 static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset)
878 struct nmk_gpio_chip *nmk_chip =
879 container_of(chip, struct nmk_gpio_chip, chip);
881 clk_enable(nmk_chip->clk);
883 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
885 clk_disable(nmk_chip->clk);
890 static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset)
892 struct nmk_gpio_chip *nmk_chip =
893 container_of(chip, struct nmk_gpio_chip, chip);
894 u32 bit = 1 << offset;
897 clk_enable(nmk_chip->clk);
899 value = (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0;
901 clk_disable(nmk_chip->clk);
906 static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset,
909 struct nmk_gpio_chip *nmk_chip =
910 container_of(chip, struct nmk_gpio_chip, chip);
912 clk_enable(nmk_chip->clk);
914 __nmk_gpio_set_output(nmk_chip, offset, val);
916 clk_disable(nmk_chip->clk);
919 static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
922 struct nmk_gpio_chip *nmk_chip =
923 container_of(chip, struct nmk_gpio_chip, chip);
925 clk_enable(nmk_chip->clk);
927 __nmk_gpio_make_output(nmk_chip, offset, val);
929 clk_disable(nmk_chip->clk);
934 static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
936 struct nmk_gpio_chip *nmk_chip =
937 container_of(chip, struct nmk_gpio_chip, chip);
939 return irq_find_mapping(nmk_chip->domain, offset);
942 #ifdef CONFIG_DEBUG_FS
944 #include <linux/seq_file.h>
946 static void nmk_gpio_dbg_show_one(struct seq_file *s, struct gpio_chip *chip,
947 unsigned offset, unsigned gpio)
949 const char *label = gpiochip_is_requested(chip, offset);
950 struct nmk_gpio_chip *nmk_chip =
951 container_of(chip, struct nmk_gpio_chip, chip);
955 u32 bit = 1 << offset;
956 const char *modes[] = {
957 [NMK_GPIO_ALT_GPIO] = "gpio",
958 [NMK_GPIO_ALT_A] = "altA",
959 [NMK_GPIO_ALT_B] = "altB",
960 [NMK_GPIO_ALT_C] = "altC",
963 clk_enable(nmk_chip->clk);
964 is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & bit);
965 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit);
966 mode = nmk_gpio_get_mode(gpio);
968 seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s",
969 gpio, label ?: "(none)",
970 is_out ? "out" : "in ",
972 ? (chip->get(chip, offset) ? "hi" : "lo")
974 (mode < 0) ? "unknown" : modes[mode],
975 pull ? "pull" : "none");
977 if (label && !is_out) {
978 int irq = gpio_to_irq(gpio);
979 struct irq_desc *desc = irq_to_desc(irq);
981 /* This races with request_irq(), set_irq_type(),
982 * and set_irq_wake() ... but those are "rare".
984 if (irq >= 0 && desc->action) {
986 u32 bitmask = nmk_gpio_get_bitmask(gpio);
988 if (nmk_chip->edge_rising & bitmask)
989 trigger = "edge-rising";
990 else if (nmk_chip->edge_falling & bitmask)
991 trigger = "edge-falling";
993 trigger = "edge-undefined";
995 seq_printf(s, " irq-%d %s%s",
997 irqd_is_wakeup_set(&desc->irq_data)
1001 clk_disable(nmk_chip->clk);
1004 static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1007 unsigned gpio = chip->base;
1009 for (i = 0; i < chip->ngpio; i++, gpio++) {
1010 nmk_gpio_dbg_show_one(s, chip, i, gpio);
1011 seq_printf(s, "\n");
1016 static inline void nmk_gpio_dbg_show_one(struct seq_file *s,
1017 struct gpio_chip *chip,
1018 unsigned offset, unsigned gpio)
1021 #define nmk_gpio_dbg_show NULL
1024 /* This structure is replicated for each GPIO block allocated at probe time */
1025 static struct gpio_chip nmk_gpio_template = {
1026 .direction_input = nmk_gpio_make_input,
1027 .get = nmk_gpio_get_input,
1028 .direction_output = nmk_gpio_make_output,
1029 .set = nmk_gpio_set_output,
1030 .to_irq = nmk_gpio_to_irq,
1031 .dbg_show = nmk_gpio_dbg_show,
1035 void nmk_gpio_clocks_enable(void)
1039 for (i = 0; i < NUM_BANKS; i++) {
1040 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1045 clk_enable(chip->clk);
1049 void nmk_gpio_clocks_disable(void)
1053 for (i = 0; i < NUM_BANKS; i++) {
1054 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1059 clk_disable(chip->clk);
1064 * Called from the suspend/resume path to only keep the real wakeup interrupts
1065 * (those that have had set_irq_wake() called on them) as wakeup interrupts,
1066 * and not the rest of the interrupts which we needed to have as wakeups for
1069 * PM ops are not used since this needs to be done at the end, after all the
1070 * other drivers are done with their suspend callbacks.
1072 void nmk_gpio_wakeups_suspend(void)
1076 for (i = 0; i < NUM_BANKS; i++) {
1077 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1082 clk_enable(chip->clk);
1084 writel(chip->rwimsc & chip->real_wake,
1085 chip->addr + NMK_GPIO_RWIMSC);
1086 writel(chip->fwimsc & chip->real_wake,
1087 chip->addr + NMK_GPIO_FWIMSC);
1089 clk_disable(chip->clk);
1093 void nmk_gpio_wakeups_resume(void)
1097 for (i = 0; i < NUM_BANKS; i++) {
1098 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1103 clk_enable(chip->clk);
1105 writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC);
1106 writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC);
1108 clk_disable(chip->clk);
1113 * Read the pull up/pull down status.
1114 * A bit set in 'pull_up' means that pull up
1115 * is selected if pull is enabled in PDIS register.
1116 * Note: only pull up/down set via this driver can
1117 * be detected due to HW limitations.
1119 void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up)
1121 if (gpio_bank < NUM_BANKS) {
1122 struct nmk_gpio_chip *chip = nmk_gpio_chips[gpio_bank];
1127 *pull_up = chip->pull_up;
1131 int nmk_gpio_irq_map(struct irq_domain *d, unsigned int irq,
1132 irq_hw_number_t hwirq)
1134 struct nmk_gpio_chip *nmk_chip = d->host_data;
1139 irq_set_chip_and_handler(irq, &nmk_gpio_irq_chip, handle_edge_irq);
1140 set_irq_flags(irq, IRQF_VALID);
1141 irq_set_chip_data(irq, nmk_chip);
1142 irq_set_irq_type(irq, IRQ_TYPE_EDGE_FALLING);
1147 const struct irq_domain_ops nmk_gpio_irq_simple_ops = {
1148 .map = nmk_gpio_irq_map,
1149 .xlate = irq_domain_xlate_twocell,
1152 static int __devinit nmk_gpio_probe(struct platform_device *dev)
1154 struct nmk_gpio_platform_data *pdata = dev->dev.platform_data;
1155 struct device_node *np = dev->dev.of_node;
1156 struct nmk_gpio_chip *nmk_chip;
1157 struct gpio_chip *chip;
1158 struct resource *res;
1165 if (!pdata && !np) {
1166 dev_err(&dev->dev, "No platform data or device tree found\n");
1171 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
1175 if (of_get_property(np, "supports-sleepmode", NULL))
1176 pdata->supports_sleepmode = true;
1178 if (of_property_read_u32(np, "gpio-bank", &dev->id)) {
1179 dev_err(&dev->dev, "gpio-bank property not found\n");
1184 pdata->first_gpio = dev->id * NMK_GPIO_PER_CHIP;
1185 pdata->num_gpio = NMK_GPIO_PER_CHIP;
1188 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1194 irq = platform_get_irq(dev, 0);
1200 secondary_irq = platform_get_irq(dev, 1);
1201 if (secondary_irq >= 0 && !pdata->get_secondary_status) {
1206 if (request_mem_region(res->start, resource_size(res),
1207 dev_name(&dev->dev)) == NULL) {
1212 base = ioremap(res->start, resource_size(res));
1218 clk = clk_get(&dev->dev, NULL);
1224 nmk_chip = kzalloc(sizeof(*nmk_chip), GFP_KERNEL);
1231 * The virt address in nmk_chip->addr is in the nomadik register space,
1232 * so we can simply convert the resource address, without remapping
1234 nmk_chip->bank = dev->id;
1235 nmk_chip->clk = clk;
1236 nmk_chip->addr = base;
1237 nmk_chip->chip = nmk_gpio_template;
1238 nmk_chip->parent_irq = irq;
1239 nmk_chip->secondary_parent_irq = secondary_irq;
1240 nmk_chip->get_secondary_status = pdata->get_secondary_status;
1241 nmk_chip->set_ioforce = pdata->set_ioforce;
1242 nmk_chip->sleepmode = pdata->supports_sleepmode;
1243 spin_lock_init(&nmk_chip->lock);
1245 chip = &nmk_chip->chip;
1246 chip->base = pdata->first_gpio;
1247 chip->ngpio = pdata->num_gpio;
1248 chip->label = pdata->name ?: dev_name(&dev->dev);
1249 chip->dev = &dev->dev;
1250 chip->owner = THIS_MODULE;
1252 clk_enable(nmk_chip->clk);
1253 nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI);
1254 clk_disable(nmk_chip->clk);
1256 #ifdef CONFIG_OF_GPIO
1260 ret = gpiochip_add(&nmk_chip->chip);
1264 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));
1266 nmk_gpio_chips[nmk_chip->bank] = nmk_chip;
1268 platform_set_drvdata(dev, nmk_chip);
1270 nmk_chip->domain = irq_domain_add_legacy(np, NMK_GPIO_PER_CHIP,
1271 NOMADIK_GPIO_TO_IRQ(pdata->first_gpio),
1272 0, &nmk_gpio_irq_simple_ops, nmk_chip);
1273 if (!nmk_chip->domain) {
1274 pr_err("%s: Failed to create irqdomain\n", np->full_name);
1279 nmk_gpio_init_irq(nmk_chip);
1281 dev_info(&dev->dev, "at address %p\n", nmk_chip->addr);
1293 release_mem_region(res->start, resource_size(res));
1295 dev_err(&dev->dev, "Failure %i for GPIO %i-%i\n", ret,
1296 pdata->first_gpio, pdata->first_gpio+31);
1303 static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev)
1305 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1307 return npct->soc->ngroups;
1310 static const char *nmk_get_group_name(struct pinctrl_dev *pctldev,
1313 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1315 return npct->soc->groups[selector].name;
1318 static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
1319 const unsigned **pins,
1322 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1324 *pins = npct->soc->groups[selector].pins;
1325 *num_pins = npct->soc->groups[selector].npins;
1329 static struct pinctrl_gpio_range *
1330 nmk_match_gpio_range(struct pinctrl_dev *pctldev, unsigned offset)
1332 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1335 for (i = 0; i < npct->soc->gpio_num_ranges; i++) {
1336 struct pinctrl_gpio_range *range;
1338 range = &npct->soc->gpio_ranges[i];
1339 if (offset >= range->pin_base &&
1340 offset <= (range->pin_base + range->npins - 1))
1346 static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
1349 struct pinctrl_gpio_range *range;
1350 struct gpio_chip *chip;
1352 range = nmk_match_gpio_range(pctldev, offset);
1353 if (!range || !range->gc) {
1354 seq_printf(s, "invalid pin offset");
1358 nmk_gpio_dbg_show_one(s, chip, offset - chip->base, offset);
1361 static struct pinctrl_ops nmk_pinctrl_ops = {
1362 .get_groups_count = nmk_get_groups_cnt,
1363 .get_group_name = nmk_get_group_name,
1364 .get_group_pins = nmk_get_group_pins,
1365 .pin_dbg_show = nmk_pin_dbg_show,
1368 static struct pinctrl_desc nmk_pinctrl_desc = {
1369 .name = "pinctrl-nomadik",
1370 .pctlops = &nmk_pinctrl_ops,
1371 .owner = THIS_MODULE,
1374 static int __devinit nmk_pinctrl_probe(struct platform_device *pdev)
1376 const struct platform_device_id *platid = platform_get_device_id(pdev);
1377 struct nmk_pinctrl *npct;
1380 npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL);
1384 /* Poke in other ASIC variants here */
1385 if (platid->driver_data == PINCTRL_NMK_DB8500)
1386 nmk_pinctrl_db8500_init(&npct->soc);
1389 * We need all the GPIO drivers to probe FIRST, or we will not be able
1390 * to obtain references to the struct gpio_chip * for them, and we
1391 * need this to proceed.
1393 for (i = 0; i < npct->soc->gpio_num_ranges; i++) {
1394 if (!nmk_gpio_chips[i]) {
1395 dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i);
1396 devm_kfree(&pdev->dev, npct);
1397 return -EPROBE_DEFER;
1399 npct->soc->gpio_ranges[i].gc = &nmk_gpio_chips[i]->chip;
1402 nmk_pinctrl_desc.pins = npct->soc->pins;
1403 nmk_pinctrl_desc.npins = npct->soc->npins;
1404 npct->dev = &pdev->dev;
1405 npct->pctl = pinctrl_register(&nmk_pinctrl_desc, &pdev->dev, npct);
1407 dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n");
1411 /* We will handle a range of GPIO pins */
1412 for (i = 0; i < npct->soc->gpio_num_ranges; i++)
1413 pinctrl_add_gpio_range(npct->pctl, &npct->soc->gpio_ranges[i]);
1415 platform_set_drvdata(pdev, npct);
1416 dev_info(&pdev->dev, "initialized Nomadik pin control driver\n");
1421 static const struct of_device_id nmk_gpio_match[] = {
1422 { .compatible = "st,nomadik-gpio", },
1426 static struct platform_driver nmk_gpio_driver = {
1428 .owner = THIS_MODULE,
1430 .of_match_table = nmk_gpio_match,
1432 .probe = nmk_gpio_probe,
1435 static const struct platform_device_id nmk_pinctrl_id[] = {
1436 { "pinctrl-stn8815", PINCTRL_NMK_STN8815 },
1437 { "pinctrl-db8500", PINCTRL_NMK_DB8500 },
1440 static struct platform_driver nmk_pinctrl_driver = {
1442 .owner = THIS_MODULE,
1443 .name = "pinctrl-nomadik",
1445 .probe = nmk_pinctrl_probe,
1446 .id_table = nmk_pinctrl_id,
1449 static int __init nmk_gpio_init(void)
1453 ret = platform_driver_register(&nmk_gpio_driver);
1456 return platform_driver_register(&nmk_pinctrl_driver);
1459 core_initcall(nmk_gpio_init);
1461 MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini");
1462 MODULE_DESCRIPTION("Nomadik GPIO Driver");
1463 MODULE_LICENSE("GPL");