2 * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/gpio.h>
15 #include <linux/module.h>
17 #include <linux/of_irq.h>
18 #include <linux/pinctrl/pinconf-generic.h>
19 #include <linux/pinctrl/pinconf.h>
20 #include <linux/pinctrl/pinmux.h>
21 #include <linux/platform_device.h>
22 #include <linux/regmap.h>
23 #include <linux/slab.h>
24 #include <linux/types.h>
26 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
29 #include "../pinctrl-utils.h"
31 #define PMIC_GPIO_ADDRESS_RANGE 0x100
33 /* type and subtype registers base address offsets */
34 #define PMIC_GPIO_REG_TYPE 0x4
35 #define PMIC_GPIO_REG_SUBTYPE 0x5
37 /* GPIO peripheral type and subtype out_values */
38 #define PMIC_GPIO_TYPE 0x10
39 #define PMIC_GPIO_SUBTYPE_GPIO_4CH 0x1
40 #define PMIC_GPIO_SUBTYPE_GPIOC_4CH 0x5
41 #define PMIC_GPIO_SUBTYPE_GPIO_8CH 0x9
42 #define PMIC_GPIO_SUBTYPE_GPIOC_8CH 0xd
43 #define PMIC_GPIO_SUBTYPE_GPIO_LV 0x10
44 #define PMIC_GPIO_SUBTYPE_GPIO_MV 0x11
46 #define PMIC_MPP_REG_RT_STS 0x10
47 #define PMIC_MPP_REG_RT_STS_VAL_MASK 0x1
49 /* control register base address offsets */
50 #define PMIC_GPIO_REG_MODE_CTL 0x40
51 #define PMIC_GPIO_REG_DIG_VIN_CTL 0x41
52 #define PMIC_GPIO_REG_DIG_PULL_CTL 0x42
53 #define PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL 0x44
54 #define PMIC_GPIO_REG_DIG_IN_CTL 0x43
55 #define PMIC_GPIO_REG_DIG_OUT_CTL 0x45
56 #define PMIC_GPIO_REG_EN_CTL 0x46
57 #define PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL 0x4A
59 /* PMIC_GPIO_REG_MODE_CTL */
60 #define PMIC_GPIO_REG_MODE_VALUE_SHIFT 0x1
61 #define PMIC_GPIO_REG_MODE_FUNCTION_SHIFT 1
62 #define PMIC_GPIO_REG_MODE_FUNCTION_MASK 0x7
63 #define PMIC_GPIO_REG_MODE_DIR_SHIFT 4
64 #define PMIC_GPIO_REG_MODE_DIR_MASK 0x7
66 #define PMIC_GPIO_MODE_DIGITAL_INPUT 0
67 #define PMIC_GPIO_MODE_DIGITAL_OUTPUT 1
68 #define PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT 2
69 #define PMIC_GPIO_MODE_ANALOG_PASS_THRU 3
70 #define PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK 0x3
72 /* PMIC_GPIO_REG_DIG_VIN_CTL */
73 #define PMIC_GPIO_REG_VIN_SHIFT 0
74 #define PMIC_GPIO_REG_VIN_MASK 0x7
76 /* PMIC_GPIO_REG_DIG_PULL_CTL */
77 #define PMIC_GPIO_REG_PULL_SHIFT 0
78 #define PMIC_GPIO_REG_PULL_MASK 0x7
80 #define PMIC_GPIO_PULL_DOWN 4
81 #define PMIC_GPIO_PULL_DISABLE 5
83 /* PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL for LV/MV */
84 #define PMIC_GPIO_LV_MV_OUTPUT_INVERT 0x80
85 #define PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT 7
86 #define PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK 0xF
88 /* PMIC_GPIO_REG_DIG_IN_CTL */
89 #define PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN 0x80
90 #define PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK 0x7
91 #define PMIC_GPIO_DIG_IN_DTEST_SEL_MASK 0xf
93 /* PMIC_GPIO_REG_DIG_OUT_CTL */
94 #define PMIC_GPIO_REG_OUT_STRENGTH_SHIFT 0
95 #define PMIC_GPIO_REG_OUT_STRENGTH_MASK 0x3
96 #define PMIC_GPIO_REG_OUT_TYPE_SHIFT 4
97 #define PMIC_GPIO_REG_OUT_TYPE_MASK 0x3
100 * Output type - indicates pin should be configured as push-pull,
101 * open drain or open source.
103 #define PMIC_GPIO_OUT_BUF_CMOS 0
104 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS 1
105 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS 2
107 /* PMIC_GPIO_REG_EN_CTL */
108 #define PMIC_GPIO_REG_MASTER_EN_SHIFT 7
110 #define PMIC_GPIO_PHYSICAL_OFFSET 1
112 /* PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL */
113 #define PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK 0x3
115 /* Qualcomm specific pin configurations */
116 #define PMIC_GPIO_CONF_PULL_UP (PIN_CONFIG_END + 1)
117 #define PMIC_GPIO_CONF_STRENGTH (PIN_CONFIG_END + 2)
118 #define PMIC_GPIO_CONF_ATEST (PIN_CONFIG_END + 3)
119 #define PMIC_GPIO_CONF_ANALOG_PASS (PIN_CONFIG_END + 4)
120 #define PMIC_GPIO_CONF_DTEST_BUFFER (PIN_CONFIG_END + 5)
122 /* The index of each function in pmic_gpio_functions[] array */
123 enum pmic_gpio_func_index {
124 PMIC_GPIO_FUNC_INDEX_NORMAL,
125 PMIC_GPIO_FUNC_INDEX_PAIRED,
126 PMIC_GPIO_FUNC_INDEX_FUNC1,
127 PMIC_GPIO_FUNC_INDEX_FUNC2,
128 PMIC_GPIO_FUNC_INDEX_FUNC3,
129 PMIC_GPIO_FUNC_INDEX_FUNC4,
130 PMIC_GPIO_FUNC_INDEX_DTEST1,
131 PMIC_GPIO_FUNC_INDEX_DTEST2,
132 PMIC_GPIO_FUNC_INDEX_DTEST3,
133 PMIC_GPIO_FUNC_INDEX_DTEST4,
137 * struct pmic_gpio_pad - keep current GPIO settings
138 * @base: Address base in SPMI device.
139 * @irq: IRQ number which this GPIO generate.
140 * @is_enabled: Set to false when GPIO should be put in high Z state.
141 * @out_value: Cached pin output value
142 * @have_buffer: Set to true if GPIO output could be configured in push-pull,
143 * open-drain or open-source mode.
144 * @output_enabled: Set to true if GPIO output logic is enabled.
145 * @input_enabled: Set to true if GPIO input buffer logic is enabled.
146 * @analog_pass: Set to true if GPIO is in analog-pass-through mode.
147 * @lv_mv_type: Set to true if GPIO subtype is GPIO_LV(0x10) or GPIO_MV(0x11).
148 * @num_sources: Number of power-sources supported by this GPIO.
149 * @power_source: Current power-source used.
150 * @buffer_type: Push-pull, open-drain or open-source.
151 * @pullup: Constant current which flow trough GPIO output buffer.
152 * @strength: No, Low, Medium, High
153 * @function: See pmic_gpio_functions[]
154 * @atest: the ATEST selection for GPIO analog-pass-through mode
155 * @dtest_buffer: the DTEST buffer selection for digital input mode.
157 struct pmic_gpio_pad {
167 unsigned int num_sources;
168 unsigned int power_source;
169 unsigned int buffer_type;
171 unsigned int strength;
172 unsigned int function;
174 unsigned int dtest_buffer;
177 struct pmic_gpio_state {
180 struct pinctrl_dev *ctrl;
181 struct gpio_chip chip;
184 static const struct pinconf_generic_params pmic_gpio_bindings[] = {
185 {"qcom,pull-up-strength", PMIC_GPIO_CONF_PULL_UP, 0},
186 {"qcom,drive-strength", PMIC_GPIO_CONF_STRENGTH, 0},
187 {"qcom,atest", PMIC_GPIO_CONF_ATEST, 0},
188 {"qcom,analog-pass", PMIC_GPIO_CONF_ANALOG_PASS, 0},
189 {"qcom,dtest-buffer", PMIC_GPIO_CONF_DTEST_BUFFER, 0},
192 #ifdef CONFIG_DEBUG_FS
193 static const struct pin_config_item pmic_conf_items[ARRAY_SIZE(pmic_gpio_bindings)] = {
194 PCONFDUMP(PMIC_GPIO_CONF_PULL_UP, "pull up strength", NULL, true),
195 PCONFDUMP(PMIC_GPIO_CONF_STRENGTH, "drive-strength", NULL, true),
196 PCONFDUMP(PMIC_GPIO_CONF_ATEST, "atest", NULL, true),
197 PCONFDUMP(PMIC_GPIO_CONF_ANALOG_PASS, "analog-pass", NULL, true),
198 PCONFDUMP(PMIC_GPIO_CONF_DTEST_BUFFER, "dtest-buffer", NULL, true),
202 static const char *const pmic_gpio_groups[] = {
203 "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8",
204 "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15",
205 "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
206 "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
207 "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36",
210 static const char *const pmic_gpio_functions[] = {
211 [PMIC_GPIO_FUNC_INDEX_NORMAL] = PMIC_GPIO_FUNC_NORMAL,
212 [PMIC_GPIO_FUNC_INDEX_PAIRED] = PMIC_GPIO_FUNC_PAIRED,
213 [PMIC_GPIO_FUNC_INDEX_FUNC1] = PMIC_GPIO_FUNC_FUNC1,
214 [PMIC_GPIO_FUNC_INDEX_FUNC2] = PMIC_GPIO_FUNC_FUNC2,
215 [PMIC_GPIO_FUNC_INDEX_FUNC3] = PMIC_GPIO_FUNC_FUNC3,
216 [PMIC_GPIO_FUNC_INDEX_FUNC4] = PMIC_GPIO_FUNC_FUNC4,
217 [PMIC_GPIO_FUNC_INDEX_DTEST1] = PMIC_GPIO_FUNC_DTEST1,
218 [PMIC_GPIO_FUNC_INDEX_DTEST2] = PMIC_GPIO_FUNC_DTEST2,
219 [PMIC_GPIO_FUNC_INDEX_DTEST3] = PMIC_GPIO_FUNC_DTEST3,
220 [PMIC_GPIO_FUNC_INDEX_DTEST4] = PMIC_GPIO_FUNC_DTEST4,
223 static int pmic_gpio_read(struct pmic_gpio_state *state,
224 struct pmic_gpio_pad *pad, unsigned int addr)
229 ret = regmap_read(state->map, pad->base + addr, &val);
231 dev_err(state->dev, "read 0x%x failed\n", addr);
238 static int pmic_gpio_write(struct pmic_gpio_state *state,
239 struct pmic_gpio_pad *pad, unsigned int addr,
244 ret = regmap_write(state->map, pad->base + addr, val);
246 dev_err(state->dev, "write 0x%x failed\n", addr);
251 static int pmic_gpio_get_groups_count(struct pinctrl_dev *pctldev)
253 /* Every PIN is a group */
254 return pctldev->desc->npins;
257 static const char *pmic_gpio_get_group_name(struct pinctrl_dev *pctldev,
260 return pctldev->desc->pins[pin].name;
263 static int pmic_gpio_get_group_pins(struct pinctrl_dev *pctldev, unsigned pin,
264 const unsigned **pins, unsigned *num_pins)
266 *pins = &pctldev->desc->pins[pin].number;
271 static const struct pinctrl_ops pmic_gpio_pinctrl_ops = {
272 .get_groups_count = pmic_gpio_get_groups_count,
273 .get_group_name = pmic_gpio_get_group_name,
274 .get_group_pins = pmic_gpio_get_group_pins,
275 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
276 .dt_free_map = pinctrl_utils_free_map,
279 static int pmic_gpio_get_functions_count(struct pinctrl_dev *pctldev)
281 return ARRAY_SIZE(pmic_gpio_functions);
284 static const char *pmic_gpio_get_function_name(struct pinctrl_dev *pctldev,
287 return pmic_gpio_functions[function];
290 static int pmic_gpio_get_function_groups(struct pinctrl_dev *pctldev,
292 const char *const **groups,
293 unsigned *const num_qgroups)
295 *groups = pmic_gpio_groups;
296 *num_qgroups = pctldev->desc->npins;
300 static int pmic_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned function,
303 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
304 struct pmic_gpio_pad *pad;
308 if (function > PMIC_GPIO_FUNC_INDEX_DTEST4) {
309 pr_err("function: %d is not defined\n", function);
313 pad = pctldev->desc->pins[pin].drv_data;
315 * Non-LV/MV subtypes only support 2 special functions,
316 * offsetting the dtestx function values by 2
318 if (!pad->lv_mv_type) {
319 if (function == PMIC_GPIO_FUNC_INDEX_FUNC3 ||
320 function == PMIC_GPIO_FUNC_INDEX_FUNC4) {
321 pr_err("LV/MV subtype doesn't have func3/func4\n");
324 if (function >= PMIC_GPIO_FUNC_INDEX_DTEST1)
325 function -= (PMIC_GPIO_FUNC_INDEX_DTEST1 -
326 PMIC_GPIO_FUNC_INDEX_FUNC3);
329 pad->function = function;
331 if (pad->analog_pass)
332 val = PMIC_GPIO_MODE_ANALOG_PASS_THRU;
333 else if (pad->output_enabled && pad->input_enabled)
334 val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT;
335 else if (pad->output_enabled)
336 val = PMIC_GPIO_MODE_DIGITAL_OUTPUT;
338 val = PMIC_GPIO_MODE_DIGITAL_INPUT;
340 if (pad->lv_mv_type) {
341 ret = pmic_gpio_write(state, pad,
342 PMIC_GPIO_REG_MODE_CTL, val);
346 val = pad->atest - 1;
347 ret = pmic_gpio_write(state, pad,
348 PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val);
353 << PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT;
355 & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
356 ret = pmic_gpio_write(state, pad,
357 PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val);
361 val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT;
362 val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
363 val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
365 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
370 val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT;
372 return pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val);
375 static const struct pinmux_ops pmic_gpio_pinmux_ops = {
376 .get_functions_count = pmic_gpio_get_functions_count,
377 .get_function_name = pmic_gpio_get_function_name,
378 .get_function_groups = pmic_gpio_get_function_groups,
379 .set_mux = pmic_gpio_set_mux,
382 static int pmic_gpio_config_get(struct pinctrl_dev *pctldev,
383 unsigned int pin, unsigned long *config)
385 unsigned param = pinconf_to_config_param(*config);
386 struct pmic_gpio_pad *pad;
389 pad = pctldev->desc->pins[pin].drv_data;
392 case PIN_CONFIG_DRIVE_PUSH_PULL:
393 if (pad->buffer_type != PMIC_GPIO_OUT_BUF_CMOS)
397 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
398 if (pad->buffer_type != PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS)
402 case PIN_CONFIG_DRIVE_OPEN_SOURCE:
403 if (pad->buffer_type != PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS)
407 case PIN_CONFIG_BIAS_PULL_DOWN:
408 if (pad->pullup != PMIC_GPIO_PULL_DOWN)
412 case PIN_CONFIG_BIAS_DISABLE:
413 if (pad->pullup != PMIC_GPIO_PULL_DISABLE)
417 case PIN_CONFIG_BIAS_PULL_UP:
418 if (pad->pullup != PMIC_GPIO_PULL_UP_30)
422 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
427 case PIN_CONFIG_POWER_SOURCE:
428 arg = pad->power_source;
430 case PIN_CONFIG_INPUT_ENABLE:
431 if (!pad->input_enabled)
435 case PIN_CONFIG_OUTPUT:
436 arg = pad->out_value;
438 case PMIC_GPIO_CONF_PULL_UP:
441 case PMIC_GPIO_CONF_STRENGTH:
444 case PMIC_GPIO_CONF_ATEST:
447 case PMIC_GPIO_CONF_ANALOG_PASS:
448 arg = pad->analog_pass;
450 case PMIC_GPIO_CONF_DTEST_BUFFER:
451 arg = pad->dtest_buffer;
457 *config = pinconf_to_config_packed(param, arg);
461 static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
462 unsigned long *configs, unsigned nconfs)
464 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
465 struct pmic_gpio_pad *pad;
470 pad = pctldev->desc->pins[pin].drv_data;
472 pad->is_enabled = true;
473 for (i = 0; i < nconfs; i++) {
474 param = pinconf_to_config_param(configs[i]);
475 arg = pinconf_to_config_argument(configs[i]);
478 case PIN_CONFIG_DRIVE_PUSH_PULL:
479 pad->buffer_type = PMIC_GPIO_OUT_BUF_CMOS;
481 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
482 if (!pad->have_buffer)
484 pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS;
486 case PIN_CONFIG_DRIVE_OPEN_SOURCE:
487 if (!pad->have_buffer)
489 pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS;
491 case PIN_CONFIG_BIAS_DISABLE:
492 pad->pullup = PMIC_GPIO_PULL_DISABLE;
494 case PIN_CONFIG_BIAS_PULL_UP:
495 pad->pullup = PMIC_GPIO_PULL_UP_30;
497 case PIN_CONFIG_BIAS_PULL_DOWN:
499 pad->pullup = PMIC_GPIO_PULL_DOWN;
501 pad->pullup = PMIC_GPIO_PULL_DISABLE;
503 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
504 pad->is_enabled = false;
506 case PIN_CONFIG_POWER_SOURCE:
507 if (arg >= pad->num_sources)
509 pad->power_source = arg;
511 case PIN_CONFIG_INPUT_ENABLE:
512 pad->input_enabled = arg ? true : false;
514 case PIN_CONFIG_OUTPUT:
515 pad->output_enabled = true;
516 pad->out_value = arg;
518 case PMIC_GPIO_CONF_PULL_UP:
519 if (arg > PMIC_GPIO_PULL_UP_1P5_30)
523 case PMIC_GPIO_CONF_STRENGTH:
524 if (arg > PMIC_GPIO_STRENGTH_LOW)
528 case PMIC_GPIO_CONF_ATEST:
529 if (!pad->lv_mv_type || arg > 4)
533 case PMIC_GPIO_CONF_ANALOG_PASS:
534 if (!pad->lv_mv_type)
536 pad->analog_pass = true;
538 case PMIC_GPIO_CONF_DTEST_BUFFER:
541 pad->dtest_buffer = arg;
548 val = pad->power_source << PMIC_GPIO_REG_VIN_SHIFT;
550 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL, val);
554 val = pad->pullup << PMIC_GPIO_REG_PULL_SHIFT;
556 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL, val);
560 val = pad->buffer_type << PMIC_GPIO_REG_OUT_TYPE_SHIFT;
561 val |= pad->strength << PMIC_GPIO_REG_OUT_STRENGTH_SHIFT;
563 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL, val);
567 if (pad->dtest_buffer == 0) {
570 if (pad->lv_mv_type) {
571 val = pad->dtest_buffer - 1;
572 val |= PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN;
574 val = BIT(pad->dtest_buffer - 1);
577 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_IN_CTL, val);
581 if (pad->analog_pass)
582 val = PMIC_GPIO_MODE_ANALOG_PASS_THRU;
583 else if (pad->output_enabled && pad->input_enabled)
584 val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT;
585 else if (pad->output_enabled)
586 val = PMIC_GPIO_MODE_DIGITAL_OUTPUT;
588 val = PMIC_GPIO_MODE_DIGITAL_INPUT;
590 if (pad->lv_mv_type) {
591 ret = pmic_gpio_write(state, pad,
592 PMIC_GPIO_REG_MODE_CTL, val);
596 val = pad->atest - 1;
597 ret = pmic_gpio_write(state, pad,
598 PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val);
603 << PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT;
605 & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
606 ret = pmic_gpio_write(state, pad,
607 PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val);
611 val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT;
612 val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
613 val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
615 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
620 val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT;
622 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val);
627 static void pmic_gpio_config_dbg_show(struct pinctrl_dev *pctldev,
628 struct seq_file *s, unsigned pin)
630 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
631 struct pmic_gpio_pad *pad;
632 int ret, val, function;
634 static const char *const biases[] = {
635 "pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA",
636 "pull-up 1.5uA + 30uA boost", "pull-down 10uA", "no pull"
638 static const char *const buffer_types[] = {
639 "push-pull", "open-drain", "open-source"
641 static const char *const strengths[] = {
642 "no", "high", "medium", "low"
645 pad = pctldev->desc->pins[pin].drv_data;
647 seq_printf(s, " gpio%-2d:", pin + PMIC_GPIO_PHYSICAL_OFFSET);
649 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_EN_CTL);
651 if (val < 0 || !(val >> PMIC_GPIO_REG_MASTER_EN_SHIFT)) {
654 if (pad->input_enabled) {
655 ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS);
659 ret &= PMIC_MPP_REG_RT_STS_VAL_MASK;
660 pad->out_value = ret;
663 * For the non-LV/MV subtypes only 2 special functions are
664 * available, offsetting the dtest function values by 2.
666 function = pad->function;
667 if (!pad->lv_mv_type &&
668 pad->function >= PMIC_GPIO_FUNC_INDEX_FUNC3)
669 function += PMIC_GPIO_FUNC_INDEX_DTEST1 -
670 PMIC_GPIO_FUNC_INDEX_FUNC3;
672 if (pad->analog_pass)
673 seq_puts(s, " analog-pass");
675 seq_printf(s, " %-4s",
676 pad->output_enabled ? "out" : "in");
677 seq_printf(s, " %-7s", pmic_gpio_functions[function]);
678 seq_printf(s, " vin-%d", pad->power_source);
679 seq_printf(s, " %-27s", biases[pad->pullup]);
680 seq_printf(s, " %-10s", buffer_types[pad->buffer_type]);
681 seq_printf(s, " %-4s", pad->out_value ? "high" : "low");
682 seq_printf(s, " %-7s", strengths[pad->strength]);
683 seq_printf(s, " atest-%d", pad->atest);
684 seq_printf(s, " dtest-%d", pad->dtest_buffer);
688 static const struct pinconf_ops pmic_gpio_pinconf_ops = {
690 .pin_config_group_get = pmic_gpio_config_get,
691 .pin_config_group_set = pmic_gpio_config_set,
692 .pin_config_group_dbg_show = pmic_gpio_config_dbg_show,
695 static int pmic_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
697 struct pmic_gpio_state *state = gpiochip_get_data(chip);
698 unsigned long config;
700 config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1);
702 return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
705 static int pmic_gpio_direction_output(struct gpio_chip *chip,
706 unsigned pin, int val)
708 struct pmic_gpio_state *state = gpiochip_get_data(chip);
709 unsigned long config;
711 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val);
713 return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
716 static int pmic_gpio_get(struct gpio_chip *chip, unsigned pin)
718 struct pmic_gpio_state *state = gpiochip_get_data(chip);
719 struct pmic_gpio_pad *pad;
722 pad = state->ctrl->desc->pins[pin].drv_data;
724 if (!pad->is_enabled)
727 if (pad->input_enabled) {
728 ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS);
732 pad->out_value = ret & PMIC_MPP_REG_RT_STS_VAL_MASK;
735 return !!pad->out_value;
738 static void pmic_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
740 struct pmic_gpio_state *state = gpiochip_get_data(chip);
741 unsigned long config;
743 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value);
745 pmic_gpio_config_set(state->ctrl, pin, &config, 1);
748 static int pmic_gpio_of_xlate(struct gpio_chip *chip,
749 const struct of_phandle_args *gpio_desc,
752 if (chip->of_gpio_n_cells < 2)
756 *flags = gpio_desc->args[1];
758 return gpio_desc->args[0] - PMIC_GPIO_PHYSICAL_OFFSET;
761 static int pmic_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
763 struct pmic_gpio_state *state = gpiochip_get_data(chip);
764 struct pmic_gpio_pad *pad;
766 pad = state->ctrl->desc->pins[pin].drv_data;
771 static void pmic_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
773 struct pmic_gpio_state *state = gpiochip_get_data(chip);
776 for (i = 0; i < chip->ngpio; i++) {
777 pmic_gpio_config_dbg_show(state->ctrl, s, i);
782 static const struct gpio_chip pmic_gpio_gpio_template = {
783 .direction_input = pmic_gpio_direction_input,
784 .direction_output = pmic_gpio_direction_output,
785 .get = pmic_gpio_get,
786 .set = pmic_gpio_set,
787 .request = gpiochip_generic_request,
788 .free = gpiochip_generic_free,
789 .of_xlate = pmic_gpio_of_xlate,
790 .to_irq = pmic_gpio_to_irq,
791 .dbg_show = pmic_gpio_dbg_show,
794 static int pmic_gpio_populate(struct pmic_gpio_state *state,
795 struct pmic_gpio_pad *pad)
797 int type, subtype, val, dir;
799 type = pmic_gpio_read(state, pad, PMIC_GPIO_REG_TYPE);
803 if (type != PMIC_GPIO_TYPE) {
804 dev_err(state->dev, "incorrect block type 0x%x at 0x%x\n",
809 subtype = pmic_gpio_read(state, pad, PMIC_GPIO_REG_SUBTYPE);
814 case PMIC_GPIO_SUBTYPE_GPIO_4CH:
815 pad->have_buffer = true;
816 case PMIC_GPIO_SUBTYPE_GPIOC_4CH:
817 pad->num_sources = 4;
819 case PMIC_GPIO_SUBTYPE_GPIO_8CH:
820 pad->have_buffer = true;
821 case PMIC_GPIO_SUBTYPE_GPIOC_8CH:
822 pad->num_sources = 8;
824 case PMIC_GPIO_SUBTYPE_GPIO_LV:
825 pad->num_sources = 1;
826 pad->have_buffer = true;
827 pad->lv_mv_type = true;
829 case PMIC_GPIO_SUBTYPE_GPIO_MV:
830 pad->num_sources = 2;
831 pad->have_buffer = true;
832 pad->lv_mv_type = true;
835 dev_err(state->dev, "unknown GPIO type 0x%x\n", subtype);
839 if (pad->lv_mv_type) {
840 val = pmic_gpio_read(state, pad,
841 PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL);
845 pad->out_value = !!(val & PMIC_GPIO_LV_MV_OUTPUT_INVERT);
846 pad->function = val & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
848 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL);
852 dir = val & PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK;
854 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL);
858 pad->out_value = val & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
860 dir = val >> PMIC_GPIO_REG_MODE_DIR_SHIFT;
861 dir &= PMIC_GPIO_REG_MODE_DIR_MASK;
862 pad->function = val >> PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
863 pad->function &= PMIC_GPIO_REG_MODE_FUNCTION_MASK;
867 case PMIC_GPIO_MODE_DIGITAL_INPUT:
868 pad->input_enabled = true;
869 pad->output_enabled = false;
871 case PMIC_GPIO_MODE_DIGITAL_OUTPUT:
872 pad->input_enabled = false;
873 pad->output_enabled = true;
875 case PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT:
876 pad->input_enabled = true;
877 pad->output_enabled = true;
879 case PMIC_GPIO_MODE_ANALOG_PASS_THRU:
880 if (!pad->lv_mv_type)
882 pad->analog_pass = true;
885 dev_err(state->dev, "unknown GPIO direction\n");
889 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL);
893 pad->power_source = val >> PMIC_GPIO_REG_VIN_SHIFT;
894 pad->power_source &= PMIC_GPIO_REG_VIN_MASK;
896 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL);
900 pad->pullup = val >> PMIC_GPIO_REG_PULL_SHIFT;
901 pad->pullup &= PMIC_GPIO_REG_PULL_MASK;
903 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_IN_CTL);
907 if (pad->lv_mv_type && (val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN))
909 (val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK) + 1;
910 else if (!pad->lv_mv_type)
911 pad->dtest_buffer = ffs(val);
913 pad->dtest_buffer = 0;
915 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL);
919 pad->strength = val >> PMIC_GPIO_REG_OUT_STRENGTH_SHIFT;
920 pad->strength &= PMIC_GPIO_REG_OUT_STRENGTH_MASK;
922 pad->buffer_type = val >> PMIC_GPIO_REG_OUT_TYPE_SHIFT;
923 pad->buffer_type &= PMIC_GPIO_REG_OUT_TYPE_MASK;
925 if (pad->lv_mv_type) {
926 val = pmic_gpio_read(state, pad,
927 PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL);
930 pad->atest = (val & PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK) + 1;
933 /* Pin could be disabled with PIN_CONFIG_BIAS_HIGH_IMPEDANCE */
934 pad->is_enabled = true;
938 static int pmic_gpio_probe(struct platform_device *pdev)
940 struct device *dev = &pdev->dev;
941 struct pinctrl_pin_desc *pindesc;
942 struct pinctrl_desc *pctrldesc;
943 struct pmic_gpio_pad *pad, *pads;
944 struct pmic_gpio_state *state;
948 ret = of_property_read_u32(dev->of_node, "reg", ®);
950 dev_err(dev, "missing base address");
954 npins = platform_irq_count(pdev);
960 BUG_ON(npins > ARRAY_SIZE(pmic_gpio_groups));
962 state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
966 platform_set_drvdata(pdev, state);
968 state->dev = &pdev->dev;
969 state->map = dev_get_regmap(dev->parent, NULL);
971 pindesc = devm_kcalloc(dev, npins, sizeof(*pindesc), GFP_KERNEL);
975 pads = devm_kcalloc(dev, npins, sizeof(*pads), GFP_KERNEL);
979 pctrldesc = devm_kzalloc(dev, sizeof(*pctrldesc), GFP_KERNEL);
983 pctrldesc->pctlops = &pmic_gpio_pinctrl_ops;
984 pctrldesc->pmxops = &pmic_gpio_pinmux_ops;
985 pctrldesc->confops = &pmic_gpio_pinconf_ops;
986 pctrldesc->owner = THIS_MODULE;
987 pctrldesc->name = dev_name(dev);
988 pctrldesc->pins = pindesc;
989 pctrldesc->npins = npins;
990 pctrldesc->num_custom_params = ARRAY_SIZE(pmic_gpio_bindings);
991 pctrldesc->custom_params = pmic_gpio_bindings;
992 #ifdef CONFIG_DEBUG_FS
993 pctrldesc->custom_conf_items = pmic_conf_items;
996 for (i = 0; i < npins; i++, pindesc++) {
998 pindesc->drv_data = pad;
1000 pindesc->name = pmic_gpio_groups[i];
1002 pad->irq = platform_get_irq(pdev, i);
1006 pad->base = reg + i * PMIC_GPIO_ADDRESS_RANGE;
1008 ret = pmic_gpio_populate(state, pad);
1013 state->chip = pmic_gpio_gpio_template;
1014 state->chip.parent = dev;
1015 state->chip.base = -1;
1016 state->chip.ngpio = npins;
1017 state->chip.label = dev_name(dev);
1018 state->chip.of_gpio_n_cells = 2;
1019 state->chip.can_sleep = false;
1021 state->ctrl = devm_pinctrl_register(dev, pctrldesc, state);
1022 if (IS_ERR(state->ctrl))
1023 return PTR_ERR(state->ctrl);
1025 ret = gpiochip_add_data(&state->chip, state);
1027 dev_err(state->dev, "can't add gpio chip\n");
1031 ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0, npins);
1033 dev_err(dev, "failed to add pin range\n");
1040 gpiochip_remove(&state->chip);
1044 static int pmic_gpio_remove(struct platform_device *pdev)
1046 struct pmic_gpio_state *state = platform_get_drvdata(pdev);
1048 gpiochip_remove(&state->chip);
1052 static const struct of_device_id pmic_gpio_of_match[] = {
1053 { .compatible = "qcom,pm8916-gpio" }, /* 4 GPIO's */
1054 { .compatible = "qcom,pm8941-gpio" }, /* 36 GPIO's */
1055 { .compatible = "qcom,pm8994-gpio" }, /* 22 GPIO's */
1056 { .compatible = "qcom,pmi8994-gpio" }, /* 10 GPIO's */
1057 { .compatible = "qcom,pma8084-gpio" }, /* 22 GPIO's */
1058 { .compatible = "qcom,spmi-gpio" }, /* Generic */
1062 MODULE_DEVICE_TABLE(of, pmic_gpio_of_match);
1064 static struct platform_driver pmic_gpio_driver = {
1066 .name = "qcom-spmi-gpio",
1067 .of_match_table = pmic_gpio_of_match,
1069 .probe = pmic_gpio_probe,
1070 .remove = pmic_gpio_remove,
1073 module_platform_driver(pmic_gpio_driver);
1075 MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>");
1076 MODULE_DESCRIPTION("Qualcomm SPMI PMIC GPIO pin control driver");
1077 MODULE_ALIAS("platform:qcom-spmi-gpio");
1078 MODULE_LICENSE("GPL v2");