2 * r8a7791/r8a7743 processor support - PFC hardware block.
4 * Copyright (C) 2013 Renesas Electronics Corporation
5 * Copyright (C) 2014-2017 Cogent Embedded, Inc.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2
9 * as published by the Free Software Foundation.
12 #include <linux/kernel.h>
17 * Pins 0-23 assigned to GPIO bank 6 can be used for SD interfaces in
18 * which case they support both 3.3V and 1.8V signalling.
20 #define CPU_ALL_PORT(fn, sfx) \
21 PORT_GP_32(0, fn, sfx), \
22 PORT_GP_26(1, fn, sfx), \
23 PORT_GP_32(2, fn, sfx), \
24 PORT_GP_32(3, fn, sfx), \
25 PORT_GP_32(4, fn, sfx), \
26 PORT_GP_32(5, fn, sfx), \
27 PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
28 PORT_GP_1(6, 24, fn, sfx), \
29 PORT_GP_1(6, 25, fn, sfx), \
30 PORT_GP_1(6, 26, fn, sfx), \
31 PORT_GP_1(6, 27, fn, sfx), \
32 PORT_GP_1(6, 28, fn, sfx), \
33 PORT_GP_1(6, 29, fn, sfx), \
34 PORT_GP_1(6, 30, fn, sfx), \
35 PORT_GP_1(6, 31, fn, sfx), \
36 PORT_GP_26(7, fn, sfx)
45 PINMUX_FUNCTION_BEGIN,
49 FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5,
50 FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11,
51 FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_18_16, FN_IP0_20_19,
52 FN_IP0_22_21, FN_IP0_24_23, FN_IP0_26_25, FN_IP0_28_27, FN_IP0_30_29,
53 FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6, FN_IP1_10_8,
54 FN_IP1_13_11, FN_IP1_16_14, FN_IP1_19_17, FN_IP1_22_20,
57 FN_IP1_25_23, FN_IP1_28_26, FN_IP1_31_29, FN_IP2_2_0, FN_IP2_4_3,
58 FN_IP2_6_5, FN_IP2_9_7, FN_IP2_12_10, FN_IP2_15_13, FN_IP2_18_16,
59 FN_IP2_20_19, FN_IP2_22_21, FN_EX_CS0_N, FN_IP2_24_23, FN_IP2_26_25,
60 FN_IP2_29_27, FN_IP3_2_0, FN_IP3_5_3, FN_IP3_8_6, FN_RD_N,
61 FN_IP3_11_9, FN_IP3_13_12, FN_IP3_15_14 , FN_IP3_17_16 , FN_IP3_19_18,
65 FN_IP3_27_25, FN_IP3_30_28, FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5,
66 FN_IP4_9_8, FN_IP4_12_10, FN_IP4_15_13, FN_IP4_18_16, FN_IP4_19,
67 FN_IP4_20, FN_IP4_21, FN_IP4_23_22, FN_IP4_25_24, FN_IP4_27_26,
68 FN_IP4_30_28, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_8_6, FN_IP5_11_9,
69 FN_IP5_14_12, FN_IP5_16_15, FN_IP5_19_17, FN_IP5_21_20, FN_IP5_23_22,
70 FN_IP5_25_24, FN_IP5_28_26, FN_IP5_31_29, FN_AUDIO_CLKA, FN_IP6_2_0,
71 FN_IP6_5_3, FN_IP6_7_6,
74 FN_IP7_5_3, FN_IP7_8_6, FN_IP7_10_9, FN_IP7_12_11, FN_IP7_14_13,
75 FN_IP7_16_15, FN_IP7_18_17, FN_IP7_20_19, FN_IP7_23_21, FN_IP7_26_24,
76 FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_11_9,
77 FN_IP8_14_12, FN_IP8_17_15, FN_IP8_20_18, FN_IP8_23_21, FN_IP8_25_24,
78 FN_IP8_27_26, FN_IP8_30_28, FN_IP9_2_0, FN_IP9_5_3, FN_IP9_6, FN_IP9_7,
79 FN_IP9_10_8, FN_IP9_11, FN_IP9_12, FN_IP9_15_13, FN_IP9_16,
83 FN_VI0_CLK, FN_IP9_20_19, FN_IP9_22_21, FN_IP9_24_23, FN_IP9_26_25,
84 FN_VI0_DATA0_VI0_B0, FN_VI0_DATA1_VI0_B1, FN_VI0_DATA2_VI0_B2,
85 FN_IP9_28_27, FN_VI0_DATA4_VI0_B4, FN_VI0_DATA5_VI0_B5,
86 FN_VI0_DATA6_VI0_B6, FN_VI0_DATA7_VI0_B7, FN_IP9_31_29, FN_IP10_2_0,
87 FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_16_15,
88 FN_IP10_18_17, FN_IP10_21_19, FN_IP10_24_22, FN_IP10_26_25,
89 FN_IP10_28_27, FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6,
90 FN_IP15_1_0, FN_IP15_3_2, FN_IP15_5_4,
93 FN_IP11_11_9, FN_IP11_14_12, FN_IP11_16_15, FN_IP11_18_17, FN_IP11_19,
94 FN_IP11_20, FN_IP11_21, FN_IP11_22, FN_IP11_23, FN_IP11_24,
95 FN_IP11_25, FN_IP11_26, FN_IP11_27, FN_IP11_29_28, FN_IP11_31_30,
96 FN_IP12_1_0, FN_IP12_3_2, FN_IP12_6_4, FN_IP12_9_7, FN_IP12_12_10,
97 FN_IP12_15_13, FN_IP12_17_16, FN_IP12_19_18, FN_IP12_21_20,
98 FN_IP12_23_22, FN_IP12_26_24, FN_IP12_29_27, FN_IP13_2_0, FN_IP13_4_3,
99 FN_IP13_6_5, FN_IP13_9_7, FN_IP3_24_22,
102 FN_IP13_10, FN_IP13_11, FN_IP13_12, FN_IP13_13, FN_IP13_14,
103 FN_IP13_15, FN_IP13_18_16, FN_IP13_21_19,
104 FN_IP13_22, FN_IP13_24_23, FN_SD1_CLK,
105 FN_IP13_25, FN_IP13_26, FN_IP13_27, FN_IP13_30_28, FN_IP14_1_0,
106 FN_IP14_2, FN_IP14_3, FN_IP14_4, FN_IP14_5, FN_IP14_6, FN_IP14_7,
107 FN_IP14_10_8, FN_IP14_13_11, FN_IP14_16_14, FN_IP14_19_17,
108 FN_IP14_22_20, FN_IP14_25_23, FN_IP14_28_26, FN_IP14_31_29,
109 FN_USB1_OVC, FN_DU0_DOTCLKIN,
112 FN_IP15_17_15, FN_IP15_20_18, FN_IP15_23_21, FN_IP15_26_24,
113 FN_IP15_29_27, FN_IP16_2_0, FN_IP16_5_3, FN_IP16_7_6, FN_IP16_9_8,
114 FN_IP16_11_10, FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14,
115 FN_IP6_18_16, FN_IP6_20_19, FN_IP6_23_21, FN_IP6_26_24, FN_IP6_29_27,
116 FN_IP7_2_0, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_14_12,
117 FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN,
120 FN_D0, FN_D1, FN_D2, FN_D3, FN_D4, FN_D5, FN_D6, FN_D7, FN_D8,
121 FN_D9, FN_D10, FN_D11, FN_D12, FN_D13, FN_D14, FN_D15,
122 FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_I2C0_SCL_C, FN_PWM2_B,
123 FN_A1, FN_MSIOF0_SYNC_B, FN_A2, FN_MSIOF0_SS1_B,
124 FN_A3, FN_MSIOF0_SS2_B, FN_A4, FN_MSIOF0_TXD_B,
125 FN_A5, FN_MSIOF0_RXD_B, FN_A6, FN_MSIOF1_SCK,
128 FN_A7, FN_MSIOF1_SYNC, FN_A8, FN_MSIOF1_SS1, FN_I2C0_SCL,
129 FN_A9, FN_MSIOF1_SS2, FN_I2C0_SDA,
130 FN_A10, FN_MSIOF1_TXD, FN_MSIOF1_TXD_D,
131 FN_A11, FN_MSIOF1_RXD, FN_I2C3_SCL_D, FN_MSIOF1_RXD_D,
132 FN_A12, FN_FMCLK, FN_I2C3_SDA_D, FN_MSIOF1_SCK_D,
133 FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D,
134 FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D,
136 FN_A16, FN_DREQ2_B, FN_FMCLK_C, FN_SCIFA1_SCK_B,
137 FN_A17, FN_DACK2_B, FN_I2C0_SDA_C,
138 FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, FN_SCIFB1_RXD_C,
141 FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, FN_SCIFB1_TXD_C, FN_SCIFB1_SCK_B,
143 FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0,
144 FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD,
145 FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD,
146 FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD,
147 FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD,
148 FN_CS0_N, FN_ATAG0_N_B, FN_I2C1_SCL,
149 FN_CS1_N_A26, FN_ATADIR0_N_B, FN_I2C1_SDA,
150 FN_EX_CS1_N, FN_MSIOF2_SCK,
151 FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC,
152 FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD, FN_ATAG0_N, FN_EX_WAIT1,
155 FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, FN_EX_WAIT2,
156 FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B,
157 FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1,
158 FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B,
159 FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2,
160 FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D,
161 FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B,
162 FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B,
163 FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B,
164 FN_DREQ0, FN_PWM3, FN_TPU_TO3,
165 FN_DACK0, FN_DRACK0, FN_REMOCON,
166 FN_SPEEDIN, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B,
167 FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D,
168 FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C, FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C,
169 FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C, FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C,
172 FN_SSI_SDATA0, FN_I2C0_SCL_B, FN_IIC0_SCL_B, FN_MSIOF2_SCK_C,
173 FN_SSI_SCK1, FN_I2C0_SDA_B, FN_IIC0_SDA_B, FN_MSIOF2_SYNC_C,
175 FN_SSI_WS1, FN_I2C1_SCL_B, FN_IIC1_SCL_B, FN_MSIOF2_TXD_C, FN_GLO_I1_D,
176 FN_SSI_SDATA1, FN_I2C1_SDA_B, FN_IIC1_SDA_B, FN_MSIOF2_RXD_C,
177 FN_SSI_SCK2, FN_I2C2_SCL, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E,
178 FN_SSI_WS2, FN_I2C2_SDA, FN_GPS_SIGN_B, FN_RX2_E,
179 FN_GLO_Q1_D, FN_HCTS1_N_E,
180 FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E,
181 FN_SSI_SCK34, FN_SSI_WS34, FN_SSI_SDATA3,
182 FN_SSI_SCK4, FN_GLO_SS_D,
183 FN_SSI_WS4, FN_GLO_RFON_D,
184 FN_SSI_SDATA4, FN_MSIOF2_SCK_D,
185 FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0,
186 FN_MSIOF2_SYNC_D, FN_VI1_R2_B,
189 FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1,
190 FN_MSIOF2_TXD_D, FN_VI1_R3_B,
191 FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0,
192 FN_MSIOF2_SS1_D, FN_VI1_R4_B,
193 FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1,
194 FN_MSIOF2_RXD_D, FN_VI1_R5_B,
195 FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B,
196 FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B,
197 FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS,
198 FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON,
199 FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B,
200 FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B,
201 FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D,
202 FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D,
203 FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D,
206 FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
207 FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E,
208 FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
209 FN_SCIFA2_RXD, FN_FMIN_E,
210 FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
211 FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N,
212 FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N,
213 FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N,
214 FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
215 FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N,
216 FN_IRQ5, FN_HTX1_C, FN_I2C1_SCL_E, FN_MSIOF2_SCK_E,
217 FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, FN_I2C1_SDA_E, FN_MSIOF2_SYNC_E,
218 FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, FN_GPS_CLK_C, FN_GPS_CLK_D,
219 FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B, FN_GPS_SIGN_C, FN_GPS_SIGN_D,
222 FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C,
223 FN_SCIF_CLK_B, FN_GPS_MAG_D,
224 FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B,
225 FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B,
226 FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B,
227 FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B,
228 FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B,
229 FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B,
230 FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B,
231 FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B,
232 FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B,
233 FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B,
234 FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B,
235 FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B,
236 FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B,
237 FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B,
238 FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B,
239 FN_SCIFA1_SCK, FN_SSI_SCK78_B,
242 FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, FN_SSI_WS78_B,
243 FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B,
244 FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B,
245 FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B,
246 FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B,
247 FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B,
248 FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B,
249 FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B, FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B,
250 FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B,
251 FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B,
252 FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B,
253 FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B,
254 FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B,
255 FN_SCIFA2_SCK, FN_SSI_SDATA9_B,
256 FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B,
257 FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX,
258 FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX,
261 FN_DU1_DB6, FN_LCDOUT22, FN_I2C3_SCL_C, FN_RX3, FN_SCIFA3_RXD,
262 FN_DU1_DB7, FN_LCDOUT23, FN_I2C3_SDA_C, FN_SCIF3_SCK, FN_SCIFA3_SCK,
263 FN_DU1_DOTCLKIN, FN_QSTVA_QVS,
264 FN_DU1_DOTCLKOUT0, FN_QCLK,
265 FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX,
266 FN_TX3_B, FN_I2C2_SCL_B, FN_PWM4,
267 FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS,
268 FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE,
269 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE,
270 FN_CAN0_RX, FN_RX3_B, FN_I2C2_SDA_B,
271 FN_DU1_DISP, FN_QPOLA,
272 FN_DU1_CDE, FN_QPOLB, FN_PWM4_B,
273 FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D,
274 FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D,
275 FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D,
276 FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D,
277 FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B,
278 FN_VI0_G0, FN_IIC1_SCL, FN_STP_IVCXO27_0_C, FN_I2C4_SCL,
279 FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N,
282 FN_VI0_G1, FN_IIC1_SDA, FN_STP_ISCLK_0_C, FN_I2C4_SDA,
283 FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N,
284 FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_I2C3_SCL_B,
285 FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N,
286 FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_I2C3_SDA_B,
287 FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N,
288 FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C,
289 FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D,
290 FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D,
291 FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D,
292 FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D,
293 FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D,
294 FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B,
295 FN_TS_SDATA0_C, FN_ATACS11_N,
296 FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B,
297 FN_TS_SCK0_C, FN_ATAG1_N,
298 FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C,
299 FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C,
300 FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_I2C1_SCL_D,
303 FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_I2C1_SDA_D,
304 FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_I2C4_SCL_B,
305 FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
306 FN_I2C4_SDA_B, FN_HRX1_D, FN_SCIFB0_RXD_D,
307 FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, FN_TX4_B, FN_SCIFA4_TXD_B,
308 FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, FN_RX4_B, FN_SCIFA4_RXD_B,
309 FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B,
310 FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B,
311 FN_VI1_CLK, FN_AVB_RXD4, FN_VI1_DATA0, FN_AVB_RXD5,
312 FN_VI1_DATA1, FN_AVB_RXD6, FN_VI1_DATA2, FN_AVB_RXD7,
313 FN_VI1_DATA3, FN_AVB_RX_ER, FN_VI1_DATA4, FN_AVB_MDIO,
314 FN_VI1_DATA5, FN_AVB_RX_DV, FN_VI1_DATA6, FN_AVB_MAGIC,
315 FN_VI1_DATA7, FN_AVB_MDC,
316 FN_ETH_MDIO, FN_AVB_RX_CLK, FN_I2C2_SCL_C,
317 FN_ETH_CRS_DV, FN_AVB_LINK, FN_I2C2_SDA_C,
320 FN_ETH_RX_ER, FN_AVB_CRS, FN_I2C3_SCL, FN_IIC0_SCL,
321 FN_ETH_RXD0, FN_AVB_PHY_INT, FN_I2C3_SDA, FN_IIC0_SDA,
322 FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
323 FN_I2C2_SCL_D, FN_MSIOF1_RXD_E,
324 FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, FN_I2C2_SDA_D, FN_MSIOF1_SCK_E,
325 FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
326 FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
327 FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
328 FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
329 FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
330 FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C,
331 FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C,
332 FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C,
333 FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
334 FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
335 FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
336 FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
339 FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
340 FN_ADICLK_B, FN_MSIOF0_SS1_C,
341 FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
342 FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
343 FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
344 FN_ADICHS2_B, FN_MSIOF0_TXD_C,
345 FN_SD0_CLK, FN_SPCLK_B, FN_SD0_CMD, FN_MOSI_IO0_B,
346 FN_SD0_DATA0, FN_MISO_IO1_B, FN_SD0_DATA1, FN_IO2_B,
347 FN_SD0_DATA2, FN_IO3_B, FN_SD0_DATA3, FN_SSL_B,
348 FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
349 FN_SCIFA5_TXD_B, FN_TX3_C,
350 FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
351 FN_SCIFA5_RXD_B, FN_RX3_C,
352 FN_SD1_CMD, FN_REMOCON_B, FN_SD1_DATA0, FN_SPEEDIN_B,
353 FN_SD1_DATA1, FN_IETX_B, FN_SD1_DATA2, FN_IECLK_B,
354 FN_SD1_DATA3, FN_IERX_B,
355 FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_I2C1_SCL_C,
358 FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C,
359 FN_SD2_CLK, FN_MMC_CLK, FN_SD2_CMD, FN_MMC_CMD,
360 FN_SD2_DATA0, FN_MMC_D0, FN_SD2_DATA1, FN_MMC_D1,
361 FN_SD2_DATA2, FN_MMC_D2, FN_SD2_DATA3, FN_MMC_D3,
362 FN_SD2_CD, FN_MMC_D4, FN_IIC1_SCL_C, FN_TX5_B, FN_SCIFA5_TXD_C,
363 FN_SD2_WP, FN_MMC_D5, FN_IIC1_SDA_C, FN_RX5_B, FN_SCIFA5_RXD_C,
364 FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, FN_VI1_CLK_C, FN_VI1_G0_B,
365 FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, FN_VI1_CLKENB_C, FN_VI1_G1_B,
366 FN_MSIOF0_TXD, FN_ADICLK, FN_VI1_FIELD_C, FN_VI1_G2_B,
367 FN_MSIOF0_RXD, FN_ADICHS0, FN_VI1_DATA0_C, FN_VI1_G3_B,
368 FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
369 FN_VI1_HSYNC_N_C, FN_IIC0_SCL_C, FN_VI1_G4_B,
370 FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
371 FN_VI1_VSYNC_N_C, FN_IIC0_SDA_C, FN_VI1_G5_B,
374 FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D,
375 FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C,
376 FN_SIM0_D, FN_IERX, FN_CAN1_RX_D,
377 FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
378 FN_PWM5_B, FN_SCIFA3_TXD_C,
379 FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
380 FN_VI1_G6_B, FN_SCIFA3_RXD_C,
381 FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
382 FN_VI1_G7_B, FN_SCIFA3_SCK_C,
383 FN_HCTS0_N, FN_SCIFB0_CTS_N, FN_GLO_I0_C, FN_TCLK1, FN_VI1_DATA1_C,
384 FN_HRTS0_N, FN_SCIFB0_RTS_N, FN_GLO_I1_C, FN_VI1_DATA2_C,
385 FN_HSCK0, FN_SCIFB0_SCK, FN_GLO_Q0_C, FN_CAN_CLK,
386 FN_TCLK2, FN_VI1_DATA3_C,
387 FN_HRX0, FN_SCIFB0_RXD, FN_GLO_Q1_C, FN_CAN0_RX_B, FN_VI1_DATA4_C,
388 FN_HTX0, FN_SCIFB0_TXD, FN_GLO_SCLK_C, FN_CAN0_TX_B, FN_VI1_DATA5_C,
391 FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B, FN_GLO_SDATA_C, FN_VI1_DATA6_C,
392 FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B, FN_GLO_SS_C, FN_VI1_DATA7_C,
393 FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CLK, FN_GLO_RFON_C,
394 FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
395 FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
398 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
399 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
400 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
401 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
402 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
403 FN_SEL_SSI9_0, FN_SEL_SSI9_1,
404 FN_SEL_SCFA_0, FN_SEL_SCFA_1,
405 FN_SEL_QSP_0, FN_SEL_QSP_1,
406 FN_SEL_SSI7_0, FN_SEL_SSI7_1,
407 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, FN_SEL_HSCIF1_3,
409 FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2,
410 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
411 FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
412 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
413 FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2,
416 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
418 FN_SEL_SCIF_0, FN_SEL_SCIF_1,
419 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
420 FN_SEL_CAN0_4, FN_SEL_CAN0_5,
421 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
422 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
423 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2,
424 FN_SEL_ADG_0, FN_SEL_ADG_1,
425 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, FN_SEL_FM_4,
426 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
427 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
428 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
429 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2,
430 FN_SEL_SIM_0, FN_SEL_SIM_1,
431 FN_SEL_SSI8_0, FN_SEL_SSI8_1,
434 FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
435 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
436 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2,
437 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2,
438 FN_SEL_I2C4_0, FN_SEL_I2C4_1, FN_SEL_I2C4_2,
439 FN_SEL_I2C3_0, FN_SEL_I2C3_1, FN_SEL_I2C3_2, FN_SEL_I2C3_3,
440 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
441 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
442 FN_SEL_MMC_0, FN_SEL_MMC_1,
443 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
444 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
445 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3,
447 FN_SEL_I2C0_0, FN_SEL_I2C0_1, FN_SEL_I2C0_2,
450 FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
452 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
453 FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2,
454 FN_SEL_RAD_0, FN_SEL_RAD_1,
455 FN_SEL_RCN_0, FN_SEL_RCN_1,
456 FN_SEL_RSP_0, FN_SEL_RSP_1,
457 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3,
459 FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, FN_SEL_SOF2_3,
461 FN_SEL_SSI1_0, FN_SEL_SSI1_1,
462 FN_SEL_SSI0_0, FN_SEL_SSI0_1,
463 FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2,
468 EX_CS0_N_MARK, RD_N_MARK,
472 VI0_CLK_MARK, VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
473 VI0_DATA2_VI0_B2_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
474 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
478 USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
482 D0_MARK, D1_MARK, D2_MARK, D3_MARK, D4_MARK, D5_MARK,
483 D6_MARK, D7_MARK, D8_MARK,
484 D9_MARK, D10_MARK, D11_MARK, D12_MARK, D13_MARK, D14_MARK, D15_MARK,
485 A0_MARK, ATAWR0_N_C_MARK, MSIOF0_SCK_B_MARK, I2C0_SCL_C_MARK,
487 A1_MARK, MSIOF0_SYNC_B_MARK, A2_MARK, MSIOF0_SS1_B_MARK,
488 A3_MARK, MSIOF0_SS2_B_MARK, A4_MARK, MSIOF0_TXD_B_MARK,
489 A5_MARK, MSIOF0_RXD_B_MARK, A6_MARK, MSIOF1_SCK_MARK,
492 A7_MARK, MSIOF1_SYNC_MARK, A8_MARK, MSIOF1_SS1_MARK, I2C0_SCL_MARK,
493 A9_MARK, MSIOF1_SS2_MARK, I2C0_SDA_MARK,
494 A10_MARK, MSIOF1_TXD_MARK, MSIOF1_TXD_D_MARK,
495 A11_MARK, MSIOF1_RXD_MARK, I2C3_SCL_D_MARK, MSIOF1_RXD_D_MARK,
496 A12_MARK, FMCLK_MARK, I2C3_SDA_D_MARK, MSIOF1_SCK_D_MARK,
497 A13_MARK, ATAG0_N_C_MARK, BPFCLK_MARK, MSIOF1_SS1_D_MARK,
498 A14_MARK, ATADIR0_N_C_MARK, FMIN_MARK, FMIN_C_MARK, MSIOF1_SYNC_D_MARK,
499 A15_MARK, BPFCLK_C_MARK,
500 A16_MARK, DREQ2_B_MARK, FMCLK_C_MARK, SCIFA1_SCK_B_MARK,
501 A17_MARK, DACK2_B_MARK, I2C0_SDA_C_MARK,
502 A18_MARK, DREQ1_MARK, SCIFA1_RXD_C_MARK, SCIFB1_RXD_C_MARK,
505 A19_MARK, DACK1_MARK, SCIFA1_TXD_C_MARK,
506 SCIFB1_TXD_C_MARK, SCIFB1_SCK_B_MARK,
507 A20_MARK, SPCLK_MARK,
508 A21_MARK, ATAWR0_N_B_MARK, MOSI_IO0_MARK,
509 A22_MARK, MISO_IO1_MARK, FMCLK_B_MARK, TX0_MARK, SCIFA0_TXD_MARK,
510 A23_MARK, IO2_MARK, BPFCLK_B_MARK, RX0_MARK, SCIFA0_RXD_MARK,
511 A24_MARK, DREQ2_MARK, IO3_MARK, TX1_MARK, SCIFA1_TXD_MARK,
512 A25_MARK, DACK2_MARK, SSL_MARK, DREQ1_C_MARK,
513 RX1_MARK, SCIFA1_RXD_MARK,
514 CS0_N_MARK, ATAG0_N_B_MARK, I2C1_SCL_MARK,
515 CS1_N_A26_MARK, ATADIR0_N_B_MARK, I2C1_SDA_MARK,
516 EX_CS1_N_MARK, MSIOF2_SCK_MARK,
517 EX_CS2_N_MARK, ATAWR0_N_MARK, MSIOF2_SYNC_MARK,
518 EX_CS3_N_MARK, ATADIR0_N_MARK, MSIOF2_TXD_MARK,
519 ATAG0_N_MARK, EX_WAIT1_MARK,
522 EX_CS4_N_MARK, ATARD0_N_MARK, MSIOF2_RXD_MARK, EX_WAIT2_MARK,
523 EX_CS5_N_MARK, ATACS00_N_MARK, MSIOF2_SS1_MARK, HRX1_B_MARK,
524 SCIFB1_RXD_B_MARK, PWM1_MARK, TPU_TO1_MARK,
525 BS_N_MARK, ATACS10_N_MARK, MSIOF2_SS2_MARK, HTX1_B_MARK,
526 SCIFB1_TXD_B_MARK, PWM2_MARK, TPU_TO2_MARK,
527 RD_WR_N_MARK, HRX2_B_MARK, FMIN_B_MARK,
528 SCIFB0_RXD_B_MARK, DREQ1_D_MARK,
529 WE0_N_MARK, HCTS2_N_B_MARK, SCIFB0_TXD_B_MARK,
530 WE1_N_MARK, ATARD0_N_B_MARK, HTX2_B_MARK, SCIFB0_RTS_N_B_MARK,
531 EX_WAIT0_MARK, HRTS2_N_B_MARK, SCIFB0_CTS_N_B_MARK,
532 DREQ0_MARK, PWM3_MARK, TPU_TO3_MARK,
533 DACK0_MARK, DRACK0_MARK, REMOCON_MARK,
534 SPEEDIN_MARK, HSCK0_C_MARK, HSCK2_C_MARK, SCIFB0_SCK_B_MARK,
535 SCIFB2_SCK_B_MARK, DREQ2_C_MARK, HTX2_D_MARK,
536 SSI_SCK0129_MARK, HRX0_C_MARK, HRX2_C_MARK,
537 SCIFB0_RXD_C_MARK, SCIFB2_RXD_C_MARK,
538 SSI_WS0129_MARK, HTX0_C_MARK, HTX2_C_MARK,
539 SCIFB0_TXD_C_MARK, SCIFB2_TXD_C_MARK,
542 SSI_SDATA0_MARK, I2C0_SCL_B_MARK, IIC0_SCL_B_MARK, MSIOF2_SCK_C_MARK,
543 SSI_SCK1_MARK, I2C0_SDA_B_MARK, IIC0_SDA_B_MARK,
544 MSIOF2_SYNC_C_MARK, GLO_I0_D_MARK,
545 SSI_WS1_MARK, I2C1_SCL_B_MARK, IIC1_SCL_B_MARK,
546 MSIOF2_TXD_C_MARK, GLO_I1_D_MARK,
547 SSI_SDATA1_MARK, I2C1_SDA_B_MARK, IIC1_SDA_B_MARK, MSIOF2_RXD_C_MARK,
548 SSI_SCK2_MARK, I2C2_SCL_MARK, GPS_CLK_B_MARK, GLO_Q0_D_MARK,
550 SSI_WS2_MARK, I2C2_SDA_MARK, GPS_SIGN_B_MARK, RX2_E_MARK,
551 GLO_Q1_D_MARK, HCTS1_N_E_MARK,
552 SSI_SDATA2_MARK, GPS_MAG_B_MARK, TX2_E_MARK, HRTS1_N_E_MARK,
553 SSI_SCK34_MARK, SSI_WS34_MARK, SSI_SDATA3_MARK,
554 SSI_SCK4_MARK, GLO_SS_D_MARK,
555 SSI_WS4_MARK, GLO_RFON_D_MARK,
556 SSI_SDATA4_MARK, MSIOF2_SCK_D_MARK,
557 SSI_SCK5_MARK, MSIOF1_SCK_C_MARK, TS_SDATA0_MARK, GLO_I0_MARK,
558 MSIOF2_SYNC_D_MARK, VI1_R2_B_MARK,
561 SSI_WS5_MARK, MSIOF1_SYNC_C_MARK, TS_SCK0_MARK, GLO_I1_MARK,
562 MSIOF2_TXD_D_MARK, VI1_R3_B_MARK,
563 SSI_SDATA5_MARK, MSIOF1_TXD_C_MARK, TS_SDEN0_MARK, GLO_Q0_MARK,
564 MSIOF2_SS1_D_MARK, VI1_R4_B_MARK,
565 SSI_SCK6_MARK, MSIOF1_RXD_C_MARK, TS_SPSYNC0_MARK, GLO_Q1_MARK,
566 MSIOF2_RXD_D_MARK, VI1_R5_B_MARK,
567 SSI_WS6_MARK, GLO_SCLK_MARK, MSIOF2_SS2_D_MARK, VI1_R6_B_MARK,
568 SSI_SDATA6_MARK, STP_IVCXO27_0_B_MARK, GLO_SDATA_MARK, VI1_R7_B_MARK,
569 SSI_SCK78_MARK, STP_ISCLK_0_B_MARK, GLO_SS_MARK,
570 SSI_WS78_MARK, TX0_D_MARK, STP_ISD_0_B_MARK, GLO_RFON_MARK,
571 SSI_SDATA7_MARK, RX0_D_MARK, STP_ISEN_0_B_MARK,
572 SSI_SDATA8_MARK, TX1_D_MARK, STP_ISSYNC_0_B_MARK,
573 SSI_SCK9_MARK, RX1_D_MARK, GLO_SCLK_D_MARK,
574 SSI_WS9_MARK, TX3_D_MARK, CAN0_TX_D_MARK, GLO_SDATA_D_MARK,
575 SSI_SDATA9_MARK, RX3_D_MARK, CAN0_RX_D_MARK,
578 AUDIO_CLKB_MARK, STP_OPWM_0_B_MARK, MSIOF1_SCK_B_MARK,
579 SCIF_CLK_MARK, DVC_MUTE_MARK, BPFCLK_E_MARK,
580 AUDIO_CLKC_MARK, SCIFB0_SCK_C_MARK, MSIOF1_SYNC_B_MARK, RX2_MARK,
581 SCIFA2_RXD_MARK, FMIN_E_MARK,
582 AUDIO_CLKOUT_MARK, MSIOF1_SS1_B_MARK, TX2_MARK, SCIFA2_TXD_MARK,
583 IRQ0_MARK, SCIFB1_RXD_D_MARK, INTC_IRQ0_N_MARK,
584 IRQ1_MARK, SCIFB1_SCK_C_MARK, INTC_IRQ1_N_MARK,
585 IRQ2_MARK, SCIFB1_TXD_D_MARK, INTC_IRQ2_N_MARK,
586 IRQ3_MARK, I2C4_SCL_C_MARK, MSIOF2_TXD_E_MARK, INTC_IRQ3_N_MARK,
587 IRQ4_MARK, HRX1_C_MARK, I2C4_SDA_C_MARK,
588 MSIOF2_RXD_E_MARK, INTC_IRQ4_N_MARK,
589 IRQ5_MARK, HTX1_C_MARK, I2C1_SCL_E_MARK, MSIOF2_SCK_E_MARK,
590 IRQ6_MARK, HSCK1_C_MARK, MSIOF1_SS2_B_MARK,
591 I2C1_SDA_E_MARK, MSIOF2_SYNC_E_MARK,
592 IRQ7_MARK, HCTS1_N_C_MARK, MSIOF1_TXD_B_MARK,
593 GPS_CLK_C_MARK, GPS_CLK_D_MARK,
594 IRQ8_MARK, HRTS1_N_C_MARK, MSIOF1_RXD_B_MARK,
595 GPS_SIGN_C_MARK, GPS_SIGN_D_MARK,
598 IRQ9_MARK, DU1_DOTCLKIN_B_MARK, CAN_CLK_D_MARK, GPS_MAG_C_MARK,
599 SCIF_CLK_B_MARK, GPS_MAG_D_MARK,
600 DU1_DR0_MARK, LCDOUT0_MARK, VI1_DATA0_B_MARK, TX0_B_MARK,
601 SCIFA0_TXD_B_MARK, MSIOF2_SCK_B_MARK,
602 DU1_DR1_MARK, LCDOUT1_MARK, VI1_DATA1_B_MARK, RX0_B_MARK,
603 SCIFA0_RXD_B_MARK, MSIOF2_SYNC_B_MARK,
604 DU1_DR2_MARK, LCDOUT2_MARK, SSI_SCK0129_B_MARK,
605 DU1_DR3_MARK, LCDOUT3_MARK, SSI_WS0129_B_MARK,
606 DU1_DR4_MARK, LCDOUT4_MARK, SSI_SDATA0_B_MARK,
607 DU1_DR5_MARK, LCDOUT5_MARK, SSI_SCK1_B_MARK,
608 DU1_DR6_MARK, LCDOUT6_MARK, SSI_WS1_B_MARK,
609 DU1_DR7_MARK, LCDOUT7_MARK, SSI_SDATA1_B_MARK,
610 DU1_DG0_MARK, LCDOUT8_MARK, VI1_DATA2_B_MARK, TX1_B_MARK,
611 SCIFA1_TXD_B_MARK, MSIOF2_SS1_B_MARK,
612 DU1_DG1_MARK, LCDOUT9_MARK, VI1_DATA3_B_MARK, RX1_B_MARK,
613 SCIFA1_RXD_B_MARK, MSIOF2_SS2_B_MARK,
614 DU1_DG2_MARK, LCDOUT10_MARK, VI1_DATA4_B_MARK, SCIF1_SCK_B_MARK,
615 SCIFA1_SCK_MARK, SSI_SCK78_B_MARK,
618 DU1_DG3_MARK, LCDOUT11_MARK, VI1_DATA5_B_MARK, SSI_WS78_B_MARK,
619 DU1_DG4_MARK, LCDOUT12_MARK, VI1_DATA6_B_MARK, HRX0_B_MARK,
620 SCIFB2_RXD_B_MARK, SSI_SDATA7_B_MARK,
621 DU1_DG5_MARK, LCDOUT13_MARK, VI1_DATA7_B_MARK, HCTS0_N_B_MARK,
622 SCIFB2_TXD_B_MARK, SSI_SDATA8_B_MARK,
623 DU1_DG6_MARK, LCDOUT14_MARK, HRTS0_N_B_MARK,
624 SCIFB2_CTS_N_B_MARK, SSI_SCK9_B_MARK,
625 DU1_DG7_MARK, LCDOUT15_MARK, HTX0_B_MARK,
626 SCIFB2_RTS_N_B_MARK, SSI_WS9_B_MARK,
627 DU1_DB0_MARK, LCDOUT16_MARK, VI1_CLK_B_MARK, TX2_B_MARK,
628 SCIFA2_TXD_B_MARK, MSIOF2_TXD_B_MARK,
629 DU1_DB1_MARK, LCDOUT17_MARK, VI1_HSYNC_N_B_MARK, RX2_B_MARK,
630 SCIFA2_RXD_B_MARK, MSIOF2_RXD_B_MARK,
631 DU1_DB2_MARK, LCDOUT18_MARK, VI1_VSYNC_N_B_MARK, SCIF2_SCK_B_MARK,
632 SCIFA2_SCK_MARK, SSI_SDATA9_B_MARK,
633 DU1_DB3_MARK, LCDOUT19_MARK, VI1_CLKENB_B_MARK,
634 DU1_DB4_MARK, LCDOUT20_MARK, VI1_FIELD_B_MARK, CAN1_RX_MARK,
635 DU1_DB5_MARK, LCDOUT21_MARK, TX3_MARK, SCIFA3_TXD_MARK, CAN1_TX_MARK,
638 DU1_DB6_MARK, LCDOUT22_MARK, I2C3_SCL_C_MARK, RX3_MARK, SCIFA3_RXD_MARK,
639 DU1_DB7_MARK, LCDOUT23_MARK, I2C3_SDA_C_MARK,
640 SCIF3_SCK_MARK, SCIFA3_SCK_MARK,
641 DU1_DOTCLKIN_MARK, QSTVA_QVS_MARK,
642 DU1_DOTCLKOUT0_MARK, QCLK_MARK,
643 DU1_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, CAN0_TX_MARK,
644 TX3_B_MARK, I2C2_SCL_B_MARK, PWM4_MARK,
645 DU1_EXHSYNC_DU1_HSYNC_MARK, QSTH_QHS_MARK,
646 DU1_EXVSYNC_DU1_VSYNC_MARK, QSTB_QHE_MARK,
647 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
648 CAN0_RX_MARK, RX3_B_MARK, I2C2_SDA_B_MARK,
649 DU1_DISP_MARK, QPOLA_MARK,
650 DU1_CDE_MARK, QPOLB_MARK, PWM4_B_MARK,
651 VI0_CLKENB_MARK, TX4_MARK, SCIFA4_TXD_MARK, TS_SDATA0_D_MARK,
652 VI0_FIELD_MARK, RX4_MARK, SCIFA4_RXD_MARK, TS_SCK0_D_MARK,
653 VI0_HSYNC_N_MARK, TX5_MARK, SCIFA5_TXD_MARK, TS_SDEN0_D_MARK,
654 VI0_VSYNC_N_MARK, RX5_MARK, SCIFA5_RXD_MARK, TS_SPSYNC0_D_MARK,
655 VI0_DATA3_VI0_B3_MARK, SCIF3_SCK_B_MARK, SCIFA3_SCK_B_MARK,
656 VI0_G0_MARK, IIC1_SCL_MARK, STP_IVCXO27_0_C_MARK, I2C4_SCL_MARK,
657 HCTS2_N_MARK, SCIFB2_CTS_N_MARK, ATAWR1_N_MARK,
660 VI0_G1_MARK, IIC1_SDA_MARK, STP_ISCLK_0_C_MARK, I2C4_SDA_MARK,
661 HRTS2_N_MARK, SCIFB2_RTS_N_MARK, ATADIR1_N_MARK,
662 VI0_G2_MARK, VI2_HSYNC_N_MARK, STP_ISD_0_C_MARK, I2C3_SCL_B_MARK,
663 HSCK2_MARK, SCIFB2_SCK_MARK, ATARD1_N_MARK,
664 VI0_G3_MARK, VI2_VSYNC_N_MARK, STP_ISEN_0_C_MARK, I2C3_SDA_B_MARK,
665 HRX2_MARK, SCIFB2_RXD_MARK, ATACS01_N_MARK,
666 VI0_G4_MARK, VI2_CLKENB_MARK, STP_ISSYNC_0_C_MARK,
667 HTX2_MARK, SCIFB2_TXD_MARK, SCIFB0_SCK_D_MARK,
668 VI0_G5_MARK, VI2_FIELD_MARK, STP_OPWM_0_C_MARK, FMCLK_D_MARK,
669 CAN0_TX_E_MARK, HTX1_D_MARK, SCIFB0_TXD_D_MARK,
670 VI0_G6_MARK, VI2_CLK_MARK, BPFCLK_D_MARK,
671 VI0_G7_MARK, VI2_DATA0_MARK, FMIN_D_MARK,
672 VI0_R0_MARK, VI2_DATA1_MARK, GLO_I0_B_MARK,
673 TS_SDATA0_C_MARK, ATACS11_N_MARK,
674 VI0_R1_MARK, VI2_DATA2_MARK, GLO_I1_B_MARK,
675 TS_SCK0_C_MARK, ATAG1_N_MARK,
676 VI0_R2_MARK, VI2_DATA3_MARK, GLO_Q0_B_MARK, TS_SDEN0_C_MARK,
677 VI0_R3_MARK, VI2_DATA4_MARK, GLO_Q1_B_MARK, TS_SPSYNC0_C_MARK,
678 VI0_R4_MARK, VI2_DATA5_MARK, GLO_SCLK_B_MARK, TX0_C_MARK,
682 VI0_R5_MARK, VI2_DATA6_MARK, GLO_SDATA_B_MARK, RX0_C_MARK,
684 VI0_R6_MARK, VI2_DATA7_MARK, GLO_SS_B_MARK, TX1_C_MARK, I2C4_SCL_B_MARK,
685 VI0_R7_MARK, GLO_RFON_B_MARK, RX1_C_MARK, CAN0_RX_E_MARK,
686 I2C4_SDA_B_MARK, HRX1_D_MARK, SCIFB0_RXD_D_MARK,
687 VI1_HSYNC_N_MARK, AVB_RXD0_MARK, TS_SDATA0_B_MARK,
688 TX4_B_MARK, SCIFA4_TXD_B_MARK,
689 VI1_VSYNC_N_MARK, AVB_RXD1_MARK, TS_SCK0_B_MARK,
690 RX4_B_MARK, SCIFA4_RXD_B_MARK,
691 VI1_CLKENB_MARK, AVB_RXD2_MARK, TS_SDEN0_B_MARK,
692 VI1_FIELD_MARK, AVB_RXD3_MARK, TS_SPSYNC0_B_MARK,
693 VI1_CLK_MARK, AVB_RXD4_MARK, VI1_DATA0_MARK, AVB_RXD5_MARK,
694 VI1_DATA1_MARK, AVB_RXD6_MARK, VI1_DATA2_MARK, AVB_RXD7_MARK,
695 VI1_DATA3_MARK, AVB_RX_ER_MARK, VI1_DATA4_MARK, AVB_MDIO_MARK,
696 VI1_DATA5_MARK, AVB_RX_DV_MARK, VI1_DATA6_MARK, AVB_MAGIC_MARK,
697 VI1_DATA7_MARK, AVB_MDC_MARK,
698 ETH_MDIO_MARK, AVB_RX_CLK_MARK, I2C2_SCL_C_MARK,
699 ETH_CRS_DV_MARK, AVB_LINK_MARK, I2C2_SDA_C_MARK,
702 ETH_RX_ER_MARK, AVB_CRS_MARK, I2C3_SCL_MARK, IIC0_SCL_MARK,
703 ETH_RXD0_MARK, AVB_PHY_INT_MARK, I2C3_SDA_MARK, IIC0_SDA_MARK,
704 ETH_RXD1_MARK, AVB_GTXREFCLK_MARK, CAN0_TX_C_MARK,
705 I2C2_SCL_D_MARK, MSIOF1_RXD_E_MARK,
706 ETH_LINK_MARK, AVB_TXD0_MARK, CAN0_RX_C_MARK,
707 I2C2_SDA_D_MARK, MSIOF1_SCK_E_MARK,
708 ETH_REFCLK_MARK, AVB_TXD1_MARK, SCIFA3_RXD_B_MARK,
709 CAN1_RX_C_MARK, MSIOF1_SYNC_E_MARK,
710 ETH_TXD1_MARK, AVB_TXD2_MARK, SCIFA3_TXD_B_MARK,
711 CAN1_TX_C_MARK, MSIOF1_TXD_E_MARK,
712 ETH_TX_EN_MARK, AVB_TXD3_MARK, TCLK1_B_MARK, CAN_CLK_B_MARK,
713 ETH_MAGIC_MARK, AVB_TXD4_MARK, IETX_C_MARK,
714 ETH_TXD0_MARK, AVB_TXD5_MARK, IECLK_C_MARK,
715 ETH_MDC_MARK, AVB_TXD6_MARK, IERX_C_MARK,
716 STP_IVCXO27_0_MARK, AVB_TXD7_MARK, SCIFB2_TXD_D_MARK,
717 ADIDATA_B_MARK, MSIOF0_SYNC_C_MARK,
718 STP_ISCLK_0_MARK, AVB_TX_EN_MARK, SCIFB2_RXD_D_MARK,
719 ADICS_SAMP_B_MARK, MSIOF0_SCK_C_MARK,
722 STP_ISD_0_MARK, AVB_TX_ER_MARK, SCIFB2_SCK_C_MARK,
723 ADICLK_B_MARK, MSIOF0_SS1_C_MARK,
724 STP_ISEN_0_MARK, AVB_TX_CLK_MARK, ADICHS0_B_MARK, MSIOF0_SS2_C_MARK,
725 STP_ISSYNC_0_MARK, AVB_COL_MARK, ADICHS1_B_MARK, MSIOF0_RXD_C_MARK,
726 STP_OPWM_0_MARK, AVB_GTX_CLK_MARK, PWM0_B_MARK,
727 ADICHS2_B_MARK, MSIOF0_TXD_C_MARK,
728 SD0_CLK_MARK, SPCLK_B_MARK, SD0_CMD_MARK, MOSI_IO0_B_MARK,
729 SD0_DATA0_MARK, MISO_IO1_B_MARK, SD0_DATA1_MARK, IO2_B_MARK,
730 SD0_DATA2_MARK, IO3_B_MARK, SD0_DATA3_MARK, SSL_B_MARK,
731 SD0_CD_MARK, MMC_D6_B_MARK, SIM0_RST_B_MARK, CAN0_RX_F_MARK,
732 SCIFA5_TXD_B_MARK, TX3_C_MARK,
733 SD0_WP_MARK, MMC_D7_B_MARK, SIM0_D_B_MARK, CAN0_TX_F_MARK,
734 SCIFA5_RXD_B_MARK, RX3_C_MARK,
735 SD1_CMD_MARK, REMOCON_B_MARK, SD1_DATA0_MARK, SPEEDIN_B_MARK,
736 SD1_DATA1_MARK, IETX_B_MARK, SD1_DATA2_MARK, IECLK_B_MARK,
737 SD1_DATA3_MARK, IERX_B_MARK,
738 SD1_CD_MARK, PWM0_MARK, TPU_TO0_MARK, I2C1_SCL_C_MARK,
741 SD1_WP_MARK, PWM1_B_MARK, I2C1_SDA_C_MARK,
742 SD2_CLK_MARK, MMC_CLK_MARK, SD2_CMD_MARK, MMC_CMD_MARK,
743 SD2_DATA0_MARK, MMC_D0_MARK, SD2_DATA1_MARK, MMC_D1_MARK,
744 SD2_DATA2_MARK, MMC_D2_MARK, SD2_DATA3_MARK, MMC_D3_MARK,
745 SD2_CD_MARK, MMC_D4_MARK, IIC1_SCL_C_MARK, TX5_B_MARK,
747 SD2_WP_MARK, MMC_D5_MARK, IIC1_SDA_C_MARK, RX5_B_MARK,
749 MSIOF0_SCK_MARK, RX2_C_MARK, ADIDATA_MARK,
750 VI1_CLK_C_MARK, VI1_G0_B_MARK,
751 MSIOF0_SYNC_MARK, TX2_C_MARK, ADICS_SAMP_MARK,
752 VI1_CLKENB_C_MARK, VI1_G1_B_MARK,
753 MSIOF0_TXD_MARK, ADICLK_MARK, VI1_FIELD_C_MARK, VI1_G2_B_MARK,
754 MSIOF0_RXD_MARK, ADICHS0_MARK, VI1_DATA0_C_MARK, VI1_G3_B_MARK,
755 MSIOF0_SS1_MARK, MMC_D6_MARK, ADICHS1_MARK, TX0_E_MARK,
756 VI1_HSYNC_N_C_MARK, IIC0_SCL_C_MARK, VI1_G4_B_MARK,
757 MSIOF0_SS2_MARK, MMC_D7_MARK, ADICHS2_MARK, RX0_E_MARK,
758 VI1_VSYNC_N_C_MARK, IIC0_SDA_C_MARK, VI1_G5_B_MARK,
761 SIM0_RST_MARK, IETX_MARK, CAN1_TX_D_MARK,
762 SIM0_CLK_MARK, IECLK_MARK, CAN_CLK_C_MARK,
763 SIM0_D_MARK, IERX_MARK, CAN1_RX_D_MARK,
764 GPS_CLK_MARK, DU1_DOTCLKIN_C_MARK, AUDIO_CLKB_B_MARK,
765 PWM5_B_MARK, SCIFA3_TXD_C_MARK,
766 GPS_SIGN_MARK, TX4_C_MARK, SCIFA4_TXD_C_MARK, PWM5_MARK,
767 VI1_G6_B_MARK, SCIFA3_RXD_C_MARK,
768 GPS_MAG_MARK, RX4_C_MARK, SCIFA4_RXD_C_MARK, PWM6_MARK,
769 VI1_G7_B_MARK, SCIFA3_SCK_C_MARK,
770 HCTS0_N_MARK, SCIFB0_CTS_N_MARK, GLO_I0_C_MARK,
771 TCLK1_MARK, VI1_DATA1_C_MARK,
772 HRTS0_N_MARK, SCIFB0_RTS_N_MARK, GLO_I1_C_MARK, VI1_DATA2_C_MARK,
773 HSCK0_MARK, SCIFB0_SCK_MARK, GLO_Q0_C_MARK, CAN_CLK_MARK,
774 TCLK2_MARK, VI1_DATA3_C_MARK,
775 HRX0_MARK, SCIFB0_RXD_MARK, GLO_Q1_C_MARK,
776 CAN0_RX_B_MARK, VI1_DATA4_C_MARK,
777 HTX0_MARK, SCIFB0_TXD_MARK, GLO_SCLK_C_MARK,
778 CAN0_TX_B_MARK, VI1_DATA5_C_MARK,
781 HRX1_MARK, SCIFB1_RXD_MARK, VI1_R0_B_MARK,
782 GLO_SDATA_C_MARK, VI1_DATA6_C_MARK,
783 HTX1_MARK, SCIFB1_TXD_MARK, VI1_R1_B_MARK,
784 GLO_SS_C_MARK, VI1_DATA7_C_MARK,
785 HSCK1_MARK, SCIFB1_SCK_MARK, MLB_CLK_MARK, GLO_RFON_C_MARK,
786 HCTS1_N_MARK, SCIFB1_CTS_N_MARK, MLB_SIG_MARK, CAN1_TX_B_MARK,
787 HRTS1_N_MARK, SCIFB1_RTS_N_MARK, MLB_DAT_MARK, CAN1_RX_B_MARK,
791 static const u16 pinmux_data[] = {
792 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
794 PINMUX_SINGLE(EX_CS0_N),
796 PINMUX_SINGLE(AUDIO_CLKA),
797 PINMUX_SINGLE(VI0_CLK),
798 PINMUX_SINGLE(VI0_DATA0_VI0_B0),
799 PINMUX_SINGLE(VI0_DATA1_VI0_B1),
800 PINMUX_SINGLE(VI0_DATA2_VI0_B2),
801 PINMUX_SINGLE(VI0_DATA4_VI0_B4),
802 PINMUX_SINGLE(VI0_DATA5_VI0_B5),
803 PINMUX_SINGLE(VI0_DATA6_VI0_B6),
804 PINMUX_SINGLE(VI0_DATA7_VI0_B7),
805 PINMUX_SINGLE(USB0_PWEN),
806 PINMUX_SINGLE(USB0_OVC),
807 PINMUX_SINGLE(USB1_PWEN),
808 PINMUX_SINGLE(USB1_OVC),
809 PINMUX_SINGLE(DU0_DOTCLKIN),
810 PINMUX_SINGLE(SD1_CLK),
813 PINMUX_IPSR_GPSR(IP0_0, D0),
814 PINMUX_IPSR_GPSR(IP0_1, D1),
815 PINMUX_IPSR_GPSR(IP0_2, D2),
816 PINMUX_IPSR_GPSR(IP0_3, D3),
817 PINMUX_IPSR_GPSR(IP0_4, D4),
818 PINMUX_IPSR_GPSR(IP0_5, D5),
819 PINMUX_IPSR_GPSR(IP0_6, D6),
820 PINMUX_IPSR_GPSR(IP0_7, D7),
821 PINMUX_IPSR_GPSR(IP0_8, D8),
822 PINMUX_IPSR_GPSR(IP0_9, D9),
823 PINMUX_IPSR_GPSR(IP0_10, D10),
824 PINMUX_IPSR_GPSR(IP0_11, D11),
825 PINMUX_IPSR_GPSR(IP0_12, D12),
826 PINMUX_IPSR_GPSR(IP0_13, D13),
827 PINMUX_IPSR_GPSR(IP0_14, D14),
828 PINMUX_IPSR_GPSR(IP0_15, D15),
829 PINMUX_IPSR_GPSR(IP0_18_16, A0),
830 PINMUX_IPSR_MSEL(IP0_18_16, ATAWR0_N_C, SEL_LBS_2),
831 PINMUX_IPSR_MSEL(IP0_18_16, MSIOF0_SCK_B, SEL_SOF0_1),
832 PINMUX_IPSR_MSEL(IP0_18_16, I2C0_SCL_C, SEL_I2C0_2),
833 PINMUX_IPSR_GPSR(IP0_18_16, PWM2_B),
834 PINMUX_IPSR_GPSR(IP0_20_19, A1),
835 PINMUX_IPSR_MSEL(IP0_20_19, MSIOF0_SYNC_B, SEL_SOF0_1),
836 PINMUX_IPSR_GPSR(IP0_22_21, A2),
837 PINMUX_IPSR_MSEL(IP0_22_21, MSIOF0_SS1_B, SEL_SOF0_1),
838 PINMUX_IPSR_GPSR(IP0_24_23, A3),
839 PINMUX_IPSR_MSEL(IP0_24_23, MSIOF0_SS2_B, SEL_SOF0_1),
840 PINMUX_IPSR_GPSR(IP0_26_25, A4),
841 PINMUX_IPSR_MSEL(IP0_26_25, MSIOF0_TXD_B, SEL_SOF0_1),
842 PINMUX_IPSR_GPSR(IP0_28_27, A5),
843 PINMUX_IPSR_MSEL(IP0_28_27, MSIOF0_RXD_B, SEL_SOF0_1),
844 PINMUX_IPSR_GPSR(IP0_30_29, A6),
845 PINMUX_IPSR_MSEL(IP0_30_29, MSIOF1_SCK, SEL_SOF1_0),
848 PINMUX_IPSR_GPSR(IP1_1_0, A7),
849 PINMUX_IPSR_MSEL(IP1_1_0, MSIOF1_SYNC, SEL_SOF1_0),
850 PINMUX_IPSR_GPSR(IP1_3_2, A8),
851 PINMUX_IPSR_MSEL(IP1_3_2, MSIOF1_SS1, SEL_SOF1_0),
852 PINMUX_IPSR_MSEL(IP1_3_2, I2C0_SCL, SEL_I2C0_0),
853 PINMUX_IPSR_GPSR(IP1_5_4, A9),
854 PINMUX_IPSR_MSEL(IP1_5_4, MSIOF1_SS2, SEL_SOF1_0),
855 PINMUX_IPSR_MSEL(IP1_5_4, I2C0_SDA, SEL_I2C0_0),
856 PINMUX_IPSR_GPSR(IP1_7_6, A10),
857 PINMUX_IPSR_MSEL(IP1_7_6, MSIOF1_TXD, SEL_SOF1_0),
858 PINMUX_IPSR_MSEL(IP1_7_6, MSIOF1_TXD_D, SEL_SOF1_3),
859 PINMUX_IPSR_GPSR(IP1_10_8, A11),
860 PINMUX_IPSR_MSEL(IP1_10_8, MSIOF1_RXD, SEL_SOF1_0),
861 PINMUX_IPSR_MSEL(IP1_10_8, I2C3_SCL_D, SEL_I2C3_3),
862 PINMUX_IPSR_MSEL(IP1_10_8, MSIOF1_RXD_D, SEL_SOF1_3),
863 PINMUX_IPSR_GPSR(IP1_13_11, A12),
864 PINMUX_IPSR_MSEL(IP1_13_11, FMCLK, SEL_FM_0),
865 PINMUX_IPSR_MSEL(IP1_13_11, I2C3_SDA_D, SEL_I2C3_3),
866 PINMUX_IPSR_MSEL(IP1_13_11, MSIOF1_SCK_D, SEL_SOF1_3),
867 PINMUX_IPSR_GPSR(IP1_16_14, A13),
868 PINMUX_IPSR_MSEL(IP1_16_14, ATAG0_N_C, SEL_LBS_2),
869 PINMUX_IPSR_MSEL(IP1_16_14, BPFCLK, SEL_FM_0),
870 PINMUX_IPSR_MSEL(IP1_16_14, MSIOF1_SS1_D, SEL_SOF1_3),
871 PINMUX_IPSR_GPSR(IP1_19_17, A14),
872 PINMUX_IPSR_MSEL(IP1_19_17, ATADIR0_N_C, SEL_LBS_2),
873 PINMUX_IPSR_MSEL(IP1_19_17, FMIN, SEL_FM_0),
874 PINMUX_IPSR_MSEL(IP1_19_17, FMIN_C, SEL_FM_2),
875 PINMUX_IPSR_MSEL(IP1_19_17, MSIOF1_SYNC_D, SEL_SOF1_3),
876 PINMUX_IPSR_GPSR(IP1_22_20, A15),
877 PINMUX_IPSR_MSEL(IP1_22_20, BPFCLK_C, SEL_FM_2),
878 PINMUX_IPSR_GPSR(IP1_25_23, A16),
879 PINMUX_IPSR_MSEL(IP1_25_23, DREQ2_B, SEL_LBS_1),
880 PINMUX_IPSR_MSEL(IP1_25_23, FMCLK_C, SEL_FM_2),
881 PINMUX_IPSR_MSEL(IP1_25_23, SCIFA1_SCK_B, SEL_SCIFA1_1),
882 PINMUX_IPSR_GPSR(IP1_28_26, A17),
883 PINMUX_IPSR_MSEL(IP1_28_26, DACK2_B, SEL_LBS_1),
884 PINMUX_IPSR_MSEL(IP1_28_26, I2C0_SDA_C, SEL_I2C0_2),
885 PINMUX_IPSR_GPSR(IP1_31_29, A18),
886 PINMUX_IPSR_MSEL(IP1_31_29, DREQ1, SEL_LBS_0),
887 PINMUX_IPSR_MSEL(IP1_31_29, SCIFA1_RXD_C, SEL_SCIFA1_2),
888 PINMUX_IPSR_MSEL(IP1_31_29, SCIFB1_RXD_C, SEL_SCIFB1_2),
891 PINMUX_IPSR_GPSR(IP2_2_0, A19),
892 PINMUX_IPSR_GPSR(IP2_2_0, DACK1),
893 PINMUX_IPSR_MSEL(IP2_2_0, SCIFA1_TXD_C, SEL_SCIFA1_2),
894 PINMUX_IPSR_MSEL(IP2_2_0, SCIFB1_TXD_C, SEL_SCIFB1_2),
895 PINMUX_IPSR_MSEL(IP2_2_0, SCIFB1_SCK_B, SEL_SCIFB1_1),
896 PINMUX_IPSR_GPSR(IP2_2_0, A20),
897 PINMUX_IPSR_MSEL(IP2_4_3, SPCLK, SEL_QSP_0),
898 PINMUX_IPSR_GPSR(IP2_6_5, A21),
899 PINMUX_IPSR_MSEL(IP2_6_5, ATAWR0_N_B, SEL_LBS_1),
900 PINMUX_IPSR_MSEL(IP2_6_5, MOSI_IO0, SEL_QSP_0),
901 PINMUX_IPSR_GPSR(IP2_9_7, A22),
902 PINMUX_IPSR_MSEL(IP2_9_7, MISO_IO1, SEL_QSP_0),
903 PINMUX_IPSR_MSEL(IP2_9_7, FMCLK_B, SEL_FM_1),
904 PINMUX_IPSR_MSEL(IP2_9_7, TX0, SEL_SCIF0_0),
905 PINMUX_IPSR_MSEL(IP2_9_7, SCIFA0_TXD, SEL_SCFA_0),
906 PINMUX_IPSR_GPSR(IP2_12_10, A23),
907 PINMUX_IPSR_MSEL(IP2_12_10, IO2, SEL_QSP_0),
908 PINMUX_IPSR_MSEL(IP2_12_10, BPFCLK_B, SEL_FM_1),
909 PINMUX_IPSR_MSEL(IP2_12_10, RX0, SEL_SCIF0_0),
910 PINMUX_IPSR_MSEL(IP2_12_10, SCIFA0_RXD, SEL_SCFA_0),
911 PINMUX_IPSR_GPSR(IP2_15_13, A24),
912 PINMUX_IPSR_MSEL(IP2_15_13, DREQ2, SEL_LBS_0),
913 PINMUX_IPSR_MSEL(IP2_15_13, IO3, SEL_QSP_0),
914 PINMUX_IPSR_MSEL(IP2_15_13, TX1, SEL_SCIF1_0),
915 PINMUX_IPSR_MSEL(IP2_15_13, SCIFA1_TXD, SEL_SCIFA1_0),
916 PINMUX_IPSR_GPSR(IP2_18_16, A25),
917 PINMUX_IPSR_MSEL(IP2_18_16, DACK2, SEL_LBS_0),
918 PINMUX_IPSR_MSEL(IP2_18_16, SSL, SEL_QSP_0),
919 PINMUX_IPSR_MSEL(IP2_18_16, DREQ1_C, SEL_LBS_2),
920 PINMUX_IPSR_MSEL(IP2_18_16, RX1, SEL_SCIF1_0),
921 PINMUX_IPSR_MSEL(IP2_18_16, SCIFA1_RXD, SEL_SCIFA1_0),
922 PINMUX_IPSR_GPSR(IP2_20_19, CS0_N),
923 PINMUX_IPSR_MSEL(IP2_20_19, ATAG0_N_B, SEL_LBS_1),
924 PINMUX_IPSR_MSEL(IP2_20_19, I2C1_SCL, SEL_I2C1_0),
925 PINMUX_IPSR_GPSR(IP2_22_21, CS1_N_A26),
926 PINMUX_IPSR_MSEL(IP2_22_21, ATADIR0_N_B, SEL_LBS_1),
927 PINMUX_IPSR_MSEL(IP2_22_21, I2C1_SDA, SEL_I2C1_0),
928 PINMUX_IPSR_GPSR(IP2_24_23, EX_CS1_N),
929 PINMUX_IPSR_MSEL(IP2_24_23, MSIOF2_SCK, SEL_SOF2_0),
930 PINMUX_IPSR_GPSR(IP2_26_25, EX_CS2_N),
931 PINMUX_IPSR_MSEL(IP2_26_25, ATAWR0_N, SEL_LBS_0),
932 PINMUX_IPSR_MSEL(IP2_26_25, MSIOF2_SYNC, SEL_SOF2_0),
933 PINMUX_IPSR_GPSR(IP2_29_27, EX_CS3_N),
934 PINMUX_IPSR_MSEL(IP2_29_27, ATADIR0_N, SEL_LBS_0),
935 PINMUX_IPSR_MSEL(IP2_29_27, MSIOF2_TXD, SEL_SOF2_0),
936 PINMUX_IPSR_MSEL(IP2_29_27, ATAG0_N, SEL_LBS_0),
937 PINMUX_IPSR_GPSR(IP2_29_27, EX_WAIT1),
940 PINMUX_IPSR_GPSR(IP3_2_0, EX_CS4_N),
941 PINMUX_IPSR_MSEL(IP3_2_0, ATARD0_N, SEL_LBS_0),
942 PINMUX_IPSR_MSEL(IP3_2_0, MSIOF2_RXD, SEL_SOF2_0),
943 PINMUX_IPSR_GPSR(IP3_2_0, EX_WAIT2),
944 PINMUX_IPSR_GPSR(IP3_5_3, EX_CS5_N),
945 PINMUX_IPSR_GPSR(IP3_5_3, ATACS00_N),
946 PINMUX_IPSR_MSEL(IP3_5_3, MSIOF2_SS1, SEL_SOF2_0),
947 PINMUX_IPSR_MSEL(IP3_5_3, HRX1_B, SEL_HSCIF1_1),
948 PINMUX_IPSR_MSEL(IP3_5_3, SCIFB1_RXD_B, SEL_SCIFB1_1),
949 PINMUX_IPSR_GPSR(IP3_5_3, PWM1),
950 PINMUX_IPSR_GPSR(IP3_5_3, TPU_TO1),
951 PINMUX_IPSR_GPSR(IP3_8_6, BS_N),
952 PINMUX_IPSR_GPSR(IP3_8_6, ATACS10_N),
953 PINMUX_IPSR_MSEL(IP3_8_6, MSIOF2_SS2, SEL_SOF2_0),
954 PINMUX_IPSR_MSEL(IP3_8_6, HTX1_B, SEL_HSCIF1_1),
955 PINMUX_IPSR_MSEL(IP3_8_6, SCIFB1_TXD_B, SEL_SCIFB1_1),
956 PINMUX_IPSR_GPSR(IP3_8_6, PWM2),
957 PINMUX_IPSR_GPSR(IP3_8_6, TPU_TO2),
958 PINMUX_IPSR_GPSR(IP3_11_9, RD_WR_N),
959 PINMUX_IPSR_MSEL(IP3_11_9, HRX2_B, SEL_HSCIF2_1),
960 PINMUX_IPSR_MSEL(IP3_11_9, FMIN_B, SEL_FM_1),
961 PINMUX_IPSR_MSEL(IP3_11_9, SCIFB0_RXD_B, SEL_SCIFB_1),
962 PINMUX_IPSR_MSEL(IP3_11_9, DREQ1_D, SEL_LBS_1),
963 PINMUX_IPSR_GPSR(IP3_13_12, WE0_N),
964 PINMUX_IPSR_MSEL(IP3_13_12, HCTS2_N_B, SEL_HSCIF2_1),
965 PINMUX_IPSR_MSEL(IP3_13_12, SCIFB0_TXD_B, SEL_SCIFB_1),
966 PINMUX_IPSR_GPSR(IP3_15_14, WE1_N),
967 PINMUX_IPSR_MSEL(IP3_15_14, ATARD0_N_B, SEL_LBS_1),
968 PINMUX_IPSR_MSEL(IP3_15_14, HTX2_B, SEL_HSCIF2_1),
969 PINMUX_IPSR_MSEL(IP3_15_14, SCIFB0_RTS_N_B, SEL_SCIFB_1),
970 PINMUX_IPSR_GPSR(IP3_17_16, EX_WAIT0),
971 PINMUX_IPSR_MSEL(IP3_17_16, HRTS2_N_B, SEL_HSCIF2_1),
972 PINMUX_IPSR_MSEL(IP3_17_16, SCIFB0_CTS_N_B, SEL_SCIFB_1),
973 PINMUX_IPSR_GPSR(IP3_19_18, DREQ0),
974 PINMUX_IPSR_GPSR(IP3_19_18, PWM3),
975 PINMUX_IPSR_GPSR(IP3_19_18, TPU_TO3),
976 PINMUX_IPSR_GPSR(IP3_21_20, DACK0),
977 PINMUX_IPSR_GPSR(IP3_21_20, DRACK0),
978 PINMUX_IPSR_MSEL(IP3_21_20, REMOCON, SEL_RCN_0),
979 PINMUX_IPSR_MSEL(IP3_24_22, SPEEDIN, SEL_RSP_0),
980 PINMUX_IPSR_MSEL(IP3_24_22, HSCK0_C, SEL_HSCIF0_2),
981 PINMUX_IPSR_MSEL(IP3_24_22, HSCK2_C, SEL_HSCIF2_2),
982 PINMUX_IPSR_MSEL(IP3_24_22, SCIFB0_SCK_B, SEL_SCIFB_1),
983 PINMUX_IPSR_MSEL(IP3_24_22, SCIFB2_SCK_B, SEL_SCIFB2_1),
984 PINMUX_IPSR_MSEL(IP3_24_22, DREQ2_C, SEL_LBS_2),
985 PINMUX_IPSR_MSEL(IP3_30_28, HTX2_C, SEL_HSCIF2_2),
986 PINMUX_IPSR_MSEL(IP3_27_25, SSI_SCK0129, SEL_SSI0_0),
987 PINMUX_IPSR_MSEL(IP3_27_25, HRX0_C, SEL_HSCIF0_2),
988 PINMUX_IPSR_MSEL(IP3_27_25, HRX2_C, SEL_HSCIF2_2),
989 PINMUX_IPSR_MSEL(IP3_27_25, SCIFB0_RXD_C, SEL_SCIFB_2),
990 PINMUX_IPSR_MSEL(IP3_27_25, SCIFB2_RXD_C, SEL_SCIFB2_2),
991 PINMUX_IPSR_MSEL(IP3_30_28, SSI_WS0129, SEL_SSI0_0),
992 PINMUX_IPSR_MSEL(IP3_30_28, HTX0_C, SEL_HSCIF0_2),
993 PINMUX_IPSR_MSEL(IP3_30_28, HTX2_C, SEL_HSCIF2_2),
994 PINMUX_IPSR_MSEL(IP3_30_28, SCIFB0_TXD_C, SEL_SCIFB_2),
995 PINMUX_IPSR_MSEL(IP3_30_28, SCIFB2_TXD_C, SEL_SCIFB2_2),
998 PINMUX_IPSR_MSEL(IP4_1_0, SSI_SDATA0, SEL_SSI0_0),
999 PINMUX_IPSR_MSEL(IP4_1_0, I2C0_SCL_B, SEL_I2C0_1),
1000 PINMUX_IPSR_MSEL(IP4_1_0, IIC0_SCL_B, SEL_IIC0_1),
1001 PINMUX_IPSR_MSEL(IP4_1_0, MSIOF2_SCK_C, SEL_SOF2_2),
1002 PINMUX_IPSR_MSEL(IP4_4_2, SSI_SCK1, SEL_SSI1_0),
1003 PINMUX_IPSR_MSEL(IP4_4_2, I2C0_SDA_B, SEL_I2C0_1),
1004 PINMUX_IPSR_MSEL(IP4_4_2, IIC0_SDA_B, SEL_IIC0_1),
1005 PINMUX_IPSR_MSEL(IP4_4_2, MSIOF2_SYNC_C, SEL_SOF2_2),
1006 PINMUX_IPSR_MSEL(IP4_4_2, GLO_I0_D, SEL_GPS_3),
1007 PINMUX_IPSR_MSEL(IP4_7_5, SSI_WS1, SEL_SSI1_0),
1008 PINMUX_IPSR_MSEL(IP4_7_5, I2C1_SCL_B, SEL_I2C1_1),
1009 PINMUX_IPSR_MSEL(IP4_7_5, IIC1_SCL_B, SEL_IIC1_1),
1010 PINMUX_IPSR_MSEL(IP4_7_5, MSIOF2_TXD_C, SEL_SOF2_2),
1011 PINMUX_IPSR_MSEL(IP4_7_5, GLO_I1_D, SEL_GPS_3),
1012 PINMUX_IPSR_MSEL(IP4_9_8, SSI_SDATA1, SEL_SSI1_0),
1013 PINMUX_IPSR_MSEL(IP4_9_8, I2C1_SDA_B, SEL_I2C1_1),
1014 PINMUX_IPSR_MSEL(IP4_9_8, IIC1_SDA_B, SEL_IIC1_1),
1015 PINMUX_IPSR_MSEL(IP4_9_8, MSIOF2_RXD_C, SEL_SOF2_2),
1016 PINMUX_IPSR_GPSR(IP4_12_10, SSI_SCK2),
1017 PINMUX_IPSR_MSEL(IP4_12_10, I2C2_SCL, SEL_I2C2_0),
1018 PINMUX_IPSR_MSEL(IP4_12_10, GPS_CLK_B, SEL_GPS_1),
1019 PINMUX_IPSR_MSEL(IP4_12_10, GLO_Q0_D, SEL_GPS_3),
1020 PINMUX_IPSR_MSEL(IP4_12_10, HSCK1_E, SEL_HSCIF1_4),
1021 PINMUX_IPSR_GPSR(IP4_15_13, SSI_WS2),
1022 PINMUX_IPSR_MSEL(IP4_15_13, I2C2_SDA, SEL_I2C2_0),
1023 PINMUX_IPSR_MSEL(IP4_15_13, GPS_SIGN_B, SEL_GPS_1),
1024 PINMUX_IPSR_MSEL(IP4_15_13, RX2_E, SEL_SCIF2_4),
1025 PINMUX_IPSR_MSEL(IP4_15_13, GLO_Q1_D, SEL_GPS_3),
1026 PINMUX_IPSR_MSEL(IP4_15_13, HCTS1_N_E, SEL_HSCIF1_4),
1027 PINMUX_IPSR_GPSR(IP4_18_16, SSI_SDATA2),
1028 PINMUX_IPSR_MSEL(IP4_18_16, GPS_MAG_B, SEL_GPS_1),
1029 PINMUX_IPSR_MSEL(IP4_18_16, TX2_E, SEL_SCIF2_4),
1030 PINMUX_IPSR_MSEL(IP4_18_16, HRTS1_N_E, SEL_HSCIF1_4),
1031 PINMUX_IPSR_GPSR(IP4_19, SSI_SCK34),
1032 PINMUX_IPSR_GPSR(IP4_20, SSI_WS34),
1033 PINMUX_IPSR_GPSR(IP4_21, SSI_SDATA3),
1034 PINMUX_IPSR_GPSR(IP4_23_22, SSI_SCK4),
1035 PINMUX_IPSR_MSEL(IP4_23_22, GLO_SS_D, SEL_GPS_3),
1036 PINMUX_IPSR_GPSR(IP4_25_24, SSI_WS4),
1037 PINMUX_IPSR_MSEL(IP4_25_24, GLO_RFON_D, SEL_GPS_3),
1038 PINMUX_IPSR_GPSR(IP4_27_26, SSI_SDATA4),
1039 PINMUX_IPSR_MSEL(IP4_27_26, MSIOF2_SCK_D, SEL_SOF2_3),
1040 PINMUX_IPSR_GPSR(IP4_30_28, SSI_SCK5),
1041 PINMUX_IPSR_MSEL(IP4_30_28, MSIOF1_SCK_C, SEL_SOF1_2),
1042 PINMUX_IPSR_MSEL(IP4_30_28, TS_SDATA0, SEL_TSIF0_0),
1043 PINMUX_IPSR_MSEL(IP4_30_28, GLO_I0, SEL_GPS_0),
1044 PINMUX_IPSR_MSEL(IP4_30_28, MSIOF2_SYNC_D, SEL_SOF2_3),
1045 PINMUX_IPSR_GPSR(IP4_30_28, VI1_R2_B),
1048 PINMUX_IPSR_GPSR(IP5_2_0, SSI_WS5),
1049 PINMUX_IPSR_MSEL(IP5_2_0, MSIOF1_SYNC_C, SEL_SOF1_2),
1050 PINMUX_IPSR_MSEL(IP5_2_0, TS_SCK0, SEL_TSIF0_0),
1051 PINMUX_IPSR_MSEL(IP5_2_0, GLO_I1, SEL_GPS_0),
1052 PINMUX_IPSR_MSEL(IP5_2_0, MSIOF2_TXD_D, SEL_SOF2_3),
1053 PINMUX_IPSR_GPSR(IP5_2_0, VI1_R3_B),
1054 PINMUX_IPSR_GPSR(IP5_5_3, SSI_SDATA5),
1055 PINMUX_IPSR_MSEL(IP5_5_3, MSIOF1_TXD_C, SEL_SOF1_2),
1056 PINMUX_IPSR_MSEL(IP5_5_3, TS_SDEN0, SEL_TSIF0_0),
1057 PINMUX_IPSR_MSEL(IP5_5_3, GLO_Q0, SEL_GPS_0),
1058 PINMUX_IPSR_MSEL(IP5_5_3, MSIOF2_SS1_D, SEL_SOF2_3),
1059 PINMUX_IPSR_GPSR(IP5_5_3, VI1_R4_B),
1060 PINMUX_IPSR_GPSR(IP5_8_6, SSI_SCK6),
1061 PINMUX_IPSR_MSEL(IP5_8_6, MSIOF1_RXD_C, SEL_SOF1_2),
1062 PINMUX_IPSR_MSEL(IP5_8_6, TS_SPSYNC0, SEL_TSIF0_0),
1063 PINMUX_IPSR_MSEL(IP5_8_6, GLO_Q1, SEL_GPS_0),
1064 PINMUX_IPSR_MSEL(IP5_8_6, MSIOF2_RXD_D, SEL_SOF2_3),
1065 PINMUX_IPSR_GPSR(IP5_8_6, VI1_R5_B),
1066 PINMUX_IPSR_GPSR(IP5_11_9, SSI_WS6),
1067 PINMUX_IPSR_MSEL(IP5_11_9, GLO_SCLK, SEL_GPS_0),
1068 PINMUX_IPSR_MSEL(IP5_11_9, MSIOF2_SS2_D, SEL_SOF2_3),
1069 PINMUX_IPSR_GPSR(IP5_11_9, VI1_R6_B),
1070 PINMUX_IPSR_GPSR(IP5_14_12, SSI_SDATA6),
1071 PINMUX_IPSR_MSEL(IP5_14_12, STP_IVCXO27_0_B, SEL_SSP_1),
1072 PINMUX_IPSR_MSEL(IP5_14_12, GLO_SDATA, SEL_GPS_0),
1073 PINMUX_IPSR_GPSR(IP5_14_12, VI1_R7_B),
1074 PINMUX_IPSR_MSEL(IP5_16_15, SSI_SCK78, SEL_SSI7_0),
1075 PINMUX_IPSR_MSEL(IP5_16_15, STP_ISCLK_0_B, SEL_SSP_1),
1076 PINMUX_IPSR_MSEL(IP5_16_15, GLO_SS, SEL_GPS_0),
1077 PINMUX_IPSR_MSEL(IP5_19_17, SSI_WS78, SEL_SSI7_0),
1078 PINMUX_IPSR_MSEL(IP5_19_17, TX0_D, SEL_SCIF0_3),
1079 PINMUX_IPSR_MSEL(IP5_19_17, STP_ISD_0_B, SEL_SSP_1),
1080 PINMUX_IPSR_MSEL(IP5_19_17, GLO_RFON, SEL_GPS_0),
1081 PINMUX_IPSR_MSEL(IP5_21_20, SSI_SDATA7, SEL_SSI7_0),
1082 PINMUX_IPSR_MSEL(IP5_21_20, RX0_D, SEL_SCIF0_3),
1083 PINMUX_IPSR_MSEL(IP5_21_20, STP_ISEN_0_B, SEL_SSP_1),
1084 PINMUX_IPSR_MSEL(IP5_23_22, SSI_SDATA8, SEL_SSI8_0),
1085 PINMUX_IPSR_MSEL(IP5_23_22, TX1_D, SEL_SCIF1_3),
1086 PINMUX_IPSR_MSEL(IP5_23_22, STP_ISSYNC_0_B, SEL_SSP_1),
1087 PINMUX_IPSR_MSEL(IP5_25_24, SSI_SCK9, SEL_SSI9_0),
1088 PINMUX_IPSR_MSEL(IP5_25_24, RX1_D, SEL_SCIF1_3),
1089 PINMUX_IPSR_MSEL(IP5_25_24, GLO_SCLK_D, SEL_GPS_3),
1090 PINMUX_IPSR_MSEL(IP5_28_26, SSI_WS9, SEL_SSI9_0),
1091 PINMUX_IPSR_MSEL(IP5_28_26, TX3_D, SEL_SCIF3_3),
1092 PINMUX_IPSR_MSEL(IP5_28_26, CAN0_TX_D, SEL_CAN0_3),
1093 PINMUX_IPSR_MSEL(IP5_28_26, GLO_SDATA_D, SEL_GPS_3),
1094 PINMUX_IPSR_MSEL(IP5_31_29, SSI_SDATA9, SEL_SSI9_0),
1095 PINMUX_IPSR_MSEL(IP5_31_29, RX3_D, SEL_SCIF3_3),
1096 PINMUX_IPSR_MSEL(IP5_31_29, CAN0_RX_D, SEL_CAN0_3),
1099 PINMUX_IPSR_MSEL(IP6_2_0, AUDIO_CLKB, SEL_ADG_0),
1100 PINMUX_IPSR_MSEL(IP6_2_0, STP_OPWM_0_B, SEL_SSP_1),
1101 PINMUX_IPSR_MSEL(IP6_2_0, MSIOF1_SCK_B, SEL_SOF1_1),
1102 PINMUX_IPSR_MSEL(IP6_2_0, SCIF_CLK, SEL_SCIF_0),
1103 PINMUX_IPSR_GPSR(IP6_2_0, DVC_MUTE),
1104 PINMUX_IPSR_MSEL(IP6_2_0, BPFCLK_E, SEL_FM_4),
1105 PINMUX_IPSR_GPSR(IP6_5_3, AUDIO_CLKC),
1106 PINMUX_IPSR_MSEL(IP6_5_3, SCIFB0_SCK_C, SEL_SCIFB_2),
1107 PINMUX_IPSR_MSEL(IP6_5_3, MSIOF1_SYNC_B, SEL_SOF1_1),
1108 PINMUX_IPSR_MSEL(IP6_5_3, RX2, SEL_SCIF2_0),
1109 PINMUX_IPSR_MSEL(IP6_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
1110 PINMUX_IPSR_MSEL(IP6_5_3, FMIN_E, SEL_FM_4),
1111 PINMUX_IPSR_GPSR(IP6_7_6, AUDIO_CLKOUT),
1112 PINMUX_IPSR_MSEL(IP6_7_6, MSIOF1_SS1_B, SEL_SOF1_1),
1113 PINMUX_IPSR_MSEL(IP6_7_6, TX2, SEL_SCIF2_0),
1114 PINMUX_IPSR_MSEL(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0),
1115 PINMUX_IPSR_GPSR(IP6_9_8, IRQ0),
1116 PINMUX_IPSR_MSEL(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3),
1117 PINMUX_IPSR_GPSR(IP6_9_8, INTC_IRQ0_N),
1118 PINMUX_IPSR_GPSR(IP6_11_10, IRQ1),
1119 PINMUX_IPSR_MSEL(IP6_11_10, SCIFB1_SCK_C, SEL_SCIFB1_2),
1120 PINMUX_IPSR_GPSR(IP6_11_10, INTC_IRQ1_N),
1121 PINMUX_IPSR_GPSR(IP6_13_12, IRQ2),
1122 PINMUX_IPSR_MSEL(IP6_13_12, SCIFB1_TXD_D, SEL_SCIFB1_3),
1123 PINMUX_IPSR_GPSR(IP6_13_12, INTC_IRQ2_N),
1124 PINMUX_IPSR_GPSR(IP6_15_14, IRQ3),
1125 PINMUX_IPSR_MSEL(IP6_15_14, I2C4_SCL_C, SEL_I2C4_2),
1126 PINMUX_IPSR_MSEL(IP6_15_14, MSIOF2_TXD_E, SEL_SOF2_4),
1127 PINMUX_IPSR_GPSR(IP6_15_14, INTC_IRQ4_N),
1128 PINMUX_IPSR_GPSR(IP6_18_16, IRQ4),
1129 PINMUX_IPSR_MSEL(IP6_18_16, HRX1_C, SEL_HSCIF1_2),
1130 PINMUX_IPSR_MSEL(IP6_18_16, I2C4_SDA_C, SEL_I2C4_2),
1131 PINMUX_IPSR_MSEL(IP6_18_16, MSIOF2_RXD_E, SEL_SOF2_4),
1132 PINMUX_IPSR_GPSR(IP6_18_16, INTC_IRQ4_N),
1133 PINMUX_IPSR_GPSR(IP6_20_19, IRQ5),
1134 PINMUX_IPSR_MSEL(IP6_20_19, HTX1_C, SEL_HSCIF1_2),
1135 PINMUX_IPSR_MSEL(IP6_20_19, I2C1_SCL_E, SEL_I2C1_4),
1136 PINMUX_IPSR_MSEL(IP6_20_19, MSIOF2_SCK_E, SEL_SOF2_4),
1137 PINMUX_IPSR_GPSR(IP6_23_21, IRQ6),
1138 PINMUX_IPSR_MSEL(IP6_23_21, HSCK1_C, SEL_HSCIF1_2),
1139 PINMUX_IPSR_MSEL(IP6_23_21, MSIOF1_SS2_B, SEL_SOF1_1),
1140 PINMUX_IPSR_MSEL(IP6_23_21, I2C1_SDA_E, SEL_I2C1_4),
1141 PINMUX_IPSR_MSEL(IP6_23_21, MSIOF2_SYNC_E, SEL_SOF2_4),
1142 PINMUX_IPSR_GPSR(IP6_26_24, IRQ7),
1143 PINMUX_IPSR_MSEL(IP6_26_24, HCTS1_N_C, SEL_HSCIF1_2),
1144 PINMUX_IPSR_MSEL(IP6_26_24, MSIOF1_TXD_B, SEL_SOF1_1),
1145 PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_C, SEL_GPS_2),
1146 PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_D, SEL_GPS_3),
1147 PINMUX_IPSR_GPSR(IP6_29_27, IRQ8),
1148 PINMUX_IPSR_MSEL(IP6_29_27, HRTS1_N_C, SEL_HSCIF1_2),
1149 PINMUX_IPSR_MSEL(IP6_29_27, MSIOF1_RXD_B, SEL_SOF1_1),
1150 PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_C, SEL_GPS_2),
1151 PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_D, SEL_GPS_3),
1154 PINMUX_IPSR_GPSR(IP7_2_0, IRQ9),
1155 PINMUX_IPSR_MSEL(IP7_2_0, DU1_DOTCLKIN_B, SEL_DIS_1),
1156 PINMUX_IPSR_MSEL(IP7_2_0, CAN_CLK_D, SEL_CANCLK_3),
1157 PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_C, SEL_GPS_2),
1158 PINMUX_IPSR_MSEL(IP7_2_0, SCIF_CLK_B, SEL_SCIF_1),
1159 PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_D, SEL_GPS_3),
1160 PINMUX_IPSR_GPSR(IP7_5_3, DU1_DR0),
1161 PINMUX_IPSR_GPSR(IP7_5_3, LCDOUT0),
1162 PINMUX_IPSR_MSEL(IP7_5_3, VI1_DATA0_B, SEL_VI1_1),
1163 PINMUX_IPSR_MSEL(IP7_5_3, TX0_B, SEL_SCIF0_1),
1164 PINMUX_IPSR_MSEL(IP7_5_3, SCIFA0_TXD_B, SEL_SCFA_1),
1165 PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_SOF2_1),
1166 PINMUX_IPSR_GPSR(IP7_8_6, DU1_DR1),
1167 PINMUX_IPSR_GPSR(IP7_8_6, LCDOUT1),
1168 PINMUX_IPSR_MSEL(IP7_8_6, VI1_DATA1_B, SEL_VI1_1),
1169 PINMUX_IPSR_MSEL(IP7_8_6, RX0_B, SEL_SCIF0_1),
1170 PINMUX_IPSR_MSEL(IP7_8_6, SCIFA0_RXD_B, SEL_SCFA_1),
1171 PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_SOF2_1),
1172 PINMUX_IPSR_GPSR(IP7_10_9, DU1_DR2),
1173 PINMUX_IPSR_GPSR(IP7_10_9, LCDOUT2),
1174 PINMUX_IPSR_MSEL(IP7_10_9, SSI_SCK0129_B, SEL_SSI0_1),
1175 PINMUX_IPSR_GPSR(IP7_12_11, DU1_DR3),
1176 PINMUX_IPSR_GPSR(IP7_12_11, LCDOUT3),
1177 PINMUX_IPSR_MSEL(IP7_12_11, SSI_WS0129_B, SEL_SSI0_1),
1178 PINMUX_IPSR_GPSR(IP7_14_13, DU1_DR4),
1179 PINMUX_IPSR_GPSR(IP7_14_13, LCDOUT4),
1180 PINMUX_IPSR_MSEL(IP7_14_13, SSI_SDATA0_B, SEL_SSI0_1),
1181 PINMUX_IPSR_GPSR(IP7_16_15, DU1_DR5),
1182 PINMUX_IPSR_GPSR(IP7_16_15, LCDOUT5),
1183 PINMUX_IPSR_MSEL(IP7_16_15, SSI_SCK1_B, SEL_SSI1_1),
1184 PINMUX_IPSR_GPSR(IP7_18_17, DU1_DR6),
1185 PINMUX_IPSR_GPSR(IP7_18_17, LCDOUT6),
1186 PINMUX_IPSR_MSEL(IP7_18_17, SSI_WS1_B, SEL_SSI1_1),
1187 PINMUX_IPSR_GPSR(IP7_20_19, DU1_DR7),
1188 PINMUX_IPSR_GPSR(IP7_20_19, LCDOUT7),
1189 PINMUX_IPSR_MSEL(IP7_20_19, SSI_SDATA1_B, SEL_SSI1_1),
1190 PINMUX_IPSR_GPSR(IP7_23_21, DU1_DG0),
1191 PINMUX_IPSR_GPSR(IP7_23_21, LCDOUT8),
1192 PINMUX_IPSR_MSEL(IP7_23_21, VI1_DATA2_B, SEL_VI1_1),
1193 PINMUX_IPSR_MSEL(IP7_23_21, TX1_B, SEL_SCIF1_1),
1194 PINMUX_IPSR_MSEL(IP7_23_21, SCIFA1_TXD_B, SEL_SCIFA1_1),
1195 PINMUX_IPSR_MSEL(IP7_23_21, MSIOF2_SS1_B, SEL_SOF2_1),
1196 PINMUX_IPSR_GPSR(IP7_26_24, DU1_DG1),
1197 PINMUX_IPSR_GPSR(IP7_26_24, LCDOUT9),
1198 PINMUX_IPSR_MSEL(IP7_26_24, VI1_DATA3_B, SEL_VI1_1),
1199 PINMUX_IPSR_MSEL(IP7_26_24, RX1_B, SEL_SCIF1_1),
1200 PINMUX_IPSR_MSEL(IP7_26_24, SCIFA1_RXD_B, SEL_SCIFA1_1),
1201 PINMUX_IPSR_MSEL(IP7_26_24, MSIOF2_SS2_B, SEL_SOF2_1),
1202 PINMUX_IPSR_GPSR(IP7_29_27, DU1_DG2),
1203 PINMUX_IPSR_GPSR(IP7_29_27, LCDOUT10),
1204 PINMUX_IPSR_MSEL(IP7_29_27, VI1_DATA4_B, SEL_VI1_1),
1205 PINMUX_IPSR_GPSR(IP7_29_27, SCIF1_SCK_B),
1206 PINMUX_IPSR_MSEL(IP7_29_27, SCIFA1_SCK, SEL_SCIFA1_0),
1207 PINMUX_IPSR_MSEL(IP7_29_27, SSI_SCK78_B, SEL_SSI7_1),
1210 PINMUX_IPSR_GPSR(IP8_2_0, DU1_DG3),
1211 PINMUX_IPSR_GPSR(IP8_2_0, LCDOUT11),
1212 PINMUX_IPSR_MSEL(IP8_2_0, VI1_DATA5_B, SEL_VI1_1),
1213 PINMUX_IPSR_MSEL(IP8_2_0, SSI_WS78_B, SEL_SSI7_1),
1214 PINMUX_IPSR_GPSR(IP8_5_3, DU1_DG4),
1215 PINMUX_IPSR_GPSR(IP8_5_3, LCDOUT12),
1216 PINMUX_IPSR_MSEL(IP8_5_3, VI1_DATA6_B, SEL_VI1_1),
1217 PINMUX_IPSR_MSEL(IP8_5_3, HRX0_B, SEL_HSCIF0_1),
1218 PINMUX_IPSR_MSEL(IP8_5_3, SCIFB2_RXD_B, SEL_SCIFB2_1),
1219 PINMUX_IPSR_MSEL(IP8_5_3, SSI_SDATA7_B, SEL_SSI7_1),
1220 PINMUX_IPSR_GPSR(IP8_8_6, DU1_DG5),
1221 PINMUX_IPSR_GPSR(IP8_8_6, LCDOUT13),
1222 PINMUX_IPSR_MSEL(IP8_8_6, VI1_DATA7_B, SEL_VI1_1),
1223 PINMUX_IPSR_MSEL(IP8_8_6, HCTS0_N_B, SEL_HSCIF0_1),
1224 PINMUX_IPSR_MSEL(IP8_8_6, SCIFB2_TXD_B, SEL_SCIFB2_1),
1225 PINMUX_IPSR_MSEL(IP8_8_6, SSI_SDATA8_B, SEL_SSI8_1),
1226 PINMUX_IPSR_GPSR(IP8_11_9, DU1_DG6),
1227 PINMUX_IPSR_GPSR(IP8_11_9, LCDOUT14),
1228 PINMUX_IPSR_MSEL(IP8_11_9, HRTS0_N_B, SEL_HSCIF0_1),
1229 PINMUX_IPSR_MSEL(IP8_11_9, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
1230 PINMUX_IPSR_MSEL(IP8_11_9, SSI_SCK9_B, SEL_SSI9_1),
1231 PINMUX_IPSR_GPSR(IP8_14_12, DU1_DG7),
1232 PINMUX_IPSR_GPSR(IP8_14_12, LCDOUT15),
1233 PINMUX_IPSR_MSEL(IP8_14_12, HTX0_B, SEL_HSCIF0_1),
1234 PINMUX_IPSR_MSEL(IP8_14_12, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
1235 PINMUX_IPSR_MSEL(IP8_14_12, SSI_WS9_B, SEL_SSI9_1),
1236 PINMUX_IPSR_GPSR(IP8_17_15, DU1_DB0),
1237 PINMUX_IPSR_GPSR(IP8_17_15, LCDOUT16),
1238 PINMUX_IPSR_MSEL(IP8_17_15, VI1_CLK_B, SEL_VI1_1),
1239 PINMUX_IPSR_MSEL(IP8_17_15, TX2_B, SEL_SCIF2_1),
1240 PINMUX_IPSR_MSEL(IP8_17_15, SCIFA2_TXD_B, SEL_SCIFA2_1),
1241 PINMUX_IPSR_MSEL(IP8_17_15, MSIOF2_TXD_B, SEL_SOF2_1),
1242 PINMUX_IPSR_GPSR(IP8_20_18, DU1_DB1),
1243 PINMUX_IPSR_GPSR(IP8_20_18, LCDOUT17),
1244 PINMUX_IPSR_MSEL(IP8_20_18, VI1_HSYNC_N_B, SEL_VI1_1),
1245 PINMUX_IPSR_MSEL(IP8_20_18, RX2_B, SEL_SCIF2_1),
1246 PINMUX_IPSR_MSEL(IP8_20_18, SCIFA2_RXD_B, SEL_SCIFA2_1),
1247 PINMUX_IPSR_MSEL(IP8_20_18, MSIOF2_RXD_B, SEL_SOF2_1),
1248 PINMUX_IPSR_GPSR(IP8_23_21, DU1_DB2),
1249 PINMUX_IPSR_GPSR(IP8_23_21, LCDOUT18),
1250 PINMUX_IPSR_MSEL(IP8_23_21, VI1_VSYNC_N_B, SEL_VI1_1),
1251 PINMUX_IPSR_GPSR(IP8_23_21, SCIF2_SCK_B),
1252 PINMUX_IPSR_MSEL(IP8_23_21, SCIFA2_SCK, SEL_SCIFA2_1),
1253 PINMUX_IPSR_MSEL(IP8_23_21, SSI_SDATA9_B, SEL_SSI9_1),
1254 PINMUX_IPSR_GPSR(IP8_25_24, DU1_DB3),
1255 PINMUX_IPSR_GPSR(IP8_25_24, LCDOUT19),
1256 PINMUX_IPSR_MSEL(IP8_25_24, VI1_CLKENB_B, SEL_VI1_1),
1257 PINMUX_IPSR_GPSR(IP8_27_26, DU1_DB4),
1258 PINMUX_IPSR_GPSR(IP8_27_26, LCDOUT20),
1259 PINMUX_IPSR_MSEL(IP8_27_26, VI1_FIELD_B, SEL_VI1_1),
1260 PINMUX_IPSR_MSEL(IP8_27_26, CAN1_RX, SEL_CAN1_0),
1261 PINMUX_IPSR_GPSR(IP8_30_28, DU1_DB5),
1262 PINMUX_IPSR_GPSR(IP8_30_28, LCDOUT21),
1263 PINMUX_IPSR_MSEL(IP8_30_28, TX3, SEL_SCIF3_0),
1264 PINMUX_IPSR_MSEL(IP8_30_28, SCIFA3_TXD, SEL_SCIFA3_0),
1265 PINMUX_IPSR_MSEL(IP8_30_28, CAN1_TX, SEL_CAN1_0),
1268 PINMUX_IPSR_GPSR(IP9_2_0, DU1_DB6),
1269 PINMUX_IPSR_GPSR(IP9_2_0, LCDOUT22),
1270 PINMUX_IPSR_MSEL(IP9_2_0, I2C3_SCL_C, SEL_I2C3_2),
1271 PINMUX_IPSR_MSEL(IP9_2_0, RX3, SEL_SCIF3_0),
1272 PINMUX_IPSR_MSEL(IP9_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
1273 PINMUX_IPSR_GPSR(IP9_5_3, DU1_DB7),
1274 PINMUX_IPSR_GPSR(IP9_5_3, LCDOUT23),
1275 PINMUX_IPSR_MSEL(IP9_5_3, I2C3_SDA_C, SEL_I2C3_2),
1276 PINMUX_IPSR_MSEL(IP9_5_3, SCIF3_SCK, SEL_SCIF3_0),
1277 PINMUX_IPSR_MSEL(IP9_5_3, SCIFA3_SCK, SEL_SCIFA3_0),
1278 PINMUX_IPSR_MSEL(IP9_6, DU1_DOTCLKIN, SEL_DIS_0),
1279 PINMUX_IPSR_GPSR(IP9_6, QSTVA_QVS),
1280 PINMUX_IPSR_GPSR(IP9_7, DU1_DOTCLKOUT0),
1281 PINMUX_IPSR_GPSR(IP9_7, QCLK),
1282 PINMUX_IPSR_GPSR(IP9_10_8, DU1_DOTCLKOUT1),
1283 PINMUX_IPSR_GPSR(IP9_10_8, QSTVB_QVE),
1284 PINMUX_IPSR_MSEL(IP9_10_8, CAN0_TX, SEL_CAN0_0),
1285 PINMUX_IPSR_MSEL(IP9_10_8, TX3_B, SEL_SCIF3_1),
1286 PINMUX_IPSR_MSEL(IP9_10_8, I2C2_SCL_B, SEL_I2C2_1),
1287 PINMUX_IPSR_GPSR(IP9_10_8, PWM4),
1288 PINMUX_IPSR_GPSR(IP9_11, DU1_EXHSYNC_DU1_HSYNC),
1289 PINMUX_IPSR_GPSR(IP9_11, QSTH_QHS),
1290 PINMUX_IPSR_GPSR(IP9_12, DU1_EXVSYNC_DU1_VSYNC),
1291 PINMUX_IPSR_GPSR(IP9_12, QSTB_QHE),
1292 PINMUX_IPSR_GPSR(IP9_15_13, DU1_EXODDF_DU1_ODDF_DISP_CDE),
1293 PINMUX_IPSR_GPSR(IP9_15_13, QCPV_QDE),
1294 PINMUX_IPSR_MSEL(IP9_15_13, CAN0_RX, SEL_CAN0_0),
1295 PINMUX_IPSR_MSEL(IP9_15_13, RX3_B, SEL_SCIF3_1),
1296 PINMUX_IPSR_MSEL(IP9_15_13, I2C2_SDA_B, SEL_I2C2_1),
1297 PINMUX_IPSR_GPSR(IP9_16, DU1_DISP),
1298 PINMUX_IPSR_GPSR(IP9_16, QPOLA),
1299 PINMUX_IPSR_GPSR(IP9_18_17, DU1_CDE),
1300 PINMUX_IPSR_GPSR(IP9_18_17, QPOLB),
1301 PINMUX_IPSR_GPSR(IP9_18_17, PWM4_B),
1302 PINMUX_IPSR_GPSR(IP9_20_19, VI0_CLKENB),
1303 PINMUX_IPSR_MSEL(IP9_20_19, TX4, SEL_SCIF4_0),
1304 PINMUX_IPSR_MSEL(IP9_20_19, SCIFA4_TXD, SEL_SCIFA4_0),
1305 PINMUX_IPSR_MSEL(IP9_20_19, TS_SDATA0_D, SEL_TSIF0_3),
1306 PINMUX_IPSR_GPSR(IP9_22_21, VI0_FIELD),
1307 PINMUX_IPSR_MSEL(IP9_22_21, RX4, SEL_SCIF4_0),
1308 PINMUX_IPSR_MSEL(IP9_22_21, SCIFA4_RXD, SEL_SCIFA4_0),
1309 PINMUX_IPSR_MSEL(IP9_22_21, TS_SCK0_D, SEL_TSIF0_3),
1310 PINMUX_IPSR_GPSR(IP9_24_23, VI0_HSYNC_N),
1311 PINMUX_IPSR_MSEL(IP9_24_23, TX5, SEL_SCIF5_0),
1312 PINMUX_IPSR_MSEL(IP9_24_23, SCIFA5_TXD, SEL_SCIFA5_0),
1313 PINMUX_IPSR_MSEL(IP9_24_23, TS_SDEN0_D, SEL_TSIF0_3),
1314 PINMUX_IPSR_GPSR(IP9_26_25, VI0_VSYNC_N),
1315 PINMUX_IPSR_MSEL(IP9_26_25, RX5, SEL_SCIF5_0),
1316 PINMUX_IPSR_MSEL(IP9_26_25, SCIFA5_RXD, SEL_SCIFA5_0),
1317 PINMUX_IPSR_MSEL(IP9_26_25, TS_SPSYNC0_D, SEL_TSIF0_3),
1318 PINMUX_IPSR_GPSR(IP9_28_27, VI0_DATA3_VI0_B3),
1319 PINMUX_IPSR_MSEL(IP9_28_27, SCIF3_SCK_B, SEL_SCIF3_1),
1320 PINMUX_IPSR_MSEL(IP9_28_27, SCIFA3_SCK_B, SEL_SCIFA3_1),
1321 PINMUX_IPSR_GPSR(IP9_31_29, VI0_G0),
1322 PINMUX_IPSR_MSEL(IP9_31_29, IIC1_SCL, SEL_IIC1_0),
1323 PINMUX_IPSR_MSEL(IP9_31_29, STP_IVCXO27_0_C, SEL_SSP_2),
1324 PINMUX_IPSR_MSEL(IP9_31_29, I2C4_SCL, SEL_I2C4_0),
1325 PINMUX_IPSR_MSEL(IP9_31_29, HCTS2_N, SEL_HSCIF2_0),
1326 PINMUX_IPSR_MSEL(IP9_31_29, SCIFB2_CTS_N, SEL_SCIFB2_0),
1327 PINMUX_IPSR_GPSR(IP9_31_29, ATAWR1_N),
1330 PINMUX_IPSR_GPSR(IP10_2_0, VI0_G1),
1331 PINMUX_IPSR_MSEL(IP10_2_0, IIC1_SDA, SEL_IIC1_0),
1332 PINMUX_IPSR_MSEL(IP10_2_0, STP_ISCLK_0_C, SEL_SSP_2),
1333 PINMUX_IPSR_MSEL(IP10_2_0, I2C4_SDA, SEL_I2C4_0),
1334 PINMUX_IPSR_MSEL(IP10_2_0, HRTS2_N, SEL_HSCIF2_0),
1335 PINMUX_IPSR_MSEL(IP10_2_0, SCIFB2_RTS_N, SEL_SCIFB2_0),
1336 PINMUX_IPSR_GPSR(IP10_2_0, ATADIR1_N),
1337 PINMUX_IPSR_GPSR(IP10_5_3, VI0_G2),
1338 PINMUX_IPSR_GPSR(IP10_5_3, VI2_HSYNC_N),
1339 PINMUX_IPSR_MSEL(IP10_5_3, STP_ISD_0_C, SEL_SSP_2),
1340 PINMUX_IPSR_MSEL(IP10_5_3, I2C3_SCL_B, SEL_I2C3_1),
1341 PINMUX_IPSR_MSEL(IP10_5_3, HSCK2, SEL_HSCIF2_0),
1342 PINMUX_IPSR_MSEL(IP10_5_3, SCIFB2_SCK, SEL_SCIFB2_0),
1343 PINMUX_IPSR_GPSR(IP10_5_3, ATARD1_N),
1344 PINMUX_IPSR_GPSR(IP10_8_6, VI0_G3),
1345 PINMUX_IPSR_GPSR(IP10_8_6, VI2_VSYNC_N),
1346 PINMUX_IPSR_MSEL(IP10_8_6, STP_ISEN_0_C, SEL_SSP_2),
1347 PINMUX_IPSR_MSEL(IP10_8_6, I2C3_SDA_B, SEL_I2C3_1),
1348 PINMUX_IPSR_MSEL(IP10_8_6, HRX2, SEL_HSCIF2_0),
1349 PINMUX_IPSR_MSEL(IP10_8_6, SCIFB2_RXD, SEL_SCIFB2_0),
1350 PINMUX_IPSR_GPSR(IP10_8_6, ATACS01_N),
1351 PINMUX_IPSR_GPSR(IP10_11_9, VI0_G4),
1352 PINMUX_IPSR_GPSR(IP10_11_9, VI2_CLKENB),
1353 PINMUX_IPSR_MSEL(IP10_11_9, STP_ISSYNC_0_C, SEL_SSP_2),
1354 PINMUX_IPSR_MSEL(IP10_11_9, HTX2, SEL_HSCIF2_0),
1355 PINMUX_IPSR_MSEL(IP10_11_9, SCIFB2_TXD, SEL_SCIFB2_0),
1356 PINMUX_IPSR_MSEL(IP10_11_9, SCIFB0_SCK_D, SEL_SCIFB_3),
1357 PINMUX_IPSR_GPSR(IP10_14_12, VI0_G5),
1358 PINMUX_IPSR_GPSR(IP10_14_12, VI2_FIELD),
1359 PINMUX_IPSR_MSEL(IP10_14_12, STP_OPWM_0_C, SEL_SSP_2),
1360 PINMUX_IPSR_MSEL(IP10_14_12, FMCLK_D, SEL_FM_3),
1361 PINMUX_IPSR_MSEL(IP10_14_12, CAN0_TX_E, SEL_CAN0_4),
1362 PINMUX_IPSR_MSEL(IP10_14_12, HTX1_D, SEL_HSCIF1_3),
1363 PINMUX_IPSR_MSEL(IP10_14_12, SCIFB0_TXD_D, SEL_SCIFB_3),
1364 PINMUX_IPSR_GPSR(IP10_16_15, VI0_G6),
1365 PINMUX_IPSR_GPSR(IP10_16_15, VI2_CLK),
1366 PINMUX_IPSR_MSEL(IP10_16_15, BPFCLK_D, SEL_FM_3),
1367 PINMUX_IPSR_GPSR(IP10_18_17, VI0_G7),
1368 PINMUX_IPSR_GPSR(IP10_18_17, VI2_DATA0),
1369 PINMUX_IPSR_MSEL(IP10_18_17, FMIN_D, SEL_FM_3),
1370 PINMUX_IPSR_GPSR(IP10_21_19, VI0_R0),
1371 PINMUX_IPSR_GPSR(IP10_21_19, VI2_DATA1),
1372 PINMUX_IPSR_MSEL(IP10_21_19, GLO_I0_B, SEL_GPS_1),
1373 PINMUX_IPSR_MSEL(IP10_21_19, TS_SDATA0_C, SEL_TSIF0_2),
1374 PINMUX_IPSR_GPSR(IP10_21_19, ATACS11_N),
1375 PINMUX_IPSR_GPSR(IP10_24_22, VI0_R1),
1376 PINMUX_IPSR_GPSR(IP10_24_22, VI2_DATA2),
1377 PINMUX_IPSR_MSEL(IP10_24_22, GLO_I1_B, SEL_GPS_1),
1378 PINMUX_IPSR_MSEL(IP10_24_22, TS_SCK0_C, SEL_TSIF0_2),
1379 PINMUX_IPSR_GPSR(IP10_24_22, ATAG1_N),
1380 PINMUX_IPSR_GPSR(IP10_26_25, VI0_R2),
1381 PINMUX_IPSR_GPSR(IP10_26_25, VI2_DATA3),
1382 PINMUX_IPSR_MSEL(IP10_26_25, GLO_Q0_B, SEL_GPS_1),
1383 PINMUX_IPSR_MSEL(IP10_26_25, TS_SDEN0_C, SEL_TSIF0_2),
1384 PINMUX_IPSR_GPSR(IP10_28_27, VI0_R3),
1385 PINMUX_IPSR_GPSR(IP10_28_27, VI2_DATA4),
1386 PINMUX_IPSR_MSEL(IP10_28_27, GLO_Q1_B, SEL_GPS_1),
1387 PINMUX_IPSR_MSEL(IP10_28_27, TS_SPSYNC0_C, SEL_TSIF0_2),
1388 PINMUX_IPSR_GPSR(IP10_31_29, VI0_R4),
1389 PINMUX_IPSR_GPSR(IP10_31_29, VI2_DATA5),
1390 PINMUX_IPSR_MSEL(IP10_31_29, GLO_SCLK_B, SEL_GPS_1),
1391 PINMUX_IPSR_MSEL(IP10_31_29, TX0_C, SEL_SCIF0_2),
1392 PINMUX_IPSR_MSEL(IP10_31_29, I2C1_SCL_D, SEL_I2C1_3),
1395 PINMUX_IPSR_GPSR(IP11_2_0, VI0_R5),
1396 PINMUX_IPSR_GPSR(IP11_2_0, VI2_DATA6),
1397 PINMUX_IPSR_MSEL(IP11_2_0, GLO_SDATA_B, SEL_GPS_1),
1398 PINMUX_IPSR_MSEL(IP11_2_0, RX0_C, SEL_SCIF0_2),
1399 PINMUX_IPSR_MSEL(IP11_2_0, I2C1_SDA_D, SEL_I2C1_3),
1400 PINMUX_IPSR_GPSR(IP11_5_3, VI0_R6),
1401 PINMUX_IPSR_GPSR(IP11_5_3, VI2_DATA7),
1402 PINMUX_IPSR_MSEL(IP11_5_3, GLO_SS_B, SEL_GPS_1),
1403 PINMUX_IPSR_MSEL(IP11_5_3, TX1_C, SEL_SCIF1_2),
1404 PINMUX_IPSR_MSEL(IP11_5_3, I2C4_SCL_B, SEL_I2C4_1),
1405 PINMUX_IPSR_GPSR(IP11_8_6, VI0_R7),
1406 PINMUX_IPSR_MSEL(IP11_8_6, GLO_RFON_B, SEL_GPS_1),
1407 PINMUX_IPSR_MSEL(IP11_8_6, RX1_C, SEL_SCIF1_2),
1408 PINMUX_IPSR_MSEL(IP11_8_6, CAN0_RX_E, SEL_CAN0_4),
1409 PINMUX_IPSR_MSEL(IP11_8_6, I2C4_SDA_B, SEL_I2C4_1),
1410 PINMUX_IPSR_MSEL(IP11_8_6, HRX1_D, SEL_HSCIF1_3),
1411 PINMUX_IPSR_MSEL(IP11_8_6, SCIFB0_RXD_D, SEL_SCIFB_3),
1412 PINMUX_IPSR_MSEL(IP11_11_9, VI1_HSYNC_N, SEL_VI1_0),
1413 PINMUX_IPSR_GPSR(IP11_11_9, AVB_RXD0),
1414 PINMUX_IPSR_MSEL(IP11_11_9, TS_SDATA0_B, SEL_TSIF0_1),
1415 PINMUX_IPSR_MSEL(IP11_11_9, TX4_B, SEL_SCIF4_1),
1416 PINMUX_IPSR_MSEL(IP11_11_9, SCIFA4_TXD_B, SEL_SCIFA4_1),
1417 PINMUX_IPSR_MSEL(IP11_14_12, VI1_VSYNC_N, SEL_VI1_0),
1418 PINMUX_IPSR_GPSR(IP11_14_12, AVB_RXD1),
1419 PINMUX_IPSR_MSEL(IP11_14_12, TS_SCK0_B, SEL_TSIF0_1),
1420 PINMUX_IPSR_MSEL(IP11_14_12, RX4_B, SEL_SCIF4_1),
1421 PINMUX_IPSR_MSEL(IP11_14_12, SCIFA4_RXD_B, SEL_SCIFA4_1),
1422 PINMUX_IPSR_MSEL(IP11_16_15, VI1_CLKENB, SEL_VI1_0),
1423 PINMUX_IPSR_GPSR(IP11_16_15, AVB_RXD2),
1424 PINMUX_IPSR_MSEL(IP11_16_15, TS_SDEN0_B, SEL_TSIF0_1),
1425 PINMUX_IPSR_MSEL(IP11_18_17, VI1_FIELD, SEL_VI1_0),
1426 PINMUX_IPSR_GPSR(IP11_18_17, AVB_RXD3),
1427 PINMUX_IPSR_MSEL(IP11_18_17, TS_SPSYNC0_B, SEL_TSIF0_1),
1428 PINMUX_IPSR_MSEL(IP11_19, VI1_CLK, SEL_VI1_0),
1429 PINMUX_IPSR_GPSR(IP11_19, AVB_RXD4),
1430 PINMUX_IPSR_MSEL(IP11_20, VI1_DATA0, SEL_VI1_0),
1431 PINMUX_IPSR_GPSR(IP11_20, AVB_RXD5),
1432 PINMUX_IPSR_MSEL(IP11_21, VI1_DATA1, SEL_VI1_0),
1433 PINMUX_IPSR_GPSR(IP11_21, AVB_RXD6),
1434 PINMUX_IPSR_MSEL(IP11_22, VI1_DATA2, SEL_VI1_0),
1435 PINMUX_IPSR_GPSR(IP11_22, AVB_RXD7),
1436 PINMUX_IPSR_MSEL(IP11_23, VI1_DATA3, SEL_VI1_0),
1437 PINMUX_IPSR_GPSR(IP11_23, AVB_RX_ER),
1438 PINMUX_IPSR_MSEL(IP11_24, VI1_DATA4, SEL_VI1_0),
1439 PINMUX_IPSR_GPSR(IP11_24, AVB_MDIO),
1440 PINMUX_IPSR_MSEL(IP11_25, VI1_DATA5, SEL_VI1_0),
1441 PINMUX_IPSR_GPSR(IP11_25, AVB_RX_DV),
1442 PINMUX_IPSR_MSEL(IP11_26, VI1_DATA6, SEL_VI1_0),
1443 PINMUX_IPSR_GPSR(IP11_26, AVB_MAGIC),
1444 PINMUX_IPSR_MSEL(IP11_27, VI1_DATA7, SEL_VI1_0),
1445 PINMUX_IPSR_GPSR(IP11_27, AVB_MDC),
1446 PINMUX_IPSR_GPSR(IP11_29_28, ETH_MDIO),
1447 PINMUX_IPSR_GPSR(IP11_29_28, AVB_RX_CLK),
1448 PINMUX_IPSR_MSEL(IP11_29_28, I2C2_SCL_C, SEL_I2C2_2),
1449 PINMUX_IPSR_GPSR(IP11_31_30, ETH_CRS_DV),
1450 PINMUX_IPSR_GPSR(IP11_31_30, AVB_LINK),
1451 PINMUX_IPSR_MSEL(IP11_31_30, I2C2_SDA_C, SEL_I2C2_2),
1454 PINMUX_IPSR_GPSR(IP12_1_0, ETH_RX_ER),
1455 PINMUX_IPSR_GPSR(IP12_1_0, AVB_CRS),
1456 PINMUX_IPSR_MSEL(IP12_1_0, I2C3_SCL, SEL_I2C3_0),
1457 PINMUX_IPSR_MSEL(IP12_1_0, IIC0_SCL, SEL_IIC0_0),
1458 PINMUX_IPSR_GPSR(IP12_3_2, ETH_RXD0),
1459 PINMUX_IPSR_GPSR(IP12_3_2, AVB_PHY_INT),
1460 PINMUX_IPSR_MSEL(IP12_3_2, I2C3_SDA, SEL_I2C3_0),
1461 PINMUX_IPSR_MSEL(IP12_3_2, IIC0_SDA, SEL_IIC0_0),
1462 PINMUX_IPSR_GPSR(IP12_6_4, ETH_RXD1),
1463 PINMUX_IPSR_GPSR(IP12_6_4, AVB_GTXREFCLK),
1464 PINMUX_IPSR_MSEL(IP12_6_4, CAN0_TX_C, SEL_CAN0_2),
1465 PINMUX_IPSR_MSEL(IP12_6_4, I2C2_SCL_D, SEL_I2C2_3),
1466 PINMUX_IPSR_MSEL(IP12_6_4, MSIOF1_RXD_E, SEL_SOF1_4),
1467 PINMUX_IPSR_GPSR(IP12_9_7, ETH_LINK),
1468 PINMUX_IPSR_GPSR(IP12_9_7, AVB_TXD0),
1469 PINMUX_IPSR_MSEL(IP12_9_7, CAN0_RX_C, SEL_CAN0_2),
1470 PINMUX_IPSR_MSEL(IP12_9_7, I2C2_SDA_D, SEL_I2C2_3),
1471 PINMUX_IPSR_MSEL(IP12_9_7, MSIOF1_SCK_E, SEL_SOF1_4),
1472 PINMUX_IPSR_GPSR(IP12_12_10, ETH_REFCLK),
1473 PINMUX_IPSR_GPSR(IP12_12_10, AVB_TXD1),
1474 PINMUX_IPSR_MSEL(IP12_12_10, SCIFA3_RXD_B, SEL_SCIFA3_1),
1475 PINMUX_IPSR_MSEL(IP12_12_10, CAN1_RX_C, SEL_CAN1_2),
1476 PINMUX_IPSR_MSEL(IP12_12_10, MSIOF1_SYNC_E, SEL_SOF1_4),
1477 PINMUX_IPSR_GPSR(IP12_15_13, ETH_TXD1),
1478 PINMUX_IPSR_GPSR(IP12_15_13, AVB_TXD2),
1479 PINMUX_IPSR_MSEL(IP12_15_13, SCIFA3_TXD_B, SEL_SCIFA3_1),
1480 PINMUX_IPSR_MSEL(IP12_15_13, CAN1_TX_C, SEL_CAN1_2),
1481 PINMUX_IPSR_MSEL(IP12_15_13, MSIOF1_TXD_E, SEL_SOF1_4),
1482 PINMUX_IPSR_GPSR(IP12_17_16, ETH_TX_EN),
1483 PINMUX_IPSR_GPSR(IP12_17_16, AVB_TXD3),
1484 PINMUX_IPSR_MSEL(IP12_17_16, TCLK1_B, SEL_TMU1_0),
1485 PINMUX_IPSR_MSEL(IP12_17_16, CAN_CLK_B, SEL_CANCLK_1),
1486 PINMUX_IPSR_GPSR(IP12_19_18, ETH_MAGIC),
1487 PINMUX_IPSR_GPSR(IP12_19_18, AVB_TXD4),
1488 PINMUX_IPSR_MSEL(IP12_19_18, IETX_C, SEL_IEB_2),
1489 PINMUX_IPSR_GPSR(IP12_21_20, ETH_TXD0),
1490 PINMUX_IPSR_GPSR(IP12_21_20, AVB_TXD5),
1491 PINMUX_IPSR_MSEL(IP12_21_20, IECLK_C, SEL_IEB_2),
1492 PINMUX_IPSR_GPSR(IP12_23_22, ETH_MDC),
1493 PINMUX_IPSR_GPSR(IP12_23_22, AVB_TXD6),
1494 PINMUX_IPSR_MSEL(IP12_23_22, IERX_C, SEL_IEB_2),
1495 PINMUX_IPSR_MSEL(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0),
1496 PINMUX_IPSR_GPSR(IP12_26_24, AVB_TXD7),
1497 PINMUX_IPSR_MSEL(IP12_26_24, SCIFB2_TXD_D, SEL_SCIFB2_3),
1498 PINMUX_IPSR_MSEL(IP12_26_24, ADIDATA_B, SEL_RAD_1),
1499 PINMUX_IPSR_MSEL(IP12_26_24, MSIOF0_SYNC_C, SEL_SOF0_2),
1500 PINMUX_IPSR_MSEL(IP12_29_27, STP_ISCLK_0, SEL_SSP_0),
1501 PINMUX_IPSR_GPSR(IP12_29_27, AVB_TX_EN),
1502 PINMUX_IPSR_MSEL(IP12_29_27, SCIFB2_RXD_D, SEL_SCIFB2_3),
1503 PINMUX_IPSR_MSEL(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1),
1504 PINMUX_IPSR_MSEL(IP12_29_27, MSIOF0_SCK_C, SEL_SOF0_2),
1507 PINMUX_IPSR_MSEL(IP13_2_0, STP_ISD_0, SEL_SSP_0),
1508 PINMUX_IPSR_GPSR(IP13_2_0, AVB_TX_ER),
1509 PINMUX_IPSR_MSEL(IP13_2_0, SCIFB2_SCK_C, SEL_SCIFB2_2),
1510 PINMUX_IPSR_MSEL(IP13_2_0, ADICLK_B, SEL_RAD_1),
1511 PINMUX_IPSR_MSEL(IP13_2_0, MSIOF0_SS1_C, SEL_SOF0_2),
1512 PINMUX_IPSR_MSEL(IP13_4_3, STP_ISEN_0, SEL_SSP_0),
1513 PINMUX_IPSR_GPSR(IP13_4_3, AVB_TX_CLK),
1514 PINMUX_IPSR_MSEL(IP13_4_3, ADICHS0_B, SEL_RAD_1),
1515 PINMUX_IPSR_MSEL(IP13_4_3, MSIOF0_SS2_C, SEL_SOF0_2),
1516 PINMUX_IPSR_MSEL(IP13_6_5, STP_ISSYNC_0, SEL_SSP_0),
1517 PINMUX_IPSR_GPSR(IP13_6_5, AVB_COL),
1518 PINMUX_IPSR_MSEL(IP13_6_5, ADICHS1_B, SEL_RAD_1),
1519 PINMUX_IPSR_MSEL(IP13_6_5, MSIOF0_RXD_C, SEL_SOF0_2),
1520 PINMUX_IPSR_MSEL(IP13_9_7, STP_OPWM_0, SEL_SSP_0),
1521 PINMUX_IPSR_GPSR(IP13_9_7, AVB_GTX_CLK),
1522 PINMUX_IPSR_GPSR(IP13_9_7, PWM0_B),
1523 PINMUX_IPSR_MSEL(IP13_9_7, ADICHS2_B, SEL_RAD_1),
1524 PINMUX_IPSR_MSEL(IP13_9_7, MSIOF0_TXD_C, SEL_SOF0_2),
1525 PINMUX_IPSR_GPSR(IP13_10, SD0_CLK),
1526 PINMUX_IPSR_MSEL(IP13_10, SPCLK_B, SEL_QSP_1),
1527 PINMUX_IPSR_GPSR(IP13_11, SD0_CMD),
1528 PINMUX_IPSR_MSEL(IP13_11, MOSI_IO0_B, SEL_QSP_1),
1529 PINMUX_IPSR_GPSR(IP13_12, SD0_DATA0),
1530 PINMUX_IPSR_MSEL(IP13_12, MISO_IO1_B, SEL_QSP_1),
1531 PINMUX_IPSR_GPSR(IP13_13, SD0_DATA1),
1532 PINMUX_IPSR_MSEL(IP13_13, IO2_B, SEL_QSP_1),
1533 PINMUX_IPSR_GPSR(IP13_14, SD0_DATA2),
1534 PINMUX_IPSR_MSEL(IP13_14, IO3_B, SEL_QSP_1),
1535 PINMUX_IPSR_GPSR(IP13_15, SD0_DATA3),
1536 PINMUX_IPSR_MSEL(IP13_15, SSL_B, SEL_QSP_1),
1537 PINMUX_IPSR_GPSR(IP13_18_16, SD0_CD),
1538 PINMUX_IPSR_MSEL(IP13_18_16, MMC_D6_B, SEL_MMC_1),
1539 PINMUX_IPSR_MSEL(IP13_18_16, SIM0_RST_B, SEL_SIM_1),
1540 PINMUX_IPSR_MSEL(IP13_18_16, CAN0_RX_F, SEL_CAN0_5),
1541 PINMUX_IPSR_MSEL(IP13_18_16, SCIFA5_TXD_B, SEL_SCIFA5_1),
1542 PINMUX_IPSR_MSEL(IP13_18_16, TX3_C, SEL_SCIF3_2),
1543 PINMUX_IPSR_GPSR(IP13_21_19, SD0_WP),
1544 PINMUX_IPSR_MSEL(IP13_21_19, MMC_D7_B, SEL_MMC_1),
1545 PINMUX_IPSR_MSEL(IP13_21_19, SIM0_D_B, SEL_SIM_1),
1546 PINMUX_IPSR_MSEL(IP13_21_19, CAN0_TX_F, SEL_CAN0_5),
1547 PINMUX_IPSR_MSEL(IP13_21_19, SCIFA5_RXD_B, SEL_SCIFA5_1),
1548 PINMUX_IPSR_MSEL(IP13_21_19, RX3_C, SEL_SCIF3_2),
1549 PINMUX_IPSR_GPSR(IP13_22, SD1_CMD),
1550 PINMUX_IPSR_MSEL(IP13_22, REMOCON_B, SEL_RCN_1),
1551 PINMUX_IPSR_GPSR(IP13_24_23, SD1_DATA0),
1552 PINMUX_IPSR_MSEL(IP13_24_23, SPEEDIN_B, SEL_RSP_1),
1553 PINMUX_IPSR_GPSR(IP13_25, SD1_DATA1),
1554 PINMUX_IPSR_MSEL(IP13_25, IETX_B, SEL_IEB_1),
1555 PINMUX_IPSR_GPSR(IP13_26, SD1_DATA2),
1556 PINMUX_IPSR_MSEL(IP13_26, IECLK_B, SEL_IEB_1),
1557 PINMUX_IPSR_GPSR(IP13_27, SD1_DATA3),
1558 PINMUX_IPSR_MSEL(IP13_27, IERX_B, SEL_IEB_1),
1559 PINMUX_IPSR_GPSR(IP13_30_28, SD1_CD),
1560 PINMUX_IPSR_GPSR(IP13_30_28, PWM0),
1561 PINMUX_IPSR_GPSR(IP13_30_28, TPU_TO0),
1562 PINMUX_IPSR_MSEL(IP13_30_28, I2C1_SCL_C, SEL_I2C1_2),
1565 PINMUX_IPSR_GPSR(IP14_1_0, SD1_WP),
1566 PINMUX_IPSR_GPSR(IP14_1_0, PWM1_B),
1567 PINMUX_IPSR_MSEL(IP14_1_0, I2C1_SDA_C, SEL_I2C1_2),
1568 PINMUX_IPSR_GPSR(IP14_2, SD2_CLK),
1569 PINMUX_IPSR_GPSR(IP14_2, MMC_CLK),
1570 PINMUX_IPSR_GPSR(IP14_3, SD2_CMD),
1571 PINMUX_IPSR_GPSR(IP14_3, MMC_CMD),
1572 PINMUX_IPSR_GPSR(IP14_4, SD2_DATA0),
1573 PINMUX_IPSR_GPSR(IP14_4, MMC_D0),
1574 PINMUX_IPSR_GPSR(IP14_5, SD2_DATA1),
1575 PINMUX_IPSR_GPSR(IP14_5, MMC_D1),
1576 PINMUX_IPSR_GPSR(IP14_6, SD2_DATA2),
1577 PINMUX_IPSR_GPSR(IP14_6, MMC_D2),
1578 PINMUX_IPSR_GPSR(IP14_7, SD2_DATA3),
1579 PINMUX_IPSR_GPSR(IP14_7, MMC_D3),
1580 PINMUX_IPSR_GPSR(IP14_10_8, SD2_CD),
1581 PINMUX_IPSR_GPSR(IP14_10_8, MMC_D4),
1582 PINMUX_IPSR_MSEL(IP14_10_8, IIC1_SCL_C, SEL_IIC1_2),
1583 PINMUX_IPSR_MSEL(IP14_10_8, TX5_B, SEL_SCIF5_1),
1584 PINMUX_IPSR_MSEL(IP14_10_8, SCIFA5_TXD_C, SEL_SCIFA5_2),
1585 PINMUX_IPSR_GPSR(IP14_13_11, SD2_WP),
1586 PINMUX_IPSR_GPSR(IP14_13_11, MMC_D5),
1587 PINMUX_IPSR_MSEL(IP14_13_11, IIC1_SDA_C, SEL_IIC1_2),
1588 PINMUX_IPSR_MSEL(IP14_13_11, RX5_B, SEL_SCIF5_1),
1589 PINMUX_IPSR_MSEL(IP14_13_11, SCIFA5_RXD_C, SEL_SCIFA5_2),
1590 PINMUX_IPSR_MSEL(IP14_16_14, MSIOF0_SCK, SEL_SOF0_0),
1591 PINMUX_IPSR_MSEL(IP14_16_14, RX2_C, SEL_SCIF2_2),
1592 PINMUX_IPSR_MSEL(IP14_16_14, ADIDATA, SEL_RAD_0),
1593 PINMUX_IPSR_MSEL(IP14_16_14, VI1_CLK_C, SEL_VI1_2),
1594 PINMUX_IPSR_GPSR(IP14_16_14, VI1_G0_B),
1595 PINMUX_IPSR_MSEL(IP14_19_17, MSIOF0_SYNC, SEL_SOF0_0),
1596 PINMUX_IPSR_MSEL(IP14_19_17, TX2_C, SEL_SCIF2_2),
1597 PINMUX_IPSR_MSEL(IP14_19_17, ADICS_SAMP, SEL_RAD_0),
1598 PINMUX_IPSR_MSEL(IP14_19_17, VI1_CLKENB_C, SEL_VI1_2),
1599 PINMUX_IPSR_GPSR(IP14_19_17, VI1_G1_B),
1600 PINMUX_IPSR_MSEL(IP14_22_20, MSIOF0_TXD, SEL_SOF0_0),
1601 PINMUX_IPSR_MSEL(IP14_22_20, ADICLK, SEL_RAD_0),
1602 PINMUX_IPSR_MSEL(IP14_22_20, VI1_FIELD_C, SEL_VI1_2),
1603 PINMUX_IPSR_GPSR(IP14_22_20, VI1_G2_B),
1604 PINMUX_IPSR_MSEL(IP14_25_23, MSIOF0_RXD, SEL_SOF0_0),
1605 PINMUX_IPSR_MSEL(IP14_25_23, ADICHS0, SEL_RAD_0),
1606 PINMUX_IPSR_MSEL(IP14_25_23, VI1_DATA0_C, SEL_VI1_2),
1607 PINMUX_IPSR_GPSR(IP14_25_23, VI1_G3_B),
1608 PINMUX_IPSR_MSEL(IP14_28_26, MSIOF0_SS1, SEL_SOF0_0),
1609 PINMUX_IPSR_MSEL(IP14_28_26, MMC_D6, SEL_MMC_0),
1610 PINMUX_IPSR_MSEL(IP14_28_26, ADICHS1, SEL_RAD_0),
1611 PINMUX_IPSR_MSEL(IP14_28_26, TX0_E, SEL_SCIF0_4),
1612 PINMUX_IPSR_MSEL(IP14_28_26, VI1_HSYNC_N_C, SEL_VI1_2),
1613 PINMUX_IPSR_MSEL(IP14_28_26, IIC0_SCL_C, SEL_IIC0_2),
1614 PINMUX_IPSR_GPSR(IP14_28_26, VI1_G4_B),
1615 PINMUX_IPSR_MSEL(IP14_31_29, MSIOF0_SS2, SEL_SOF0_0),
1616 PINMUX_IPSR_MSEL(IP14_31_29, MMC_D7, SEL_MMC_0),
1617 PINMUX_IPSR_MSEL(IP14_31_29, ADICHS2, SEL_RAD_0),
1618 PINMUX_IPSR_MSEL(IP14_31_29, RX0_E, SEL_SCIF0_4),
1619 PINMUX_IPSR_MSEL(IP14_31_29, VI1_VSYNC_N_C, SEL_VI1_2),
1620 PINMUX_IPSR_MSEL(IP14_31_29, IIC0_SDA_C, SEL_IIC0_2),
1621 PINMUX_IPSR_GPSR(IP14_31_29, VI1_G5_B),
1624 PINMUX_IPSR_MSEL(IP15_1_0, SIM0_RST, SEL_SIM_0),
1625 PINMUX_IPSR_MSEL(IP15_1_0, IETX, SEL_IEB_0),
1626 PINMUX_IPSR_MSEL(IP15_1_0, CAN1_TX_D, SEL_CAN1_3),
1627 PINMUX_IPSR_GPSR(IP15_3_2, SIM0_CLK),
1628 PINMUX_IPSR_MSEL(IP15_3_2, IECLK, SEL_IEB_0),
1629 PINMUX_IPSR_MSEL(IP15_3_2, CAN_CLK_C, SEL_CANCLK_2),
1630 PINMUX_IPSR_MSEL(IP15_5_4, SIM0_D, SEL_SIM_0),
1631 PINMUX_IPSR_MSEL(IP15_5_4, IERX, SEL_IEB_0),
1632 PINMUX_IPSR_MSEL(IP15_5_4, CAN1_RX_D, SEL_CAN1_3),
1633 PINMUX_IPSR_MSEL(IP15_8_6, GPS_CLK, SEL_GPS_0),
1634 PINMUX_IPSR_MSEL(IP15_8_6, DU1_DOTCLKIN_C, SEL_DIS_2),
1635 PINMUX_IPSR_MSEL(IP15_8_6, AUDIO_CLKB_B, SEL_ADG_1),
1636 PINMUX_IPSR_GPSR(IP15_8_6, PWM5_B),
1637 PINMUX_IPSR_MSEL(IP15_8_6, SCIFA3_TXD_C, SEL_SCIFA3_2),
1638 PINMUX_IPSR_MSEL(IP15_11_9, GPS_SIGN, SEL_GPS_0),
1639 PINMUX_IPSR_MSEL(IP15_11_9, TX4_C, SEL_SCIF4_2),
1640 PINMUX_IPSR_MSEL(IP15_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
1641 PINMUX_IPSR_GPSR(IP15_11_9, PWM5),
1642 PINMUX_IPSR_GPSR(IP15_11_9, VI1_G6_B),
1643 PINMUX_IPSR_MSEL(IP15_11_9, SCIFA3_RXD_C, SEL_SCIFA3_2),
1644 PINMUX_IPSR_MSEL(IP15_14_12, GPS_MAG, SEL_GPS_0),
1645 PINMUX_IPSR_MSEL(IP15_14_12, RX4_C, SEL_SCIF4_2),
1646 PINMUX_IPSR_MSEL(IP15_14_12, SCIFA4_RXD_C, SEL_SCIFA4_2),
1647 PINMUX_IPSR_GPSR(IP15_14_12, PWM6),
1648 PINMUX_IPSR_GPSR(IP15_14_12, VI1_G7_B),
1649 PINMUX_IPSR_MSEL(IP15_14_12, SCIFA3_SCK_C, SEL_SCIFA3_2),
1650 PINMUX_IPSR_MSEL(IP15_17_15, HCTS0_N, SEL_HSCIF0_0),
1651 PINMUX_IPSR_MSEL(IP15_17_15, SCIFB0_CTS_N, SEL_SCIFB_0),
1652 PINMUX_IPSR_MSEL(IP15_17_15, GLO_I0_C, SEL_GPS_2),
1653 PINMUX_IPSR_MSEL(IP15_17_15, TCLK1, SEL_TMU1_0),
1654 PINMUX_IPSR_MSEL(IP15_17_15, VI1_DATA1_C, SEL_VI1_2),
1655 PINMUX_IPSR_MSEL(IP15_20_18, HRTS0_N, SEL_HSCIF0_0),
1656 PINMUX_IPSR_MSEL(IP15_20_18, SCIFB0_RTS_N, SEL_SCIFB_0),
1657 PINMUX_IPSR_MSEL(IP15_20_18, GLO_I1_C, SEL_GPS_2),
1658 PINMUX_IPSR_MSEL(IP15_20_18, VI1_DATA2_C, SEL_VI1_2),
1659 PINMUX_IPSR_MSEL(IP15_23_21, HSCK0, SEL_HSCIF0_0),
1660 PINMUX_IPSR_MSEL(IP15_23_21, SCIFB0_SCK, SEL_SCIFB_0),
1661 PINMUX_IPSR_MSEL(IP15_23_21, GLO_Q0_C, SEL_GPS_2),
1662 PINMUX_IPSR_MSEL(IP15_23_21, CAN_CLK, SEL_CANCLK_0),
1663 PINMUX_IPSR_GPSR(IP15_23_21, TCLK2),
1664 PINMUX_IPSR_MSEL(IP15_23_21, VI1_DATA3_C, SEL_VI1_2),
1665 PINMUX_IPSR_MSEL(IP15_26_24, HRX0, SEL_HSCIF0_0),
1666 PINMUX_IPSR_MSEL(IP15_26_24, SCIFB0_RXD, SEL_SCIFB_0),
1667 PINMUX_IPSR_MSEL(IP15_26_24, GLO_Q1_C, SEL_GPS_2),
1668 PINMUX_IPSR_MSEL(IP15_26_24, CAN0_RX_B, SEL_CAN0_1),
1669 PINMUX_IPSR_MSEL(IP15_26_24, VI1_DATA4_C, SEL_VI1_2),
1670 PINMUX_IPSR_MSEL(IP15_29_27, HTX0, SEL_HSCIF0_0),
1671 PINMUX_IPSR_MSEL(IP15_29_27, SCIFB0_TXD, SEL_SCIFB_0),
1672 PINMUX_IPSR_MSEL(IP15_29_27, GLO_SCLK_C, SEL_GPS_2),
1673 PINMUX_IPSR_MSEL(IP15_29_27, CAN0_TX_B, SEL_CAN0_1),
1674 PINMUX_IPSR_MSEL(IP15_29_27, VI1_DATA5_C, SEL_VI1_2),
1677 PINMUX_IPSR_MSEL(IP16_2_0, HRX1, SEL_HSCIF1_0),
1678 PINMUX_IPSR_MSEL(IP16_2_0, SCIFB1_RXD, SEL_SCIFB1_0),
1679 PINMUX_IPSR_GPSR(IP16_2_0, VI1_R0_B),
1680 PINMUX_IPSR_MSEL(IP16_2_0, GLO_SDATA_C, SEL_GPS_2),
1681 PINMUX_IPSR_MSEL(IP16_2_0, VI1_DATA6_C, SEL_VI1_2),
1682 PINMUX_IPSR_MSEL(IP16_5_3, HTX1, SEL_HSCIF1_0),
1683 PINMUX_IPSR_MSEL(IP16_5_3, SCIFB1_TXD, SEL_SCIFB1_0),
1684 PINMUX_IPSR_GPSR(IP16_5_3, VI1_R1_B),
1685 PINMUX_IPSR_MSEL(IP16_5_3, GLO_SS_C, SEL_GPS_2),
1686 PINMUX_IPSR_MSEL(IP16_5_3, VI1_DATA7_C, SEL_VI1_2),
1687 PINMUX_IPSR_MSEL(IP16_7_6, HSCK1, SEL_HSCIF1_0),
1688 PINMUX_IPSR_MSEL(IP16_7_6, SCIFB1_SCK, SEL_SCIFB1_0),
1689 PINMUX_IPSR_GPSR(IP16_7_6, MLB_CLK),
1690 PINMUX_IPSR_MSEL(IP16_7_6, GLO_RFON_C, SEL_GPS_2),
1691 PINMUX_IPSR_MSEL(IP16_9_8, HCTS1_N, SEL_HSCIF1_0),
1692 PINMUX_IPSR_GPSR(IP16_9_8, SCIFB1_CTS_N),
1693 PINMUX_IPSR_GPSR(IP16_9_8, MLB_SIG),
1694 PINMUX_IPSR_MSEL(IP16_9_8, CAN1_TX_B, SEL_CAN1_1),
1695 PINMUX_IPSR_MSEL(IP16_11_10, HRTS1_N, SEL_HSCIF1_0),
1696 PINMUX_IPSR_GPSR(IP16_11_10, SCIFB1_RTS_N),
1697 PINMUX_IPSR_GPSR(IP16_11_10, MLB_DAT),
1698 PINMUX_IPSR_MSEL(IP16_11_10, CAN1_RX_B, SEL_CAN1_1),
1701 static const struct sh_pfc_pin pinmux_pins[] = {
1702 PINMUX_GPIO_GP_ALL(),
1705 /* - ADI -------------------------------------------------------------------- */
1706 static const unsigned int adi_common_pins[] = {
1707 /* ADIDATA, ADICS/SAMP, ADICLK */
1708 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
1710 static const unsigned int adi_common_mux[] = {
1711 /* ADIDATA, ADICS/SAMP, ADICLK */
1712 ADIDATA_MARK, ADICS_SAMP_MARK, ADICLK_MARK,
1714 static const unsigned int adi_chsel0_pins[] = {
1718 static const unsigned int adi_chsel0_mux[] = {
1722 static const unsigned int adi_chsel1_pins[] = {
1726 static const unsigned int adi_chsel1_mux[] = {
1730 static const unsigned int adi_chsel2_pins[] = {
1734 static const unsigned int adi_chsel2_mux[] = {
1738 static const unsigned int adi_common_b_pins[] = {
1739 /* ADIDATA B, ADICS/SAMP B, ADICLK B */
1740 RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
1742 static const unsigned int adi_common_b_mux[] = {
1743 /* ADIDATA B, ADICS/SAMP B, ADICLK B */
1744 ADIDATA_B_MARK, ADICS_SAMP_B_MARK, ADICLK_B_MARK,
1746 static const unsigned int adi_chsel0_b_pins[] = {
1750 static const unsigned int adi_chsel0_b_mux[] = {
1754 static const unsigned int adi_chsel1_b_pins[] = {
1758 static const unsigned int adi_chsel1_b_mux[] = {
1762 static const unsigned int adi_chsel2_b_pins[] = {
1766 static const unsigned int adi_chsel2_b_mux[] = {
1771 /* - Audio Clock ------------------------------------------------------------ */
1772 static const unsigned int audio_clk_a_pins[] = {
1777 static const unsigned int audio_clk_a_mux[] = {
1781 static const unsigned int audio_clk_b_pins[] = {
1786 static const unsigned int audio_clk_b_mux[] = {
1790 static const unsigned int audio_clk_b_b_pins[] = {
1795 static const unsigned int audio_clk_b_b_mux[] = {
1799 static const unsigned int audio_clk_c_pins[] = {
1804 static const unsigned int audio_clk_c_mux[] = {
1808 static const unsigned int audio_clkout_pins[] = {
1813 static const unsigned int audio_clkout_mux[] = {
1817 /* - AVB -------------------------------------------------------------------- */
1818 static const unsigned int avb_link_pins[] = {
1821 static const unsigned int avb_link_mux[] = {
1824 static const unsigned int avb_magic_pins[] = {
1827 static const unsigned int avb_magic_mux[] = {
1830 static const unsigned int avb_phy_int_pins[] = {
1833 static const unsigned int avb_phy_int_mux[] = {
1836 static const unsigned int avb_mdio_pins[] = {
1837 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 9),
1839 static const unsigned int avb_mdio_mux[] = {
1840 AVB_MDC_MARK, AVB_MDIO_MARK,
1842 static const unsigned int avb_mii_pins[] = {
1843 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
1846 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1849 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 10),
1850 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
1851 RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 29),
1853 static const unsigned int avb_mii_mux[] = {
1854 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1857 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1860 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1861 AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
1862 AVB_TX_CLK_MARK, AVB_COL_MARK,
1864 static const unsigned int avb_gmii_pins[] = {
1865 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
1866 RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
1867 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
1869 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1870 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1871 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1873 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 10),
1874 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 17),
1875 RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 28),
1878 static const unsigned int avb_gmii_mux[] = {
1879 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1880 AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
1881 AVB_TXD6_MARK, AVB_TXD7_MARK,
1883 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1884 AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
1885 AVB_RXD6_MARK, AVB_RXD7_MARK,
1887 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1888 AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
1889 AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
1893 /* - CAN -------------------------------------------------------------------- */
1895 static const unsigned int can0_data_pins[] = {
1897 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 29),
1900 static const unsigned int can0_data_mux[] = {
1901 CAN0_TX_MARK, CAN0_RX_MARK,
1904 static const unsigned int can0_data_b_pins[] = {
1906 RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 3),
1909 static const unsigned int can0_data_b_mux[] = {
1910 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1913 static const unsigned int can0_data_c_pins[] = {
1915 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
1918 static const unsigned int can0_data_c_mux[] = {
1919 CAN0_TX_C_MARK, CAN0_RX_C_MARK,
1922 static const unsigned int can0_data_d_pins[] = {
1924 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27),
1927 static const unsigned int can0_data_d_mux[] = {
1928 CAN0_TX_D_MARK, CAN0_RX_D_MARK,
1931 static const unsigned int can0_data_e_pins[] = {
1933 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 28),
1936 static const unsigned int can0_data_e_mux[] = {
1937 CAN0_TX_E_MARK, CAN0_RX_E_MARK,
1940 static const unsigned int can0_data_f_pins[] = {
1942 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
1945 static const unsigned int can0_data_f_mux[] = {
1946 CAN0_TX_F_MARK, CAN0_RX_F_MARK,
1949 static const unsigned int can1_data_pins[] = {
1951 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 20),
1954 static const unsigned int can1_data_mux[] = {
1955 CAN1_TX_MARK, CAN1_RX_MARK,
1958 static const unsigned int can1_data_b_pins[] = {
1960 RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
1963 static const unsigned int can1_data_b_mux[] = {
1964 CAN1_TX_B_MARK, CAN1_RX_B_MARK,
1967 static const unsigned int can1_data_c_pins[] = {
1969 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 19),
1972 static const unsigned int can1_data_c_mux[] = {
1973 CAN1_TX_C_MARK, CAN1_RX_C_MARK,
1976 static const unsigned int can1_data_d_pins[] = {
1978 RCAR_GP_PIN(4, 29), RCAR_GP_PIN(4, 31),
1981 static const unsigned int can1_data_d_mux[] = {
1982 CAN1_TX_D_MARK, CAN1_RX_D_MARK,
1985 static const unsigned int can_clk_pins[] = {
1990 static const unsigned int can_clk_mux[] = {
1994 static const unsigned int can_clk_b_pins[] = {
1999 static const unsigned int can_clk_b_mux[] = {
2003 static const unsigned int can_clk_c_pins[] = {
2008 static const unsigned int can_clk_c_mux[] = {
2012 static const unsigned int can_clk_d_pins[] = {
2017 static const unsigned int can_clk_d_mux[] = {
2021 /* - DU --------------------------------------------------------------------- */
2022 static const unsigned int du_rgb666_pins[] = {
2023 /* R[7:2], G[7:2], B[7:2] */
2024 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 5),
2025 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2),
2026 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
2027 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10),
2028 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
2029 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
2031 static const unsigned int du_rgb666_mux[] = {
2032 DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
2033 DU1_DR3_MARK, DU1_DR2_MARK,
2034 DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
2035 DU1_DG3_MARK, DU1_DG2_MARK,
2036 DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
2037 DU1_DB3_MARK, DU1_DB2_MARK,
2039 static const unsigned int du_rgb888_pins[] = {
2040 /* R[7:0], G[7:0], B[7:0] */
2041 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 5),
2042 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2),
2043 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
2044 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
2045 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10),
2046 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
2047 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
2048 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
2049 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
2051 static const unsigned int du_rgb888_mux[] = {
2052 DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
2053 DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
2054 DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
2055 DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
2056 DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
2057 DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
2059 static const unsigned int du_clk_out_0_pins[] = {
2063 static const unsigned int du_clk_out_0_mux[] = {
2066 static const unsigned int du_clk_out_1_pins[] = {
2070 static const unsigned int du_clk_out_1_mux[] = {
2073 static const unsigned int du_sync_pins[] = {
2074 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2075 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27),
2077 static const unsigned int du_sync_mux[] = {
2078 DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK
2080 static const unsigned int du_oddf_pins[] = {
2081 /* EXDISP/EXODDF/EXCDE */
2084 static const unsigned int du_oddf_mux[] = {
2085 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
2087 static const unsigned int du_cde_pins[] = {
2091 static const unsigned int du_cde_mux[] = {
2094 static const unsigned int du_disp_pins[] = {
2098 static const unsigned int du_disp_mux[] = {
2101 static const unsigned int du0_clk_in_pins[] = {
2105 static const unsigned int du0_clk_in_mux[] = {
2108 static const unsigned int du1_clk_in_pins[] = {
2112 static const unsigned int du1_clk_in_mux[] = {
2115 static const unsigned int du1_clk_in_b_pins[] = {
2119 static const unsigned int du1_clk_in_b_mux[] = {
2120 DU1_DOTCLKIN_B_MARK,
2122 static const unsigned int du1_clk_in_c_pins[] = {
2126 static const unsigned int du1_clk_in_c_mux[] = {
2127 DU1_DOTCLKIN_C_MARK,
2129 /* - ETH -------------------------------------------------------------------- */
2130 static const unsigned int eth_link_pins[] = {
2134 static const unsigned int eth_link_mux[] = {
2137 static const unsigned int eth_magic_pins[] = {
2141 static const unsigned int eth_magic_mux[] = {
2144 static const unsigned int eth_mdio_pins[] = {
2146 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 13),
2148 static const unsigned int eth_mdio_mux[] = {
2149 ETH_MDC_MARK, ETH_MDIO_MARK,
2151 static const unsigned int eth_rmii_pins[] = {
2152 /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
2153 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 15),
2154 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 20),
2155 RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 19),
2157 static const unsigned int eth_rmii_mux[] = {
2158 ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
2159 ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK,
2162 /* - HSCIF0 ----------------------------------------------------------------- */
2163 static const unsigned int hscif0_data_pins[] = {
2165 RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4),
2167 static const unsigned int hscif0_data_mux[] = {
2168 HRX0_MARK, HTX0_MARK,
2170 static const unsigned int hscif0_clk_pins[] = {
2174 static const unsigned int hscif0_clk_mux[] = {
2177 static const unsigned int hscif0_ctrl_pins[] = {
2179 RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0),
2181 static const unsigned int hscif0_ctrl_mux[] = {
2182 HRTS0_N_MARK, HCTS0_N_MARK,
2184 static const unsigned int hscif0_data_b_pins[] = {
2186 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 15),
2188 static const unsigned int hscif0_data_b_mux[] = {
2189 HRX0_B_MARK, HTX0_B_MARK,
2191 static const unsigned int hscif0_ctrl_b_pins[] = {
2193 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
2195 static const unsigned int hscif0_ctrl_b_mux[] = {
2196 HRTS0_N_B_MARK, HCTS0_N_B_MARK,
2198 static const unsigned int hscif0_data_c_pins[] = {
2200 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
2202 static const unsigned int hscif0_data_c_mux[] = {
2203 HRX0_C_MARK, HTX0_C_MARK,
2205 static const unsigned int hscif0_clk_c_pins[] = {
2209 static const unsigned int hscif0_clk_c_mux[] = {
2212 /* - HSCIF1 ----------------------------------------------------------------- */
2213 static const unsigned int hscif1_data_pins[] = {
2215 RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
2217 static const unsigned int hscif1_data_mux[] = {
2218 HRX1_MARK, HTX1_MARK,
2220 static const unsigned int hscif1_clk_pins[] = {
2224 static const unsigned int hscif1_clk_mux[] = {
2227 static const unsigned int hscif1_ctrl_pins[] = {
2229 RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8),
2231 static const unsigned int hscif1_ctrl_mux[] = {
2232 HRTS1_N_MARK, HCTS1_N_MARK,
2234 static const unsigned int hscif1_data_b_pins[] = {
2236 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
2238 static const unsigned int hscif1_data_b_mux[] = {
2239 HRX1_B_MARK, HTX1_B_MARK,
2241 static const unsigned int hscif1_data_c_pins[] = {
2243 RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
2245 static const unsigned int hscif1_data_c_mux[] = {
2246 HRX1_C_MARK, HTX1_C_MARK,
2248 static const unsigned int hscif1_clk_c_pins[] = {
2252 static const unsigned int hscif1_clk_c_mux[] = {
2255 static const unsigned int hscif1_ctrl_c_pins[] = {
2257 RCAR_GP_PIN(7, 18), RCAR_GP_PIN(7, 17),
2259 static const unsigned int hscif1_ctrl_c_mux[] = {
2260 HRTS1_N_C_MARK, HCTS1_N_C_MARK,
2262 static const unsigned int hscif1_data_d_pins[] = {
2264 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18),
2266 static const unsigned int hscif1_data_d_mux[] = {
2267 HRX1_D_MARK, HTX1_D_MARK,
2269 static const unsigned int hscif1_data_e_pins[] = {
2271 RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
2273 static const unsigned int hscif1_data_e_mux[] = {
2274 HRX1_C_MARK, HTX1_C_MARK,
2276 static const unsigned int hscif1_clk_e_pins[] = {
2280 static const unsigned int hscif1_clk_e_mux[] = {
2283 static const unsigned int hscif1_ctrl_e_pins[] = {
2285 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 7),
2287 static const unsigned int hscif1_ctrl_e_mux[] = {
2288 HRTS1_N_E_MARK, HCTS1_N_E_MARK,
2290 /* - HSCIF2 ----------------------------------------------------------------- */
2291 static const unsigned int hscif2_data_pins[] = {
2293 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
2295 static const unsigned int hscif2_data_mux[] = {
2296 HRX2_MARK, HTX2_MARK,
2298 static const unsigned int hscif2_clk_pins[] = {
2302 static const unsigned int hscif2_clk_mux[] = {
2305 static const unsigned int hscif2_ctrl_pins[] = {
2307 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
2309 static const unsigned int hscif2_ctrl_mux[] = {
2310 HRTS2_N_MARK, HCTS2_N_MARK,
2312 static const unsigned int hscif2_data_b_pins[] = {
2314 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 22),
2316 static const unsigned int hscif2_data_b_mux[] = {
2317 HRX2_B_MARK, HTX2_B_MARK,
2319 static const unsigned int hscif2_ctrl_b_pins[] = {
2321 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 21),
2323 static const unsigned int hscif2_ctrl_b_mux[] = {
2324 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2326 static const unsigned int hscif2_data_c_pins[] = {
2328 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
2330 static const unsigned int hscif2_data_c_mux[] = {
2331 HRX2_C_MARK, HTX2_C_MARK,
2333 static const unsigned int hscif2_clk_c_pins[] = {
2337 static const unsigned int hscif2_clk_c_mux[] = {
2340 static const unsigned int hscif2_data_d_pins[] = {
2342 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(5, 31),
2344 static const unsigned int hscif2_data_d_mux[] = {
2345 HRX2_B_MARK, HTX2_D_MARK,
2347 /* - I2C0 ------------------------------------------------------------------- */
2348 static const unsigned int i2c0_pins[] = {
2350 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2352 static const unsigned int i2c0_mux[] = {
2353 I2C0_SCL_MARK, I2C0_SDA_MARK,
2355 static const unsigned int i2c0_b_pins[] = {
2357 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
2359 static const unsigned int i2c0_b_mux[] = {
2360 I2C0_SCL_B_MARK, I2C0_SDA_B_MARK,
2362 static const unsigned int i2c0_c_pins[] = {
2364 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(1, 1),
2366 static const unsigned int i2c0_c_mux[] = {
2367 I2C0_SCL_C_MARK, I2C0_SDA_C_MARK,
2369 /* - I2C1 ------------------------------------------------------------------- */
2370 static const unsigned int i2c1_pins[] = {
2372 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
2374 static const unsigned int i2c1_mux[] = {
2375 I2C1_SCL_MARK, I2C1_SDA_MARK,
2377 static const unsigned int i2c1_b_pins[] = {
2379 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
2381 static const unsigned int i2c1_b_mux[] = {
2382 I2C1_SCL_B_MARK, I2C1_SDA_B_MARK,
2384 static const unsigned int i2c1_c_pins[] = {
2386 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
2388 static const unsigned int i2c1_c_mux[] = {
2389 I2C1_SCL_C_MARK, I2C1_SDA_C_MARK,
2391 static const unsigned int i2c1_d_pins[] = {
2393 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
2395 static const unsigned int i2c1_d_mux[] = {
2396 I2C1_SCL_D_MARK, I2C1_SDA_D_MARK,
2398 static const unsigned int i2c1_e_pins[] = {
2400 RCAR_GP_PIN(7, 15), RCAR_GP_PIN(7, 16),
2402 static const unsigned int i2c1_e_mux[] = {
2403 I2C1_SCL_E_MARK, I2C1_SDA_E_MARK,
2405 /* - I2C2 ------------------------------------------------------------------- */
2406 static const unsigned int i2c2_pins[] = {
2408 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
2410 static const unsigned int i2c2_mux[] = {
2411 I2C2_SCL_MARK, I2C2_SDA_MARK,
2413 static const unsigned int i2c2_b_pins[] = {
2415 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 29),
2417 static const unsigned int i2c2_b_mux[] = {
2418 I2C2_SCL_B_MARK, I2C2_SDA_B_MARK,
2420 static const unsigned int i2c2_c_pins[] = {
2422 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2424 static const unsigned int i2c2_c_mux[] = {
2425 I2C2_SCL_C_MARK, I2C2_SDA_C_MARK,
2427 static const unsigned int i2c2_d_pins[] = {
2429 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
2431 static const unsigned int i2c2_d_mux[] = {
2432 I2C2_SCL_D_MARK, I2C2_SDA_D_MARK,
2434 /* - I2C3 ------------------------------------------------------------------- */
2435 static const unsigned int i2c3_pins[] = {
2437 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2439 static const unsigned int i2c3_mux[] = {
2440 I2C3_SCL_MARK, I2C3_SDA_MARK,
2442 static const unsigned int i2c3_b_pins[] = {
2444 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
2446 static const unsigned int i2c3_b_mux[] = {
2447 I2C3_SCL_B_MARK, I2C3_SDA_B_MARK,
2449 static const unsigned int i2c3_c_pins[] = {
2451 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
2453 static const unsigned int i2c3_c_mux[] = {
2454 I2C3_SCL_C_MARK, I2C3_SDA_C_MARK,
2456 static const unsigned int i2c3_d_pins[] = {
2458 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
2460 static const unsigned int i2c3_d_mux[] = {
2461 I2C3_SCL_D_MARK, I2C3_SDA_D_MARK,
2463 /* - I2C4 ------------------------------------------------------------------- */
2464 static const unsigned int i2c4_pins[] = {
2466 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
2468 static const unsigned int i2c4_mux[] = {
2469 I2C4_SCL_MARK, I2C4_SDA_MARK,
2471 static const unsigned int i2c4_b_pins[] = {
2473 RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
2475 static const unsigned int i2c4_b_mux[] = {
2476 I2C4_SCL_B_MARK, I2C4_SDA_B_MARK,
2478 static const unsigned int i2c4_c_pins[] = {
2480 RCAR_GP_PIN(7, 13), RCAR_GP_PIN(7, 14),
2482 static const unsigned int i2c4_c_mux[] = {
2483 I2C4_SCL_C_MARK, I2C4_SDA_C_MARK,
2485 /* - I2C7 ------------------------------------------------------------------- */
2486 static const unsigned int i2c7_pins[] = {
2488 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2490 static const unsigned int i2c7_mux[] = {
2491 IIC0_SCL_MARK, IIC0_SDA_MARK,
2493 static const unsigned int i2c7_b_pins[] = {
2495 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
2497 static const unsigned int i2c7_b_mux[] = {
2498 IIC0_SCL_B_MARK, IIC0_SDA_B_MARK,
2500 static const unsigned int i2c7_c_pins[] = {
2502 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
2504 static const unsigned int i2c7_c_mux[] = {
2505 IIC0_SCL_C_MARK, IIC0_SDA_C_MARK,
2507 /* - I2C8 ------------------------------------------------------------------- */
2508 static const unsigned int i2c8_pins[] = {
2510 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
2512 static const unsigned int i2c8_mux[] = {
2513 IIC1_SCL_MARK, IIC1_SDA_MARK,
2515 static const unsigned int i2c8_b_pins[] = {
2517 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
2519 static const unsigned int i2c8_b_mux[] = {
2520 IIC1_SCL_B_MARK, IIC1_SDA_B_MARK,
2522 static const unsigned int i2c8_c_pins[] = {
2524 RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
2526 static const unsigned int i2c8_c_mux[] = {
2527 IIC1_SCL_C_MARK, IIC1_SDA_C_MARK,
2529 /* - INTC ------------------------------------------------------------------- */
2530 static const unsigned int intc_irq0_pins[] = {
2534 static const unsigned int intc_irq0_mux[] = {
2537 static const unsigned int intc_irq1_pins[] = {
2541 static const unsigned int intc_irq1_mux[] = {
2544 static const unsigned int intc_irq2_pins[] = {
2548 static const unsigned int intc_irq2_mux[] = {
2551 static const unsigned int intc_irq3_pins[] = {
2555 static const unsigned int intc_irq3_mux[] = {
2558 /* - MLB+ ------------------------------------------------------------------- */
2559 static const unsigned int mlb_3pin_pins[] = {
2560 RCAR_GP_PIN(7, 7), RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
2562 static const unsigned int mlb_3pin_mux[] = {
2563 MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
2565 /* - MMCIF ------------------------------------------------------------------ */
2566 static const unsigned int mmc_data1_pins[] = {
2570 static const unsigned int mmc_data1_mux[] = {
2573 static const unsigned int mmc_data4_pins[] = {
2575 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2576 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2578 static const unsigned int mmc_data4_mux[] = {
2579 MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2581 static const unsigned int mmc_data8_pins[] = {
2583 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2584 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2585 RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
2586 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
2588 static const unsigned int mmc_data8_mux[] = {
2589 MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2590 MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
2592 static const unsigned int mmc_ctrl_pins[] = {
2594 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
2596 static const unsigned int mmc_ctrl_mux[] = {
2597 MMC_CLK_MARK, MMC_CMD_MARK,
2599 /* - MSIOF0 ----------------------------------------------------------------- */
2600 static const unsigned int msiof0_clk_pins[] = {
2604 static const unsigned int msiof0_clk_mux[] = {
2607 static const unsigned int msiof0_sync_pins[] = {
2611 static const unsigned int msiof0_sync_mux[] = {
2614 static const unsigned int msiof0_ss1_pins[] = {
2618 static const unsigned int msiof0_ss1_mux[] = {
2621 static const unsigned int msiof0_ss2_pins[] = {
2625 static const unsigned int msiof0_ss2_mux[] = {
2628 static const unsigned int msiof0_rx_pins[] = {
2632 static const unsigned int msiof0_rx_mux[] = {
2635 static const unsigned int msiof0_tx_pins[] = {
2639 static const unsigned int msiof0_tx_mux[] = {
2643 static const unsigned int msiof0_clk_b_pins[] = {
2647 static const unsigned int msiof0_clk_b_mux[] = {
2650 static const unsigned int msiof0_sync_b_pins[] = {
2654 static const unsigned int msiof0_sync_b_mux[] = {
2657 static const unsigned int msiof0_ss1_b_pins[] = {
2661 static const unsigned int msiof0_ss1_b_mux[] = {
2664 static const unsigned int msiof0_ss2_b_pins[] = {
2668 static const unsigned int msiof0_ss2_b_mux[] = {
2671 static const unsigned int msiof0_rx_b_pins[] = {
2675 static const unsigned int msiof0_rx_b_mux[] = {
2678 static const unsigned int msiof0_tx_b_pins[] = {
2682 static const unsigned int msiof0_tx_b_mux[] = {
2686 static const unsigned int msiof0_clk_c_pins[] = {
2690 static const unsigned int msiof0_clk_c_mux[] = {
2693 static const unsigned int msiof0_sync_c_pins[] = {
2697 static const unsigned int msiof0_sync_c_mux[] = {
2700 static const unsigned int msiof0_ss1_c_pins[] = {
2704 static const unsigned int msiof0_ss1_c_mux[] = {
2707 static const unsigned int msiof0_ss2_c_pins[] = {
2711 static const unsigned int msiof0_ss2_c_mux[] = {
2714 static const unsigned int msiof0_rx_c_pins[] = {
2718 static const unsigned int msiof0_rx_c_mux[] = {
2721 static const unsigned int msiof0_tx_c_pins[] = {
2725 static const unsigned int msiof0_tx_c_mux[] = {
2728 /* - MSIOF1 ----------------------------------------------------------------- */
2729 static const unsigned int msiof1_clk_pins[] = {
2733 static const unsigned int msiof1_clk_mux[] = {
2736 static const unsigned int msiof1_sync_pins[] = {
2740 static const unsigned int msiof1_sync_mux[] = {
2743 static const unsigned int msiof1_ss1_pins[] = {
2747 static const unsigned int msiof1_ss1_mux[] = {
2750 static const unsigned int msiof1_ss2_pins[] = {
2754 static const unsigned int msiof1_ss2_mux[] = {
2757 static const unsigned int msiof1_rx_pins[] = {
2761 static const unsigned int msiof1_rx_mux[] = {
2764 static const unsigned int msiof1_tx_pins[] = {
2768 static const unsigned int msiof1_tx_mux[] = {
2772 static const unsigned int msiof1_clk_b_pins[] = {
2776 static const unsigned int msiof1_clk_b_mux[] = {
2779 static const unsigned int msiof1_sync_b_pins[] = {
2783 static const unsigned int msiof1_sync_b_mux[] = {
2786 static const unsigned int msiof1_ss1_b_pins[] = {
2790 static const unsigned int msiof1_ss1_b_mux[] = {
2793 static const unsigned int msiof1_ss2_b_pins[] = {
2797 static const unsigned int msiof1_ss2_b_mux[] = {
2800 static const unsigned int msiof1_rx_b_pins[] = {
2804 static const unsigned int msiof1_rx_b_mux[] = {
2807 static const unsigned int msiof1_tx_b_pins[] = {
2811 static const unsigned int msiof1_tx_b_mux[] = {
2815 static const unsigned int msiof1_clk_c_pins[] = {
2819 static const unsigned int msiof1_clk_c_mux[] = {
2822 static const unsigned int msiof1_sync_c_pins[] = {
2826 static const unsigned int msiof1_sync_c_mux[] = {
2829 static const unsigned int msiof1_rx_c_pins[] = {
2833 static const unsigned int msiof1_rx_c_mux[] = {
2836 static const unsigned int msiof1_tx_c_pins[] = {
2840 static const unsigned int msiof1_tx_c_mux[] = {
2844 static const unsigned int msiof1_clk_d_pins[] = {
2848 static const unsigned int msiof1_clk_d_mux[] = {
2851 static const unsigned int msiof1_sync_d_pins[] = {
2855 static const unsigned int msiof1_sync_d_mux[] = {
2858 static const unsigned int msiof1_ss1_d_pins[] = {
2862 static const unsigned int msiof1_ss1_d_mux[] = {
2865 static const unsigned int msiof1_rx_d_pins[] = {
2869 static const unsigned int msiof1_rx_d_mux[] = {
2872 static const unsigned int msiof1_tx_d_pins[] = {
2876 static const unsigned int msiof1_tx_d_mux[] = {
2880 static const unsigned int msiof1_clk_e_pins[] = {
2884 static const unsigned int msiof1_clk_e_mux[] = {
2887 static const unsigned int msiof1_sync_e_pins[] = {
2891 static const unsigned int msiof1_sync_e_mux[] = {
2894 static const unsigned int msiof1_rx_e_pins[] = {
2898 static const unsigned int msiof1_rx_e_mux[] = {
2901 static const unsigned int msiof1_tx_e_pins[] = {
2905 static const unsigned int msiof1_tx_e_mux[] = {
2908 /* - MSIOF2 ----------------------------------------------------------------- */
2909 static const unsigned int msiof2_clk_pins[] = {
2913 static const unsigned int msiof2_clk_mux[] = {
2916 static const unsigned int msiof2_sync_pins[] = {
2920 static const unsigned int msiof2_sync_mux[] = {
2923 static const unsigned int msiof2_ss1_pins[] = {
2927 static const unsigned int msiof2_ss1_mux[] = {
2930 static const unsigned int msiof2_ss2_pins[] = {
2934 static const unsigned int msiof2_ss2_mux[] = {
2937 static const unsigned int msiof2_rx_pins[] = {
2941 static const unsigned int msiof2_rx_mux[] = {
2944 static const unsigned int msiof2_tx_pins[] = {
2948 static const unsigned int msiof2_tx_mux[] = {
2952 static const unsigned int msiof2_clk_b_pins[] = {
2956 static const unsigned int msiof2_clk_b_mux[] = {
2959 static const unsigned int msiof2_sync_b_pins[] = {
2963 static const unsigned int msiof2_sync_b_mux[] = {
2966 static const unsigned int msiof2_ss1_b_pins[] = {
2970 static const unsigned int msiof2_ss1_b_mux[] = {
2973 static const unsigned int msiof2_ss2_b_pins[] = {
2977 static const unsigned int msiof2_ss2_b_mux[] = {
2980 static const unsigned int msiof2_rx_b_pins[] = {
2984 static const unsigned int msiof2_rx_b_mux[] = {
2987 static const unsigned int msiof2_tx_b_pins[] = {
2991 static const unsigned int msiof2_tx_b_mux[] = {
2995 static const unsigned int msiof2_clk_c_pins[] = {
2999 static const unsigned int msiof2_clk_c_mux[] = {
3002 static const unsigned int msiof2_sync_c_pins[] = {
3006 static const unsigned int msiof2_sync_c_mux[] = {
3009 static const unsigned int msiof2_rx_c_pins[] = {
3013 static const unsigned int msiof2_rx_c_mux[] = {
3016 static const unsigned int msiof2_tx_c_pins[] = {
3020 static const unsigned int msiof2_tx_c_mux[] = {
3024 static const unsigned int msiof2_clk_d_pins[] = {
3028 static const unsigned int msiof2_clk_d_mux[] = {
3031 static const unsigned int msiof2_sync_d_pins[] = {
3035 static const unsigned int msiof2_sync_d_mux[] = {
3038 static const unsigned int msiof2_ss1_d_pins[] = {
3042 static const unsigned int msiof2_ss1_d_mux[] = {
3045 static const unsigned int msiof2_ss2_d_pins[] = {
3049 static const unsigned int msiof2_ss2_d_mux[] = {
3052 static const unsigned int msiof2_rx_d_pins[] = {
3056 static const unsigned int msiof2_rx_d_mux[] = {
3059 static const unsigned int msiof2_tx_d_pins[] = {
3063 static const unsigned int msiof2_tx_d_mux[] = {
3067 static const unsigned int msiof2_clk_e_pins[] = {
3071 static const unsigned int msiof2_clk_e_mux[] = {
3074 static const unsigned int msiof2_sync_e_pins[] = {
3078 static const unsigned int msiof2_sync_e_mux[] = {
3081 static const unsigned int msiof2_rx_e_pins[] = {
3085 static const unsigned int msiof2_rx_e_mux[] = {
3088 static const unsigned int msiof2_tx_e_pins[] = {
3092 static const unsigned int msiof2_tx_e_mux[] = {
3095 /* - PWM -------------------------------------------------------------------- */
3096 static const unsigned int pwm0_pins[] = {
3099 static const unsigned int pwm0_mux[] = {
3102 static const unsigned int pwm0_b_pins[] = {
3105 static const unsigned int pwm0_b_mux[] = {
3108 static const unsigned int pwm1_pins[] = {
3111 static const unsigned int pwm1_mux[] = {
3114 static const unsigned int pwm1_b_pins[] = {
3117 static const unsigned int pwm1_b_mux[] = {
3120 static const unsigned int pwm2_pins[] = {
3123 static const unsigned int pwm2_mux[] = {
3126 static const unsigned int pwm2_b_pins[] = {
3129 static const unsigned int pwm2_b_mux[] = {
3132 static const unsigned int pwm3_pins[] = {
3135 static const unsigned int pwm3_mux[] = {
3138 static const unsigned int pwm4_pins[] = {
3141 static const unsigned int pwm4_mux[] = {
3144 static const unsigned int pwm4_b_pins[] = {
3147 static const unsigned int pwm4_b_mux[] = {
3150 static const unsigned int pwm5_pins[] = {
3153 static const unsigned int pwm5_mux[] = {
3156 static const unsigned int pwm5_b_pins[] = {
3159 static const unsigned int pwm5_b_mux[] = {
3162 static const unsigned int pwm6_pins[] = {
3165 static const unsigned int pwm6_mux[] = {
3168 /* - QSPI ------------------------------------------------------------------- */
3169 static const unsigned int qspi_ctrl_pins[] = {
3171 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
3173 static const unsigned int qspi_ctrl_mux[] = {
3174 SPCLK_MARK, SSL_MARK,
3176 static const unsigned int qspi_data2_pins[] = {
3177 /* MOSI_IO0, MISO_IO1 */
3178 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3180 static const unsigned int qspi_data2_mux[] = {
3181 MOSI_IO0_MARK, MISO_IO1_MARK,
3183 static const unsigned int qspi_data4_pins[] = {
3184 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
3185 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3188 static const unsigned int qspi_data4_mux[] = {
3189 MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
3192 static const unsigned int qspi_ctrl_b_pins[] = {
3194 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 5),
3196 static const unsigned int qspi_ctrl_b_mux[] = {
3197 SPCLK_B_MARK, SSL_B_MARK,
3199 static const unsigned int qspi_data2_b_pins[] = {
3200 /* MOSI_IO0, MISO_IO1 */
3201 RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2),
3203 static const unsigned int qspi_data2_b_mux[] = {
3204 MOSI_IO0_B_MARK, MISO_IO1_B_MARK,
3206 static const unsigned int qspi_data4_b_pins[] = {
3207 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
3208 RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
3211 static const unsigned int qspi_data4_b_mux[] = {
3212 SPCLK_B_MARK, MOSI_IO0_B_MARK, MISO_IO1_B_MARK,
3213 IO2_B_MARK, IO3_B_MARK, SSL_B_MARK,
3215 /* - SCIF0 ------------------------------------------------------------------ */
3216 static const unsigned int scif0_data_pins[] = {
3218 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
3220 static const unsigned int scif0_data_mux[] = {
3223 static const unsigned int scif0_data_b_pins[] = {
3225 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
3227 static const unsigned int scif0_data_b_mux[] = {
3228 RX0_B_MARK, TX0_B_MARK,
3230 static const unsigned int scif0_data_c_pins[] = {
3232 RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 25),
3234 static const unsigned int scif0_data_c_mux[] = {
3235 RX0_C_MARK, TX0_C_MARK,
3237 static const unsigned int scif0_data_d_pins[] = {
3239 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22),
3241 static const unsigned int scif0_data_d_mux[] = {
3242 RX0_D_MARK, TX0_D_MARK,
3244 static const unsigned int scif0_data_e_pins[] = {
3246 RCAR_GP_PIN(6, 29), RCAR_GP_PIN(6, 28),
3248 static const unsigned int scif0_data_e_mux[] = {
3249 RX0_E_MARK, TX0_E_MARK,
3251 /* - SCIF1 ------------------------------------------------------------------ */
3252 static const unsigned int scif1_data_pins[] = {
3254 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
3256 static const unsigned int scif1_data_mux[] = {
3259 static const unsigned int scif1_data_b_pins[] = {
3261 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
3263 static const unsigned int scif1_data_b_mux[] = {
3264 RX1_B_MARK, TX1_B_MARK,
3266 static const unsigned int scif1_clk_b_pins[] = {
3270 static const unsigned int scif1_clk_b_mux[] = {
3273 static const unsigned int scif1_data_c_pins[] = {
3275 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 27),
3277 static const unsigned int scif1_data_c_mux[] = {
3278 RX1_C_MARK, TX1_C_MARK,
3280 static const unsigned int scif1_data_d_pins[] = {
3282 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
3284 static const unsigned int scif1_data_d_mux[] = {
3285 RX1_D_MARK, TX1_D_MARK,
3287 /* - SCIF2 ------------------------------------------------------------------ */
3288 static const unsigned int scif2_data_pins[] = {
3290 RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31),
3292 static const unsigned int scif2_data_mux[] = {
3295 static const unsigned int scif2_data_b_pins[] = {
3297 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
3299 static const unsigned int scif2_data_b_mux[] = {
3300 RX2_B_MARK, TX2_B_MARK,
3302 static const unsigned int scif2_clk_b_pins[] = {
3306 static const unsigned int scif2_clk_b_mux[] = {
3309 static const unsigned int scif2_data_c_pins[] = {
3311 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3313 static const unsigned int scif2_data_c_mux[] = {
3314 RX2_C_MARK, TX2_C_MARK,
3316 static const unsigned int scif2_data_e_pins[] = {
3318 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
3320 static const unsigned int scif2_data_e_mux[] = {
3321 RX2_E_MARK, TX2_E_MARK,
3323 /* - SCIF3 ------------------------------------------------------------------ */
3324 static const unsigned int scif3_data_pins[] = {
3326 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
3328 static const unsigned int scif3_data_mux[] = {
3331 static const unsigned int scif3_clk_pins[] = {
3335 static const unsigned int scif3_clk_mux[] = {
3338 static const unsigned int scif3_data_b_pins[] = {
3340 RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 26),
3342 static const unsigned int scif3_data_b_mux[] = {
3343 RX3_B_MARK, TX3_B_MARK,
3345 static const unsigned int scif3_clk_b_pins[] = {
3349 static const unsigned int scif3_clk_b_mux[] = {
3352 static const unsigned int scif3_data_c_pins[] = {
3354 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
3356 static const unsigned int scif3_data_c_mux[] = {
3357 RX3_C_MARK, TX3_C_MARK,
3359 static const unsigned int scif3_data_d_pins[] = {
3361 RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 26),
3363 static const unsigned int scif3_data_d_mux[] = {
3364 RX3_D_MARK, TX3_D_MARK,
3366 /* - SCIF4 ------------------------------------------------------------------ */
3367 static const unsigned int scif4_data_pins[] = {
3369 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1),
3371 static const unsigned int scif4_data_mux[] = {
3374 static const unsigned int scif4_data_b_pins[] = {
3376 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0),
3378 static const unsigned int scif4_data_b_mux[] = {
3379 RX4_B_MARK, TX4_B_MARK,
3381 static const unsigned int scif4_data_c_pins[] = {
3383 RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21),
3385 static const unsigned int scif4_data_c_mux[] = {
3386 RX4_C_MARK, TX4_C_MARK,
3388 /* - SCIF5 ------------------------------------------------------------------ */
3389 static const unsigned int scif5_data_pins[] = {
3391 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3),
3393 static const unsigned int scif5_data_mux[] = {
3396 static const unsigned int scif5_data_b_pins[] = {
3398 RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22),
3400 static const unsigned int scif5_data_b_mux[] = {
3401 RX5_B_MARK, TX5_B_MARK,
3403 /* - SCIFA0 ----------------------------------------------------------------- */
3404 static const unsigned int scifa0_data_pins[] = {
3406 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
3408 static const unsigned int scifa0_data_mux[] = {
3409 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
3411 static const unsigned int scifa0_data_b_pins[] = {
3413 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
3415 static const unsigned int scifa0_data_b_mux[] = {
3416 SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
3418 /* - SCIFA1 ----------------------------------------------------------------- */
3419 static const unsigned int scifa1_data_pins[] = {
3421 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
3423 static const unsigned int scifa1_data_mux[] = {
3424 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
3426 static const unsigned int scifa1_clk_pins[] = {
3430 static const unsigned int scifa1_clk_mux[] = {
3433 static const unsigned int scifa1_data_b_pins[] = {
3435 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
3437 static const unsigned int scifa1_data_b_mux[] = {
3438 SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
3440 static const unsigned int scifa1_clk_b_pins[] = {
3444 static const unsigned int scifa1_clk_b_mux[] = {
3447 static const unsigned int scifa1_data_c_pins[] = {
3449 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3451 static const unsigned int scifa1_data_c_mux[] = {
3452 SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
3454 /* - SCIFA2 ----------------------------------------------------------------- */
3455 static const unsigned int scifa2_data_pins[] = {
3457 RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31),
3459 static const unsigned int scifa2_data_mux[] = {
3460 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
3462 static const unsigned int scifa2_clk_pins[] = {
3466 static const unsigned int scifa2_clk_mux[] = {
3469 static const unsigned int scifa2_data_b_pins[] = {
3471 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
3473 static const unsigned int scifa2_data_b_mux[] = {
3474 SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
3476 /* - SCIFA3 ----------------------------------------------------------------- */
3477 static const unsigned int scifa3_data_pins[] = {
3479 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
3481 static const unsigned int scifa3_data_mux[] = {
3482 SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
3484 static const unsigned int scifa3_clk_pins[] = {
3488 static const unsigned int scifa3_clk_mux[] = {
3491 static const unsigned int scifa3_data_b_pins[] = {
3493 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
3495 static const unsigned int scifa3_data_b_mux[] = {
3496 SCIFA3_RXD_B_MARK, SCIFA3_TXD_B_MARK,
3498 static const unsigned int scifa3_clk_b_pins[] = {
3502 static const unsigned int scifa3_clk_b_mux[] = {
3505 static const unsigned int scifa3_data_c_pins[] = {
3507 RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 20),
3509 static const unsigned int scifa3_data_c_mux[] = {
3510 SCIFA3_RXD_C_MARK, SCIFA3_TXD_C_MARK,
3512 static const unsigned int scifa3_clk_c_pins[] = {
3516 static const unsigned int scifa3_clk_c_mux[] = {
3519 /* - SCIFA4 ----------------------------------------------------------------- */
3520 static const unsigned int scifa4_data_pins[] = {
3522 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1),
3524 static const unsigned int scifa4_data_mux[] = {
3525 SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
3527 static const unsigned int scifa4_data_b_pins[] = {
3529 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0),
3531 static const unsigned int scifa4_data_b_mux[] = {
3532 SCIFA4_RXD_B_MARK, SCIFA4_TXD_B_MARK,
3534 static const unsigned int scifa4_data_c_pins[] = {
3536 RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21),
3538 static const unsigned int scifa4_data_c_mux[] = {
3539 SCIFA4_RXD_C_MARK, SCIFA4_TXD_C_MARK,
3541 /* - SCIFA5 ----------------------------------------------------------------- */
3542 static const unsigned int scifa5_data_pins[] = {
3544 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3),
3546 static const unsigned int scifa5_data_mux[] = {
3547 SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
3549 static const unsigned int scifa5_data_b_pins[] = {
3551 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
3553 static const unsigned int scifa5_data_b_mux[] = {
3554 SCIFA5_RXD_B_MARK, SCIFA5_TXD_B_MARK,
3556 static const unsigned int scifa5_data_c_pins[] = {
3558 RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22),
3560 static const unsigned int scifa5_data_c_mux[] = {
3561 SCIFA5_RXD_C_MARK, SCIFA5_TXD_C_MARK,
3563 /* - SCIFB0 ----------------------------------------------------------------- */
3564 static const unsigned int scifb0_data_pins[] = {
3566 RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4),
3568 static const unsigned int scifb0_data_mux[] = {
3569 SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
3571 static const unsigned int scifb0_clk_pins[] = {
3575 static const unsigned int scifb0_clk_mux[] = {
3578 static const unsigned int scifb0_ctrl_pins[] = {
3580 RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0),
3582 static const unsigned int scifb0_ctrl_mux[] = {
3583 SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
3585 static const unsigned int scifb0_data_b_pins[] = {
3587 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21),
3589 static const unsigned int scifb0_data_b_mux[] = {
3590 SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK,
3592 static const unsigned int scifb0_clk_b_pins[] = {
3596 static const unsigned int scifb0_clk_b_mux[] = {
3599 static const unsigned int scifb0_ctrl_b_pins[] = {
3601 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 23),
3603 static const unsigned int scifb0_ctrl_b_mux[] = {
3604 SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK,
3606 static const unsigned int scifb0_data_c_pins[] = {
3608 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3610 static const unsigned int scifb0_data_c_mux[] = {
3611 SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK,
3613 static const unsigned int scifb0_clk_c_pins[] = {
3617 static const unsigned int scifb0_clk_c_mux[] = {
3620 static const unsigned int scifb0_data_d_pins[] = {
3622 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18),
3624 static const unsigned int scifb0_data_d_mux[] = {
3625 SCIFB0_RXD_D_MARK, SCIFB0_TXD_D_MARK,
3627 static const unsigned int scifb0_clk_d_pins[] = {
3631 static const unsigned int scifb0_clk_d_mux[] = {
3634 /* - SCIFB1 ----------------------------------------------------------------- */
3635 static const unsigned int scifb1_data_pins[] = {
3637 RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
3639 static const unsigned int scifb1_data_mux[] = {
3640 SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
3642 static const unsigned int scifb1_clk_pins[] = {
3646 static const unsigned int scifb1_clk_mux[] = {
3649 static const unsigned int scifb1_ctrl_pins[] = {
3651 RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8),
3653 static const unsigned int scifb1_ctrl_mux[] = {
3654 SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK,
3656 static const unsigned int scifb1_data_b_pins[] = {
3658 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3660 static const unsigned int scifb1_data_b_mux[] = {
3661 SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK,
3663 static const unsigned int scifb1_clk_b_pins[] = {
3667 static const unsigned int scifb1_clk_b_mux[] = {
3670 static const unsigned int scifb1_data_c_pins[] = {
3672 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3674 static const unsigned int scifb1_data_c_mux[] = {
3675 SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK,
3677 static const unsigned int scifb1_clk_c_pins[] = {
3681 static const unsigned int scifb1_clk_c_mux[] = {
3684 static const unsigned int scifb1_data_d_pins[] = {
3686 RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 12),
3688 static const unsigned int scifb1_data_d_mux[] = {
3689 SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK,
3691 /* - SCIFB2 ----------------------------------------------------------------- */
3692 static const unsigned int scifb2_data_pins[] = {
3694 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
3696 static const unsigned int scifb2_data_mux[] = {
3697 SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
3699 static const unsigned int scifb2_clk_pins[] = {
3703 static const unsigned int scifb2_clk_mux[] = {
3706 static const unsigned int scifb2_ctrl_pins[] = {
3708 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
3710 static const unsigned int scifb2_ctrl_mux[] = {
3711 SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
3713 static const unsigned int scifb2_data_b_pins[] = {
3715 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
3717 static const unsigned int scifb2_data_b_mux[] = {
3718 SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK,
3720 static const unsigned int scifb2_clk_b_pins[] = {
3724 static const unsigned int scifb2_clk_b_mux[] = {
3727 static const unsigned int scifb2_ctrl_b_pins[] = {
3729 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14),
3731 static const unsigned int scifb2_ctrl_b_mux[] = {
3732 SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK,
3734 static const unsigned int scifb2_data_c_pins[] = {
3736 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3738 static const unsigned int scifb2_data_c_mux[] = {
3739 SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
3741 static const unsigned int scifb2_clk_c_pins[] = {
3745 static const unsigned int scifb2_clk_c_mux[] = {
3748 static const unsigned int scifb2_data_d_pins[] = {
3750 RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 25),
3752 static const unsigned int scifb2_data_d_mux[] = {
3753 SCIFB2_RXD_D_MARK, SCIFB2_TXD_D_MARK,
3756 /* - SCIF Clock ------------------------------------------------------------- */
3757 static const unsigned int scif_clk_pins[] = {
3761 static const unsigned int scif_clk_mux[] = {
3764 static const unsigned int scif_clk_b_pins[] = {
3768 static const unsigned int scif_clk_b_mux[] = {
3772 /* - SDHI0 ------------------------------------------------------------------ */
3773 static const unsigned int sdhi0_data1_pins[] = {
3777 static const unsigned int sdhi0_data1_mux[] = {
3780 static const unsigned int sdhi0_data4_pins[] = {
3782 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
3783 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
3785 static const unsigned int sdhi0_data4_mux[] = {
3786 SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK,
3788 static const unsigned int sdhi0_ctrl_pins[] = {
3790 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3792 static const unsigned int sdhi0_ctrl_mux[] = {
3793 SD0_CLK_MARK, SD0_CMD_MARK,
3795 static const unsigned int sdhi0_cd_pins[] = {
3799 static const unsigned int sdhi0_cd_mux[] = {
3802 static const unsigned int sdhi0_wp_pins[] = {
3806 static const unsigned int sdhi0_wp_mux[] = {
3809 /* - SDHI1 ------------------------------------------------------------------ */
3810 static const unsigned int sdhi1_data1_pins[] = {
3814 static const unsigned int sdhi1_data1_mux[] = {
3817 static const unsigned int sdhi1_data4_pins[] = {
3819 RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
3820 RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
3822 static const unsigned int sdhi1_data4_mux[] = {
3823 SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK,
3825 static const unsigned int sdhi1_ctrl_pins[] = {
3827 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3829 static const unsigned int sdhi1_ctrl_mux[] = {
3830 SD1_CLK_MARK, SD1_CMD_MARK,
3832 static const unsigned int sdhi1_cd_pins[] = {
3836 static const unsigned int sdhi1_cd_mux[] = {
3839 static const unsigned int sdhi1_wp_pins[] = {
3843 static const unsigned int sdhi1_wp_mux[] = {
3846 /* - SDHI2 ------------------------------------------------------------------ */
3847 static const unsigned int sdhi2_data1_pins[] = {
3851 static const unsigned int sdhi2_data1_mux[] = {
3854 static const unsigned int sdhi2_data4_pins[] = {
3856 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
3857 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
3859 static const unsigned int sdhi2_data4_mux[] = {
3860 SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK,
3862 static const unsigned int sdhi2_ctrl_pins[] = {
3864 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
3866 static const unsigned int sdhi2_ctrl_mux[] = {
3867 SD2_CLK_MARK, SD2_CMD_MARK,
3869 static const unsigned int sdhi2_cd_pins[] = {
3873 static const unsigned int sdhi2_cd_mux[] = {
3876 static const unsigned int sdhi2_wp_pins[] = {
3880 static const unsigned int sdhi2_wp_mux[] = {
3884 /* - SSI -------------------------------------------------------------------- */
3885 static const unsigned int ssi0_data_pins[] = {
3890 static const unsigned int ssi0_data_mux[] = {
3894 static const unsigned int ssi0_data_b_pins[] = {
3899 static const unsigned int ssi0_data_b_mux[] = {
3903 static const unsigned int ssi0129_ctrl_pins[] = {
3905 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3908 static const unsigned int ssi0129_ctrl_mux[] = {
3909 SSI_SCK0129_MARK, SSI_WS0129_MARK,
3912 static const unsigned int ssi0129_ctrl_b_pins[] = {
3914 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3917 static const unsigned int ssi0129_ctrl_b_mux[] = {
3918 SSI_SCK0129_B_MARK, SSI_WS0129_B_MARK,
3921 static const unsigned int ssi1_data_pins[] = {
3926 static const unsigned int ssi1_data_mux[] = {
3930 static const unsigned int ssi1_data_b_pins[] = {
3935 static const unsigned int ssi1_data_b_mux[] = {
3939 static const unsigned int ssi1_ctrl_pins[] = {
3941 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
3944 static const unsigned int ssi1_ctrl_mux[] = {
3945 SSI_SCK1_MARK, SSI_WS1_MARK,
3948 static const unsigned int ssi1_ctrl_b_pins[] = {
3950 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
3953 static const unsigned int ssi1_ctrl_b_mux[] = {
3954 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3957 static const unsigned int ssi2_data_pins[] = {
3962 static const unsigned int ssi2_data_mux[] = {
3966 static const unsigned int ssi2_ctrl_pins[] = {
3968 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3971 static const unsigned int ssi2_ctrl_mux[] = {
3972 SSI_SCK2_MARK, SSI_WS2_MARK,
3975 static const unsigned int ssi3_data_pins[] = {
3980 static const unsigned int ssi3_data_mux[] = {
3984 static const unsigned int ssi34_ctrl_pins[] = {
3986 RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
3989 static const unsigned int ssi34_ctrl_mux[] = {
3990 SSI_SCK34_MARK, SSI_WS34_MARK,
3993 static const unsigned int ssi4_data_pins[] = {
3998 static const unsigned int ssi4_data_mux[] = {
4002 static const unsigned int ssi4_ctrl_pins[] = {
4004 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
4007 static const unsigned int ssi4_ctrl_mux[] = {
4008 SSI_SCK4_MARK, SSI_WS4_MARK,
4011 static const unsigned int ssi5_data_pins[] = {
4016 static const unsigned int ssi5_data_mux[] = {
4020 static const unsigned int ssi5_ctrl_pins[] = {
4022 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
4025 static const unsigned int ssi5_ctrl_mux[] = {
4026 SSI_SCK5_MARK, SSI_WS5_MARK,
4029 static const unsigned int ssi6_data_pins[] = {
4034 static const unsigned int ssi6_data_mux[] = {
4038 static const unsigned int ssi6_ctrl_pins[] = {
4040 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
4043 static const unsigned int ssi6_ctrl_mux[] = {
4044 SSI_SCK6_MARK, SSI_WS6_MARK,
4047 static const unsigned int ssi7_data_pins[] = {
4052 static const unsigned int ssi7_data_mux[] = {
4056 static const unsigned int ssi7_data_b_pins[] = {
4061 static const unsigned int ssi7_data_b_mux[] = {
4065 static const unsigned int ssi78_ctrl_pins[] = {
4067 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
4070 static const unsigned int ssi78_ctrl_mux[] = {
4071 SSI_SCK78_MARK, SSI_WS78_MARK,
4074 static const unsigned int ssi78_ctrl_b_pins[] = {
4076 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
4079 static const unsigned int ssi78_ctrl_b_mux[] = {
4080 SSI_SCK78_B_MARK, SSI_WS78_B_MARK,
4083 static const unsigned int ssi8_data_pins[] = {
4088 static const unsigned int ssi8_data_mux[] = {
4092 static const unsigned int ssi8_data_b_pins[] = {
4097 static const unsigned int ssi8_data_b_mux[] = {
4101 static const unsigned int ssi9_data_pins[] = {
4106 static const unsigned int ssi9_data_mux[] = {
4110 static const unsigned int ssi9_data_b_pins[] = {
4115 static const unsigned int ssi9_data_b_mux[] = {
4119 static const unsigned int ssi9_ctrl_pins[] = {
4121 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
4124 static const unsigned int ssi9_ctrl_mux[] = {
4125 SSI_SCK9_MARK, SSI_WS9_MARK,
4128 static const unsigned int ssi9_ctrl_b_pins[] = {
4130 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
4133 static const unsigned int ssi9_ctrl_b_mux[] = {
4134 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
4137 /* - USB0 ------------------------------------------------------------------- */
4138 static const unsigned int usb0_pins[] = {
4139 RCAR_GP_PIN(7, 23), /* PWEN */
4140 RCAR_GP_PIN(7, 24), /* OVC */
4142 static const unsigned int usb0_mux[] = {
4146 /* - USB1 ------------------------------------------------------------------- */
4147 static const unsigned int usb1_pins[] = {
4148 RCAR_GP_PIN(7, 25), /* PWEN */
4149 RCAR_GP_PIN(6, 30), /* OVC */
4151 static const unsigned int usb1_mux[] = {
4155 /* - VIN0 ------------------------------------------------------------------- */
4156 static const union vin_data vin0_data_pins = {
4159 RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6),
4160 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
4161 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
4162 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
4164 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
4165 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
4166 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
4167 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
4169 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22),
4170 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
4171 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
4172 RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
4175 static const union vin_data vin0_data_mux = {
4178 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
4179 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
4180 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
4181 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
4183 VI0_G0_MARK, VI0_G1_MARK,
4184 VI0_G2_MARK, VI0_G3_MARK,
4185 VI0_G4_MARK, VI0_G5_MARK,
4186 VI0_G6_MARK, VI0_G7_MARK,
4188 VI0_R0_MARK, VI0_R1_MARK,
4189 VI0_R2_MARK, VI0_R3_MARK,
4190 VI0_R4_MARK, VI0_R5_MARK,
4191 VI0_R6_MARK, VI0_R7_MARK,
4194 static const unsigned int vin0_data18_pins[] = {
4196 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
4197 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
4198 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
4200 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
4201 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
4202 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
4204 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
4205 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
4206 RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
4208 static const unsigned int vin0_data18_mux[] = {
4210 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
4211 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
4212 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
4214 VI0_G2_MARK, VI0_G3_MARK,
4215 VI0_G4_MARK, VI0_G5_MARK,
4216 VI0_G6_MARK, VI0_G7_MARK,
4218 VI0_R2_MARK, VI0_R3_MARK,
4219 VI0_R4_MARK, VI0_R5_MARK,
4220 VI0_R6_MARK, VI0_R7_MARK,
4222 static const unsigned int vin0_sync_pins[] = {
4223 RCAR_GP_PIN(4, 3), /* HSYNC */
4224 RCAR_GP_PIN(4, 4), /* VSYNC */
4226 static const unsigned int vin0_sync_mux[] = {
4230 static const unsigned int vin0_field_pins[] = {
4233 static const unsigned int vin0_field_mux[] = {
4236 static const unsigned int vin0_clkenb_pins[] = {
4239 static const unsigned int vin0_clkenb_mux[] = {
4242 static const unsigned int vin0_clk_pins[] = {
4245 static const unsigned int vin0_clk_mux[] = {
4248 /* - VIN1 ----------------------------------------------------------------- */
4249 static const unsigned int vin1_data8_pins[] = {
4250 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
4251 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
4252 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
4253 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
4255 static const unsigned int vin1_data8_mux[] = {
4256 VI1_DATA0_MARK, VI1_DATA1_MARK,
4257 VI1_DATA2_MARK, VI1_DATA3_MARK,
4258 VI1_DATA4_MARK, VI1_DATA5_MARK,
4259 VI1_DATA6_MARK, VI1_DATA7_MARK,
4261 static const unsigned int vin1_sync_pins[] = {
4262 RCAR_GP_PIN(5, 0), /* HSYNC */
4263 RCAR_GP_PIN(5, 1), /* VSYNC */
4265 static const unsigned int vin1_sync_mux[] = {
4269 static const unsigned int vin1_field_pins[] = {
4272 static const unsigned int vin1_field_mux[] = {
4275 static const unsigned int vin1_clkenb_pins[] = {
4278 static const unsigned int vin1_clkenb_mux[] = {
4281 static const unsigned int vin1_clk_pins[] = {
4284 static const unsigned int vin1_clk_mux[] = {
4287 static const union vin_data vin1_b_data_pins = {
4290 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
4291 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
4292 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
4293 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
4295 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
4296 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
4297 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
4298 RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
4300 RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
4301 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
4302 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
4303 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
4306 static const union vin_data vin1_b_data_mux = {
4309 VI1_DATA0_B_MARK, VI1_DATA1_B_MARK,
4310 VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
4311 VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
4312 VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
4314 VI1_G0_B_MARK, VI1_G1_B_MARK,
4315 VI1_G2_B_MARK, VI1_G3_B_MARK,
4316 VI1_G4_B_MARK, VI1_G5_B_MARK,
4317 VI1_G6_B_MARK, VI1_G7_B_MARK,
4319 VI1_R0_B_MARK, VI1_R1_B_MARK,
4320 VI1_R2_B_MARK, VI1_R3_B_MARK,
4321 VI1_R4_B_MARK, VI1_R5_B_MARK,
4322 VI1_R6_B_MARK, VI1_R7_B_MARK,
4325 static const unsigned int vin1_b_data18_pins[] = {
4327 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
4328 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
4329 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
4331 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
4332 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
4333 RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
4335 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
4336 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
4337 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
4339 static const unsigned int vin1_b_data18_mux[] = {
4341 VI1_DATA0_B_MARK, VI1_DATA1_B_MARK,
4342 VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
4343 VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
4344 VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
4346 VI1_G0_B_MARK, VI1_G1_B_MARK,
4347 VI1_G2_B_MARK, VI1_G3_B_MARK,
4348 VI1_G4_B_MARK, VI1_G5_B_MARK,
4349 VI1_G6_B_MARK, VI1_G7_B_MARK,
4351 VI1_R0_B_MARK, VI1_R1_B_MARK,
4352 VI1_R2_B_MARK, VI1_R3_B_MARK,
4353 VI1_R4_B_MARK, VI1_R5_B_MARK,
4354 VI1_R6_B_MARK, VI1_R7_B_MARK,
4356 static const unsigned int vin1_b_sync_pins[] = {
4357 RCAR_GP_PIN(3, 17), /* HSYNC */
4358 RCAR_GP_PIN(3, 18), /* VSYNC */
4360 static const unsigned int vin1_b_sync_mux[] = {
4364 static const unsigned int vin1_b_field_pins[] = {
4367 static const unsigned int vin1_b_field_mux[] = {
4370 static const unsigned int vin1_b_clkenb_pins[] = {
4373 static const unsigned int vin1_b_clkenb_mux[] = {
4376 static const unsigned int vin1_b_clk_pins[] = {
4379 static const unsigned int vin1_b_clk_mux[] = {
4382 /* - VIN2 ----------------------------------------------------------------- */
4383 static const unsigned int vin2_data8_pins[] = {
4384 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
4385 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
4386 RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25),
4387 RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 27),
4389 static const unsigned int vin2_data8_mux[] = {
4390 VI2_DATA0_MARK, VI2_DATA1_MARK,
4391 VI2_DATA2_MARK, VI2_DATA3_MARK,
4392 VI2_DATA4_MARK, VI2_DATA5_MARK,
4393 VI2_DATA6_MARK, VI2_DATA7_MARK,
4395 static const unsigned int vin2_sync_pins[] = {
4396 RCAR_GP_PIN(4, 15), /* HSYNC */
4397 RCAR_GP_PIN(4, 16), /* VSYNC */
4399 static const unsigned int vin2_sync_mux[] = {
4403 static const unsigned int vin2_field_pins[] = {
4406 static const unsigned int vin2_field_mux[] = {
4409 static const unsigned int vin2_clkenb_pins[] = {
4412 static const unsigned int vin2_clkenb_mux[] = {
4415 static const unsigned int vin2_clk_pins[] = {
4418 static const unsigned int vin2_clk_mux[] = {
4422 static const struct {
4423 struct sh_pfc_pin_group common[341];
4424 struct sh_pfc_pin_group r8a779x[9];
4427 SH_PFC_PIN_GROUP(audio_clk_a),
4428 SH_PFC_PIN_GROUP(audio_clk_b),
4429 SH_PFC_PIN_GROUP(audio_clk_b_b),
4430 SH_PFC_PIN_GROUP(audio_clk_c),
4431 SH_PFC_PIN_GROUP(audio_clkout),
4432 SH_PFC_PIN_GROUP(avb_link),
4433 SH_PFC_PIN_GROUP(avb_magic),
4434 SH_PFC_PIN_GROUP(avb_phy_int),
4435 SH_PFC_PIN_GROUP(avb_mdio),
4436 SH_PFC_PIN_GROUP(avb_mii),
4437 SH_PFC_PIN_GROUP(avb_gmii),
4438 SH_PFC_PIN_GROUP(can0_data),
4439 SH_PFC_PIN_GROUP(can0_data_b),
4440 SH_PFC_PIN_GROUP(can0_data_c),
4441 SH_PFC_PIN_GROUP(can0_data_d),
4442 SH_PFC_PIN_GROUP(can0_data_e),
4443 SH_PFC_PIN_GROUP(can0_data_f),
4444 SH_PFC_PIN_GROUP(can1_data),
4445 SH_PFC_PIN_GROUP(can1_data_b),
4446 SH_PFC_PIN_GROUP(can1_data_c),
4447 SH_PFC_PIN_GROUP(can1_data_d),
4448 SH_PFC_PIN_GROUP(can_clk),
4449 SH_PFC_PIN_GROUP(can_clk_b),
4450 SH_PFC_PIN_GROUP(can_clk_c),
4451 SH_PFC_PIN_GROUP(can_clk_d),
4452 SH_PFC_PIN_GROUP(du_rgb666),
4453 SH_PFC_PIN_GROUP(du_rgb888),
4454 SH_PFC_PIN_GROUP(du_clk_out_0),
4455 SH_PFC_PIN_GROUP(du_clk_out_1),
4456 SH_PFC_PIN_GROUP(du_sync),
4457 SH_PFC_PIN_GROUP(du_oddf),
4458 SH_PFC_PIN_GROUP(du_cde),
4459 SH_PFC_PIN_GROUP(du_disp),
4460 SH_PFC_PIN_GROUP(du0_clk_in),
4461 SH_PFC_PIN_GROUP(du1_clk_in),
4462 SH_PFC_PIN_GROUP(du1_clk_in_b),
4463 SH_PFC_PIN_GROUP(du1_clk_in_c),
4464 SH_PFC_PIN_GROUP(eth_link),
4465 SH_PFC_PIN_GROUP(eth_magic),
4466 SH_PFC_PIN_GROUP(eth_mdio),
4467 SH_PFC_PIN_GROUP(eth_rmii),
4468 SH_PFC_PIN_GROUP(hscif0_data),
4469 SH_PFC_PIN_GROUP(hscif0_clk),
4470 SH_PFC_PIN_GROUP(hscif0_ctrl),
4471 SH_PFC_PIN_GROUP(hscif0_data_b),
4472 SH_PFC_PIN_GROUP(hscif0_ctrl_b),
4473 SH_PFC_PIN_GROUP(hscif0_data_c),
4474 SH_PFC_PIN_GROUP(hscif0_clk_c),
4475 SH_PFC_PIN_GROUP(hscif1_data),
4476 SH_PFC_PIN_GROUP(hscif1_clk),
4477 SH_PFC_PIN_GROUP(hscif1_ctrl),
4478 SH_PFC_PIN_GROUP(hscif1_data_b),
4479 SH_PFC_PIN_GROUP(hscif1_data_c),
4480 SH_PFC_PIN_GROUP(hscif1_clk_c),
4481 SH_PFC_PIN_GROUP(hscif1_ctrl_c),
4482 SH_PFC_PIN_GROUP(hscif1_data_d),
4483 SH_PFC_PIN_GROUP(hscif1_data_e),
4484 SH_PFC_PIN_GROUP(hscif1_clk_e),
4485 SH_PFC_PIN_GROUP(hscif1_ctrl_e),
4486 SH_PFC_PIN_GROUP(hscif2_data),
4487 SH_PFC_PIN_GROUP(hscif2_clk),
4488 SH_PFC_PIN_GROUP(hscif2_ctrl),
4489 SH_PFC_PIN_GROUP(hscif2_data_b),
4490 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4491 SH_PFC_PIN_GROUP(hscif2_data_c),
4492 SH_PFC_PIN_GROUP(hscif2_clk_c),
4493 SH_PFC_PIN_GROUP(hscif2_data_d),
4494 SH_PFC_PIN_GROUP(i2c0),
4495 SH_PFC_PIN_GROUP(i2c0_b),
4496 SH_PFC_PIN_GROUP(i2c0_c),
4497 SH_PFC_PIN_GROUP(i2c1),
4498 SH_PFC_PIN_GROUP(i2c1_b),
4499 SH_PFC_PIN_GROUP(i2c1_c),
4500 SH_PFC_PIN_GROUP(i2c1_d),
4501 SH_PFC_PIN_GROUP(i2c1_e),
4502 SH_PFC_PIN_GROUP(i2c2),
4503 SH_PFC_PIN_GROUP(i2c2_b),
4504 SH_PFC_PIN_GROUP(i2c2_c),
4505 SH_PFC_PIN_GROUP(i2c2_d),
4506 SH_PFC_PIN_GROUP(i2c3),
4507 SH_PFC_PIN_GROUP(i2c3_b),
4508 SH_PFC_PIN_GROUP(i2c3_c),
4509 SH_PFC_PIN_GROUP(i2c3_d),
4510 SH_PFC_PIN_GROUP(i2c4),
4511 SH_PFC_PIN_GROUP(i2c4_b),
4512 SH_PFC_PIN_GROUP(i2c4_c),
4513 SH_PFC_PIN_GROUP(i2c7),
4514 SH_PFC_PIN_GROUP(i2c7_b),
4515 SH_PFC_PIN_GROUP(i2c7_c),
4516 SH_PFC_PIN_GROUP(i2c8),
4517 SH_PFC_PIN_GROUP(i2c8_b),
4518 SH_PFC_PIN_GROUP(i2c8_c),
4519 SH_PFC_PIN_GROUP(intc_irq0),
4520 SH_PFC_PIN_GROUP(intc_irq1),
4521 SH_PFC_PIN_GROUP(intc_irq2),
4522 SH_PFC_PIN_GROUP(intc_irq3),
4523 SH_PFC_PIN_GROUP(mmc_data1),
4524 SH_PFC_PIN_GROUP(mmc_data4),
4525 SH_PFC_PIN_GROUP(mmc_data8),
4526 SH_PFC_PIN_GROUP(mmc_ctrl),
4527 SH_PFC_PIN_GROUP(msiof0_clk),
4528 SH_PFC_PIN_GROUP(msiof0_sync),
4529 SH_PFC_PIN_GROUP(msiof0_ss1),
4530 SH_PFC_PIN_GROUP(msiof0_ss2),
4531 SH_PFC_PIN_GROUP(msiof0_rx),
4532 SH_PFC_PIN_GROUP(msiof0_tx),
4533 SH_PFC_PIN_GROUP(msiof0_clk_b),
4534 SH_PFC_PIN_GROUP(msiof0_sync_b),
4535 SH_PFC_PIN_GROUP(msiof0_ss1_b),
4536 SH_PFC_PIN_GROUP(msiof0_ss2_b),
4537 SH_PFC_PIN_GROUP(msiof0_rx_b),
4538 SH_PFC_PIN_GROUP(msiof0_tx_b),
4539 SH_PFC_PIN_GROUP(msiof0_clk_c),
4540 SH_PFC_PIN_GROUP(msiof0_sync_c),
4541 SH_PFC_PIN_GROUP(msiof0_ss1_c),
4542 SH_PFC_PIN_GROUP(msiof0_ss2_c),
4543 SH_PFC_PIN_GROUP(msiof0_rx_c),
4544 SH_PFC_PIN_GROUP(msiof0_tx_c),
4545 SH_PFC_PIN_GROUP(msiof1_clk),
4546 SH_PFC_PIN_GROUP(msiof1_sync),
4547 SH_PFC_PIN_GROUP(msiof1_ss1),
4548 SH_PFC_PIN_GROUP(msiof1_ss2),
4549 SH_PFC_PIN_GROUP(msiof1_rx),
4550 SH_PFC_PIN_GROUP(msiof1_tx),
4551 SH_PFC_PIN_GROUP(msiof1_clk_b),
4552 SH_PFC_PIN_GROUP(msiof1_sync_b),
4553 SH_PFC_PIN_GROUP(msiof1_ss1_b),
4554 SH_PFC_PIN_GROUP(msiof1_ss2_b),
4555 SH_PFC_PIN_GROUP(msiof1_rx_b),
4556 SH_PFC_PIN_GROUP(msiof1_tx_b),
4557 SH_PFC_PIN_GROUP(msiof1_clk_c),
4558 SH_PFC_PIN_GROUP(msiof1_sync_c),
4559 SH_PFC_PIN_GROUP(msiof1_rx_c),
4560 SH_PFC_PIN_GROUP(msiof1_tx_c),
4561 SH_PFC_PIN_GROUP(msiof1_clk_d),
4562 SH_PFC_PIN_GROUP(msiof1_sync_d),
4563 SH_PFC_PIN_GROUP(msiof1_ss1_d),
4564 SH_PFC_PIN_GROUP(msiof1_rx_d),
4565 SH_PFC_PIN_GROUP(msiof1_tx_d),
4566 SH_PFC_PIN_GROUP(msiof1_clk_e),
4567 SH_PFC_PIN_GROUP(msiof1_sync_e),
4568 SH_PFC_PIN_GROUP(msiof1_rx_e),
4569 SH_PFC_PIN_GROUP(msiof1_tx_e),
4570 SH_PFC_PIN_GROUP(msiof2_clk),
4571 SH_PFC_PIN_GROUP(msiof2_sync),
4572 SH_PFC_PIN_GROUP(msiof2_ss1),
4573 SH_PFC_PIN_GROUP(msiof2_ss2),
4574 SH_PFC_PIN_GROUP(msiof2_rx),
4575 SH_PFC_PIN_GROUP(msiof2_tx),
4576 SH_PFC_PIN_GROUP(msiof2_clk_b),
4577 SH_PFC_PIN_GROUP(msiof2_sync_b),
4578 SH_PFC_PIN_GROUP(msiof2_ss1_b),
4579 SH_PFC_PIN_GROUP(msiof2_ss2_b),
4580 SH_PFC_PIN_GROUP(msiof2_rx_b),
4581 SH_PFC_PIN_GROUP(msiof2_tx_b),
4582 SH_PFC_PIN_GROUP(msiof2_clk_c),
4583 SH_PFC_PIN_GROUP(msiof2_sync_c),
4584 SH_PFC_PIN_GROUP(msiof2_rx_c),
4585 SH_PFC_PIN_GROUP(msiof2_tx_c),
4586 SH_PFC_PIN_GROUP(msiof2_clk_d),
4587 SH_PFC_PIN_GROUP(msiof2_sync_d),
4588 SH_PFC_PIN_GROUP(msiof2_ss1_d),
4589 SH_PFC_PIN_GROUP(msiof2_ss2_d),
4590 SH_PFC_PIN_GROUP(msiof2_rx_d),
4591 SH_PFC_PIN_GROUP(msiof2_tx_d),
4592 SH_PFC_PIN_GROUP(msiof2_clk_e),
4593 SH_PFC_PIN_GROUP(msiof2_sync_e),
4594 SH_PFC_PIN_GROUP(msiof2_rx_e),
4595 SH_PFC_PIN_GROUP(msiof2_tx_e),
4596 SH_PFC_PIN_GROUP(pwm0),
4597 SH_PFC_PIN_GROUP(pwm0_b),
4598 SH_PFC_PIN_GROUP(pwm1),
4599 SH_PFC_PIN_GROUP(pwm1_b),
4600 SH_PFC_PIN_GROUP(pwm2),
4601 SH_PFC_PIN_GROUP(pwm2_b),
4602 SH_PFC_PIN_GROUP(pwm3),
4603 SH_PFC_PIN_GROUP(pwm4),
4604 SH_PFC_PIN_GROUP(pwm4_b),
4605 SH_PFC_PIN_GROUP(pwm5),
4606 SH_PFC_PIN_GROUP(pwm5_b),
4607 SH_PFC_PIN_GROUP(pwm6),
4608 SH_PFC_PIN_GROUP(qspi_ctrl),
4609 SH_PFC_PIN_GROUP(qspi_data2),
4610 SH_PFC_PIN_GROUP(qspi_data4),
4611 SH_PFC_PIN_GROUP(qspi_ctrl_b),
4612 SH_PFC_PIN_GROUP(qspi_data2_b),
4613 SH_PFC_PIN_GROUP(qspi_data4_b),
4614 SH_PFC_PIN_GROUP(scif0_data),
4615 SH_PFC_PIN_GROUP(scif0_data_b),
4616 SH_PFC_PIN_GROUP(scif0_data_c),
4617 SH_PFC_PIN_GROUP(scif0_data_d),
4618 SH_PFC_PIN_GROUP(scif0_data_e),
4619 SH_PFC_PIN_GROUP(scif1_data),
4620 SH_PFC_PIN_GROUP(scif1_data_b),
4621 SH_PFC_PIN_GROUP(scif1_clk_b),
4622 SH_PFC_PIN_GROUP(scif1_data_c),
4623 SH_PFC_PIN_GROUP(scif1_data_d),
4624 SH_PFC_PIN_GROUP(scif2_data),
4625 SH_PFC_PIN_GROUP(scif2_data_b),
4626 SH_PFC_PIN_GROUP(scif2_clk_b),
4627 SH_PFC_PIN_GROUP(scif2_data_c),
4628 SH_PFC_PIN_GROUP(scif2_data_e),
4629 SH_PFC_PIN_GROUP(scif3_data),
4630 SH_PFC_PIN_GROUP(scif3_clk),
4631 SH_PFC_PIN_GROUP(scif3_data_b),
4632 SH_PFC_PIN_GROUP(scif3_clk_b),
4633 SH_PFC_PIN_GROUP(scif3_data_c),
4634 SH_PFC_PIN_GROUP(scif3_data_d),
4635 SH_PFC_PIN_GROUP(scif4_data),
4636 SH_PFC_PIN_GROUP(scif4_data_b),
4637 SH_PFC_PIN_GROUP(scif4_data_c),
4638 SH_PFC_PIN_GROUP(scif5_data),
4639 SH_PFC_PIN_GROUP(scif5_data_b),
4640 SH_PFC_PIN_GROUP(scifa0_data),
4641 SH_PFC_PIN_GROUP(scifa0_data_b),
4642 SH_PFC_PIN_GROUP(scifa1_data),
4643 SH_PFC_PIN_GROUP(scifa1_clk),
4644 SH_PFC_PIN_GROUP(scifa1_data_b),
4645 SH_PFC_PIN_GROUP(scifa1_clk_b),
4646 SH_PFC_PIN_GROUP(scifa1_data_c),
4647 SH_PFC_PIN_GROUP(scifa2_data),
4648 SH_PFC_PIN_GROUP(scifa2_clk),
4649 SH_PFC_PIN_GROUP(scifa2_data_b),
4650 SH_PFC_PIN_GROUP(scifa3_data),
4651 SH_PFC_PIN_GROUP(scifa3_clk),
4652 SH_PFC_PIN_GROUP(scifa3_data_b),
4653 SH_PFC_PIN_GROUP(scifa3_clk_b),
4654 SH_PFC_PIN_GROUP(scifa3_data_c),
4655 SH_PFC_PIN_GROUP(scifa3_clk_c),
4656 SH_PFC_PIN_GROUP(scifa4_data),
4657 SH_PFC_PIN_GROUP(scifa4_data_b),
4658 SH_PFC_PIN_GROUP(scifa4_data_c),
4659 SH_PFC_PIN_GROUP(scifa5_data),
4660 SH_PFC_PIN_GROUP(scifa5_data_b),
4661 SH_PFC_PIN_GROUP(scifa5_data_c),
4662 SH_PFC_PIN_GROUP(scifb0_data),
4663 SH_PFC_PIN_GROUP(scifb0_clk),
4664 SH_PFC_PIN_GROUP(scifb0_ctrl),
4665 SH_PFC_PIN_GROUP(scifb0_data_b),
4666 SH_PFC_PIN_GROUP(scifb0_clk_b),
4667 SH_PFC_PIN_GROUP(scifb0_ctrl_b),
4668 SH_PFC_PIN_GROUP(scifb0_data_c),
4669 SH_PFC_PIN_GROUP(scifb0_clk_c),
4670 SH_PFC_PIN_GROUP(scifb0_data_d),
4671 SH_PFC_PIN_GROUP(scifb0_clk_d),
4672 SH_PFC_PIN_GROUP(scifb1_data),
4673 SH_PFC_PIN_GROUP(scifb1_clk),
4674 SH_PFC_PIN_GROUP(scifb1_ctrl),
4675 SH_PFC_PIN_GROUP(scifb1_data_b),
4676 SH_PFC_PIN_GROUP(scifb1_clk_b),
4677 SH_PFC_PIN_GROUP(scifb1_data_c),
4678 SH_PFC_PIN_GROUP(scifb1_clk_c),
4679 SH_PFC_PIN_GROUP(scifb1_data_d),
4680 SH_PFC_PIN_GROUP(scifb2_data),
4681 SH_PFC_PIN_GROUP(scifb2_clk),
4682 SH_PFC_PIN_GROUP(scifb2_ctrl),
4683 SH_PFC_PIN_GROUP(scifb2_data_b),
4684 SH_PFC_PIN_GROUP(scifb2_clk_b),
4685 SH_PFC_PIN_GROUP(scifb2_ctrl_b),
4686 SH_PFC_PIN_GROUP(scifb2_data_c),
4687 SH_PFC_PIN_GROUP(scifb2_clk_c),
4688 SH_PFC_PIN_GROUP(scifb2_data_d),
4689 SH_PFC_PIN_GROUP(scif_clk),
4690 SH_PFC_PIN_GROUP(scif_clk_b),
4691 SH_PFC_PIN_GROUP(sdhi0_data1),
4692 SH_PFC_PIN_GROUP(sdhi0_data4),
4693 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4694 SH_PFC_PIN_GROUP(sdhi0_cd),
4695 SH_PFC_PIN_GROUP(sdhi0_wp),
4696 SH_PFC_PIN_GROUP(sdhi1_data1),
4697 SH_PFC_PIN_GROUP(sdhi1_data4),
4698 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4699 SH_PFC_PIN_GROUP(sdhi1_cd),
4700 SH_PFC_PIN_GROUP(sdhi1_wp),
4701 SH_PFC_PIN_GROUP(sdhi2_data1),
4702 SH_PFC_PIN_GROUP(sdhi2_data4),
4703 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4704 SH_PFC_PIN_GROUP(sdhi2_cd),
4705 SH_PFC_PIN_GROUP(sdhi2_wp),
4706 SH_PFC_PIN_GROUP(ssi0_data),
4707 SH_PFC_PIN_GROUP(ssi0_data_b),
4708 SH_PFC_PIN_GROUP(ssi0129_ctrl),
4709 SH_PFC_PIN_GROUP(ssi0129_ctrl_b),
4710 SH_PFC_PIN_GROUP(ssi1_data),
4711 SH_PFC_PIN_GROUP(ssi1_data_b),
4712 SH_PFC_PIN_GROUP(ssi1_ctrl),
4713 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4714 SH_PFC_PIN_GROUP(ssi2_data),
4715 SH_PFC_PIN_GROUP(ssi2_ctrl),
4716 SH_PFC_PIN_GROUP(ssi3_data),
4717 SH_PFC_PIN_GROUP(ssi34_ctrl),
4718 SH_PFC_PIN_GROUP(ssi4_data),
4719 SH_PFC_PIN_GROUP(ssi4_ctrl),
4720 SH_PFC_PIN_GROUP(ssi5_data),
4721 SH_PFC_PIN_GROUP(ssi5_ctrl),
4722 SH_PFC_PIN_GROUP(ssi6_data),
4723 SH_PFC_PIN_GROUP(ssi6_ctrl),
4724 SH_PFC_PIN_GROUP(ssi7_data),
4725 SH_PFC_PIN_GROUP(ssi7_data_b),
4726 SH_PFC_PIN_GROUP(ssi78_ctrl),
4727 SH_PFC_PIN_GROUP(ssi78_ctrl_b),
4728 SH_PFC_PIN_GROUP(ssi8_data),
4729 SH_PFC_PIN_GROUP(ssi8_data_b),
4730 SH_PFC_PIN_GROUP(ssi9_data),
4731 SH_PFC_PIN_GROUP(ssi9_data_b),
4732 SH_PFC_PIN_GROUP(ssi9_ctrl),
4733 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4734 SH_PFC_PIN_GROUP(usb0),
4735 SH_PFC_PIN_GROUP(usb1),
4736 VIN_DATA_PIN_GROUP(vin0_data, 24),
4737 VIN_DATA_PIN_GROUP(vin0_data, 20),
4738 SH_PFC_PIN_GROUP(vin0_data18),
4739 VIN_DATA_PIN_GROUP(vin0_data, 16),
4740 VIN_DATA_PIN_GROUP(vin0_data, 12),
4741 VIN_DATA_PIN_GROUP(vin0_data, 10),
4742 VIN_DATA_PIN_GROUP(vin0_data, 8),
4743 SH_PFC_PIN_GROUP(vin0_sync),
4744 SH_PFC_PIN_GROUP(vin0_field),
4745 SH_PFC_PIN_GROUP(vin0_clkenb),
4746 SH_PFC_PIN_GROUP(vin0_clk),
4747 SH_PFC_PIN_GROUP(vin1_data8),
4748 SH_PFC_PIN_GROUP(vin1_sync),
4749 SH_PFC_PIN_GROUP(vin1_field),
4750 SH_PFC_PIN_GROUP(vin1_clkenb),
4751 SH_PFC_PIN_GROUP(vin1_clk),
4752 VIN_DATA_PIN_GROUP(vin1_b_data, 24),
4753 VIN_DATA_PIN_GROUP(vin1_b_data, 20),
4754 SH_PFC_PIN_GROUP(vin1_b_data18),
4755 VIN_DATA_PIN_GROUP(vin1_b_data, 16),
4756 VIN_DATA_PIN_GROUP(vin1_b_data, 12),
4757 VIN_DATA_PIN_GROUP(vin1_b_data, 10),
4758 VIN_DATA_PIN_GROUP(vin1_b_data, 8),
4759 SH_PFC_PIN_GROUP(vin1_b_sync),
4760 SH_PFC_PIN_GROUP(vin1_b_field),
4761 SH_PFC_PIN_GROUP(vin1_b_clkenb),
4762 SH_PFC_PIN_GROUP(vin1_b_clk),
4763 SH_PFC_PIN_GROUP(vin2_data8),
4764 SH_PFC_PIN_GROUP(vin2_sync),
4765 SH_PFC_PIN_GROUP(vin2_field),
4766 SH_PFC_PIN_GROUP(vin2_clkenb),
4767 SH_PFC_PIN_GROUP(vin2_clk),
4770 SH_PFC_PIN_GROUP(adi_common),
4771 SH_PFC_PIN_GROUP(adi_chsel0),
4772 SH_PFC_PIN_GROUP(adi_chsel1),
4773 SH_PFC_PIN_GROUP(adi_chsel2),
4774 SH_PFC_PIN_GROUP(adi_common_b),
4775 SH_PFC_PIN_GROUP(adi_chsel0_b),
4776 SH_PFC_PIN_GROUP(adi_chsel1_b),
4777 SH_PFC_PIN_GROUP(adi_chsel2_b),
4778 SH_PFC_PIN_GROUP(mlb_3pin),
4782 static const char * const adi_groups[] = {
4793 static const char * const audio_clk_groups[] = {
4801 static const char * const avb_groups[] = {
4810 static const char * const can0_groups[] = {
4823 static const char * const can1_groups[] = {
4834 static const char * const du_groups[] = {
4845 static const char * const du0_groups[] = {
4849 static const char * const du1_groups[] = {
4855 static const char * const eth_groups[] = {
4862 static const char * const hscif0_groups[] = {
4872 static const char * const hscif1_groups[] = {
4886 static const char * const hscif2_groups[] = {
4897 static const char * const i2c0_groups[] = {
4903 static const char * const i2c1_groups[] = {
4911 static const char * const i2c2_groups[] = {
4918 static const char * const i2c3_groups[] = {
4925 static const char * const i2c4_groups[] = {
4931 static const char * const i2c7_groups[] = {
4937 static const char * const i2c8_groups[] = {
4943 static const char * const intc_groups[] = {
4950 static const char * const mlb_groups[] = {
4954 static const char * const mmc_groups[] = {
4961 static const char * const msiof0_groups[] = {
4982 static const char * const msiof1_groups[] = {
5010 static const char * const msiof2_groups[] = {
5039 static const char * const pwm0_groups[] = {
5044 static const char * const pwm1_groups[] = {
5049 static const char * const pwm2_groups[] = {
5054 static const char * const pwm3_groups[] = {
5058 static const char * const pwm4_groups[] = {
5063 static const char * const pwm5_groups[] = {
5068 static const char * const pwm6_groups[] = {
5072 static const char * const qspi_groups[] = {
5081 static const char * const scif0_groups[] = {
5089 static const char * const scif1_groups[] = {
5097 static const char * const scif2_groups[] = {
5104 static const char * const scif3_groups[] = {
5112 static const char * const scif4_groups[] = {
5117 static const char * const scif5_groups[] = {
5121 static const char * const scifa0_groups[] = {
5125 static const char * const scifa1_groups[] = {
5132 static const char * const scifa2_groups[] = {
5137 static const char * const scifa3_groups[] = {
5145 static const char * const scifa4_groups[] = {
5150 static const char * const scifa5_groups[] = {
5155 static const char * const scifb0_groups[] = {
5167 static const char * const scifb1_groups[] = {
5177 static const char * const scifb2_groups[] = {
5189 static const char * const scif_clk_groups[] = {
5194 static const char * const sdhi0_groups[] = {
5202 static const char * const sdhi1_groups[] = {
5210 static const char * const sdhi2_groups[] = {
5218 static const char * const ssi_groups[] = {
5249 static const char * const usb0_groups[] = {
5252 static const char * const usb1_groups[] = {
5256 static const char * const vin0_groups[] = {
5270 static const char * const vin1_groups[] = {
5289 static const char * const vin2_groups[] = {
5297 static const struct {
5298 struct sh_pfc_function common[56];
5299 struct sh_pfc_function r8a779x[2];
5300 } pinmux_functions = {
5302 SH_PFC_FUNCTION(audio_clk),
5303 SH_PFC_FUNCTION(avb),
5304 SH_PFC_FUNCTION(can0),
5305 SH_PFC_FUNCTION(can1),
5306 SH_PFC_FUNCTION(du),
5307 SH_PFC_FUNCTION(du0),
5308 SH_PFC_FUNCTION(du1),
5309 SH_PFC_FUNCTION(eth),
5310 SH_PFC_FUNCTION(hscif0),
5311 SH_PFC_FUNCTION(hscif1),
5312 SH_PFC_FUNCTION(hscif2),
5313 SH_PFC_FUNCTION(i2c0),
5314 SH_PFC_FUNCTION(i2c1),
5315 SH_PFC_FUNCTION(i2c2),
5316 SH_PFC_FUNCTION(i2c3),
5317 SH_PFC_FUNCTION(i2c4),
5318 SH_PFC_FUNCTION(i2c7),
5319 SH_PFC_FUNCTION(i2c8),
5320 SH_PFC_FUNCTION(intc),
5321 SH_PFC_FUNCTION(mmc),
5322 SH_PFC_FUNCTION(msiof0),
5323 SH_PFC_FUNCTION(msiof1),
5324 SH_PFC_FUNCTION(msiof2),
5325 SH_PFC_FUNCTION(pwm0),
5326 SH_PFC_FUNCTION(pwm1),
5327 SH_PFC_FUNCTION(pwm2),
5328 SH_PFC_FUNCTION(pwm3),
5329 SH_PFC_FUNCTION(pwm4),
5330 SH_PFC_FUNCTION(pwm5),
5331 SH_PFC_FUNCTION(pwm6),
5332 SH_PFC_FUNCTION(qspi),
5333 SH_PFC_FUNCTION(scif0),
5334 SH_PFC_FUNCTION(scif1),
5335 SH_PFC_FUNCTION(scif2),
5336 SH_PFC_FUNCTION(scif3),
5337 SH_PFC_FUNCTION(scif4),
5338 SH_PFC_FUNCTION(scif5),
5339 SH_PFC_FUNCTION(scifa0),
5340 SH_PFC_FUNCTION(scifa1),
5341 SH_PFC_FUNCTION(scifa2),
5342 SH_PFC_FUNCTION(scifa3),
5343 SH_PFC_FUNCTION(scifa4),
5344 SH_PFC_FUNCTION(scifa5),
5345 SH_PFC_FUNCTION(scifb0),
5346 SH_PFC_FUNCTION(scifb1),
5347 SH_PFC_FUNCTION(scifb2),
5348 SH_PFC_FUNCTION(scif_clk),
5349 SH_PFC_FUNCTION(sdhi0),
5350 SH_PFC_FUNCTION(sdhi1),
5351 SH_PFC_FUNCTION(sdhi2),
5352 SH_PFC_FUNCTION(ssi),
5353 SH_PFC_FUNCTION(usb0),
5354 SH_PFC_FUNCTION(usb1),
5355 SH_PFC_FUNCTION(vin0),
5356 SH_PFC_FUNCTION(vin1),
5357 SH_PFC_FUNCTION(vin2),
5360 SH_PFC_FUNCTION(adi),
5361 SH_PFC_FUNCTION(mlb),
5365 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5366 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
5367 GP_0_31_FN, FN_IP1_22_20,
5368 GP_0_30_FN, FN_IP1_19_17,
5369 GP_0_29_FN, FN_IP1_16_14,
5370 GP_0_28_FN, FN_IP1_13_11,
5371 GP_0_27_FN, FN_IP1_10_8,
5372 GP_0_26_FN, FN_IP1_7_6,
5373 GP_0_25_FN, FN_IP1_5_4,
5374 GP_0_24_FN, FN_IP1_3_2,
5375 GP_0_23_FN, FN_IP1_1_0,
5376 GP_0_22_FN, FN_IP0_30_29,
5377 GP_0_21_FN, FN_IP0_28_27,
5378 GP_0_20_FN, FN_IP0_26_25,
5379 GP_0_19_FN, FN_IP0_24_23,
5380 GP_0_18_FN, FN_IP0_22_21,
5381 GP_0_17_FN, FN_IP0_20_19,
5382 GP_0_16_FN, FN_IP0_18_16,
5383 GP_0_15_FN, FN_IP0_15,
5384 GP_0_14_FN, FN_IP0_14,
5385 GP_0_13_FN, FN_IP0_13,
5386 GP_0_12_FN, FN_IP0_12,
5387 GP_0_11_FN, FN_IP0_11,
5388 GP_0_10_FN, FN_IP0_10,
5389 GP_0_9_FN, FN_IP0_9,
5390 GP_0_8_FN, FN_IP0_8,
5391 GP_0_7_FN, FN_IP0_7,
5392 GP_0_6_FN, FN_IP0_6,
5393 GP_0_5_FN, FN_IP0_5,
5394 GP_0_4_FN, FN_IP0_4,
5395 GP_0_3_FN, FN_IP0_3,
5396 GP_0_2_FN, FN_IP0_2,
5397 GP_0_1_FN, FN_IP0_1,
5398 GP_0_0_FN, FN_IP0_0, }
5400 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
5407 GP_1_25_FN, FN_IP3_21_20,
5408 GP_1_24_FN, FN_IP3_19_18,
5409 GP_1_23_FN, FN_IP3_17_16,
5410 GP_1_22_FN, FN_IP3_15_14,
5411 GP_1_21_FN, FN_IP3_13_12,
5412 GP_1_20_FN, FN_IP3_11_9,
5413 GP_1_19_FN, FN_RD_N,
5414 GP_1_18_FN, FN_IP3_8_6,
5415 GP_1_17_FN, FN_IP3_5_3,
5416 GP_1_16_FN, FN_IP3_2_0,
5417 GP_1_15_FN, FN_IP2_29_27,
5418 GP_1_14_FN, FN_IP2_26_25,
5419 GP_1_13_FN, FN_IP2_24_23,
5420 GP_1_12_FN, FN_EX_CS0_N,
5421 GP_1_11_FN, FN_IP2_22_21,
5422 GP_1_10_FN, FN_IP2_20_19,
5423 GP_1_9_FN, FN_IP2_18_16,
5424 GP_1_8_FN, FN_IP2_15_13,
5425 GP_1_7_FN, FN_IP2_12_10,
5426 GP_1_6_FN, FN_IP2_9_7,
5427 GP_1_5_FN, FN_IP2_6_5,
5428 GP_1_4_FN, FN_IP2_4_3,
5429 GP_1_3_FN, FN_IP2_2_0,
5430 GP_1_2_FN, FN_IP1_31_29,
5431 GP_1_1_FN, FN_IP1_28_26,
5432 GP_1_0_FN, FN_IP1_25_23, }
5434 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
5435 GP_2_31_FN, FN_IP6_7_6,
5436 GP_2_30_FN, FN_IP6_5_3,
5437 GP_2_29_FN, FN_IP6_2_0,
5438 GP_2_28_FN, FN_AUDIO_CLKA,
5439 GP_2_27_FN, FN_IP5_31_29,
5440 GP_2_26_FN, FN_IP5_28_26,
5441 GP_2_25_FN, FN_IP5_25_24,
5442 GP_2_24_FN, FN_IP5_23_22,
5443 GP_2_23_FN, FN_IP5_21_20,
5444 GP_2_22_FN, FN_IP5_19_17,
5445 GP_2_21_FN, FN_IP5_16_15,
5446 GP_2_20_FN, FN_IP5_14_12,
5447 GP_2_19_FN, FN_IP5_11_9,
5448 GP_2_18_FN, FN_IP5_8_6,
5449 GP_2_17_FN, FN_IP5_5_3,
5450 GP_2_16_FN, FN_IP5_2_0,
5451 GP_2_15_FN, FN_IP4_30_28,
5452 GP_2_14_FN, FN_IP4_27_26,
5453 GP_2_13_FN, FN_IP4_25_24,
5454 GP_2_12_FN, FN_IP4_23_22,
5455 GP_2_11_FN, FN_IP4_21,
5456 GP_2_10_FN, FN_IP4_20,
5457 GP_2_9_FN, FN_IP4_19,
5458 GP_2_8_FN, FN_IP4_18_16,
5459 GP_2_7_FN, FN_IP4_15_13,
5460 GP_2_6_FN, FN_IP4_12_10,
5461 GP_2_5_FN, FN_IP4_9_8,
5462 GP_2_4_FN, FN_IP4_7_5,
5463 GP_2_3_FN, FN_IP4_4_2,
5464 GP_2_2_FN, FN_IP4_1_0,
5465 GP_2_1_FN, FN_IP3_30_28,
5466 GP_2_0_FN, FN_IP3_27_25 }
5468 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
5469 GP_3_31_FN, FN_IP9_18_17,
5470 GP_3_30_FN, FN_IP9_16,
5471 GP_3_29_FN, FN_IP9_15_13,
5472 GP_3_28_FN, FN_IP9_12,
5473 GP_3_27_FN, FN_IP9_11,
5474 GP_3_26_FN, FN_IP9_10_8,
5475 GP_3_25_FN, FN_IP9_7,
5476 GP_3_24_FN, FN_IP9_6,
5477 GP_3_23_FN, FN_IP9_5_3,
5478 GP_3_22_FN, FN_IP9_2_0,
5479 GP_3_21_FN, FN_IP8_30_28,
5480 GP_3_20_FN, FN_IP8_27_26,
5481 GP_3_19_FN, FN_IP8_25_24,
5482 GP_3_18_FN, FN_IP8_23_21,
5483 GP_3_17_FN, FN_IP8_20_18,
5484 GP_3_16_FN, FN_IP8_17_15,
5485 GP_3_15_FN, FN_IP8_14_12,
5486 GP_3_14_FN, FN_IP8_11_9,
5487 GP_3_13_FN, FN_IP8_8_6,
5488 GP_3_12_FN, FN_IP8_5_3,
5489 GP_3_11_FN, FN_IP8_2_0,
5490 GP_3_10_FN, FN_IP7_29_27,
5491 GP_3_9_FN, FN_IP7_26_24,
5492 GP_3_8_FN, FN_IP7_23_21,
5493 GP_3_7_FN, FN_IP7_20_19,
5494 GP_3_6_FN, FN_IP7_18_17,
5495 GP_3_5_FN, FN_IP7_16_15,
5496 GP_3_4_FN, FN_IP7_14_13,
5497 GP_3_3_FN, FN_IP7_12_11,
5498 GP_3_2_FN, FN_IP7_10_9,
5499 GP_3_1_FN, FN_IP7_8_6,
5500 GP_3_0_FN, FN_IP7_5_3 }
5502 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
5503 GP_4_31_FN, FN_IP15_5_4,
5504 GP_4_30_FN, FN_IP15_3_2,
5505 GP_4_29_FN, FN_IP15_1_0,
5506 GP_4_28_FN, FN_IP11_8_6,
5507 GP_4_27_FN, FN_IP11_5_3,
5508 GP_4_26_FN, FN_IP11_2_0,
5509 GP_4_25_FN, FN_IP10_31_29,
5510 GP_4_24_FN, FN_IP10_28_27,
5511 GP_4_23_FN, FN_IP10_26_25,
5512 GP_4_22_FN, FN_IP10_24_22,
5513 GP_4_21_FN, FN_IP10_21_19,
5514 GP_4_20_FN, FN_IP10_18_17,
5515 GP_4_19_FN, FN_IP10_16_15,
5516 GP_4_18_FN, FN_IP10_14_12,
5517 GP_4_17_FN, FN_IP10_11_9,
5518 GP_4_16_FN, FN_IP10_8_6,
5519 GP_4_15_FN, FN_IP10_5_3,
5520 GP_4_14_FN, FN_IP10_2_0,
5521 GP_4_13_FN, FN_IP9_31_29,
5522 GP_4_12_FN, FN_VI0_DATA7_VI0_B7,
5523 GP_4_11_FN, FN_VI0_DATA6_VI0_B6,
5524 GP_4_10_FN, FN_VI0_DATA5_VI0_B5,
5525 GP_4_9_FN, FN_VI0_DATA4_VI0_B4,
5526 GP_4_8_FN, FN_IP9_28_27,
5527 GP_4_7_FN, FN_VI0_DATA2_VI0_B2,
5528 GP_4_6_FN, FN_VI0_DATA1_VI0_B1,
5529 GP_4_5_FN, FN_VI0_DATA0_VI0_B0,
5530 GP_4_4_FN, FN_IP9_26_25,
5531 GP_4_3_FN, FN_IP9_24_23,
5532 GP_4_2_FN, FN_IP9_22_21,
5533 GP_4_1_FN, FN_IP9_20_19,
5534 GP_4_0_FN, FN_VI0_CLK }
5536 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
5537 GP_5_31_FN, FN_IP3_24_22,
5538 GP_5_30_FN, FN_IP13_9_7,
5539 GP_5_29_FN, FN_IP13_6_5,
5540 GP_5_28_FN, FN_IP13_4_3,
5541 GP_5_27_FN, FN_IP13_2_0,
5542 GP_5_26_FN, FN_IP12_29_27,
5543 GP_5_25_FN, FN_IP12_26_24,
5544 GP_5_24_FN, FN_IP12_23_22,
5545 GP_5_23_FN, FN_IP12_21_20,
5546 GP_5_22_FN, FN_IP12_19_18,
5547 GP_5_21_FN, FN_IP12_17_16,
5548 GP_5_20_FN, FN_IP12_15_13,
5549 GP_5_19_FN, FN_IP12_12_10,
5550 GP_5_18_FN, FN_IP12_9_7,
5551 GP_5_17_FN, FN_IP12_6_4,
5552 GP_5_16_FN, FN_IP12_3_2,
5553 GP_5_15_FN, FN_IP12_1_0,
5554 GP_5_14_FN, FN_IP11_31_30,
5555 GP_5_13_FN, FN_IP11_29_28,
5556 GP_5_12_FN, FN_IP11_27,
5557 GP_5_11_FN, FN_IP11_26,
5558 GP_5_10_FN, FN_IP11_25,
5559 GP_5_9_FN, FN_IP11_24,
5560 GP_5_8_FN, FN_IP11_23,
5561 GP_5_7_FN, FN_IP11_22,
5562 GP_5_6_FN, FN_IP11_21,
5563 GP_5_5_FN, FN_IP11_20,
5564 GP_5_4_FN, FN_IP11_19,
5565 GP_5_3_FN, FN_IP11_18_17,
5566 GP_5_2_FN, FN_IP11_16_15,
5567 GP_5_1_FN, FN_IP11_14_12,
5568 GP_5_0_FN, FN_IP11_11_9 }
5570 { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
5571 GP_6_31_FN, FN_DU0_DOTCLKIN,
5572 GP_6_30_FN, FN_USB1_OVC,
5573 GP_6_29_FN, FN_IP14_31_29,
5574 GP_6_28_FN, FN_IP14_28_26,
5575 GP_6_27_FN, FN_IP14_25_23,
5576 GP_6_26_FN, FN_IP14_22_20,
5577 GP_6_25_FN, FN_IP14_19_17,
5578 GP_6_24_FN, FN_IP14_16_14,
5579 GP_6_23_FN, FN_IP14_13_11,
5580 GP_6_22_FN, FN_IP14_10_8,
5581 GP_6_21_FN, FN_IP14_7,
5582 GP_6_20_FN, FN_IP14_6,
5583 GP_6_19_FN, FN_IP14_5,
5584 GP_6_18_FN, FN_IP14_4,
5585 GP_6_17_FN, FN_IP14_3,
5586 GP_6_16_FN, FN_IP14_2,
5587 GP_6_15_FN, FN_IP14_1_0,
5588 GP_6_14_FN, FN_IP13_30_28,
5589 GP_6_13_FN, FN_IP13_27,
5590 GP_6_12_FN, FN_IP13_26,
5591 GP_6_11_FN, FN_IP13_25,
5592 GP_6_10_FN, FN_IP13_24_23,
5593 GP_6_9_FN, FN_IP13_22,
5594 GP_6_8_FN, FN_SD1_CLK,
5595 GP_6_7_FN, FN_IP13_21_19,
5596 GP_6_6_FN, FN_IP13_18_16,
5597 GP_6_5_FN, FN_IP13_15,
5598 GP_6_4_FN, FN_IP13_14,
5599 GP_6_3_FN, FN_IP13_13,
5600 GP_6_2_FN, FN_IP13_12,
5601 GP_6_1_FN, FN_IP13_11,
5602 GP_6_0_FN, FN_IP13_10 }
5604 { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1) {
5611 GP_7_25_FN, FN_USB1_PWEN,
5612 GP_7_24_FN, FN_USB0_OVC,
5613 GP_7_23_FN, FN_USB0_PWEN,
5614 GP_7_22_FN, FN_IP15_14_12,
5615 GP_7_21_FN, FN_IP15_11_9,
5616 GP_7_20_FN, FN_IP15_8_6,
5617 GP_7_19_FN, FN_IP7_2_0,
5618 GP_7_18_FN, FN_IP6_29_27,
5619 GP_7_17_FN, FN_IP6_26_24,
5620 GP_7_16_FN, FN_IP6_23_21,
5621 GP_7_15_FN, FN_IP6_20_19,
5622 GP_7_14_FN, FN_IP6_18_16,
5623 GP_7_13_FN, FN_IP6_15_14,
5624 GP_7_12_FN, FN_IP6_13_12,
5625 GP_7_11_FN, FN_IP6_11_10,
5626 GP_7_10_FN, FN_IP6_9_8,
5627 GP_7_9_FN, FN_IP16_11_10,
5628 GP_7_8_FN, FN_IP16_9_8,
5629 GP_7_7_FN, FN_IP16_7_6,
5630 GP_7_6_FN, FN_IP16_5_3,
5631 GP_7_5_FN, FN_IP16_2_0,
5632 GP_7_4_FN, FN_IP15_29_27,
5633 GP_7_3_FN, FN_IP15_26_24,
5634 GP_7_2_FN, FN_IP15_23_21,
5635 GP_7_1_FN, FN_IP15_20_18,
5636 GP_7_0_FN, FN_IP15_17_15 }
5638 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
5639 1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1, 1, 1, 1, 1,
5640 1, 1, 1, 1, 1, 1, 1, 1) {
5644 FN_A6, FN_MSIOF1_SCK,
5647 FN_A5, FN_MSIOF0_RXD_B,
5650 FN_A4, FN_MSIOF0_TXD_B,
5653 FN_A3, FN_MSIOF0_SS2_B,
5656 FN_A2, FN_MSIOF0_SS1_B,
5659 FN_A1, FN_MSIOF0_SYNC_B,
5662 FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_I2C0_SCL_C, FN_PWM2_B,
5697 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
5698 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2) {
5700 FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, 0, FN_SCIFB1_RXD_C,
5703 FN_A17, FN_DACK2_B, 0, FN_I2C0_SDA_C,
5706 FN_A16, FN_DREQ2_B, FN_FMCLK_C, 0, FN_SCIFA1_SCK_B,
5709 FN_A15, FN_BPFCLK_C,
5712 FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D,
5715 FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D,
5718 FN_A12, FN_FMCLK, FN_I2C3_SDA_D, FN_MSIOF1_SCK_D,
5721 FN_A11, FN_MSIOF1_RXD, FN_I2C3_SCL_D, FN_MSIOF1_RXD_D,
5724 FN_A10, FN_MSIOF1_TXD, 0, FN_MSIOF1_TXD_D,
5726 FN_A9, FN_MSIOF1_SS2, FN_I2C0_SDA, 0,
5728 FN_A8, FN_MSIOF1_SS1, FN_I2C0_SCL, 0,
5730 FN_A7, FN_MSIOF1_SYNC,
5733 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
5734 2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3) {
5738 FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD,
5739 FN_ATAG0_N, 0, FN_EX_WAIT1,
5742 FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC, 0,
5744 FN_EX_CS1_N, FN_MSIOF2_SCK, 0, 0,
5746 FN_CS1_N_A26, FN_ATADIR0_N_B, FN_I2C1_SDA, 0,
5748 FN_CS0_N, FN_ATAG0_N_B, FN_I2C1_SCL, 0,
5750 FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD,
5753 FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD,
5756 FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD,
5759 FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD,
5762 FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0, 0,
5764 FN_A20, FN_SPCLK, 0, 0,
5766 FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, 0,
5767 FN_SCIFB1_TXD_C, 0, FN_SCIFB1_SCK_B, 0, }
5769 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
5770 1, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 3) {
5774 FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C,
5775 FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C,
5778 FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C,
5779 FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C,
5782 FN_SPEEDIN, 0, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B,
5783 FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D,
5785 FN_DACK0, FN_DRACK0, FN_REMOCON, 0,
5787 FN_DREQ0, FN_PWM3, FN_TPU_TO3, 0,
5789 FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B, 0,
5791 FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B,
5793 FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B, 0,
5795 FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D,
5798 FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B,
5799 FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2, 0,
5801 FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B,
5802 FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1, 0,
5804 FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, 0, FN_EX_WAIT2,
5807 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5808 1, 3, 2, 2, 2, 1, 1, 1, 3, 3, 3, 2, 3, 3, 2) {
5812 FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0,
5813 FN_MSIOF2_SYNC_D, FN_VI1_R2_B,
5816 FN_SSI_SDATA4, FN_MSIOF2_SCK_D, 0, 0,
5818 FN_SSI_WS4, FN_GLO_RFON_D, 0, 0,
5820 FN_SSI_SCK4, FN_GLO_SS_D, 0, 0,
5828 FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E,
5831 FN_SSI_WS2, FN_I2C2_SDA, FN_GPS_SIGN_B, FN_RX2_E,
5832 FN_GLO_Q1_D, FN_HCTS1_N_E,
5835 FN_SSI_SCK2, FN_I2C2_SCL, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E,
5838 FN_SSI_SDATA1, FN_I2C1_SDA_B, FN_IIC1_SDA_B, FN_MSIOF2_RXD_C,
5840 FN_SSI_WS1, FN_I2C1_SCL_B, FN_IIC1_SCL_B, FN_MSIOF2_TXD_C,
5841 FN_GLO_I1_D, 0, 0, 0,
5843 FN_SSI_SCK1, FN_I2C0_SDA_B, FN_IIC0_SDA_B,
5844 FN_MSIOF2_SYNC_C, FN_GLO_I0_D,
5847 FN_SSI_SDATA0, FN_I2C0_SCL_B, FN_IIC0_SCL_B, FN_MSIOF2_SCK_C, }
5849 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5850 3, 3, 2, 2, 2, 3, 2, 3, 3, 3, 3, 3) {
5852 FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D,
5855 FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D,
5858 FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D, 0,
5860 FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B, 0,
5862 FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B, 0,
5864 FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON,
5867 FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS, 0,
5869 FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B,
5872 FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B,
5875 FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1,
5876 FN_MSIOF2_RXD_D, FN_VI1_R5_B,
5879 FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0,
5880 FN_MSIOF2_SS1_D, FN_VI1_R4_B,
5883 FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1,
5884 FN_MSIOF2_TXD_D, FN_VI1_R3_B,
5887 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5888 2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3) {
5892 FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B,
5893 FN_GPS_SIGN_C, FN_GPS_SIGN_D,
5896 FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B,
5897 FN_GPS_CLK_C, FN_GPS_CLK_D,
5900 FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B,
5901 FN_I2C1_SDA_E, FN_MSIOF2_SYNC_E,
5904 FN_IRQ5, FN_HTX1_C, FN_I2C1_SCL_E, FN_MSIOF2_SCK_E,
5906 FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E,
5907 FN_INTC_IRQ4_N, 0, 0, 0,
5909 FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
5911 FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, 0,
5913 FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N, 0,
5915 FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N, 0,
5917 FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
5919 FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
5920 FN_SCIFA2_RXD, FN_FMIN_E,
5923 FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
5924 FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E,
5927 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
5928 2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 3) {
5932 FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B,
5933 FN_SCIFA1_SCK, FN_SSI_SCK78_B,
5936 FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B,
5937 FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B,
5940 FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B,
5941 FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B,
5944 FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B, 0,
5946 FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B, 0,
5948 FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B, 0,
5950 FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B, 0,
5952 FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B, 0,
5954 FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B, 0,
5956 FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B,
5957 FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B,
5960 FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B,
5961 FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B,
5964 FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C,
5965 FN_SCIF_CLK_B, FN_GPS_MAG_D,
5968 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
5969 1, 3, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3) {
5973 FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX,
5976 FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX,
5978 FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B, 0,
5980 FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B,
5981 FN_SCIFA2_SCK, FN_SSI_SDATA9_B,
5984 FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B,
5985 FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B,
5988 FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B,
5989 FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B,
5992 FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B,
5993 FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B,
5996 FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B,
5997 FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B,
6000 FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B,
6001 FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B,
6004 FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B,
6005 FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B,
6008 FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, 0, FN_SSI_WS78_B,
6011 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
6012 3, 2, 2, 2, 2, 2, 2, 1, 3, 1, 1, 3, 1, 1, 3, 3) {
6014 FN_VI0_G0, FN_IIC1_SCL, FN_STP_IVCXO27_0_C, FN_I2C4_SCL,
6015 FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N, 0,
6017 FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B, 0,
6019 FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D,
6021 FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D,
6023 FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D,
6025 FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D,
6027 FN_DU1_CDE, FN_QPOLB, FN_PWM4_B, 0,
6029 FN_DU1_DISP, FN_QPOLA,
6031 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE,
6032 FN_CAN0_RX, FN_RX3_B, FN_I2C2_SDA_B,
6035 FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE,
6037 FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS,
6039 FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX,
6040 FN_TX3_B, FN_I2C2_SCL_B, FN_PWM4,
6043 FN_DU1_DOTCLKOUT0, FN_QCLK,
6045 FN_DU1_DOTCLKIN, FN_QSTVA_QVS,
6047 FN_DU1_DB7, FN_LCDOUT23, FN_I2C3_SDA_C,
6048 FN_SCIF3_SCK, FN_SCIFA3_SCK,
6051 FN_DU1_DB6, FN_LCDOUT22, FN_I2C3_SCL_C, FN_RX3, FN_SCIFA3_RXD,
6054 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
6055 3, 2, 2, 3, 3, 2, 2, 3, 3, 3, 3, 3) {
6056 /* IP10_31_29 [3] */
6057 FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_I2C1_SCL_D,
6059 /* IP10_28_27 [2] */
6060 FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C,
6061 /* IP10_26_25 [2] */
6062 FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C,
6063 /* IP10_24_22 [3] */
6064 FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B, FN_TS_SCK0_C, FN_ATAG1_N,
6066 /* IP10_21_19 [3] */
6067 FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B,
6068 FN_TS_SDATA0_C, FN_ATACS11_N,
6070 /* IP10_18_17 [2] */
6071 FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D, 0,
6072 /* IP10_16_15 [2] */
6073 FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D, 0,
6074 /* IP10_14_12 [3] */
6075 FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D,
6076 FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D, 0,
6078 FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C,
6079 FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D,
6082 FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_I2C3_SDA_B,
6083 FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N, 0,
6085 FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_I2C3_SCL_B,
6086 FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N, 0,
6088 FN_VI0_G1, FN_IIC1_SDA, FN_STP_ISCLK_0_C, FN_I2C4_SDA,
6089 FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, 0, }
6091 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
6092 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
6094 /* IP11_31_30 [2] */
6095 FN_ETH_CRS_DV, FN_AVB_LINK, FN_I2C2_SDA_C, 0,
6096 /* IP11_29_28 [2] */
6097 FN_ETH_MDIO, FN_AVB_RX_CLK, FN_I2C2_SCL_C, 0,
6099 FN_VI1_DATA7, FN_AVB_MDC,
6101 FN_VI1_DATA6, FN_AVB_MAGIC,
6103 FN_VI1_DATA5, FN_AVB_RX_DV,
6105 FN_VI1_DATA4, FN_AVB_MDIO,
6107 FN_VI1_DATA3, FN_AVB_RX_ER,
6109 FN_VI1_DATA2, FN_AVB_RXD7,
6111 FN_VI1_DATA1, FN_AVB_RXD6,
6113 FN_VI1_DATA0, FN_AVB_RXD5,
6115 FN_VI1_CLK, FN_AVB_RXD4,
6116 /* IP11_18_17 [2] */
6117 FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, 0,
6118 /* IP11_16_15 [2] */
6119 FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, 0,
6120 /* IP11_14_12 [3] */
6121 FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B,
6122 FN_RX4_B, FN_SCIFA4_RXD_B,
6125 FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B,
6126 FN_TX4_B, FN_SCIFA4_TXD_B,
6129 FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
6130 FN_I2C4_SDA_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 0,
6132 FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_I2C4_SCL_B,
6135 FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C,
6136 FN_I2C1_SDA_D, 0, 0, 0, }
6138 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
6139 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2) {
6140 /* IP12_31_30 [2] */
6142 /* IP12_29_27 [3] */
6143 FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
6144 FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
6146 /* IP12_26_24 [3] */
6147 FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
6148 FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
6150 /* IP12_23_22 [2] */
6151 FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, 0,
6152 /* IP12_21_20 [2] */
6153 FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, 0,
6154 /* IP12_19_18 [2] */
6155 FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, 0,
6156 /* IP12_17_16 [2] */
6157 FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
6158 /* IP12_15_13 [3] */
6159 FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
6160 FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
6162 /* IP12_12_10 [3] */
6163 FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
6164 FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
6167 FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C,
6168 FN_I2C2_SDA_D, FN_MSIOF1_SCK_E,
6171 FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
6172 FN_I2C2_SCL_D, FN_MSIOF1_RXD_E,
6175 FN_ETH_RXD0, FN_AVB_PHY_INT, FN_I2C3_SDA, FN_IIC0_SDA,
6177 FN_ETH_RX_ER, FN_AVB_CRS, FN_I2C3_SCL, FN_IIC0_SCL, }
6179 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
6180 1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1, 1, 1, 1,
6184 /* IP13_30_28 [3] */
6185 FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_I2C1_SCL_C,
6188 FN_SD1_DATA3, FN_IERX_B,
6190 FN_SD1_DATA2, FN_IECLK_B,
6192 FN_SD1_DATA1, FN_IETX_B,
6193 /* IP13_24_23 [2] */
6194 FN_SD1_DATA0, FN_SPEEDIN_B, 0, 0,
6196 FN_SD1_CMD, FN_REMOCON_B,
6197 /* IP13_21_19 [3] */
6198 FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
6199 FN_SCIFA5_RXD_B, FN_RX3_C,
6201 /* IP13_18_16 [3] */
6202 FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
6203 FN_SCIFA5_TXD_B, FN_TX3_C,
6206 FN_SD0_DATA3, FN_SSL_B,
6208 FN_SD0_DATA2, FN_IO3_B,
6210 FN_SD0_DATA1, FN_IO2_B,
6212 FN_SD0_DATA0, FN_MISO_IO1_B,
6214 FN_SD0_CMD, FN_MOSI_IO0_B,
6216 FN_SD0_CLK, FN_SPCLK_B,
6218 FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
6219 FN_ADICHS2_B, FN_MSIOF0_TXD_C,
6222 FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
6224 FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
6226 FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
6227 FN_ADICLK_B, FN_MSIOF0_SS1_C,
6230 { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
6231 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 2) {
6232 /* IP14_31_29 [3] */
6233 FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
6234 FN_VI1_VSYNC_N_C, FN_IIC0_SDA_C, FN_VI1_G5_B, 0,
6235 /* IP14_28_26 [3] */
6236 FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
6237 FN_VI1_HSYNC_N_C, FN_IIC0_SCL_C, FN_VI1_G4_B, 0,
6238 /* IP14_25_23 [3] */
6239 FN_MSIOF0_RXD, FN_ADICHS0, 0, FN_VI1_DATA0_C, FN_VI1_G3_B,
6241 /* IP14_22_20 [3] */
6242 FN_MSIOF0_TXD, FN_ADICLK, 0, FN_VI1_FIELD_C, FN_VI1_G2_B,
6244 /* IP14_19_17 [3] */
6245 FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, 0,
6246 FN_VI1_CLKENB_C, FN_VI1_G1_B,
6248 /* IP14_16_14 [3] */
6249 FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, 0,
6250 FN_VI1_CLK_C, FN_VI1_G0_B,
6252 /* IP14_13_11 [3] */
6253 FN_SD2_WP, FN_MMC_D5, FN_IIC1_SDA_C, FN_RX5_B, FN_SCIFA5_RXD_C,
6256 FN_SD2_CD, FN_MMC_D4, FN_IIC1_SCL_C, FN_TX5_B, FN_SCIFA5_TXD_C,
6259 FN_SD2_DATA3, FN_MMC_D3,
6261 FN_SD2_DATA2, FN_MMC_D2,
6263 FN_SD2_DATA1, FN_MMC_D1,
6265 FN_SD2_DATA0, FN_MMC_D0,
6267 FN_SD2_CMD, FN_MMC_CMD,
6269 FN_SD2_CLK, FN_MMC_CLK,
6271 FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C, 0, }
6273 { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
6274 2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2) {
6275 /* IP15_31_30 [2] */
6277 /* IP15_29_27 [3] */
6278 FN_HTX0, FN_SCIFB0_TXD, 0, FN_GLO_SCLK_C,
6279 FN_CAN0_TX_B, FN_VI1_DATA5_C,
6281 /* IP15_26_24 [3] */
6282 FN_HRX0, FN_SCIFB0_RXD, 0, FN_GLO_Q1_C,
6283 FN_CAN0_RX_B, FN_VI1_DATA4_C,
6285 /* IP15_23_21 [3] */
6286 FN_HSCK0, FN_SCIFB0_SCK, 0, FN_GLO_Q0_C, FN_CAN_CLK,
6287 FN_TCLK2, FN_VI1_DATA3_C, 0,
6288 /* IP15_20_18 [3] */
6289 FN_HRTS0_N, FN_SCIFB0_RTS_N, 0, FN_GLO_I1_C, FN_VI1_DATA2_C,
6291 /* IP15_17_15 [3] */
6292 FN_HCTS0_N, FN_SCIFB0_CTS_N, 0, FN_GLO_I0_C,
6293 FN_TCLK1, FN_VI1_DATA1_C,
6295 /* IP15_14_12 [3] */
6296 FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
6297 FN_VI1_G7_B, FN_SCIFA3_SCK_C,
6300 FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
6301 FN_VI1_G6_B, FN_SCIFA3_RXD_C,
6304 FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
6305 FN_PWM5_B, FN_SCIFA3_TXD_C,
6308 FN_SIM0_D, FN_IERX, FN_CAN1_RX_D, 0,
6310 FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C, 0,
6312 FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, }
6314 { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
6315 4, 4, 4, 4, 4, 2, 2, 2, 3, 3) {
6316 /* IP16_31_28 [4] */
6317 0, 0, 0, 0, 0, 0, 0, 0,
6318 0, 0, 0, 0, 0, 0, 0, 0,
6319 /* IP16_27_24 [4] */
6320 0, 0, 0, 0, 0, 0, 0, 0,
6321 0, 0, 0, 0, 0, 0, 0, 0,
6322 /* IP16_23_20 [4] */
6323 0, 0, 0, 0, 0, 0, 0, 0,
6324 0, 0, 0, 0, 0, 0, 0, 0,
6325 /* IP16_19_16 [4] */
6326 0, 0, 0, 0, 0, 0, 0, 0,
6327 0, 0, 0, 0, 0, 0, 0, 0,
6328 /* IP16_15_12 [4] */
6329 0, 0, 0, 0, 0, 0, 0, 0,
6330 0, 0, 0, 0, 0, 0, 0, 0,
6331 /* IP16_11_10 [2] */
6332 FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
6334 FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
6336 FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CLK, FN_GLO_RFON_C,
6338 FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B,
6339 FN_GLO_SS_C, FN_VI1_DATA7_C,
6342 FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B,
6343 FN_GLO_SDATA_C, FN_VI1_DATA6_C,
6346 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
6347 1, 2, 2, 2, 3, 2, 1, 1, 1, 1,
6348 3, 2, 2, 2, 1, 2, 2, 2) {
6352 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
6354 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
6355 /* SEL_SCIFB2 [2] */
6356 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1,
6357 FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
6358 /* SEL_SCIFB1 [3] */
6359 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1,
6360 FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
6362 /* SEL_SCIFA1 [2] */
6363 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
6365 FN_SEL_SSI9_0, FN_SEL_SSI9_1,
6367 FN_SEL_SCFA_0, FN_SEL_SCFA_1,
6369 FN_SEL_QSP_0, FN_SEL_QSP_1,
6371 FN_SEL_SSI7_0, FN_SEL_SSI7_1,
6372 /* SEL_HSCIF1 [3] */
6373 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2,
6374 FN_SEL_HSCIF1_3, FN_SEL_HSCIF1_4,
6379 FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0,
6383 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
6385 FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
6387 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
6389 FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, }
6391 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
6392 3, 1, 1, 3, 2, 1, 1, 2, 2,
6393 1, 3, 2, 1, 2, 2, 2, 1, 1, 1) {
6395 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2,
6396 FN_SEL_SCIF0_3, FN_SEL_SCIF0_4,
6401 FN_SEL_SCIF_0, FN_SEL_SCIF_1,
6403 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
6404 FN_SEL_CAN0_4, FN_SEL_CAN0_5,
6407 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
6410 /* SEL_SCIFA2 [1] */
6411 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
6413 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0,
6417 FN_SEL_ADG_0, FN_SEL_ADG_1,
6419 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2,
6420 FN_SEL_FM_3, FN_SEL_FM_4,
6422 /* SEL_SCIFA5 [2] */
6423 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0,
6427 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
6428 /* SEL_SCIFA4 [2] */
6429 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 0,
6430 /* SEL_SCIFA3 [2] */
6431 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0,
6433 FN_SEL_SIM_0, FN_SEL_SIM_1,
6437 FN_SEL_SSI8_0, FN_SEL_SSI8_1, }
6439 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
6440 2, 2, 2, 2, 2, 2, 2, 2,
6441 1, 1, 2, 2, 3, 2, 2, 2, 1) {
6442 /* SEL_HSCIF2 [2] */
6443 FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,
6444 FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
6445 /* SEL_CANCLK [2] */
6446 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
6447 FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
6449 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0,
6451 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0,
6453 FN_SEL_I2C4_0, FN_SEL_I2C4_1, FN_SEL_I2C4_2, 0,
6455 FN_SEL_I2C3_0, FN_SEL_I2C3_1, FN_SEL_I2C3_2, FN_SEL_I2C3_3,
6457 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
6459 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
6461 FN_SEL_MMC_0, FN_SEL_MMC_1,
6463 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
6467 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
6469 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3,
6473 FN_SEL_I2C0_0, FN_SEL_I2C0_1, FN_SEL_I2C0_2, 0,
6481 { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32,
6482 3, 2, 2, 1, 1, 1, 1, 3, 2,
6483 2, 3, 1, 1, 1, 2, 2, 2, 2) {
6485 FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
6488 /* SEL_HSCIF0 [2] */
6489 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 0,
6491 FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0,
6495 FN_SEL_RAD_0, FN_SEL_RAD_1,
6497 FN_SEL_RCN_0, FN_SEL_RCN_1,
6499 FN_SEL_RSP_0, FN_SEL_RSP_1,
6501 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
6502 FN_SEL_SCIF2_3, FN_SEL_SCIF2_4,
6509 FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2,
6510 FN_SEL_SOF2_3, FN_SEL_SOF2_4,
6515 FN_SEL_SSI1_0, FN_SEL_SSI1_1,
6517 FN_SEL_SSI0_0, FN_SEL_SSI0_1,
6519 FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0,
6530 static int r8a7791_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
6532 if (pin < RCAR_GP_PIN(6, 0) || pin > RCAR_GP_PIN(6, 23))
6535 *pocctrl = 0xe606008c;
6537 return 31 - (pin & 0x1f);
6540 static const struct sh_pfc_soc_operations r8a7791_pinmux_ops = {
6541 .pin_to_pocctrl = r8a7791_pin_to_pocctrl,
6544 #ifdef CONFIG_PINCTRL_PFC_R8A7743
6545 const struct sh_pfc_soc_info r8a7743_pinmux_info = {
6546 .name = "r8a77430_pfc",
6547 .ops = &r8a7791_pinmux_ops,
6548 .unlock_reg = 0xe6060000, /* PMMR */
6550 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6552 .pins = pinmux_pins,
6553 .nr_pins = ARRAY_SIZE(pinmux_pins),
6554 .groups = pinmux_groups.common,
6555 .nr_groups = ARRAY_SIZE(pinmux_groups.common),
6556 .functions = pinmux_functions.common,
6557 .nr_functions = ARRAY_SIZE(pinmux_functions.common),
6559 .cfg_regs = pinmux_config_regs,
6561 .pinmux_data = pinmux_data,
6562 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6566 #ifdef CONFIG_PINCTRL_PFC_R8A7791
6567 const struct sh_pfc_soc_info r8a7791_pinmux_info = {
6568 .name = "r8a77910_pfc",
6569 .ops = &r8a7791_pinmux_ops,
6570 .unlock_reg = 0xe6060000, /* PMMR */
6572 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6574 .pins = pinmux_pins,
6575 .nr_pins = ARRAY_SIZE(pinmux_pins),
6576 .groups = pinmux_groups.common,
6577 .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
6578 ARRAY_SIZE(pinmux_groups.r8a779x),
6579 .functions = pinmux_functions.common,
6580 .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
6581 ARRAY_SIZE(pinmux_functions.r8a779x),
6583 .cfg_regs = pinmux_config_regs,
6585 .pinmux_data = pinmux_data,
6586 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6590 #ifdef CONFIG_PINCTRL_PFC_R8A7793
6591 const struct sh_pfc_soc_info r8a7793_pinmux_info = {
6592 .name = "r8a77930_pfc",
6593 .ops = &r8a7791_pinmux_ops,
6594 .unlock_reg = 0xe6060000, /* PMMR */
6596 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6598 .pins = pinmux_pins,
6599 .nr_pins = ARRAY_SIZE(pinmux_pins),
6600 .groups = pinmux_groups.common,
6601 .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
6602 ARRAY_SIZE(pinmux_groups.r8a779x),
6603 .functions = pinmux_functions.common,
6604 .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
6605 ARRAY_SIZE(pinmux_functions.r8a779x),
6607 .cfg_regs = pinmux_config_regs,
6609 .pinmux_data = pinmux_data,
6610 .pinmux_data_size = ARRAY_SIZE(pinmux_data),