drivers/pinctrl/sunxi/pinctrl-sunxi.h

   1 /*
   2  * Allwinner A1X SoCs pinctrl driver.
   3  *
   4  * Copyright (C) 2012 Maxime Ripard
   5  *
   6  * Maxime Ripard <maxime.ripard@free-electrons.com>
   7  *
   8  * This file is licensed under the terms of the GNU General Public
   9  * License version 2.  This program is licensed "as is" without any
  10  * warranty of any kind, whether express or implied.
  11  */
  12
  13 #ifndef __PINCTRL_SUNXI_H
  14 #define __PINCTRL_SUNXI_H
  15
  16 #include <linux/kernel.h>
  17 #include <linux/spinlock.h>
  18
  19 #define PA_BASE 0
  20 #define PB_BASE 32
  21 #define PC_BASE 64
  22 #define PD_BASE 96
  23 #define PE_BASE 128
  24 #define PF_BASE 160
  25 #define PG_BASE 192
  26 #define PH_BASE 224
  27 #define PI_BASE 256
  28 #define PL_BASE 352
  29 #define PM_BASE 384
  30 #define PN_BASE 416
  31
  32 #define SUNXI_PINCTRL_PIN(bank, pin)            \
  33         PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin)
  34
  35 #define SUNXI_PIN_NAME_MAX_LEN  5
  36
  37 #define BANK_MEM_SIZE           0x24
  38 #define MUX_REGS_OFFSET         0x0
  39 #define DATA_REGS_OFFSET        0x10
  40 #define DLEVEL_REGS_OFFSET      0x14
  41 #define PULL_REGS_OFFSET        0x1c
  42
  43 #define PINS_PER_BANK           32
  44 #define MUX_PINS_PER_REG        8
  45 #define MUX_PINS_BITS           4
  46 #define MUX_PINS_MASK           0x0f
  47 #define DATA_PINS_PER_REG       32
  48 #define DATA_PINS_BITS          1
  49 #define DATA_PINS_MASK          0x01
  50 #define DLEVEL_PINS_PER_REG     16
  51 #define DLEVEL_PINS_BITS        2
  52 #define DLEVEL_PINS_MASK        0x03
  53 #define PULL_PINS_PER_REG       16
  54 #define PULL_PINS_BITS          2
  55 #define PULL_PINS_MASK          0x03
  56
  57 #define IRQ_PER_BANK            32
  58
  59 #define IRQ_CFG_REG             0x200
  60 #define IRQ_CFG_IRQ_PER_REG             8
  61 #define IRQ_CFG_IRQ_BITS                4
  62 #define IRQ_CFG_IRQ_MASK                ((1 << IRQ_CFG_IRQ_BITS) - 1)
  63 #define IRQ_CTRL_REG            0x210
  64 #define IRQ_CTRL_IRQ_PER_REG            32
  65 #define IRQ_CTRL_IRQ_BITS               1
  66 #define IRQ_CTRL_IRQ_MASK               ((1 << IRQ_CTRL_IRQ_BITS) - 1)
  67 #define IRQ_STATUS_REG          0x214
  68 #define IRQ_STATUS_IRQ_PER_REG          32
  69 #define IRQ_STATUS_IRQ_BITS             1
  70 #define IRQ_STATUS_IRQ_MASK             ((1 << IRQ_STATUS_IRQ_BITS) - 1)
  71
  72 #define IRQ_MEM_SIZE            0x20
  73
  74 #define IRQ_EDGE_RISING         0x00
  75 #define IRQ_EDGE_FALLING        0x01
  76 #define IRQ_LEVEL_HIGH          0x02
  77 #define IRQ_LEVEL_LOW           0x03
  78 #define IRQ_EDGE_BOTH           0x04
  79
  80 struct sunxi_desc_function {
  81         const char      *name;
  82         u8              muxval;
  83         u8              irqbank;
  84         u8              irqnum;
  85 };
  86
  87 struct sunxi_desc_pin {
  88         struct pinctrl_pin_desc         pin;
  89         struct sunxi_desc_function      *functions;
  90 };
  91
  92 struct sunxi_pinctrl_desc {
  93         const struct sunxi_desc_pin     *pins;
  94         int                             npins;
  95         unsigned                        pin_base;
  96         unsigned                        irq_banks;
  97 };
  98
  99 struct sunxi_pinctrl_function {
 100         const char      *name;
 101         const char      **groups;
 102         unsigned        ngroups;
 103 };
 104
 105 struct sunxi_pinctrl_group {
 106         const char      *name;
 107         unsigned long   config;
 108         unsigned        pin;
 109 };
 110
 111 struct sunxi_pinctrl {
 112         void __iomem                    *membase;
 113         struct gpio_chip                *chip;
 114         const struct sunxi_pinctrl_desc *desc;
 115         struct device                   *dev;
 116         struct irq_domain               *domain;
 117         struct sunxi_pinctrl_function   *functions;
 118         unsigned                        nfunctions;
 119         struct sunxi_pinctrl_group      *groups;
 120         unsigned                        ngroups;
 121         int                             *irq;
 122         unsigned                        *irq_array;
 123         spinlock_t                      lock;
 124         struct pinctrl_dev              *pctl_dev;
 125 };
 126
 127 #define SUNXI_PIN(_pin, ...)                                    \
 128         {                                                       \
 129                 .pin = _pin,                                    \
 130                 .functions = (struct sunxi_desc_function[]){    \
 131                         __VA_ARGS__, { } },                     \
 132         }
 133
 134 #define SUNXI_FUNCTION(_val, _name)                             \
 135         {                                                       \
 136                 .name = _name,                                  \
 137                 .muxval = _val,                                 \
 138         }
 139
 140 #define SUNXI_FUNCTION_IRQ(_val, _irq)                          \
 141         {                                                       \
 142                 .name = "irq",                                  \
 143                 .muxval = _val,                                 \
 144                 .irqnum = _irq,                                 \
 145         }
 146
 147 #define SUNXI_FUNCTION_IRQ_BANK(_val, _bank, _irq)              \
 148         {                                                       \
 149                 .name = "irq",                                  \
 150                 .muxval = _val,                                 \
 151                 .irqbank = _bank,                               \
 152                 .irqnum = _irq,                                 \
 153         }
 154
 155 /*
 156  * The sunXi PIO registers are organized as is:
 157  * 0x00 - 0x0c  Muxing values.
 158  *              8 pins per register, each pin having a 4bits value
 159  * 0x10         Pin values
 160  *              32 bits per register, each pin corresponding to one bit
 161  * 0x14 - 0x18  Drive level
 162  *              16 pins per register, each pin having a 2bits value
 163  * 0x1c - 0x20  Pull-Up values
 164  *              16 pins per register, each pin having a 2bits value
 165  *
 166  * This is for the first bank. Each bank will have the same layout,
 167  * with an offset being a multiple of 0x24.
 168  *
 169  * The following functions calculate from the pin number the register
 170  * and the bit offset that we should access.
 171  */
 172 static inline u32 sunxi_mux_reg(u16 pin)
 173 {
 174         u8 bank = pin / PINS_PER_BANK;
 175         u32 offset = bank * BANK_MEM_SIZE;
 176         offset += MUX_REGS_OFFSET;
 177         offset += pin % PINS_PER_BANK / MUX_PINS_PER_REG * 0x04;
 178         return round_down(offset, 4);
 179 }
 180
 181 static inline u32 sunxi_mux_offset(u16 pin)
 182 {
 183         u32 pin_num = pin % MUX_PINS_PER_REG;
 184         return pin_num * MUX_PINS_BITS;
 185 }
 186
 187 static inline u32 sunxi_data_reg(u16 pin)
 188 {
 189         u8 bank = pin / PINS_PER_BANK;
 190         u32 offset = bank * BANK_MEM_SIZE;
 191         offset += DATA_REGS_OFFSET;
 192         offset += pin % PINS_PER_BANK / DATA_PINS_PER_REG * 0x04;
 193         return round_down(offset, 4);
 194 }
 195
 196 static inline u32 sunxi_data_offset(u16 pin)
 197 {
 198         u32 pin_num = pin % DATA_PINS_PER_REG;
 199         return pin_num * DATA_PINS_BITS;
 200 }
 201
 202 static inline u32 sunxi_dlevel_reg(u16 pin)
 203 {
 204         u8 bank = pin / PINS_PER_BANK;
 205         u32 offset = bank * BANK_MEM_SIZE;
 206         offset += DLEVEL_REGS_OFFSET;
 207         offset += pin % PINS_PER_BANK / DLEVEL_PINS_PER_REG * 0x04;
 208         return round_down(offset, 4);
 209 }
 210
 211 static inline u32 sunxi_dlevel_offset(u16 pin)
 212 {
 213         u32 pin_num = pin % DLEVEL_PINS_PER_REG;
 214         return pin_num * DLEVEL_PINS_BITS;
 215 }
 216
 217 static inline u32 sunxi_pull_reg(u16 pin)
 218 {
 219         u8 bank = pin / PINS_PER_BANK;
 220         u32 offset = bank * BANK_MEM_SIZE;
 221         offset += PULL_REGS_OFFSET;
 222         offset += pin % PINS_PER_BANK / PULL_PINS_PER_REG * 0x04;
 223         return round_down(offset, 4);
 224 }
 225
 226 static inline u32 sunxi_pull_offset(u16 pin)
 227 {
 228         u32 pin_num = pin % PULL_PINS_PER_REG;
 229         return pin_num * PULL_PINS_BITS;
 230 }
 231
 232 static inline u32 sunxi_irq_cfg_reg(u16 irq)
 233 {
 234         u8 bank = irq / IRQ_PER_BANK;
 235         u8 reg = (irq % IRQ_PER_BANK) / IRQ_CFG_IRQ_PER_REG * 0x04;
 236
 237         return IRQ_CFG_REG + bank * IRQ_MEM_SIZE + reg;
 238 }
 239
 240 static inline u32 sunxi_irq_cfg_offset(u16 irq)
 241 {
 242         u32 irq_num = irq % IRQ_CFG_IRQ_PER_REG;
 243         return irq_num * IRQ_CFG_IRQ_BITS;
 244 }
 245
 246 static inline u32 sunxi_irq_ctrl_reg_from_bank(u8 bank)
 247 {
 248         return IRQ_CTRL_REG + bank * IRQ_MEM_SIZE;
 249 }
 250
 251 static inline u32 sunxi_irq_ctrl_reg(u16 irq)
 252 {
 253         u8 bank = irq / IRQ_PER_BANK;
 254
 255         return sunxi_irq_ctrl_reg_from_bank(bank);
 256 }
 257
 258 static inline u32 sunxi_irq_ctrl_offset(u16 irq)
 259 {
 260         u32 irq_num = irq % IRQ_CTRL_IRQ_PER_REG;
 261         return irq_num * IRQ_CTRL_IRQ_BITS;
 262 }
 263
 264 static inline u32 sunxi_irq_status_reg_from_bank(u8 bank)
 265 {
 266         return IRQ_STATUS_REG + bank * IRQ_MEM_SIZE;
 267 }
 268
 269 static inline u32 sunxi_irq_status_reg(u16 irq)
 270 {
 271         u8 bank = irq / IRQ_PER_BANK;
 272
 273         return sunxi_irq_status_reg_from_bank(bank);
 274 }
 275
 276 static inline u32 sunxi_irq_status_offset(u16 irq)
 277 {
 278         u32 irq_num = irq % IRQ_STATUS_IRQ_PER_REG;
 279         return irq_num * IRQ_STATUS_IRQ_BITS;
 280 }
 281
 282 int sunxi_pinctrl_init(struct platform_device *pdev,
 283                        const struct sunxi_pinctrl_desc *desc);
 284
 285 #endif /* __PINCTRL_SUNXI_H */