1 /* Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
2 * Copyright (C) 2019 XiaoMi, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #ifndef __SMB2_CHARGER_REG_H
15 #define __SMB2_CHARGER_REG_H
17 #include <linux/bitops.h>
19 #define CHGR_BASE 0x1000
20 #define OTG_BASE 0x1100
21 #define BATIF_BASE 0x1200
22 #define USBIN_BASE 0x1300
23 #define DCIN_BASE 0x1400
24 #define MISC_BASE 0x1600
25 #define CHGR_FREQ_BASE 0x1900
27 #define PERPH_TYPE_OFFSET 0x04
28 #define TYPE_MASK GENMASK(7, 0)
29 #define PERPH_SUBTYPE_OFFSET 0x05
30 #define SUBTYPE_MASK GENMASK(7, 0)
31 #define INT_RT_STS_OFFSET 0x10
33 #ifdef CONFIG_MACH_XIAOMI_MSM8998
34 #define HVDCP_PULSE_COUNT_MAX_REG (USBIN_BASE + 0x5B)
35 #define PULSE_COUNT_QC2P0_12V BIT(7)
36 #define PULSE_COUNT_QC2P0_9V BIT(6)
37 #define PULSE_COUNT_QC3P0_mask GENMASK(5, 0)
40 /* CHGR Peripheral Registers */
41 #define BATTERY_CHARGER_STATUS_1_REG (CHGR_BASE + 0x06)
42 #define BVR_INITIAL_RAMP_BIT BIT(7)
43 #define CC_SOFT_TERMINATE_BIT BIT(6)
44 #define STEP_CHARGING_STATUS_SHIFT 3
45 #define STEP_CHARGING_STATUS_MASK GENMASK(5, 3)
46 #define BATTERY_CHARGER_STATUS_MASK GENMASK(2, 0)
58 #define BATTERY_CHARGER_STATUS_2_REG (CHGR_BASE + 0x07)
59 #define INPUT_CURRENT_LIMITED_BIT BIT(7)
60 #define CHARGER_ERROR_STATUS_SFT_EXPIRE_BIT BIT(6)
61 #define CHARGER_ERROR_STATUS_BAT_OV_BIT BIT(5)
62 #define CHARGER_ERROR_STATUS_BAT_TERM_MISSING_BIT BIT(4)
63 #define BAT_TEMP_STATUS_MASK GENMASK(3, 0)
64 #define BAT_TEMP_STATUS_SOFT_LIMIT_MASK GENMASK(3, 2)
65 #define BAT_TEMP_STATUS_HOT_SOFT_LIMIT_BIT BIT(3)
66 #define BAT_TEMP_STATUS_COLD_SOFT_LIMIT_BIT BIT(2)
67 #define BAT_TEMP_STATUS_TOO_HOT_BIT BIT(1)
68 #define BAT_TEMP_STATUS_TOO_COLD_BIT BIT(0)
70 #define CHG_OPTION_REG (CHGR_BASE + 0x08)
71 #define PIN_BIT BIT(7)
73 #define BATTERY_CHARGER_STATUS_3_REG (CHGR_BASE + 0x09)
74 #define FV_POST_JEITA_MASK GENMASK(7, 0)
76 #define BATTERY_CHARGER_STATUS_4_REG (CHGR_BASE + 0x0A)
77 #define CHARGE_CURRENT_POST_JEITA_MASK GENMASK(7, 0)
79 #define BATTERY_CHARGER_STATUS_5_REG (CHGR_BASE + 0x0B)
80 #define VALID_INPUT_POWER_SOURCE_BIT BIT(7)
81 #define DISABLE_CHARGING_BIT BIT(6)
82 #define FORCE_ZERO_CHARGE_CURRENT_BIT BIT(5)
83 #define CHARGING_ENABLE_BIT BIT(4)
84 #define TAPER_BIT BIT(3)
85 #define ENABLE_CHG_SENSORS_BIT BIT(2)
86 #define ENABLE_TAPER_SENSOR_BIT BIT(1)
87 #define TAPER_REGION_BIT BIT(0)
89 #define BATTERY_CHARGER_STATUS_6_REG (CHGR_BASE + 0x0C)
90 #define GF_BATT_OV_BIT BIT(7)
91 #define DROP_IN_BATTERY_VOLTAGE_REFERENCE_BIT BIT(6)
92 #define VBATT_LTET_RECHARGE_BIT BIT(5)
93 #define VBATT_GTET_INHIBIT_BIT BIT(4)
94 #define VBATT_GTET_FLOAT_VOLTAGE_BIT BIT(3)
95 #define BATT_GT_PRE_TO_FAST_BIT BIT(2)
96 #define BATT_GT_FULL_ON_BIT BIT(1)
97 #define VBATT_LT_2V_BIT BIT(0)
99 #define BATTERY_CHARGER_STATUS_7_REG (CHGR_BASE + 0x0D)
100 #define ENABLE_TRICKLE_BIT BIT(7)
101 #define ENABLE_PRE_CHARGING_BIT BIT(6)
102 #define ENABLE_FAST_CHARGING_BIT BIT(5)
103 #define ENABLE_FULLON_MODE_BIT BIT(4)
104 #define TOO_COLD_ADC_BIT BIT(3)
105 #define TOO_HOT_ADC_BIT BIT(2)
106 #define HOT_SL_ADC_BIT BIT(1)
107 #define COLD_SL_ADC_BIT BIT(0)
109 #define BATTERY_CHARGER_STATUS_8_REG (CHGR_BASE + 0x0E)
110 #define PRE_FAST_BIT BIT(7)
111 #define PRE_FULLON_BIT BIT(6)
112 #define PRE_RCHG_BIT BIT(5)
113 #define PRE_INHIBIT_BIT BIT(4)
114 #define PRE_OVRV_BIT BIT(3)
115 #define PRE_TERM_BIT BIT(2)
116 #define BAT_ID_BMISS_CMP_BIT BIT(1)
117 #define THERM_CMP_BIT BIT(0)
119 /* CHGR Interrupt Bits */
120 #define CHGR_7_RT_STS_BIT BIT(7)
121 #define CHGR_6_RT_STS_BIT BIT(6)
122 #define FG_FVCAL_QUALIFIED_RT_STS_BIT BIT(5)
123 #define STEP_CHARGING_SOC_UPDATE_REQUEST_RT_STS_BIT BIT(4)
124 #define STEP_CHARGING_SOC_UPDATE_FAIL_RT_STS_BIT BIT(3)
125 #define STEP_CHARGING_STATE_CHANGE_RT_STS_BIT BIT(2)
126 #define CHARGING_STATE_CHANGE_RT_STS_BIT BIT(1)
127 #define CHGR_ERROR_RT_STS_BIT BIT(0)
129 #define STEP_CHG_SOC_VBATT_V_REG (CHGR_BASE + 0x40)
130 #define STEP_CHG_SOC_VBATT_V_MASK GENMASK(7, 0)
132 #define STEP_CHG_SOC_VBATT_V_UPDATE_REG (CHGR_BASE + 0x41)
133 #define STEP_CHG_SOC_VBATT_V_UPDATE_BIT BIT(0)
135 #define CHARGING_ENABLE_CMD_REG (CHGR_BASE + 0x42)
136 #define CHARGING_ENABLE_CMD_BIT BIT(0)
138 #define ALLOW_FAST_CHARGING_CMD_REG (CHGR_BASE + 0x43)
139 #define ALLOW_FAST_CHARGING_CMD_BIT BIT(0)
141 #define QNOVO_PT_ENABLE_CMD_REG (CHGR_BASE + 0x44)
142 #define QNOVO_PT_ENABLE_CMD_BIT BIT(0)
144 #define CHGR_CFG1_REG (CHGR_BASE + 0x50)
145 #define INCREASE_RCHG_TIMEOUT_CFG_BIT BIT(1)
146 #define LOAD_BAT_BIT BIT(0)
148 #define CHGR_CFG2_REG (CHGR_BASE + 0x51)
149 #define CHG_EN_SRC_BIT BIT(7)
150 #define CHG_EN_POLARITY_BIT BIT(6)
151 #define PRETOFAST_TRANSITION_CFG_BIT BIT(5)
152 #define BAT_OV_ECC_BIT BIT(4)
153 #define I_TERM_BIT BIT(3)
154 #define AUTO_RECHG_BIT BIT(2)
155 #define EN_ANALOG_DROP_IN_VBATT_BIT BIT(1)
156 #define CHARGER_INHIBIT_BIT BIT(0)
158 #define CHARGER_ENABLE_CFG_REG (CHGR_BASE + 0x52)
159 #define CHG_ENB_TIMEOUT_SETTING_BIT BIT(1)
160 #define FORCE_ZERO_CFG_BIT BIT(0)
162 #define CFG_REG (CHGR_BASE + 0x53)
163 #define CHG_OPTION_PIN_TRIM_BIT BIT(7)
164 #define BATN_SNS_CFG_BIT BIT(4)
165 #define CFG_TAPER_DIS_AFVC_BIT BIT(3)
166 #define BATFET_SHUTDOWN_CFG_BIT BIT(2)
167 #define VDISCHG_EN_CFG_BIT BIT(1)
168 #define VCHG_EN_CFG_BIT BIT(0)
170 #define CHARGER_SPARE_REG (CHGR_BASE + 0x54)
171 #define CHARGER_SPARE_MASK GENMASK(5, 0)
173 #define PRE_CHARGE_CURRENT_CFG_REG (CHGR_BASE + 0x60)
174 #define PRE_CHARGE_CURRENT_SETTING_MASK GENMASK(5, 0)
176 #define FAST_CHARGE_CURRENT_CFG_REG (CHGR_BASE + 0x61)
177 #define FAST_CHARGE_CURRENT_SETTING_MASK GENMASK(7, 0)
179 #define CHARGE_CURRENT_TERMINATION_CFG_REG (CHGR_BASE + 0x62)
180 #define ANALOG_CHARGE_CURRENT_TERMINATION_SETTING_MASK GENMASK(2, 0)
182 #define TCCC_CHARGE_CURRENT_TERMINATION_CFG_REG (CHGR_BASE + 0x63)
183 #define TCCC_CHARGE_CURRENT_TERMINATION_SETTING_MASK GENMASK(3, 0)
185 #define CHARGE_CURRENT_SOFTSTART_SETTING_CFG_REG (CHGR_BASE + 0x64)
186 #define CHARGE_CURRENT_SOFTSTART_SETTING_MASK GENMASK(1, 0)
188 #define FLOAT_VOLTAGE_CFG_REG (CHGR_BASE + 0x70)
189 #define FLOAT_VOLTAGE_SETTING_MASK GENMASK(7, 0)
191 #define AUTO_FLOAT_VOLTAGE_COMPENSATION_CFG_REG (CHGR_BASE + 0x71)
192 #define AUTO_FLOAT_VOLTAGE_COMPENSATION_MASK GENMASK(2, 0)
194 #define CHARGE_INHIBIT_THRESHOLD_CFG_REG (CHGR_BASE + 0x72)
195 #define CHARGE_INHIBIT_THRESHOLD_MASK GENMASK(1, 0)
196 #define CHARGE_INHIBIT_THRESHOLD_50MV 0
197 #define CHARGE_INHIBIT_THRESHOLD_100MV 1
198 #define CHARGE_INHIBIT_THRESHOLD_200MV 2
199 #define CHARGE_INHIBIT_THRESHOLD_300MV 3
201 #define RECHARGE_THRESHOLD_CFG_REG (CHGR_BASE + 0x73)
202 #define RECHARGE_THRESHOLD_MASK GENMASK(1, 0)
204 #define PRE_TO_FAST_CHARGE_THRESHOLD_CFG_REG (CHGR_BASE + 0x74)
205 #define PRE_TO_FAST_CHARGE_THRESHOLD_MASK GENMASK(1, 0)
207 #define FV_HYSTERESIS_CFG_REG (CHGR_BASE + 0x75)
208 #define FV_DROP_HYSTERESIS_CFG_MASK GENMASK(7, 4)
209 #define THRESH_HYSTERESIS_CFG_MASK GENMASK(3, 0)
211 #define FVC_CHARGE_INHIBIT_THRESHOLD_CFG_REG (CHGR_BASE + 0x80)
212 #define FVC_CHARGE_INHIBIT_THRESHOLD_MASK GENMASK(5, 0)
214 #define FVC_RECHARGE_THRESHOLD_CFG_REG (CHGR_BASE + 0x81)
215 #define FVC_RECHARGE_THRESHOLD_MASK GENMASK(7, 0)
217 #define FVC_PRE_TO_FAST_CHARGE_THRESHOLD_CFG_REG (CHGR_BASE + 0x82)
218 #define FVC_PRE_TO_FAST_CHARGE_THRESHOLD_MASK GENMASK(7, 0)
220 #define FVC_FULL_ON_THRESHOLD_CFG_REG (CHGR_BASE + 0x83)
221 #define FVC_FULL_ON_THRESHOLD_MASK GENMASK(7, 0)
223 #define FVC_CC_MODE_GLITCH_FILTER_SEL_CFG_REG (CHGR_BASE + 0x84)
224 #define FVC_CC_MODE_GLITCH_FILTER_SEL_MASK GENMASK(1, 0)
226 #define FVC_TERMINATION_GLITCH_FILTER_SEL_CFG_REG (CHGR_BASE + 0x85)
227 #define FVC_TERMINATION_GLITCH_FILTER_SEL_MASK GENMASK(1, 0)
229 #define JEITA_EN_CFG_REG (CHGR_BASE + 0x90)
230 #define JEITA_EN_HARDLIMIT_BIT BIT(4)
231 #define JEITA_EN_HOT_SL_FCV_BIT BIT(3)
232 #define JEITA_EN_COLD_SL_FCV_BIT BIT(2)
233 #define JEITA_EN_HOT_SL_CCC_BIT BIT(1)
234 #define JEITA_EN_COLD_SL_CCC_BIT BIT(0)
236 #define JEITA_FVCOMP_CFG_REG (CHGR_BASE + 0x91)
237 #define JEITA_FVCOMP_MASK GENMASK(7, 0)
239 #define JEITA_CCCOMP_CFG_REG (CHGR_BASE + 0x92)
240 #define JEITA_CCCOMP_MASK GENMASK(7, 0)
242 #define FV_CAL_CFG_REG (CHGR_BASE + 0x76)
243 #define FV_CALIBRATION_CFG_MASK GENMASK(2, 0)
245 #define FV_ADJUST_REG (CHGR_BASE + 0x77)
246 #define FLOAT_VOLTAGE_ADJUSTMENT_MASK GENMASK(4, 0)
248 #define FG_VADC_DISQ_THRESH_REG (CHGR_BASE + 0x78)
249 #define VADC_DISQUAL_THRESH_MASK GENMASK(7, 0)
251 #define FG_IADC_DISQ_THRESH_REG (CHGR_BASE + 0x79)
252 #define IADC_DISQUAL_THRESH_MASK GENMASK(7, 0)
254 #define FG_UPDATE_CFG_1_REG (CHGR_BASE + 0x7A)
255 #define BT_TMPR_TCOLD_BIT BIT(7)
256 #define BT_TMPR_COLD_BIT BIT(6)
257 #define BT_TMPR_HOT_BIT BIT(5)
258 #define BT_TMPR_THOT_BIT BIT(4)
259 #define CHG_DIE_TMPR_HOT_BIT BIT(3)
260 #define CHG_DIE_TMPR_THOT_BIT BIT(2)
261 #define SKIN_TMPR_HOT_BIT BIT(1)
262 #define SKIN_TMPR_THOT_BIT BIT(0)
264 #define FG_UPDATE_CFG_1_SEL_REG (CHGR_BASE + 0x7B)
265 #define BT_TMPR_TCOLD_SEL_BIT BIT(7)
266 #define BT_TMPR_COLD_SEL_BIT BIT(6)
267 #define BT_TMPR_HOT_SEL_BIT BIT(5)
268 #define BT_TMPR_THOT_SEL_BIT BIT(4)
269 #define CHG_DIE_TMPR_HOT_SEL_BIT BIT(3)
270 #define CHG_DIE_TMPR_THOT_SEL_BIT BIT(2)
271 #define SKIN_TMPR_HOT_SEL_BIT BIT(1)
272 #define SKIN_TMPR_THOT_SEL_BIT BIT(0)
274 #define FG_UPDATE_CFG_2_REG (CHGR_BASE + 0x7C)
275 #define SOC_LT_OTG_THRESH_BIT BIT(3)
276 #define SOC_LT_CHG_RECHARGE_THRESH_BIT BIT(2)
277 #define VBT_LT_CHG_RECHARGE_THRESH_BIT BIT(1)
278 #define IBT_LT_CHG_TERM_THRESH_BIT BIT(0)
280 #define FG_UPDATE_CFG_2_SEL_REG (CHGR_BASE + 0x7D)
281 #define SOC_LT_OTG_THRESH_SEL_BIT BIT(3)
282 #define SOC_LT_CHG_RECHARGE_THRESH_SEL_BIT BIT(2)
283 #define VBT_LT_CHG_RECHARGE_THRESH_SEL_BIT BIT(1)
284 #define IBT_LT_CHG_TERM_THRESH_SEL_BIT BIT(0)
286 #define FG_CHG_INTERFACE_CFG_REG (CHGR_BASE + 0x7E)
287 #define ESR_ISINK_CFG_MASK GENMASK(7, 6)
288 #define ESR_FASTCHG_DECR_CFG_MASK GENMASK(5, 4)
289 #define FG_CHARGER_INHIBIT_BIT BIT(3)
290 #define FG_BATFET_BIT BIT(2)
291 #define IADC_SYNC_CNV_BIT BIT(1)
292 #define VADC_SYNC_CNV_BIT BIT(0)
294 #define FG_CHG_INTERFACE_CFG_SEL_REG (CHGR_BASE + 0x7F)
295 #define ESR_ISINK_CFG_SEL_BIT BIT(5)
296 #define ESR_FASTCHG_DECR_CFG_SEL_BIT BIT(4)
297 #define FG_CHARGER_INHIBIT_SEL_BIT BIT(3)
298 #define FG_BATFET_SEL_BIT BIT(2)
299 #define IADC_SYNC_CNV_SEL_BIT BIT(1)
300 #define VADC_SYNC_CNV_SEL_BIT BIT(0)
302 #define CHGR_STEP_CHG_MODE_CFG_REG (CHGR_BASE + 0xB0)
303 #define STEP_CHARGING_SOC_FAIL_OPTION_BIT BIT(3)
304 #define STEP_CHARGING_MODE_SELECT_BIT BIT(2)
305 #define STEP_CHARGING_SOURCE_SELECT_BIT BIT(1)
306 #define STEP_CHARGING_ENABLE_BIT BIT(0)
308 #define STEP_CHG_UPDATE_REQUEST_TIMEOUT_CFG_REG (CHGR_BASE + 0xB1)
309 #define STEP_CHG_UPDATE_REQUEST_TIMEOUT_CFG_MASK GENMASK(0, 1)
310 #define STEP_CHG_UPDATE_REQUEST_TIMEOUT_5S 0
311 #define STEP_CHG_UPDATE_REQUEST_TIMEOUT_10S 1
312 #define STEP_CHG_UPDATE_REQUEST_TIMEOUT_20S 2
313 #define STEP_CHG_UPDATE_REQUEST_TIMEOUT_40S 3
315 #define STEP_CHG_UPDATE_FAIL_TIMEOUT_CFG_REG (CHGR_BASE + 0xB2)
316 #define STEP_CHG_UPDATE_FAIL_TIMEOUT_CFG_MASK GENMASK(0, 1)
317 #define STEP_CHG_UPDATE_FAIL_TIMEOUT_10S 0
318 #define STEP_CHG_UPDATE_FAIL_TIMEOUT_30S 1
319 #define STEP_CHG_UPDATE_FAIL_TIMEOUT_60S 2
320 #define STEP_CHG_UPDATE_FAIL_TIMEOUT_120S 3
322 #define STEP_CHG_SOC_OR_BATT_V_TH1_REG (CHGR_BASE + 0xB3)
323 #define STEP_CHG_SOC_OR_BATT_V_TH2_REG (CHGR_BASE + 0xB4)
324 #define STEP_CHG_SOC_OR_BATT_V_TH3_REG (CHGR_BASE + 0xB5)
325 #define STEP_CHG_SOC_OR_BATT_V_TH4_REG (CHGR_BASE + 0xB6)
326 #define STEP_CHG_CURRENT_DELTA1_REG (CHGR_BASE + 0xB7)
327 #define STEP_CHG_CURRENT_DELTA2_REG (CHGR_BASE + 0xB8)
328 #define STEP_CHG_CURRENT_DELTA3_REG (CHGR_BASE + 0xB9)
329 #define STEP_CHG_CURRENT_DELTA4_REG (CHGR_BASE + 0xBA)
330 #define STEP_CHG_CURRENT_DELTA5_REG (CHGR_BASE + 0xBB)
332 /* OTG Peripheral Registers */
333 #define RID_CC_CONTROL_23_16_REG (OTG_BASE + 0x06)
334 #define RID_CC_CONTROL_23_BIT BIT(7)
335 #define VCONN_SOFTSTART_EN_BIT BIT(6)
336 #define VCONN_SFTST_CFG_MASK GENMASK(5, 4)
337 #define CONNECT_RIDCC_SENSOR_TO_CC_MASK GENMASK(3, 2)
338 #define EN_CC_1P1CLAMP_BIT BIT(1)
339 #define ENABLE_CRUDESEN_CC_1_BIT BIT(0)
341 #define RID_CC_CONTROL_15_8_REG (OTG_BASE + 0x07)
342 #define ENABLE_CRUDESEN_CC_0_BIT BIT(7)
343 #define EN_FMB_2P5UA_CC_MASK GENMASK(6, 5)
344 #define EN_ISRC_180UA_BIT BIT(4)
345 #define ENABLE_CURRENTSOURCE_CC_MASK GENMASK(3, 2)
346 #define EN_BANDGAP_RID_C_DET_BIT BIT(1)
347 #define ENABLE_RD_CC_1_BIT BIT(0)
349 #define RID_CC_CONTROL_7_0_REG (OTG_BASE + 0x08)
350 #define ENABLE_RD_CC_0_BIT BIT(7)
351 #define VCONN_ILIM500MA_BIT BIT(6)
352 #define EN_MICRO_USB_MODE_BIT BIT(5)
353 #define UFP_DFP_MODE_BIT BIT(4)
354 #define VCONN_EN_CC_MASK GENMASK(3, 2)
355 #define VREF_SEL_RIDCC_SENSOR_MASK GENMASK(1, 0)
357 #define OTG_STATUS_REG (OTG_BASE + 0x09)
358 #define BOOST_SOFTSTART_DONE_BIT BIT(3)
359 #define OTG_STATE_MASK GENMASK(2, 0)
360 #define OTG_STATE_ENABLED 0x2
362 /* OTG Interrupt Bits */
363 #define TESTMODE_CHANGE_DETECT_RT_STS_BIT BIT(3)
364 #define OTG_OC_DIS_SW_STS_RT_STS_BIT BIT(2)
365 #define OTG_OVERCURRENT_RT_STS_BIT BIT(1)
366 #define OTG_FAIL_RT_STS_BIT BIT(0)
368 #define CMD_OTG_REG (OTG_BASE + 0x40)
369 #define OTG_EN_BIT BIT(0)
371 #define BAT_UVLO_THRESHOLD_CFG_REG (OTG_BASE + 0x51)
372 #define BAT_UVLO_THRESHOLD_MASK GENMASK(1, 0)
374 #define OTG_CURRENT_LIMIT_CFG_REG (OTG_BASE + 0x52)
375 #define OTG_CURRENT_LIMIT_MASK GENMASK(2, 0)
377 #define OTG_CFG_REG (OTG_BASE + 0x53)
378 #define OTG_RESERVED_MASK GENMASK(7, 6)
379 #define DIS_OTG_ON_TLIM_BIT BIT(5)
380 #define QUICKSTART_OTG_FASTROLESWAP_BIT BIT(4)
381 #define INCREASE_DFP_TIME_BIT BIT(3)
382 #define ENABLE_OTG_IN_DEBUG_MODE_BIT BIT(2)
383 #define OTG_EN_SRC_CFG_BIT BIT(1)
384 #define CONCURRENT_MODE_CFG_BIT BIT(0)
386 #define OTG_ENG_OTG_CFG_REG (OTG_BASE + 0xC0)
387 #define ENG_BUCKBOOST_HALT1_8_MODE_BIT BIT(0)
389 /* BATIF Peripheral Registers */
390 /* BATIF Interrupt Bits */
391 #define BAT_7_RT_STS_BIT BIT(7)
392 #define BAT_6_RT_STS_BIT BIT(6)
393 #define BAT_TERMINAL_MISSING_RT_STS_BIT BIT(5)
394 #define BAT_THERM_OR_ID_MISSING_RT_STS_BIT BIT(4)
395 #define BAT_LOW_RT_STS_BIT BIT(3)
396 #define BAT_OV_RT_STS_BIT BIT(2)
397 #define BAT_OCP_RT_STS_BIT BIT(1)
398 #define BAT_TEMP_RT_STS_BIT BIT(0)
400 #define SHIP_MODE_REG (BATIF_BASE + 0x40)
401 #define SHIP_MODE_EN_BIT BIT(0)
403 #define BATOCP_THRESHOLD_CFG_REG (BATIF_BASE + 0x50)
404 #define BATOCP_ENABLE_CFG_BIT BIT(3)
405 #define BATOCP_THRESHOLD_MASK GENMASK(2, 0)
407 #define BATOCP_INTRPT_DELAY_TMR_CFG_REG (BATIF_BASE + 0x51)
408 #define BATOCP_INTRPT_TIMEOUT_MASK GENMASK(5, 3)
409 #define BATOCP_DELAY_TIMEOUT_MASK GENMASK(2, 0)
411 #define BATOCP_RESET_TMR_CFG_REG (BATIF_BASE + 0x52)
412 #define EN_BATOCP_RESET_TMR_BIT BIT(3)
413 #define BATOCP_RESET_TIMEOUT_MASK GENMASK(2, 0)
415 #define LOW_BATT_DETECT_EN_CFG_REG (BATIF_BASE + 0x60)
416 #define LOW_BATT_DETECT_EN_BIT BIT(0)
418 #define LOW_BATT_THRESHOLD_CFG_REG (BATIF_BASE + 0x61)
419 #define LOW_BATT_THRESHOLD_MASK GENMASK(3, 0)
421 #define BAT_FET_CFG_REG (BATIF_BASE + 0x62)
422 #define BAT_FET_CFG_BIT BIT(0)
424 #define BAT_MISS_SRC_CFG_REG (BATIF_BASE + 0x70)
425 #define BAT_MISS_ALG_EN_BIT BIT(2)
426 #define BAT_MISS_RESERVED_BIT BIT(1)
427 #define BAT_MISS_PIN_SRC_EN_BIT BIT(0)
429 #define BAT_MISS_ALG_OPTIONS_CFG_REG (BATIF_BASE + 0x71)
430 #define BAT_MISS_INPUT_PLUGIN_BIT BIT(2)
431 #define BAT_MISS_TMR_START_OPTION_BIT BIT(1)
432 #define BAT_MISS_POLL_EN_BIT BIT(0)
434 #define BAT_MISS_PIN_GF_CFG_REG (BATIF_BASE + 0x72)
435 #define BAT_MISS_PIN_GF_MASK GENMASK(1, 0)
437 /* USBIN Peripheral Registers */
438 #define USBIN_INPUT_STATUS_REG (USBIN_BASE + 0x06)
439 #define USBIN_INPUT_STATUS_7_BIT BIT(7)
440 #define USBIN_INPUT_STATUS_6_BIT BIT(6)
441 #define USBIN_12V_BIT BIT(5)
442 #define USBIN_9V_TO_12V_BIT BIT(4)
443 #define USBIN_9V_BIT BIT(3)
444 #define USBIN_5V_TO_12V_BIT BIT(2)
445 #define USBIN_5V_TO_9V_BIT BIT(1)
446 #define USBIN_5V_BIT BIT(0)
447 #define QC_2P0_STATUS_MASK GENMASK(2, 0)
449 #define APSD_STATUS_REG (USBIN_BASE + 0x07)
450 #define APSD_STATUS_7_BIT BIT(7)
451 #define HVDCP_CHECK_TIMEOUT_BIT BIT(6)
452 #define SLOW_PLUGIN_TIMEOUT_BIT BIT(5)
453 #define ENUMERATION_DONE_BIT BIT(4)
454 #define VADP_CHANGE_DONE_AFTER_AUTH_BIT BIT(3)
455 #define QC_AUTH_DONE_STATUS_BIT BIT(2)
456 #define QC_CHARGER_BIT BIT(1)
457 #define APSD_DTC_STATUS_DONE_BIT BIT(0)
459 #define APSD_RESULT_STATUS_REG (USBIN_BASE + 0x08)
460 #define ICL_OVERRIDE_LATCH_BIT BIT(7)
461 #define APSD_RESULT_STATUS_MASK GENMASK(6, 0)
462 #define QC_3P0_BIT BIT(6)
463 #define QC_2P0_BIT BIT(5)
464 #define FLOAT_CHARGER_BIT BIT(4)
465 #define DCP_CHARGER_BIT BIT(3)
466 #define CDP_CHARGER_BIT BIT(2)
467 #define OCP_CHARGER_BIT BIT(1)
468 #define SDP_CHARGER_BIT BIT(0)
470 #define QC_CHANGE_STATUS_REG (USBIN_BASE + 0x09)
471 #define QC_CHANGE_STATUS_7_BIT BIT(7)
472 #define QC_CHANGE_STATUS_6_BIT BIT(6)
473 #define QC_9V_TO_12V_REASON_BIT BIT(5)
474 #define QC_5V_TO_9V_REASON_BIT BIT(4)
475 #define QC_CONTINUOUS_BIT BIT(3)
476 #define QC_12V_BIT BIT(2)
477 #define QC_9V_BIT BIT(1)
478 #define QC_5V_BIT BIT(0)
480 #define QC_PULSE_COUNT_STATUS_REG (USBIN_BASE + 0x0A)
481 #define QC_PULSE_COUNT_STATUS_7_BIT BIT(7)
482 #define QC_PULSE_COUNT_STATUS_6_BIT BIT(6)
483 #define QC_PULSE_COUNT_MASK GENMASK(5, 0)
485 #define TYPE_C_STATUS_1_REG (USBIN_BASE + 0x0B)
486 #define UFP_TYPEC_MASK GENMASK(7, 5)
487 #define UFP_TYPEC_RDSTD_BIT BIT(7)
488 #define UFP_TYPEC_RD1P5_BIT BIT(6)
489 #define UFP_TYPEC_RD3P0_BIT BIT(5)
490 #define UFP_TYPEC_FMB_255K_BIT BIT(4)
491 #define UFP_TYPEC_FMB_301K_BIT BIT(3)
492 #define UFP_TYPEC_FMB_523K_BIT BIT(2)
493 #define UFP_TYPEC_FMB_619K_BIT BIT(1)
494 #define UFP_TYPEC_OPEN_OPEN_BIT BIT(0)
496 #define TYPE_C_STATUS_2_REG (USBIN_BASE + 0x0C)
497 #define DFP_RA_OPEN_BIT BIT(7)
498 #define TIMER_STAGE_BIT BIT(6)
499 #define EXIT_UFP_MODE_BIT BIT(5)
500 #define EXIT_DFP_MODE_BIT BIT(4)
501 #define DFP_TYPEC_MASK GENMASK(3, 0)
502 #define DFP_RD_OPEN_BIT BIT(3)
503 #define DFP_RD_RA_VCONN_BIT BIT(2)
504 #define DFP_RD_RD_BIT BIT(1)
505 #define DFP_RA_RA_BIT BIT(0)
507 #define TYPE_C_STATUS_3_REG (USBIN_BASE + 0x0D)
508 #define ENABLE_BANDGAP_BIT BIT(7)
509 #define U_USB_GND_NOVBUS_BIT BIT(6)
510 #define U_USB_FLOAT_NOVBUS_BIT BIT(5)
511 #define U_USB_GND_BIT BIT(4)
512 #define U_USB_FMB1_BIT BIT(3)
513 #define U_USB_FLOAT1_BIT BIT(2)
514 #define U_USB_FMB2_BIT BIT(1)
515 #define U_USB_FLOAT2_BIT BIT(0)
517 #define TYPE_C_STATUS_4_REG (USBIN_BASE + 0x0E)
518 #define UFP_DFP_MODE_STATUS_BIT BIT(7)
519 #define TYPEC_VBUS_STATUS_BIT BIT(6)
520 #define TYPEC_VBUS_ERROR_STATUS_BIT BIT(5)
521 #define TYPEC_DEBOUNCE_DONE_STATUS_BIT BIT(4)
522 #define TYPEC_UFP_AUDIO_ADAPT_STATUS_BIT BIT(3)
523 #define TYPEC_VCONN_OVERCURR_STATUS_BIT BIT(2)
524 #define CC_ORIENTATION_BIT BIT(1)
525 #define CC_ATTACHED_BIT BIT(0)
527 #define TYPE_C_STATUS_5_REG (USBIN_BASE + 0x0F)
528 #define TRY_SOURCE_FAILED_BIT BIT(6)
529 #define TRY_SINK_FAILED_BIT BIT(5)
530 #define TIMER_STAGE_2_BIT BIT(4)
531 #define TYPEC_LEGACY_CABLE_STATUS_BIT BIT(3)
532 #define TYPEC_NONCOMP_LEGACY_CABLE_STATUS_BIT BIT(2)
533 #define TYPEC_TRYSOURCE_DETECT_STATUS_BIT BIT(1)
534 #define TYPEC_TRYSINK_DETECT_STATUS_BIT BIT(0)
536 /* USBIN Interrupt Bits */
537 #define TYPE_C_CHANGE_RT_STS_BIT BIT(7)
538 #define USBIN_ICL_CHANGE_RT_STS_BIT BIT(6)
539 #define USBIN_SOURCE_CHANGE_RT_STS_BIT BIT(5)
540 #define USBIN_PLUGIN_RT_STS_BIT BIT(4)
541 #define USBIN_OV_RT_STS_BIT BIT(3)
542 #define USBIN_UV_RT_STS_BIT BIT(2)
543 #define USBIN_LT_3P6V_RT_STS_BIT BIT(1)
544 #define USBIN_COLLAPSE_RT_STS_BIT BIT(0)
546 #define QC_PULSE_COUNT_STATUS_1_REG (USBIN_BASE + 0x30)
548 #define USBIN_CMD_IL_REG (USBIN_BASE + 0x40)
549 #define BAT_2_SYS_FET_DIS_BIT BIT(1)
550 #define USBIN_SUSPEND_BIT BIT(0)
552 #define CMD_APSD_REG (USBIN_BASE + 0x41)
553 #define ICL_OVERRIDE_BIT BIT(1)
554 #define APSD_RERUN_BIT BIT(0)
556 #define CMD_HVDCP_2_REG (USBIN_BASE + 0x43)
557 #define RESTART_AICL_BIT BIT(7)
558 #define TRIGGER_AICL_BIT BIT(6)
559 #define FORCE_12V_BIT BIT(5)
560 #define FORCE_9V_BIT BIT(4)
561 #define FORCE_5V_BIT BIT(3)
562 #define IDLE_BIT BIT(2)
563 #define SINGLE_DECREMENT_BIT BIT(1)
564 #define SINGLE_INCREMENT_BIT BIT(0)
566 #define USB_MISC2_REG (USBIN_BASE + 0x57)
567 #define USB_MISC2_MASK GENMASK(1, 0)
569 #define TYPE_C_CFG_REG (USBIN_BASE + 0x58)
570 #define APSD_START_ON_CC_BIT BIT(7)
571 #define WAIT_FOR_APSD_BIT BIT(6)
572 #define FACTORY_MODE_DETECTION_EN_BIT BIT(5)
573 #define FACTORY_MODE_ICL_3A_4A_BIT BIT(4)
574 #define FACTORY_MODE_DIS_CHGING_CFG_BIT BIT(3)
575 #define SUSPEND_NON_COMPLIANT_CFG_BIT BIT(2)
576 #define VCONN_OC_CFG_BIT BIT(1)
577 #define TYPE_C_OR_U_USB_BIT BIT(0)
579 #define TYPE_C_CFG_2_REG (USBIN_BASE + 0x59)
580 #define TYPE_C_DFP_CURRSRC_MODE_BIT BIT(7)
581 #define VCONN_ILIM500MA_CFG_BIT BIT(6)
582 #define VCONN_SOFTSTART_CFG_MASK GENMASK(5, 4)
583 #define EN_TRY_SOURCE_MODE_BIT BIT(3)
584 #define USB_FACTORY_MODE_ENABLE_BIT BIT(2)
585 #define TYPE_C_UFP_MODE_BIT BIT(1)
586 #define EN_80UA_180UA_CUR_SOURCE_BIT BIT(0)
588 #define TYPE_C_CFG_3_REG (USBIN_BASE + 0x5A)
589 #define TVBUS_DEBOUNCE_BIT BIT(7)
590 #define TYPEC_LEGACY_CABLE_INT_EN_BIT BIT(6)
591 #define TYPEC_NONCOMPLIANT_LEGACY_CABLE_INT_EN_BIT BIT(5)
592 #define TYPEC_TRYSOURCE_DETECT_INT_EN_BIT BIT(4)
593 #define TYPEC_TRYSINK_DETECT_INT_EN_BIT BIT(3)
594 #define EN_TRYSINK_MODE_BIT BIT(2)
595 #define EN_LEGACY_CABLE_DETECTION_BIT BIT(1)
596 #define ALLOW_PD_DRING_UFP_TCCDB_BIT BIT(0)
598 #define HVDCP_PULSE_COUNT_MAX_REG (USBIN_BASE + 0x5B)
599 #define PULSE_COUNT_QC2P0_12V BIT(7)
600 #define PULSE_COUNT_QC2P0_9V BIT(6)
601 #define PULSE_COUNT_QC3P0_mask GENMASK(5, 0)
603 #define USBIN_ADAPTER_ALLOW_CFG_REG (USBIN_BASE + 0x60)
604 #define USBIN_ADAPTER_ALLOW_MASK GENMASK(3, 0)
606 USBIN_ADAPTER_ALLOW_5V = 0,
607 USBIN_ADAPTER_ALLOW_9V = 2,
608 USBIN_ADAPTER_ALLOW_5V_OR_9V = 3,
609 USBIN_ADAPTER_ALLOW_12V = 4,
610 USBIN_ADAPTER_ALLOW_5V_OR_12V = 5,
611 USBIN_ADAPTER_ALLOW_9V_TO_12V = 6,
612 USBIN_ADAPTER_ALLOW_5V_OR_9V_TO_12V = 7,
613 USBIN_ADAPTER_ALLOW_5V_TO_9V = 8,
614 USBIN_ADAPTER_ALLOW_5V_TO_12V = 12,
617 #define USBIN_OPTIONS_1_CFG_REG (USBIN_BASE + 0x62)
618 #define CABLE_R_SEL_BIT BIT(7)
619 #define HVDCP_AUTH_ALG_EN_CFG_BIT BIT(6)
620 #define HVDCP_AUTONOMOUS_MODE_EN_CFG_BIT BIT(5)
621 #define INPUT_PRIORITY_BIT BIT(4)
622 #define AUTO_SRC_DETECT_BIT BIT(3)
623 #define HVDCP_EN_BIT BIT(2)
624 #define VADP_INCREMENT_VOLTAGE_LIMIT_BIT BIT(1)
625 #define VADP_TAPER_TIMER_EN_BIT BIT(0)
627 #define USBIN_OPTIONS_2_CFG_REG (USBIN_BASE + 0x63)
628 #define WIPWR_RST_EUD_CFG_BIT BIT(7)
629 #define SWITCHER_START_CFG_BIT BIT(6)
630 #define DCD_TIMEOUT_SEL_BIT BIT(5)
631 #define OCD_CURRENT_SEL_BIT BIT(4)
632 #define SLOW_PLUGIN_TIMER_EN_CFG_BIT BIT(3)
633 #define FLOAT_OPTIONS_MASK GENMASK(2, 0)
634 #define FLOAT_DIS_CHGING_CFG_BIT BIT(2)
635 #define SUSPEND_FLOAT_CFG_BIT BIT(1)
636 #define FORCE_FLOAT_SDP_CFG_BIT BIT(0)
638 #define TAPER_TIMER_SEL_CFG_REG (USBIN_BASE + 0x64)
639 #define TYPEC_SPARE_CFG_BIT BIT(7)
640 #define TYPEC_DRP_DFP_TIME_CFG_BIT BIT(5)
641 #define TAPER_TIMER_SEL_MASK GENMASK(1, 0)
643 #define USBIN_LOAD_CFG_REG (USBIN_BASE + 0x65)
644 #define USBIN_OV_CH_LOAD_OPTION_BIT BIT(7)
645 #define ICL_OVERRIDE_AFTER_APSD_BIT BIT(4)
646 #define USBIN_COLLAPSE_SEL_MASK GENMASK(1, 0)
648 #define USBIN_ICL_OPTIONS_REG (USBIN_BASE + 0x66)
649 #define CFG_USB3P0_SEL_BIT BIT(2)
650 #define USB51_MODE_BIT BIT(1)
651 #define USBIN_MODE_CHG_BIT BIT(0)
653 #define TYPE_C_INTRPT_ENB_REG (USBIN_BASE + 0x67)
654 #define TYPEC_CCOUT_DETACH_INT_EN_BIT BIT(7)
655 #define TYPEC_CCOUT_ATTACH_INT_EN_BIT BIT(6)
656 #define TYPEC_VBUS_ERROR_INT_EN_BIT BIT(5)
657 #define TYPEC_UFP_AUDIOADAPT_INT_EN_BIT BIT(4)
658 #define TYPEC_DEBOUNCE_DONE_INT_EN_BIT BIT(3)
659 #define TYPEC_CCSTATE_CHANGE_INT_EN_BIT BIT(2)
660 #define TYPEC_VBUS_DEASSERT_INT_EN_BIT BIT(1)
661 #define TYPEC_VBUS_ASSERT_INT_EN_BIT BIT(0)
663 #define TYPE_C_INTRPT_ENB_SOFTWARE_CTRL_REG (USBIN_BASE + 0x68)
664 #define EXIT_SNK_BASED_ON_CC_BIT BIT(7)
665 #define VCONN_EN_ORIENTATION_BIT BIT(6)
666 #define TYPEC_VCONN_OVERCURR_INT_EN_BIT BIT(5)
667 #define VCONN_EN_SRC_BIT BIT(4)
668 #define VCONN_EN_VALUE_BIT BIT(3)
669 #define TYPEC_POWER_ROLE_CMD_MASK GENMASK(2, 0)
670 #define UFP_EN_CMD_BIT BIT(2)
671 #define DFP_EN_CMD_BIT BIT(1)
672 #define TYPEC_DISABLE_CMD_BIT BIT(0)
674 #define USBIN_SOURCE_CHANGE_INTRPT_ENB_REG (USBIN_BASE + 0x69)
675 #define SLOW_IRQ_EN_CFG_BIT BIT(5)
676 #define ENUMERATION_IRQ_EN_CFG_BIT BIT(4)
677 #define VADP_IRQ_EN_CFG_BIT BIT(3)
678 #define AUTH_IRQ_EN_CFG_BIT BIT(2)
679 #define HVDCP_IRQ_EN_CFG_BIT BIT(1)
680 #define APSD_IRQ_EN_CFG_BIT BIT(0)
682 #define USBIN_CURRENT_LIMIT_CFG_REG (USBIN_BASE + 0x70)
683 #define USBIN_CURRENT_LIMIT_MASK GENMASK(7, 0)
685 #define USBIN_AICL_OPTIONS_CFG_REG (USBIN_BASE + 0x80)
686 #define SUSPEND_ON_COLLAPSE_USBIN_BIT BIT(7)
687 #define USBIN_AICL_HDC_EN_BIT BIT(6)
688 #define USBIN_AICL_START_AT_MAX_BIT BIT(5)
689 #define USBIN_AICL_RERUN_EN_BIT BIT(4)
690 #define USBIN_AICL_ADC_EN_BIT BIT(3)
691 #define USBIN_AICL_EN_BIT BIT(2)
692 #define USBIN_HV_COLLAPSE_RESPONSE_BIT BIT(1)
693 #define USBIN_LV_COLLAPSE_RESPONSE_BIT BIT(0)
695 #define USBIN_5V_AICL_THRESHOLD_CFG_REG (USBIN_BASE + 0x81)
696 #define USBIN_5V_AICL_THRESHOLD_CFG_MASK GENMASK(2, 0)
698 #define USBIN_9V_AICL_THRESHOLD_CFG_REG (USBIN_BASE + 0x82)
699 #define USBIN_9V_AICL_THRESHOLD_CFG_MASK GENMASK(2, 0)
701 #define USBIN_12V_AICL_THRESHOLD_CFG_REG (USBIN_BASE + 0x83)
702 #define USBIN_12V_AICL_THRESHOLD_CFG_MASK GENMASK(2, 0)
704 #define USBIN_CONT_AICL_THRESHOLD_CFG_REG (USBIN_BASE + 0x84)
705 #define USBIN_CONT_AICL_THRESHOLD_CFG_MASK GENMASK(5, 0)
707 /* DCIN Peripheral Registers */
708 #define DCIN_INPUT_STATUS_REG (DCIN_BASE + 0x06)
709 #define DCIN_INPUT_STATUS_7_BIT BIT(7)
710 #define DCIN_INPUT_STATUS_6_BIT BIT(6)
711 #define DCIN_12V_BIT BIT(5)
712 #define DCIN_9V_TO_12V_BIT BIT(4)
713 #define DCIN_9V_BIT BIT(3)
714 #define DCIN_5V_TO_12V_BIT BIT(2)
715 #define DCIN_5V_TO_9V_BIT BIT(1)
716 #define DCIN_5V_BIT BIT(0)
718 #define WIPWR_STATUS_REG (DCIN_BASE + 0x07)
719 #define WIPWR_STATUS_7_BIT BIT(7)
720 #define WIPWR_STATUS_6_BIT BIT(6)
721 #define WIPWR_STATUS_5_BIT BIT(5)
722 #define DCIN_WIPWR_OV_DG_BIT BIT(4)
723 #define DIV2_EN_DG_BIT BIT(3)
724 #define SHUTDOWN_N_LATCH_BIT BIT(2)
725 #define CHG_OK_PIN_BIT BIT(1)
726 #define WIPWR_CHARGING_ENABLED_BIT BIT(0)
728 #define WIPWR_RANGE_STATUS_REG (DCIN_BASE + 0x08)
729 #define WIPWR_RANGE_STATUS_MASK GENMASK(4, 0)
731 /* DCIN Interrupt Bits */
732 #define WIPWR_VOLTAGE_RANGE_RT_STS_BIT BIT(7)
733 #define DCIN_ICL_CHANGE_RT_STS_BIT BIT(6)
734 #define DIV2_EN_DG_RT_STS_BIT BIT(5)
735 #define DCIN_PLUGIN_RT_STS_BIT BIT(4)
736 #define DCIN_OV_RT_STS_BIT BIT(3)
737 #define DCIN_UV_RT_STS_BIT BIT(2)
738 #define DCIN_LT_3P6V_RT_STS_BIT BIT(1)
739 #define DCIN_COLLAPSE_RT_STS_BIT BIT(0)
741 #define DCIN_CMD_IL_REG (DCIN_BASE + 0x40)
742 #define WIRELESS_CHG_DIS_BIT BIT(3)
743 #define SHDN_N_CLEAR_CMD_BIT BIT(2)
744 #define SHDN_N_SET_CMD_BIT BIT(1)
745 #define DCIN_SUSPEND_BIT BIT(0)
747 #define DC_SPARE_REG (DCIN_BASE + 0x58)
748 #define DC_SPARE_MASK GENMASK(3, 0)
750 #define DCIN_ADAPTER_ALLOW_CFG_REG (DCIN_BASE + 0x60)
751 #define DCIN_ADAPTER_ALLOW_MASK GENMASK(3, 0)
753 #define DCIN_LOAD_CFG_REG (DCIN_BASE + 0x65)
754 #define DCIN_OV_CH_LOAD_OPTION_BIT BIT(7)
756 #define DCIN_CURRENT_LIMIT_CFG_REG (DCIN_BASE + 0x70)
757 #define DCIN_CURRENT_LIMIT_MASK GENMASK(7, 0)
759 #define DCIN_AICL_OPTIONS_CFG_REG (DCIN_BASE + 0x80)
760 #define SUSPEND_ON_COLLAPSE_DCIN_BIT BIT(7)
761 #define DCIN_AICL_HDC_EN_BIT BIT(6)
762 #define DCIN_AICL_START_AT_MAX_BIT BIT(5)
763 #define DCIN_AICL_RERUN_EN_BIT BIT(4)
764 #define DCIN_AICL_ADC_EN_BIT BIT(3)
765 #define DCIN_AICL_EN_BIT BIT(2)
766 #define DCIN_HV_COLLAPSE_RESPONSE_BIT BIT(1)
767 #define DCIN_LV_COLLAPSE_RESPONSE_BIT BIT(0)
769 #define DCIN_AICL_REF_SEL_CFG_REG (DCIN_BASE + 0x81)
770 #define DCIN_CONT_AICL_THRESHOLD_CFG_MASK GENMASK(5, 0)
772 #define DCIN_ICL_START_CFG_REG (DCIN_BASE + 0x82)
773 #define DCIN_ICL_START_CFG_BIT BIT(0)
775 #define DIV2_EN_GF_TIME_CFG_REG (DCIN_BASE + 0x90)
776 #define DIV2_EN_GF_TIME_CFG_MASK GENMASK(1, 0)
778 #define WIPWR_IRQ_TMR_CFG_REG (DCIN_BASE + 0x91)
779 #define WIPWR_IRQ_TMR_MASK GENMASK(2, 0)
781 #define ZIN_ICL_PT_REG (DCIN_BASE + 0x92)
782 #define ZIN_ICL_PT_MASK GENMASK(7, 0)
784 #define ZIN_ICL_LV_REG (DCIN_BASE + 0x93)
785 #define ZIN_ICL_LV_MASK GENMASK(7, 0)
787 #define ZIN_ICL_HV_REG (DCIN_BASE + 0x94)
788 #define ZIN_ICL_HV_MASK GENMASK(7, 0)
790 #define WI_PWR_OPTIONS_REG (DCIN_BASE + 0x95)
791 #define CHG_OK_BIT BIT(7)
792 #define WIPWR_UVLO_IRQ_OPT_BIT BIT(6)
793 #define BUCK_HOLDOFF_ENABLE_BIT BIT(5)
794 #define CHG_OK_HW_SW_SELECT_BIT BIT(4)
795 #define WIPWR_RST_ENABLE_BIT BIT(3)
796 #define DCIN_WIPWR_IRQ_SELECT_BIT BIT(2)
797 #define AICL_SWITCH_ENABLE_BIT BIT(1)
798 #define ZIN_ICL_ENABLE_BIT BIT(0)
800 #define ZIN_ICL_PT_HV_REG (DCIN_BASE + 0x96)
801 #define ZIN_ICL_PT_HV_MASK GENMASK(7, 0)
803 #define ZIN_ICL_MID_LV_REG (DCIN_BASE + 0x97)
804 #define ZIN_ICL_MID_LV_MASK GENMASK(7, 0)
806 #define ZIN_ICL_MID_HV_REG (DCIN_BASE + 0x98)
807 #define ZIN_ICL_MID_HV_MASK GENMASK(7, 0)
810 ZIN_ICL_PT_MAX_MV = 8000,
811 ZIN_ICL_PT_HV_MAX_MV = 9000,
812 ZIN_ICL_LV_MAX_MV = 5500,
813 ZIN_ICL_MID_LV_MAX_MV = 6500,
814 ZIN_ICL_MID_HV_MAX_MV = 8000,
815 ZIN_ICL_HV_MAX_MV = 11000,
818 #define DC_ENG_SSUPPLY_CFG2_REG (DCIN_BASE + 0xC1)
819 #define ENG_SSUPPLY_IVREF_OTG_SS_MASK GENMASK(2, 0)
820 #define OTG_SS_SLOW 0x3
822 #define DC_ENG_SSUPPLY_CFG3_REG (DCIN_BASE + 0xC2)
823 #define ENG_SSUPPLY_HI_CAP_BIT BIT(6)
824 #define ENG_SSUPPLY_HI_RES_BIT BIT(5)
825 #define ENG_SSUPPLY_CFG_SKIP_TH_V0P2_BIT BIT(3)
826 #define ENG_SSUPPLY_CFG_SYSOV_TH_4P8_BIT BIT(2)
827 #define ENG_SSUPPLY_5V_OV_OPT_BIT BIT(0)
829 /* MISC Peripheral Registers */
830 #define REVISION1_REG (MISC_BASE + 0x00)
831 #define DIG_MINOR_MASK GENMASK(7, 0)
833 #define REVISION2_REG (MISC_BASE + 0x01)
834 #define DIG_MAJOR_MASK GENMASK(7, 0)
836 #define REVISION3_REG (MISC_BASE + 0x02)
837 #define ANA_MINOR_MASK GENMASK(7, 0)
839 #define REVISION4_REG (MISC_BASE + 0x03)
840 #define ANA_MAJOR_MASK GENMASK(7, 0)
842 #define TEMP_RANGE_STATUS_REG (MISC_BASE + 0x06)
843 #define TEMP_RANGE_STATUS_7_BIT BIT(7)
844 #define THERM_REG_ACTIVE_BIT BIT(6)
845 #define TLIM_BIT BIT(5)
846 #define TEMP_RANGE_MASK GENMASK(4, 1)
847 #define ALERT_LEVEL_BIT BIT(4)
848 #define TEMP_ABOVE_RANGE_BIT BIT(3)
849 #define TEMP_WITHIN_RANGE_BIT BIT(2)
850 #define TEMP_BELOW_RANGE_BIT BIT(1)
851 #define THERMREG_DISABLED_BIT BIT(0)
853 #define ICL_STATUS_REG (MISC_BASE + 0x07)
854 #define INPUT_CURRENT_LIMIT_MASK GENMASK(7, 0)
856 #define ADAPTER_5V_ICL_STATUS_REG (MISC_BASE + 0x08)
857 #define ADAPTER_5V_ICL_MASK GENMASK(7, 0)
859 #define ADAPTER_9V_ICL_STATUS_REG (MISC_BASE + 0x09)
860 #define ADAPTER_9V_ICL_MASK GENMASK(7, 0)
862 #define AICL_STATUS_REG (MISC_BASE + 0x0A)
863 #define AICL_STATUS_7_BIT BIT(7)
864 #define SOFT_ILIMIT_BIT BIT(6)
865 #define HIGHEST_DC_BIT BIT(5)
866 #define USBIN_CH_COLLAPSE_BIT BIT(4)
867 #define DCIN_CH_COLLAPSE_BIT BIT(3)
868 #define ICL_IMIN_BIT BIT(2)
869 #define AICL_FAIL_BIT BIT(1)
870 #define AICL_DONE_BIT BIT(0)
872 #define POWER_PATH_STATUS_REG (MISC_BASE + 0x0B)
873 #define INPUT_SS_DONE_BIT BIT(7)
874 #define USBIN_SUSPEND_STS_BIT BIT(6)
875 #define DCIN_SUSPEND_STS_BIT BIT(5)
876 #define USE_USBIN_BIT BIT(4)
877 #define USE_DCIN_BIT BIT(3)
878 #define POWER_PATH_MASK GENMASK(2, 1)
879 #define VALID_INPUT_POWER_SOURCE_STS_BIT BIT(0)
881 #define WDOG_STATUS_REG (MISC_BASE + 0x0C)
882 #define WDOG_STATUS_7_BIT BIT(7)
883 #define WDOG_STATUS_6_BIT BIT(6)
884 #define WDOG_STATUS_5_BIT BIT(5)
885 #define WDOG_STATUS_4_BIT BIT(4)
886 #define WDOG_STATUS_3_BIT BIT(3)
887 #define WDOG_STATUS_2_BIT BIT(2)
888 #define WDOG_STATUS_1_BIT BIT(1)
889 #define BARK_BITE_STATUS_BIT BIT(0)
891 #define SYSOK_REASON_STATUS_REG (MISC_BASE + 0x0D)
892 #define SYSOK_REASON_DCIN_BIT BIT(1)
893 #define SYSOK_REASON_USBIN_BIT BIT(0)
895 /* MISC Interrupt Bits */
896 #define SWITCHER_POWER_OK_RT_STS_BIT BIT(7)
897 #define TEMPERATURE_CHANGE_RT_STS_BIT BIT(6)
898 #define INPUT_CURRENT_LIMITING_RT_STS_BIT BIT(5)
899 #define HIGH_DUTY_CYCLE_RT_STS_BIT BIT(4)
900 #define AICL_DONE_RT_STS_BIT BIT(3)
901 #define AICL_FAIL_RT_STS_BIT BIT(2)
902 #define WDOG_BARK_RT_STS_BIT BIT(1)
903 #define WDOG_SNARL_RT_STS_BIT BIT(0)
905 #define WDOG_RST_REG (MISC_BASE + 0x40)
906 #define WDOG_RST_BIT BIT(0)
908 #define AFP_MODE_REG (MISC_BASE + 0x41)
909 #define AFP_MODE_EN_BIT BIT(0)
911 #define GSM_PA_ON_ADJ_EN_REG (MISC_BASE + 0x42)
912 #define GSM_PA_ON_ADJ_EN_BIT BIT(0)
914 #define BARK_BITE_WDOG_PET_REG (MISC_BASE + 0x43)
915 #define BARK_BITE_WDOG_PET_BIT BIT(0)
917 #define PHYON_CMD_REG (MISC_BASE + 0x44)
918 #define PHYON_CMD_BIT BIT(0)
920 #define SHDN_CMD_REG (MISC_BASE + 0x45)
921 #define SHDN_CMD_BIT BIT(0)
923 #define FINISH_COPY_COMMAND_REG (MISC_BASE + 0x4F)
924 #define START_COPY_BIT BIT(0)
926 #define WD_CFG_REG (MISC_BASE + 0x51)
927 #define WATCHDOG_TRIGGER_AFP_EN_BIT BIT(7)
928 #define BARK_WDOG_INT_EN_BIT BIT(6)
929 #define BITE_WDOG_INT_EN_BIT BIT(5)
930 #define SFT_AFTER_WDOG_IRQ_MASK GENMASK(4, 3)
931 #define WDOG_IRQ_SFT_BIT BIT(2)
932 #define WDOG_TIMER_EN_ON_PLUGIN_BIT BIT(1)
933 #define WDOG_TIMER_EN_BIT BIT(0)
935 #define MISC_CFG_REG (MISC_BASE + 0x52)
936 #define GSM_PA_ON_ADJ_SEL_BIT BIT(0)
937 #define STAT_PARALLEL_1400MA_EN_CFG_BIT BIT(3)
938 #define TCC_DEBOUNCE_20MS_BIT BIT(5)
940 #define SNARL_BARK_BITE_WD_CFG_REG (MISC_BASE + 0x53)
941 #define BITE_WDOG_DISABLE_CHARGING_CFG_BIT BIT(7)
942 #define SNARL_WDOG_TIMEOUT_MASK GENMASK(6, 4)
943 #define BARK_WDOG_TIMEOUT_MASK GENMASK(3, 2)
944 #define BITE_WDOG_TIMEOUT_MASK GENMASK(1, 0)
946 #define PHYON_CFG_REG (MISC_BASE + 0x54)
947 #define USBPHYON_PUSHPULL_CFG_BIT BIT(1)
948 #define PHYON_SW_SEL_BIT BIT(0)
950 #define CHGR_TRIM_OPTIONS_7_0_REG (MISC_BASE + 0x55)
951 #define TLIM_DIS_TBIT_BIT BIT(0)
953 #define CH_OV_OPTION_CFG_REG (MISC_BASE + 0x56)
954 #define OV_OPTION_TBIT_BIT BIT(0)
956 #define AICL_CFG_REG (MISC_BASE + 0x60)
957 #define TREG_ALLOW_DECREASE_BIT BIT(1)
958 #define AICL_HIGH_DC_INC_BIT BIT(0)
960 #define AICL_RERUN_TIME_CFG_REG (MISC_BASE + 0x61)
961 #define AICL_RERUN_TIME_MASK GENMASK(1, 0)
963 #define AICL_RERUN_TEMP_TIME_CFG_REG (MISC_BASE + 0x62)
964 #define AICL_RERUN_TEMP_TIME_MASK GENMASK(1, 0)
966 #define THERMREG_SRC_CFG_REG (MISC_BASE + 0x70)
967 #define SKIN_ADC_CFG_BIT BIT(3)
968 #define THERMREG_SKIN_ADC_SRC_EN_BIT BIT(2)
969 #define THERMREG_DIE_ADC_SRC_EN_BIT BIT(1)
970 #define THERMREG_DIE_CMP_SRC_EN_BIT BIT(0)
972 #define TREG_DIE_CMP_INC_CYCLE_TIME_CFG_REG (MISC_BASE + 0x71)
973 #define TREG_DIE_CMP_INC_CYCLE_TIME_MASK GENMASK(1, 0)
975 #define TREG_DIE_CMP_DEC_CYCLE_TIME_CFG_REG (MISC_BASE + 0x72)
976 #define TREG_DIE_CMP_DEC_CYCLE_TIME_MASK GENMASK(1, 0)
978 #define TREG_DIE_ADC_INC_CYCLE_TIME_CFG_REG (MISC_BASE + 0x73)
979 #define TREG_DIE_ADC_INC_CYCLE_TIME_MASK GENMASK(1, 0)
981 #define TREG_DIE_ADC_DEC_CYCLE_TIME_CFG_REG (MISC_BASE + 0x74)
982 #define TREG_DIE_ADC_DEC_CYCLE_TIME_MASK GENMASK(1, 0)
984 #define TREG_SKIN_ADC_INC_CYCLE_TIME_CFG_REG (MISC_BASE + 0x75)
985 #define TREG_SKIN_ADC_INC_CYCLE_TIME_MASK GENMASK(1, 0)
987 #define TREG_SKIN_ADC_DEC_CYCLE_TIME_CFG_REG (MISC_BASE + 0x76)
988 #define TREG_SKIN_ADC_DEC_CYCLE_TIME_MASK GENMASK(1, 0)
990 #define BUCK_OPTIONS_CFG_REG (MISC_BASE + 0x80)
991 #define CHG_EN_PIN_SUSPEND_CFG_BIT BIT(6)
992 #define HICCUP_OPTIONS_MASK GENMASK(5, 4)
993 #define INPUT_CURRENT_LIMIT_SOFTSTART_EN_BIT BIT(3)
994 #define HV_HIGH_DUTY_CYCLE_PROTECT_EN_BIT BIT(2)
995 #define BUCK_OC_PROTECT_EN_BIT BIT(1)
996 #define INPUT_MISS_POLL_EN_BIT BIT(0)
998 #define ICL_SOFTSTART_RATE_CFG_REG (MISC_BASE + 0x81)
999 #define ICL_SOFTSTART_RATE_MASK GENMASK(1, 0)
1001 #define ICL_SOFTSTOP_RATE_CFG_REG (MISC_BASE + 0x82)
1002 #define ICL_SOFTSTOP_RATE_MASK GENMASK(1, 0)
1004 #define VSYS_MIN_SEL_CFG_REG (MISC_BASE + 0x83)
1005 #define VSYS_MIN_SEL_MASK GENMASK(1, 0)
1007 #define TRACKING_VOLTAGE_SEL_CFG_REG (MISC_BASE + 0x84)
1008 #define TRACKING_VOLTAGE_SEL_BIT BIT(0)
1010 #define STAT_CFG_REG (MISC_BASE + 0x90)
1011 #define STAT_SW_OVERRIDE_VALUE_BIT BIT(7)
1012 #define STAT_SW_OVERRIDE_CFG_BIT BIT(6)
1013 #define STAT_PARALLEL_OFF_DG_CFG_MASK GENMASK(5, 4)
1014 #define STAT_POLARITY_CFG_BIT BIT(3)
1015 #define STAT_PARALLEL_CFG_BIT BIT(2)
1016 #define STAT_FUNCTION_CFG_BIT BIT(1)
1017 #define STAT_IRQ_PULSING_EN_BIT BIT(0)
1019 #define LBC_EN_CFG_REG (MISC_BASE + 0x91)
1020 #define LBC_DURING_CHARGING_CFG_BIT BIT(1)
1021 #define LBC_EN_BIT BIT(0)
1023 #define LBC_PERIOD_CFG_REG (MISC_BASE + 0x92)
1024 #define LBC_PERIOD_MASK GENMASK(2, 0)
1026 #define LBC_DUTY_CYCLE_CFG_REG (MISC_BASE + 0x93)
1027 #define LBC_DUTY_CYCLE_MASK GENMASK(2, 0)
1029 #define SYSOK_CFG_REG (MISC_BASE + 0x94)
1030 #define SYSOK_PUSHPULL_CFG_BIT BIT(5)
1031 #define SYSOK_B_OR_C_SEL_BIT BIT(4)
1032 #define SYSOK_POL_BIT BIT(3)
1033 #define SYSOK_OPTIONS_MASK GENMASK(2, 0)
1035 #define CFG_BUCKBOOST_FREQ_SELECT_BUCK_REG (MISC_BASE + 0xA0)
1036 #define CFG_BUCKBOOST_FREQ_SELECT_BOOST_REG (MISC_BASE + 0xA1)
1038 #define TM_IO_DTEST4_SEL (MISC_BASE + 0xE9)
1040 /* CHGR FREQ Peripheral registers */
1041 #define FREQ_CLK_DIV_REG (CHGR_FREQ_BASE + 0x50)
1043 #endif /* __SMB2_CHARGER_REG_H */