1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2020 Facebook */
5 #include <linux/kernel.h>
6 #include <linux/module.h>
7 #include <linux/debugfs.h>
8 #include <linux/init.h>
10 #include <linux/serial_8250.h>
11 #include <linux/clkdev.h>
12 #include <linux/clk-provider.h>
13 #include <linux/platform_device.h>
14 #include <linux/ptp_clock_kernel.h>
15 #include <linux/spi/spi.h>
16 #include <linux/spi/xilinx_spi.h>
17 #include <net/devlink.h>
18 #include <linux/i2c.h>
19 #include <linux/mtd/mtd.h>
21 #ifndef PCI_VENDOR_ID_FACEBOOK
22 #define PCI_VENDOR_ID_FACEBOOK 0x1d9b
25 #ifndef PCI_DEVICE_ID_FACEBOOK_TIMECARD
26 #define PCI_DEVICE_ID_FACEBOOK_TIMECARD 0x0400
29 static struct class timecard_class = {
57 #define OCP_CTRL_ENABLE BIT(0)
58 #define OCP_CTRL_ADJUST_TIME BIT(1)
59 #define OCP_CTRL_ADJUST_OFFSET BIT(2)
60 #define OCP_CTRL_ADJUST_DRIFT BIT(3)
61 #define OCP_CTRL_ADJUST_SERVO BIT(8)
62 #define OCP_CTRL_READ_TIME_REQ BIT(30)
63 #define OCP_CTRL_READ_TIME_DONE BIT(31)
65 #define OCP_STATUS_IN_SYNC BIT(0)
66 #define OCP_STATUS_IN_HOLDOVER BIT(1)
68 #define OCP_SELECT_CLK_NONE 0
69 #define OCP_SELECT_CLK_REG 0xfe
84 #define TOD_CTRL_PROTOCOL BIT(28)
85 #define TOD_CTRL_DISABLE_FMT_A BIT(17)
86 #define TOD_CTRL_DISABLE_FMT_B BIT(16)
87 #define TOD_CTRL_ENABLE BIT(0)
88 #define TOD_CTRL_GNSS_MASK ((1U << 4) - 1)
89 #define TOD_CTRL_GNSS_SHIFT 24
91 #define TOD_STATUS_UTC_MASK 0xff
92 #define TOD_STATUS_UTC_VALID BIT(8)
93 #define TOD_STATUS_LEAP_VALID BIT(16)
121 #define PPS_STATUS_FILTER_ERR BIT(0)
122 #define PPS_STATUS_SUPERV_ERR BIT(1)
135 struct irig_master_reg {
144 #define IRIG_M_CTRL_ENABLE BIT(0)
146 struct irig_slave_reg {
155 #define IRIG_S_CTRL_ENABLE BIT(0)
157 struct dcf_master_reg {
165 #define DCF_M_CTRL_ENABLE BIT(0)
167 struct dcf_slave_reg {
175 #define DCF_S_CTRL_ENABLE BIT(0)
177 struct ptp_ocp_flash_info {
184 struct ptp_ocp_i2c_info {
186 unsigned long fixed_rate;
191 struct ptp_ocp_ext_info {
193 irqreturn_t (*irq_fcn)(int irq, void *priv);
194 int (*enable)(void *priv, u32 req, bool enable);
197 struct ptp_ocp_ext_src {
200 struct ptp_ocp_ext_info *info;
205 struct pci_dev *pdev;
208 struct ocp_reg __iomem *reg;
209 struct tod_reg __iomem *tod;
210 struct pps_reg __iomem *pps_to_ext;
211 struct pps_reg __iomem *pps_to_clk;
212 struct gpio_reg __iomem *pps_select;
213 struct gpio_reg __iomem *sma;
214 struct irig_master_reg __iomem *irig_out;
215 struct irig_slave_reg __iomem *irig_in;
216 struct dcf_master_reg __iomem *dcf_out;
217 struct dcf_slave_reg __iomem *dcf_in;
218 struct tod_reg __iomem *nmea_out;
219 struct ptp_ocp_ext_src *pps;
220 struct ptp_ocp_ext_src *ts0;
221 struct ptp_ocp_ext_src *ts1;
222 struct ptp_ocp_ext_src *ts2;
223 struct img_reg __iomem *image;
224 struct ptp_clock *ptp;
225 struct ptp_clock_info ptp_info;
226 struct platform_device *i2c_ctrl;
227 struct platform_device *spi_flash;
228 struct clk_hw *i2c_clk;
229 struct timer_list watchdog;
230 struct dentry *debug_root;
236 int mac_port; /* miniature atomic clock */
243 u32 ts_window_adjust;
246 #define OCP_REQ_TIMESTAMP BIT(0)
247 #define OCP_REQ_PPS BIT(1)
249 struct ocp_resource {
250 unsigned long offset;
253 int (*setup)(struct ptp_ocp *bp, struct ocp_resource *r);
255 unsigned long bp_offset;
256 const char * const name;
259 static int ptp_ocp_register_mem(struct ptp_ocp *bp, struct ocp_resource *r);
260 static int ptp_ocp_register_i2c(struct ptp_ocp *bp, struct ocp_resource *r);
261 static int ptp_ocp_register_spi(struct ptp_ocp *bp, struct ocp_resource *r);
262 static int ptp_ocp_register_serial(struct ptp_ocp *bp, struct ocp_resource *r);
263 static int ptp_ocp_register_ext(struct ptp_ocp *bp, struct ocp_resource *r);
264 static int ptp_ocp_fb_board_init(struct ptp_ocp *bp, struct ocp_resource *r);
265 static irqreturn_t ptp_ocp_ts_irq(int irq, void *priv);
266 static int ptp_ocp_ts_enable(void *priv, u32 req, bool enable);
268 #define bp_assign_entry(bp, res, val) ({ \
269 uintptr_t addr = (uintptr_t)(bp) + (res)->bp_offset; \
270 *(typeof(val) *)addr = val; \
273 #define OCP_RES_LOCATION(member) \
274 .name = #member, .bp_offset = offsetof(struct ptp_ocp, member)
276 #define OCP_MEM_RESOURCE(member) \
277 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_mem
279 #define OCP_SERIAL_RESOURCE(member) \
280 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_serial
282 #define OCP_I2C_RESOURCE(member) \
283 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_i2c
285 #define OCP_SPI_RESOURCE(member) \
286 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_spi
288 #define OCP_EXT_RESOURCE(member) \
289 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_ext
291 /* This is the MSI vector mapping used.
300 * 8: HWICAP (notused)
305 static struct ocp_resource ocp_fb_resource[] = {
307 OCP_MEM_RESOURCE(reg),
308 .offset = 0x01000000, .size = 0x10000,
311 OCP_EXT_RESOURCE(ts0),
312 .offset = 0x01010000, .size = 0x10000, .irq_vec = 1,
313 .extra = &(struct ptp_ocp_ext_info) {
315 .irq_fcn = ptp_ocp_ts_irq,
316 .enable = ptp_ocp_ts_enable,
320 OCP_EXT_RESOURCE(ts1),
321 .offset = 0x01020000, .size = 0x10000, .irq_vec = 2,
322 .extra = &(struct ptp_ocp_ext_info) {
324 .irq_fcn = ptp_ocp_ts_irq,
325 .enable = ptp_ocp_ts_enable,
329 OCP_EXT_RESOURCE(ts2),
330 .offset = 0x01060000, .size = 0x10000, .irq_vec = 6,
331 .extra = &(struct ptp_ocp_ext_info) {
333 .irq_fcn = ptp_ocp_ts_irq,
334 .enable = ptp_ocp_ts_enable,
338 OCP_EXT_RESOURCE(pps),
339 .offset = 0x010C0000, .size = 0x10000, .irq_vec = 0,
340 .extra = &(struct ptp_ocp_ext_info) {
342 .irq_fcn = ptp_ocp_ts_irq,
343 .enable = ptp_ocp_ts_enable,
347 OCP_MEM_RESOURCE(pps_to_ext),
348 .offset = 0x01030000, .size = 0x10000,
351 OCP_MEM_RESOURCE(pps_to_clk),
352 .offset = 0x01040000, .size = 0x10000,
355 OCP_MEM_RESOURCE(tod),
356 .offset = 0x01050000, .size = 0x10000,
359 OCP_MEM_RESOURCE(irig_in),
360 .offset = 0x01070000, .size = 0x10000,
363 OCP_MEM_RESOURCE(irig_out),
364 .offset = 0x01080000, .size = 0x10000,
367 OCP_MEM_RESOURCE(dcf_in),
368 .offset = 0x01090000, .size = 0x10000,
371 OCP_MEM_RESOURCE(dcf_out),
372 .offset = 0x010A0000, .size = 0x10000,
375 OCP_MEM_RESOURCE(nmea_out),
376 .offset = 0x010B0000, .size = 0x10000,
379 OCP_MEM_RESOURCE(image),
380 .offset = 0x00020000, .size = 0x1000,
383 OCP_MEM_RESOURCE(pps_select),
384 .offset = 0x00130000, .size = 0x1000,
387 OCP_MEM_RESOURCE(sma),
388 .offset = 0x00140000, .size = 0x1000,
391 OCP_I2C_RESOURCE(i2c_ctrl),
392 .offset = 0x00150000, .size = 0x10000, .irq_vec = 7,
393 .extra = &(struct ptp_ocp_i2c_info) {
395 .fixed_rate = 50000000,
399 OCP_SERIAL_RESOURCE(gnss_port),
400 .offset = 0x00160000 + 0x1000, .irq_vec = 3,
403 OCP_SERIAL_RESOURCE(gnss2_port),
404 .offset = 0x00170000 + 0x1000, .irq_vec = 4,
407 OCP_SERIAL_RESOURCE(mac_port),
408 .offset = 0x00180000 + 0x1000, .irq_vec = 5,
411 OCP_SERIAL_RESOURCE(nmea_port),
412 .offset = 0x00190000 + 0x1000, .irq_vec = 10,
415 OCP_SPI_RESOURCE(spi_flash),
416 .offset = 0x00310000, .size = 0x10000, .irq_vec = 9,
417 .extra = &(struct ptp_ocp_flash_info) {
418 .name = "xilinx_spi", .pci_offset = 0,
419 .data_size = sizeof(struct xspi_platform_data),
420 .data = &(struct xspi_platform_data) {
424 .devices = &(struct spi_board_info) {
425 .modalias = "spi-nor",
431 .setup = ptp_ocp_fb_board_init,
436 static const struct pci_device_id ptp_ocp_pcidev_id[] = {
437 { PCI_DEVICE_DATA(FACEBOOK, TIMECARD, &ocp_fb_resource) },
440 MODULE_DEVICE_TABLE(pci, ptp_ocp_pcidev_id);
442 static DEFINE_MUTEX(ptp_ocp_lock);
443 static DEFINE_IDR(ptp_ocp_idr);
445 struct ocp_selector {
450 static struct ocp_selector ptp_ocp_clock[] = {
451 { .name = "NONE", .value = 0 },
452 { .name = "TOD", .value = 1 },
453 { .name = "IRIG", .value = 2 },
454 { .name = "PPS", .value = 3 },
455 { .name = "PTP", .value = 4 },
456 { .name = "RTC", .value = 5 },
457 { .name = "DCF", .value = 6 },
458 { .name = "REGS", .value = 0xfe },
459 { .name = "EXT", .value = 0xff },
463 static struct ocp_selector ptp_ocp_sma_in[] = {
464 { .name = "10Mhz", .value = 0x00 },
465 { .name = "PPS1", .value = 0x01 },
466 { .name = "PPS2", .value = 0x02 },
467 { .name = "TS1", .value = 0x04 },
468 { .name = "TS2", .value = 0x08 },
469 { .name = "IRIG", .value = 0x10 },
470 { .name = "DCF", .value = 0x20 },
474 static struct ocp_selector ptp_ocp_sma_out[] = {
475 { .name = "10Mhz", .value = 0x00 },
476 { .name = "PHC", .value = 0x01 },
477 { .name = "MAC", .value = 0x02 },
478 { .name = "GNSS", .value = 0x04 },
479 { .name = "GNSS2", .value = 0x08 },
480 { .name = "IRIG", .value = 0x10 },
481 { .name = "DCF", .value = 0x20 },
486 ptp_ocp_select_name_from_val(struct ocp_selector *tbl, int val)
490 for (i = 0; tbl[i].name; i++)
491 if (tbl[i].value == val)
497 ptp_ocp_select_val_from_name(struct ocp_selector *tbl, const char *name)
502 for (i = 0; tbl[i].name; i++) {
503 select = tbl[i].name;
504 if (!strncasecmp(name, select, strlen(select)))
511 ptp_ocp_select_table_show(struct ocp_selector *tbl, char *buf)
517 for (i = 0; tbl[i].name; i++)
518 count += sysfs_emit_at(buf, count, "%s ", tbl[i].name);
521 count += sysfs_emit_at(buf, count, "\n");
526 __ptp_ocp_gettime_locked(struct ptp_ocp *bp, struct timespec64 *ts,
527 struct ptp_system_timestamp *sts)
529 u32 ctrl, time_sec, time_ns;
532 ptp_read_system_prets(sts);
534 ctrl = OCP_CTRL_READ_TIME_REQ | OCP_CTRL_ENABLE;
535 iowrite32(ctrl, &bp->reg->ctrl);
537 for (i = 0; i < 100; i++) {
538 ctrl = ioread32(&bp->reg->ctrl);
539 if (ctrl & OCP_CTRL_READ_TIME_DONE)
542 ptp_read_system_postts(sts);
544 if (sts && bp->ts_window_adjust) {
545 s64 ns = timespec64_to_ns(&sts->post_ts);
547 sts->post_ts = ns_to_timespec64(ns - bp->ts_window_adjust);
550 time_ns = ioread32(&bp->reg->time_ns);
551 time_sec = ioread32(&bp->reg->time_sec);
553 ts->tv_sec = time_sec;
554 ts->tv_nsec = time_ns;
556 return ctrl & OCP_CTRL_READ_TIME_DONE ? 0 : -ETIMEDOUT;
560 ptp_ocp_gettimex(struct ptp_clock_info *ptp_info, struct timespec64 *ts,
561 struct ptp_system_timestamp *sts)
563 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
567 spin_lock_irqsave(&bp->lock, flags);
568 err = __ptp_ocp_gettime_locked(bp, ts, sts);
569 spin_unlock_irqrestore(&bp->lock, flags);
575 __ptp_ocp_settime_locked(struct ptp_ocp *bp, const struct timespec64 *ts)
577 u32 ctrl, time_sec, time_ns;
580 time_ns = ts->tv_nsec;
581 time_sec = ts->tv_sec;
583 select = ioread32(&bp->reg->select);
584 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
586 iowrite32(time_ns, &bp->reg->adjust_ns);
587 iowrite32(time_sec, &bp->reg->adjust_sec);
589 ctrl = OCP_CTRL_ADJUST_TIME | OCP_CTRL_ENABLE;
590 iowrite32(ctrl, &bp->reg->ctrl);
592 /* restore clock selection */
593 iowrite32(select >> 16, &bp->reg->select);
597 ptp_ocp_settime(struct ptp_clock_info *ptp_info, const struct timespec64 *ts)
599 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
602 spin_lock_irqsave(&bp->lock, flags);
603 __ptp_ocp_settime_locked(bp, ts);
604 spin_unlock_irqrestore(&bp->lock, flags);
610 __ptp_ocp_adjtime_locked(struct ptp_ocp *bp, u64 adj_val)
614 select = ioread32(&bp->reg->select);
615 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
617 iowrite32(adj_val, &bp->reg->offset_ns);
618 iowrite32(adj_val & 0x7f, &bp->reg->offset_window_ns);
620 ctrl = OCP_CTRL_ADJUST_OFFSET | OCP_CTRL_ENABLE;
621 iowrite32(ctrl, &bp->reg->ctrl);
623 /* restore clock selection */
624 iowrite32(select >> 16, &bp->reg->select);
628 ptp_ocp_adjtime(struct ptp_clock_info *ptp_info, s64 delta_ns)
630 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
634 sign = delta_ns < 0 ? BIT(31) : 0;
635 adj_ns = sign ? -delta_ns : delta_ns;
637 spin_lock_irqsave(&bp->lock, flags);
638 __ptp_ocp_adjtime_locked(bp, sign | adj_ns);
639 spin_unlock_irqrestore(&bp->lock, flags);
645 ptp_ocp_null_adjfine(struct ptp_clock_info *ptp_info, long scaled_ppm)
654 ptp_ocp_null_adjphase(struct ptp_clock_info *ptp_info, s32 phase_ns)
660 ptp_ocp_enable(struct ptp_clock_info *ptp_info, struct ptp_clock_request *rq,
663 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
664 struct ptp_ocp_ext_src *ext = NULL;
669 case PTP_CLK_REQ_EXTTS:
670 req = OCP_REQ_TIMESTAMP;
671 switch (rq->extts.index) {
686 case PTP_CLK_REQ_PPS:
690 case PTP_CLK_REQ_PEROUT:
692 (rq->perout.period.sec != 1 || rq->perout.period.nsec != 0))
694 /* This is a request for 1PPS on an output SMA.
695 * Allow, but assume manual configuration.
704 err = ext->info->enable(ext, req, on);
709 static const struct ptp_clock_info ptp_ocp_clock_info = {
710 .owner = THIS_MODULE,
711 .name = KBUILD_MODNAME,
712 .max_adj = 100000000,
713 .gettimex64 = ptp_ocp_gettimex,
714 .settime64 = ptp_ocp_settime,
715 .adjtime = ptp_ocp_adjtime,
716 .adjfine = ptp_ocp_null_adjfine,
717 .adjphase = ptp_ocp_null_adjphase,
718 .enable = ptp_ocp_enable,
725 __ptp_ocp_clear_drift_locked(struct ptp_ocp *bp)
729 select = ioread32(&bp->reg->select);
730 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
732 iowrite32(0, &bp->reg->drift_ns);
734 ctrl = OCP_CTRL_ADJUST_DRIFT | OCP_CTRL_ENABLE;
735 iowrite32(ctrl, &bp->reg->ctrl);
737 /* restore clock selection */
738 iowrite32(select >> 16, &bp->reg->select);
742 ptp_ocp_watchdog(struct timer_list *t)
744 struct ptp_ocp *bp = from_timer(bp, t, watchdog);
748 status = ioread32(&bp->pps_to_clk->status);
750 if (status & PPS_STATUS_SUPERV_ERR) {
751 iowrite32(status, &bp->pps_to_clk->status);
752 if (!bp->gnss_lost) {
753 spin_lock_irqsave(&bp->lock, flags);
754 __ptp_ocp_clear_drift_locked(bp);
755 spin_unlock_irqrestore(&bp->lock, flags);
756 bp->gnss_lost = ktime_get_real_seconds();
759 } else if (bp->gnss_lost) {
763 mod_timer(&bp->watchdog, jiffies + HZ);
767 ptp_ocp_estimate_pci_timing(struct ptp_ocp *bp)
773 ctrl = ioread32(&bp->reg->ctrl);
774 ctrl = OCP_CTRL_READ_TIME_REQ | OCP_CTRL_ENABLE;
776 iowrite32(ctrl, &bp->reg->ctrl);
778 start = ktime_get_ns();
780 ctrl = ioread32(&bp->reg->ctrl);
782 end = ktime_get_ns();
785 bp->ts_window_adjust = (delay >> 5) * 3;
789 ptp_ocp_init_clock(struct ptp_ocp *bp)
791 struct timespec64 ts;
795 ctrl = OCP_CTRL_ENABLE;
796 iowrite32(ctrl, &bp->reg->ctrl);
798 /* NO DRIFT Correction */
799 /* offset_p:i 1/8, offset_i: 1/16, drift_p: 0, drift_i: 0 */
800 iowrite32(0x2000, &bp->reg->servo_offset_p);
801 iowrite32(0x1000, &bp->reg->servo_offset_i);
802 iowrite32(0, &bp->reg->servo_drift_p);
803 iowrite32(0, &bp->reg->servo_drift_i);
805 /* latch servo values */
806 ctrl |= OCP_CTRL_ADJUST_SERVO;
807 iowrite32(ctrl, &bp->reg->ctrl);
809 if ((ioread32(&bp->reg->ctrl) & OCP_CTRL_ENABLE) == 0) {
810 dev_err(&bp->pdev->dev, "clock not enabled\n");
814 ptp_ocp_estimate_pci_timing(bp);
816 sync = ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC;
818 ktime_get_clocktai_ts64(&ts);
819 ptp_ocp_settime(&bp->ptp_info, &ts);
822 /* If there is a clock supervisor, then enable the watchdog */
823 if (bp->pps_to_clk) {
824 timer_setup(&bp->watchdog, ptp_ocp_watchdog, 0);
825 mod_timer(&bp->watchdog, jiffies + HZ);
832 ptp_ocp_utc_distribute(struct ptp_ocp *bp, u32 val)
836 spin_lock_irqsave(&bp->lock, flags);
838 bp->utc_tai_offset = val;
841 iowrite32(val, &bp->irig_out->adj_sec);
843 iowrite32(val, &bp->dcf_out->adj_sec);
845 iowrite32(val, &bp->nmea_out->adj_sec);
847 spin_unlock_irqrestore(&bp->lock, flags);
851 ptp_ocp_tod_init(struct ptp_ocp *bp)
855 ctrl = ioread32(&bp->tod->ctrl);
856 ctrl |= TOD_CTRL_PROTOCOL | TOD_CTRL_ENABLE;
857 ctrl &= ~(TOD_CTRL_DISABLE_FMT_A | TOD_CTRL_DISABLE_FMT_B);
858 iowrite32(ctrl, &bp->tod->ctrl);
860 reg = ioread32(&bp->tod->utc_status);
861 if (reg & TOD_STATUS_UTC_VALID)
862 ptp_ocp_utc_distribute(bp, reg & TOD_STATUS_UTC_MASK);
866 ptp_ocp_tod_info(struct ptp_ocp *bp)
868 static const char * const proto_name[] = {
869 "NMEA", "NMEA_ZDA", "NMEA_RMC", "NMEA_none",
870 "UBX", "UBX_UTC", "UBX_LS", "UBX_none"
872 static const char * const gnss_name[] = {
873 "ALL", "COMBINED", "GPS", "GLONASS", "GALILEO", "BEIDOU",
875 u32 version, ctrl, reg;
878 version = ioread32(&bp->tod->version);
879 dev_info(&bp->pdev->dev, "TOD Version %d.%d.%d\n",
880 version >> 24, (version >> 16) & 0xff, version & 0xffff);
882 ctrl = ioread32(&bp->tod->ctrl);
883 idx = ctrl & TOD_CTRL_PROTOCOL ? 4 : 0;
884 idx += (ctrl >> 16) & 3;
885 dev_info(&bp->pdev->dev, "control: %x\n", ctrl);
886 dev_info(&bp->pdev->dev, "TOD Protocol %s %s\n", proto_name[idx],
887 ctrl & TOD_CTRL_ENABLE ? "enabled" : "");
889 idx = (ctrl >> TOD_CTRL_GNSS_SHIFT) & TOD_CTRL_GNSS_MASK;
890 if (idx < ARRAY_SIZE(gnss_name))
891 dev_info(&bp->pdev->dev, "GNSS %s\n", gnss_name[idx]);
893 reg = ioread32(&bp->tod->status);
894 dev_info(&bp->pdev->dev, "status: %x\n", reg);
896 reg = ioread32(&bp->tod->adj_sec);
897 dev_info(&bp->pdev->dev, "correction: %d\n", reg);
899 reg = ioread32(&bp->tod->utc_status);
900 dev_info(&bp->pdev->dev, "utc_status: %x\n", reg);
901 dev_info(&bp->pdev->dev, "utc_offset: %d valid:%d leap_valid:%d\n",
902 reg & TOD_STATUS_UTC_MASK, reg & TOD_STATUS_UTC_VALID ? 1 : 0,
903 reg & TOD_STATUS_LEAP_VALID ? 1 : 0);
907 ptp_ocp_firstchild(struct device *dev, void *data)
913 ptp_ocp_read_i2c(struct i2c_adapter *adap, u8 addr, u8 reg, u8 sz, u8 *data)
915 struct i2c_msg msgs[2] = {
931 /* xiic-i2c for some stupid reason only does 2 byte reads. */
933 len = min_t(u8, sz, 2);
935 err = i2c_transfer(adap, msgs, 2);
936 if (err != msgs[1].len)
946 ptp_ocp_get_serial_number(struct ptp_ocp *bp)
948 struct i2c_adapter *adap;
955 dev = device_find_child(&bp->i2c_ctrl->dev, NULL, ptp_ocp_firstchild);
957 dev_err(&bp->pdev->dev, "Can't find I2C adapter\n");
961 adap = i2c_verify_adapter(dev);
963 dev_err(&bp->pdev->dev, "device '%s' isn't an I2C adapter\n",
968 err = ptp_ocp_read_i2c(adap, 0x58, 0x9A, 6, bp->serial);
970 dev_err(&bp->pdev->dev, "could not read eeprom: %d\n", err);
974 bp->has_serial = true;
980 static struct device *
981 ptp_ocp_find_flash(struct ptp_ocp *bp)
983 struct device *dev, *last;
986 dev = &bp->spi_flash->dev;
988 while ((dev = device_find_child(dev, NULL, ptp_ocp_firstchild))) {
989 if (!strcmp("mtd", dev_bus_name(dev)))
1000 ptp_ocp_devlink_flash(struct devlink *devlink, struct device *dev,
1001 const struct firmware *fw)
1003 struct mtd_info *mtd = dev_get_drvdata(dev);
1004 struct ptp_ocp *bp = devlink_priv(devlink);
1005 size_t off, len, resid, wrote;
1006 struct erase_info erase;
1011 base = bp->flash_start;
1016 devlink_flash_update_status_notify(devlink, "Flashing",
1017 NULL, off, fw->size);
1019 len = min_t(size_t, resid, blksz);
1020 erase.addr = base + off;
1023 err = mtd_erase(mtd, &erase);
1027 err = mtd_write(mtd, base + off, len, &wrote, &fw->data[off]);
1039 ptp_ocp_devlink_flash_update(struct devlink *devlink,
1040 struct devlink_flash_update_params *params,
1041 struct netlink_ext_ack *extack)
1043 struct ptp_ocp *bp = devlink_priv(devlink);
1048 dev = ptp_ocp_find_flash(bp);
1050 dev_err(&bp->pdev->dev, "Can't find Flash SPI adapter\n");
1054 devlink_flash_update_status_notify(devlink, "Preparing to flash",
1057 err = ptp_ocp_devlink_flash(devlink, dev, params->fw);
1059 msg = err ? "Flash error" : "Flash complete";
1060 devlink_flash_update_status_notify(devlink, msg, NULL, 0, 0);
1067 ptp_ocp_devlink_info_get(struct devlink *devlink, struct devlink_info_req *req,
1068 struct netlink_ext_ack *extack)
1070 struct ptp_ocp *bp = devlink_priv(devlink);
1074 err = devlink_info_driver_name_put(req, KBUILD_MODNAME);
1079 u32 ver = ioread32(&bp->image->version);
1082 sprintf(buf, "%d", ver);
1083 err = devlink_info_version_running_put(req,
1087 sprintf(buf, "%d", ver >> 16);
1088 err = devlink_info_version_running_put(req,
1096 if (!bp->has_serial)
1097 ptp_ocp_get_serial_number(bp);
1099 if (bp->has_serial) {
1100 sprintf(buf, "%pM", bp->serial);
1101 err = devlink_info_serial_number_put(req, buf);
1109 static const struct devlink_ops ptp_ocp_devlink_ops = {
1110 .flash_update = ptp_ocp_devlink_flash_update,
1111 .info_get = ptp_ocp_devlink_info_get,
1114 static void __iomem *
1115 __ptp_ocp_get_mem(struct ptp_ocp *bp, unsigned long start, int size)
1117 struct resource res = DEFINE_RES_MEM_NAMED(start, size, "ptp_ocp");
1119 return devm_ioremap_resource(&bp->pdev->dev, &res);
1122 static void __iomem *
1123 ptp_ocp_get_mem(struct ptp_ocp *bp, struct ocp_resource *r)
1125 unsigned long start;
1127 start = pci_resource_start(bp->pdev, 0) + r->offset;
1128 return __ptp_ocp_get_mem(bp, start, r->size);
1132 ptp_ocp_set_irq_resource(struct resource *res, int irq)
1134 struct resource r = DEFINE_RES_IRQ(irq);
1139 ptp_ocp_set_mem_resource(struct resource *res, unsigned long start, int size)
1141 struct resource r = DEFINE_RES_MEM(start, size);
1146 ptp_ocp_register_spi(struct ptp_ocp *bp, struct ocp_resource *r)
1148 struct ptp_ocp_flash_info *info;
1149 struct pci_dev *pdev = bp->pdev;
1150 struct platform_device *p;
1151 struct resource res[2];
1152 unsigned long start;
1155 start = pci_resource_start(pdev, 0) + r->offset;
1156 ptp_ocp_set_mem_resource(&res[0], start, r->size);
1157 ptp_ocp_set_irq_resource(&res[1], pci_irq_vector(pdev, r->irq_vec));
1160 id = pci_dev_id(pdev) << 1;
1161 id += info->pci_offset;
1163 p = platform_device_register_resndata(&pdev->dev, info->name, id,
1169 bp_assign_entry(bp, r, p);
1174 static struct platform_device *
1175 ptp_ocp_i2c_bus(struct pci_dev *pdev, struct ocp_resource *r, int id)
1177 struct ptp_ocp_i2c_info *info;
1178 struct resource res[2];
1179 unsigned long start;
1182 start = pci_resource_start(pdev, 0) + r->offset;
1183 ptp_ocp_set_mem_resource(&res[0], start, r->size);
1184 ptp_ocp_set_irq_resource(&res[1], pci_irq_vector(pdev, r->irq_vec));
1186 return platform_device_register_resndata(&pdev->dev, info->name,
1188 info->data, info->data_size);
1192 ptp_ocp_register_i2c(struct ptp_ocp *bp, struct ocp_resource *r)
1194 struct pci_dev *pdev = bp->pdev;
1195 struct ptp_ocp_i2c_info *info;
1196 struct platform_device *p;
1202 id = pci_dev_id(bp->pdev);
1204 sprintf(buf, "AXI.%d", id);
1205 clk = clk_hw_register_fixed_rate(&pdev->dev, buf, NULL, 0,
1208 return PTR_ERR(clk);
1211 sprintf(buf, "%s.%d", info->name, id);
1212 devm_clk_hw_register_clkdev(&pdev->dev, clk, NULL, buf);
1213 p = ptp_ocp_i2c_bus(bp->pdev, r, id);
1217 bp_assign_entry(bp, r, p);
1223 ptp_ocp_ts_irq(int irq, void *priv)
1225 struct ptp_ocp_ext_src *ext = priv;
1226 struct ts_reg __iomem *reg = ext->mem;
1227 struct ptp_clock_event ev;
1230 if (ext == ext->bp->pps) {
1231 if (ext->bp->pps_req_map & OCP_REQ_PPS) {
1232 ev.type = PTP_CLOCK_PPS;
1233 ptp_clock_event(ext->bp->ptp, &ev);
1236 if ((ext->bp->pps_req_map & ~OCP_REQ_PPS) == 0)
1240 /* XXX should fix API - this converts s/ns -> ts -> s/ns */
1241 sec = ioread32(®->time_sec);
1242 nsec = ioread32(®->time_ns);
1244 ev.type = PTP_CLOCK_EXTTS;
1245 ev.index = ext->info->index;
1246 ev.timestamp = sec * NSEC_PER_SEC + nsec;
1248 ptp_clock_event(ext->bp->ptp, &ev);
1251 iowrite32(1, ®->intr); /* write 1 to ack */
1257 ptp_ocp_ts_enable(void *priv, u32 req, bool enable)
1259 struct ptp_ocp_ext_src *ext = priv;
1260 struct ts_reg __iomem *reg = ext->mem;
1261 struct ptp_ocp *bp = ext->bp;
1263 if (ext == bp->pps) {
1264 u32 old_map = bp->pps_req_map;
1267 bp->pps_req_map |= req;
1269 bp->pps_req_map &= ~req;
1271 /* if no state change, just return */
1272 if ((!!old_map ^ !!bp->pps_req_map) == 0)
1277 iowrite32(1, ®->enable);
1278 iowrite32(1, ®->intr_mask);
1279 iowrite32(1, ®->intr);
1281 iowrite32(0, ®->intr_mask);
1282 iowrite32(0, ®->enable);
1289 ptp_ocp_unregister_ext(struct ptp_ocp_ext_src *ext)
1291 ext->info->enable(ext, ~0, false);
1292 pci_free_irq(ext->bp->pdev, ext->irq_vec, ext);
1297 ptp_ocp_register_ext(struct ptp_ocp *bp, struct ocp_resource *r)
1299 struct pci_dev *pdev = bp->pdev;
1300 struct ptp_ocp_ext_src *ext;
1303 ext = kzalloc(sizeof(*ext), GFP_KERNEL);
1307 ext->mem = ptp_ocp_get_mem(bp, r);
1308 if (IS_ERR(ext->mem)) {
1309 err = PTR_ERR(ext->mem);
1314 ext->info = r->extra;
1315 ext->irq_vec = r->irq_vec;
1317 err = pci_request_irq(pdev, r->irq_vec, ext->info->irq_fcn, NULL,
1318 ext, "ocp%d.%s", bp->id, r->name);
1320 dev_err(&pdev->dev, "Could not get irq %d\n", r->irq_vec);
1324 bp_assign_entry(bp, r, ext);
1334 ptp_ocp_serial_line(struct ptp_ocp *bp, struct ocp_resource *r)
1336 struct pci_dev *pdev = bp->pdev;
1337 struct uart_8250_port uart;
1339 /* Setting UPF_IOREMAP and leaving port.membase unspecified lets
1340 * the serial port device claim and release the pci resource.
1342 memset(&uart, 0, sizeof(uart));
1343 uart.port.dev = &pdev->dev;
1344 uart.port.iotype = UPIO_MEM;
1345 uart.port.regshift = 2;
1346 uart.port.mapbase = pci_resource_start(pdev, 0) + r->offset;
1347 uart.port.irq = pci_irq_vector(pdev, r->irq_vec);
1348 uart.port.uartclk = 50000000;
1349 uart.port.flags = UPF_FIXED_TYPE | UPF_IOREMAP;
1350 uart.port.type = PORT_16550A;
1352 return serial8250_register_8250_port(&uart);
1356 ptp_ocp_register_serial(struct ptp_ocp *bp, struct ocp_resource *r)
1360 port = ptp_ocp_serial_line(bp, r);
1364 bp_assign_entry(bp, r, port);
1370 ptp_ocp_register_mem(struct ptp_ocp *bp, struct ocp_resource *r)
1374 mem = ptp_ocp_get_mem(bp, r);
1376 return PTR_ERR(mem);
1378 bp_assign_entry(bp, r, mem);
1384 ptp_ocp_nmea_out_init(struct ptp_ocp *bp)
1389 iowrite32(0, &bp->nmea_out->ctrl); /* disable */
1390 iowrite32(7, &bp->nmea_out->uart_baud); /* 115200 */
1391 iowrite32(1, &bp->nmea_out->ctrl); /* enable */
1394 /* FB specific board initializers; last "resource" registered. */
1396 ptp_ocp_fb_board_init(struct ptp_ocp *bp, struct ocp_resource *r)
1398 bp->flash_start = 1024 * 4096;
1400 ptp_ocp_tod_init(bp);
1401 ptp_ocp_nmea_out_init(bp);
1403 return ptp_ocp_init_clock(bp);
1407 ptp_ocp_allow_irq(struct ptp_ocp *bp, struct ocp_resource *r)
1409 bool allow = !r->irq_vec || r->irq_vec < bp->n_irqs;
1412 dev_err(&bp->pdev->dev, "irq %d out of range, skipping %s\n",
1413 r->irq_vec, r->name);
1418 ptp_ocp_register_resources(struct ptp_ocp *bp, kernel_ulong_t driver_data)
1420 struct ocp_resource *r, *table;
1423 table = (struct ocp_resource *)driver_data;
1424 for (r = table; r->setup; r++) {
1425 if (!ptp_ocp_allow_irq(bp, r))
1427 err = r->setup(bp, r);
1429 dev_err(&bp->pdev->dev,
1430 "Could not register %s: err %d\n",
1439 ptp_ocp_enable_fpga(u32 __iomem *reg, u32 bit, bool enable)
1444 ctrl = ioread32(reg);
1448 ctrl |= enable ? bit : 0;
1449 iowrite32(ctrl, reg);
1454 ptp_ocp_irig_out(struct ptp_ocp *bp, bool enable)
1456 return ptp_ocp_enable_fpga(&bp->irig_out->ctrl,
1457 IRIG_M_CTRL_ENABLE, enable);
1461 ptp_ocp_irig_in(struct ptp_ocp *bp, bool enable)
1463 return ptp_ocp_enable_fpga(&bp->irig_in->ctrl,
1464 IRIG_S_CTRL_ENABLE, enable);
1468 ptp_ocp_dcf_out(struct ptp_ocp *bp, bool enable)
1470 return ptp_ocp_enable_fpga(&bp->dcf_out->ctrl,
1471 DCF_M_CTRL_ENABLE, enable);
1475 ptp_ocp_dcf_in(struct ptp_ocp *bp, bool enable)
1477 return ptp_ocp_enable_fpga(&bp->dcf_in->ctrl,
1478 DCF_S_CTRL_ENABLE, enable);
1482 __handle_signal_outputs(struct ptp_ocp *bp, u32 val)
1484 ptp_ocp_irig_out(bp, val & 0x00100010);
1485 ptp_ocp_dcf_out(bp, val & 0x00200020);
1489 __handle_signal_inputs(struct ptp_ocp *bp, u32 val)
1491 ptp_ocp_irig_in(bp, val & 0x00100010);
1492 ptp_ocp_dcf_in(bp, val & 0x00200020);
1499 * ANT3 == sma3 (out)
1500 * ANT4 == sma4 (out)
1503 enum ptp_ocp_sma_mode {
1508 static struct ptp_ocp_sma_connector {
1509 enum ptp_ocp_sma_mode mode;
1511 u16 default_out_idx;
1512 } ptp_ocp_sma_map[4] = {
1514 .mode = SMA_MODE_IN,
1518 .mode = SMA_MODE_IN,
1522 .mode = SMA_MODE_OUT,
1524 .default_out_idx = 0, /* 10Mhz */
1527 .mode = SMA_MODE_OUT,
1529 .default_out_idx = 1, /* PHC */
1534 ptp_ocp_show_output(u32 val, char *buf, int default_idx)
1539 count = sysfs_emit(buf, "OUT: ");
1540 name = ptp_ocp_select_name_from_val(ptp_ocp_sma_out, val);
1542 name = ptp_ocp_sma_out[default_idx].name;
1543 count += sysfs_emit_at(buf, count, "%s\n", name);
1548 ptp_ocp_show_inputs(u32 val, char *buf, const char *zero_in)
1554 count = sysfs_emit(buf, "IN: ");
1555 for (i = 0; i < ARRAY_SIZE(ptp_ocp_sma_in); i++) {
1556 if (val & ptp_ocp_sma_in[i].value) {
1557 name = ptp_ocp_sma_in[i].name;
1558 count += sysfs_emit_at(buf, count, "%s ", name);
1561 if (!val && zero_in)
1562 count += sysfs_emit_at(buf, count, "%s ", zero_in);
1565 count += sysfs_emit_at(buf, count, "\n");
1570 sma_parse_inputs(const char *buf, enum ptp_ocp_sma_mode *mode)
1572 struct ocp_selector *tbl[] = { ptp_ocp_sma_in, ptp_ocp_sma_out };
1573 int idx, count, dir;
1577 argv = argv_split(GFP_KERNEL, buf, &count);
1586 dir = *mode == SMA_MODE_IN ? 0 : 1;
1587 if (!strcasecmp("IN:", argv[idx])) {
1591 if (!strcasecmp("OUT:", argv[0])) {
1595 *mode = dir == 0 ? SMA_MODE_IN : SMA_MODE_OUT;
1598 for (; idx < count; idx++)
1599 ret |= ptp_ocp_select_val_from_name(tbl[dir], argv[idx]);
1609 ptp_ocp_sma_show(struct ptp_ocp *bp, int sma_nr, u32 val, char *buf,
1610 const char *zero_in)
1612 struct ptp_ocp_sma_connector *sma = &ptp_ocp_sma_map[sma_nr - 1];
1614 if (sma->mode == SMA_MODE_IN)
1615 return ptp_ocp_show_inputs(val, buf, zero_in);
1617 return ptp_ocp_show_output(val, buf, sma->default_out_idx);
1621 sma1_show(struct device *dev, struct device_attribute *attr, char *buf)
1623 struct ptp_ocp *bp = dev_get_drvdata(dev);
1626 val = ioread32(&bp->sma->gpio1) & 0x3f;
1627 return ptp_ocp_sma_show(bp, 1, val, buf, ptp_ocp_sma_in[0].name);
1631 sma2_show(struct device *dev, struct device_attribute *attr, char *buf)
1633 struct ptp_ocp *bp = dev_get_drvdata(dev);
1636 val = (ioread32(&bp->sma->gpio1) >> 16) & 0x3f;
1637 return ptp_ocp_sma_show(bp, 2, val, buf, NULL);
1641 sma3_show(struct device *dev, struct device_attribute *attr, char *buf)
1643 struct ptp_ocp *bp = dev_get_drvdata(dev);
1646 val = ioread32(&bp->sma->gpio2) & 0x3f;
1647 return ptp_ocp_sma_show(bp, 3, val, buf, NULL);
1651 sma4_show(struct device *dev, struct device_attribute *attr, char *buf)
1653 struct ptp_ocp *bp = dev_get_drvdata(dev);
1656 val = (ioread32(&bp->sma->gpio2) >> 16) & 0x3f;
1657 return ptp_ocp_sma_show(bp, 4, val, buf, NULL);
1661 ptp_ocp_sma_store_output(struct ptp_ocp *bp, u32 val, u32 shift)
1663 unsigned long flags;
1666 mask = 0xffff << (16 - shift);
1668 spin_lock_irqsave(&bp->lock, flags);
1670 gpio = ioread32(&bp->sma->gpio2);
1671 gpio = (gpio & mask) | (val << shift);
1673 __handle_signal_outputs(bp, gpio);
1675 iowrite32(gpio, &bp->sma->gpio2);
1677 spin_unlock_irqrestore(&bp->lock, flags);
1681 ptp_ocp_sma_store_inputs(struct ptp_ocp *bp, u32 val, u32 shift)
1683 unsigned long flags;
1686 mask = 0xffff << (16 - shift);
1688 spin_lock_irqsave(&bp->lock, flags);
1690 gpio = ioread32(&bp->sma->gpio1);
1691 gpio = (gpio & mask) | (val << shift);
1693 __handle_signal_inputs(bp, gpio);
1695 iowrite32(gpio, &bp->sma->gpio1);
1697 spin_unlock_irqrestore(&bp->lock, flags);
1701 ptp_ocp_sma_store(struct ptp_ocp *bp, const char *buf, int sma_nr, u32 shift)
1703 struct ptp_ocp_sma_connector *sma = &ptp_ocp_sma_map[sma_nr - 1];
1704 enum ptp_ocp_sma_mode mode;
1708 val = sma_parse_inputs(buf, &mode);
1712 if (mode != sma->mode && sma->fixed_mode)
1715 if (mode != sma->mode) {
1716 pr_err("Mode changes not supported yet.\n");
1720 if (sma->mode == SMA_MODE_IN)
1721 ptp_ocp_sma_store_inputs(bp, val, shift);
1723 ptp_ocp_sma_store_output(bp, val, shift);
1729 sma1_store(struct device *dev, struct device_attribute *attr,
1730 const char *buf, size_t count)
1732 struct ptp_ocp *bp = dev_get_drvdata(dev);
1735 err = ptp_ocp_sma_store(bp, buf, 1, 0);
1736 return err ? err : count;
1740 sma2_store(struct device *dev, struct device_attribute *attr,
1741 const char *buf, size_t count)
1743 struct ptp_ocp *bp = dev_get_drvdata(dev);
1746 err = ptp_ocp_sma_store(bp, buf, 2, 16);
1747 return err ? err : count;
1751 sma3_store(struct device *dev, struct device_attribute *attr,
1752 const char *buf, size_t count)
1754 struct ptp_ocp *bp = dev_get_drvdata(dev);
1757 err = ptp_ocp_sma_store(bp, buf, 3, 0);
1758 return err ? err : count;
1762 sma4_store(struct device *dev, struct device_attribute *attr,
1763 const char *buf, size_t count)
1765 struct ptp_ocp *bp = dev_get_drvdata(dev);
1768 err = ptp_ocp_sma_store(bp, buf, 4, 16);
1769 return err ? err : count;
1771 static DEVICE_ATTR_RW(sma1);
1772 static DEVICE_ATTR_RW(sma2);
1773 static DEVICE_ATTR_RW(sma3);
1774 static DEVICE_ATTR_RW(sma4);
1777 available_sma_inputs_show(struct device *dev,
1778 struct device_attribute *attr, char *buf)
1780 return ptp_ocp_select_table_show(ptp_ocp_sma_in, buf);
1782 static DEVICE_ATTR_RO(available_sma_inputs);
1785 available_sma_outputs_show(struct device *dev,
1786 struct device_attribute *attr, char *buf)
1788 return ptp_ocp_select_table_show(ptp_ocp_sma_out, buf);
1790 static DEVICE_ATTR_RO(available_sma_outputs);
1793 serialnum_show(struct device *dev, struct device_attribute *attr, char *buf)
1795 struct ptp_ocp *bp = dev_get_drvdata(dev);
1797 if (!bp->has_serial)
1798 ptp_ocp_get_serial_number(bp);
1800 return sysfs_emit(buf, "%pM\n", bp->serial);
1802 static DEVICE_ATTR_RO(serialnum);
1805 gnss_sync_show(struct device *dev, struct device_attribute *attr, char *buf)
1807 struct ptp_ocp *bp = dev_get_drvdata(dev);
1811 ret = sysfs_emit(buf, "LOST @ %ptT\n", &bp->gnss_lost);
1813 ret = sysfs_emit(buf, "SYNC\n");
1817 static DEVICE_ATTR_RO(gnss_sync);
1820 utc_tai_offset_show(struct device *dev,
1821 struct device_attribute *attr, char *buf)
1823 struct ptp_ocp *bp = dev_get_drvdata(dev);
1825 return sysfs_emit(buf, "%d\n", bp->utc_tai_offset);
1829 utc_tai_offset_store(struct device *dev,
1830 struct device_attribute *attr,
1831 const char *buf, size_t count)
1833 struct ptp_ocp *bp = dev_get_drvdata(dev);
1837 err = kstrtou32(buf, 0, &val);
1841 ptp_ocp_utc_distribute(bp, val);
1845 static DEVICE_ATTR_RW(utc_tai_offset);
1848 ts_window_adjust_show(struct device *dev,
1849 struct device_attribute *attr, char *buf)
1851 struct ptp_ocp *bp = dev_get_drvdata(dev);
1853 return sysfs_emit(buf, "%d\n", bp->ts_window_adjust);
1857 ts_window_adjust_store(struct device *dev,
1858 struct device_attribute *attr,
1859 const char *buf, size_t count)
1861 struct ptp_ocp *bp = dev_get_drvdata(dev);
1865 err = kstrtou32(buf, 0, &val);
1869 bp->ts_window_adjust = val;
1873 static DEVICE_ATTR_RW(ts_window_adjust);
1876 irig_b_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1878 struct ptp_ocp *bp = dev_get_drvdata(dev);
1881 val = ioread32(&bp->irig_out->ctrl);
1882 val = (val >> 16) & 0x07;
1883 return sysfs_emit(buf, "%d\n", val);
1887 irig_b_mode_store(struct device *dev,
1888 struct device_attribute *attr,
1889 const char *buf, size_t count)
1891 struct ptp_ocp *bp = dev_get_drvdata(dev);
1892 unsigned long flags;
1897 err = kstrtou8(buf, 0, &val);
1903 reg = ((val & 0x7) << 16);
1905 spin_lock_irqsave(&bp->lock, flags);
1906 iowrite32(0, &bp->irig_out->ctrl); /* disable */
1907 iowrite32(reg, &bp->irig_out->ctrl); /* change mode */
1908 iowrite32(reg | IRIG_M_CTRL_ENABLE, &bp->irig_out->ctrl);
1909 spin_unlock_irqrestore(&bp->lock, flags);
1913 static DEVICE_ATTR_RW(irig_b_mode);
1916 clock_source_show(struct device *dev, struct device_attribute *attr, char *buf)
1918 struct ptp_ocp *bp = dev_get_drvdata(dev);
1922 select = ioread32(&bp->reg->select);
1923 p = ptp_ocp_select_name_from_val(ptp_ocp_clock, select >> 16);
1925 return sysfs_emit(buf, "%s\n", p);
1929 clock_source_store(struct device *dev, struct device_attribute *attr,
1930 const char *buf, size_t count)
1932 struct ptp_ocp *bp = dev_get_drvdata(dev);
1933 unsigned long flags;
1936 val = ptp_ocp_select_val_from_name(ptp_ocp_clock, buf);
1940 spin_lock_irqsave(&bp->lock, flags);
1941 iowrite32(val, &bp->reg->select);
1942 spin_unlock_irqrestore(&bp->lock, flags);
1946 static DEVICE_ATTR_RW(clock_source);
1949 available_clock_sources_show(struct device *dev,
1950 struct device_attribute *attr, char *buf)
1952 return ptp_ocp_select_table_show(ptp_ocp_clock, buf);
1954 static DEVICE_ATTR_RO(available_clock_sources);
1956 static struct attribute *timecard_attrs[] = {
1957 &dev_attr_serialnum.attr,
1958 &dev_attr_gnss_sync.attr,
1959 &dev_attr_clock_source.attr,
1960 &dev_attr_available_clock_sources.attr,
1961 &dev_attr_sma1.attr,
1962 &dev_attr_sma2.attr,
1963 &dev_attr_sma3.attr,
1964 &dev_attr_sma4.attr,
1965 &dev_attr_available_sma_inputs.attr,
1966 &dev_attr_available_sma_outputs.attr,
1967 &dev_attr_irig_b_mode.attr,
1968 &dev_attr_utc_tai_offset.attr,
1969 &dev_attr_ts_window_adjust.attr,
1972 ATTRIBUTE_GROUPS(timecard);
1975 gpio_map(u32 gpio, u32 bit, const char *pri, const char *sec, const char *def)
1979 if (gpio & (1 << bit))
1981 else if (gpio & (1 << (bit + 16)))
1989 gpio_multi_map(char *buf, u32 gpio, u32 bit,
1990 const char *pri, const char *sec, const char *def)
1995 if (gpio & (1 << bit))
1996 ans += sprintf(ans, "%s ", pri);
1997 if (gpio & (1 << (bit + 16)))
1998 ans += sprintf(ans, "%s ", sec);
2002 ptp_ocp_summary_show(struct seq_file *s, void *data)
2004 struct device *dev = s->private;
2005 struct ptp_system_timestamp sts;
2006 u32 sma_in, sma_out, ctrl, val;
2007 struct ts_reg __iomem *ts_reg;
2008 struct timespec64 ts;
2014 buf = (char *)__get_free_page(GFP_KERNEL);
2018 bp = dev_get_drvdata(dev);
2019 sma_in = ioread32(&bp->sma->gpio1);
2020 sma_out = ioread32(&bp->sma->gpio2);
2022 seq_printf(s, "%7s: /dev/ptp%d\n", "PTP", ptp_clock_index(bp->ptp));
2024 sma1_show(dev, NULL, buf);
2025 seq_printf(s, " sma1: %s", buf);
2027 sma2_show(dev, NULL, buf);
2028 seq_printf(s, " sma2: %s", buf);
2030 sma3_show(dev, NULL, buf);
2031 seq_printf(s, " sma3: %s", buf);
2033 sma4_show(dev, NULL, buf);
2034 seq_printf(s, " sma4: %s", buf);
2037 ts_reg = bp->ts0->mem;
2038 on = ioread32(&ts_reg->enable);
2040 seq_printf(s, "%7s: %s, src: %s\n", "TS0",
2041 on ? " ON" : "OFF", src);
2045 ts_reg = bp->ts1->mem;
2046 on = ioread32(&ts_reg->enable);
2047 src = gpio_map(sma_in, 2, "sma1", "sma2", "----");
2048 seq_printf(s, "%7s: %s, src: %s\n", "TS1",
2049 on ? " ON" : "OFF", src);
2053 ts_reg = bp->ts2->mem;
2054 on = ioread32(&ts_reg->enable);
2055 src = gpio_map(sma_in, 3, "sma1", "sma2", "----");
2056 seq_printf(s, "%7s: %s, src: %s\n", "TS2",
2057 on ? " ON" : "OFF", src);
2061 ts_reg = bp->pps->mem;
2063 on = ioread32(&ts_reg->enable);
2064 map = !!(bp->pps_req_map & OCP_REQ_TIMESTAMP);
2065 seq_printf(s, "%7s: %s, src: %s\n", "TS3",
2066 on && map ? " ON" : "OFF", src);
2068 map = !!(bp->pps_req_map & OCP_REQ_PPS);
2069 seq_printf(s, "%7s: %s, src: %s\n", "PPS",
2070 on && map ? " ON" : "OFF", src);
2074 ctrl = ioread32(&bp->irig_out->ctrl);
2075 on = ctrl & IRIG_M_CTRL_ENABLE;
2076 val = ioread32(&bp->irig_out->status);
2077 gpio_multi_map(buf, sma_out, 4, "sma3", "sma4", "----");
2078 seq_printf(s, "%7s: %s, error: %d, mode %d, out: %s\n", "IRIG",
2079 on ? " ON" : "OFF", val, (ctrl >> 16), buf);
2083 on = ioread32(&bp->irig_in->ctrl) & IRIG_S_CTRL_ENABLE;
2084 val = ioread32(&bp->irig_in->status);
2085 src = gpio_map(sma_in, 4, "sma1", "sma2", "----");
2086 seq_printf(s, "%7s: %s, error: %d, src: %s\n", "IRIG in",
2087 on ? " ON" : "OFF", val, src);
2091 on = ioread32(&bp->dcf_out->ctrl) & DCF_M_CTRL_ENABLE;
2092 val = ioread32(&bp->dcf_out->status);
2093 gpio_multi_map(buf, sma_out, 5, "sma3", "sma4", "----");
2094 seq_printf(s, "%7s: %s, error: %d, out: %s\n", "DCF",
2095 on ? " ON" : "OFF", val, buf);
2099 on = ioread32(&bp->dcf_in->ctrl) & DCF_S_CTRL_ENABLE;
2100 val = ioread32(&bp->dcf_in->status);
2101 src = gpio_map(sma_in, 5, "sma1", "sma2", "----");
2102 seq_printf(s, "%7s: %s, error: %d, src: %s\n", "DCF in",
2103 on ? " ON" : "OFF", val, src);
2107 on = ioread32(&bp->nmea_out->ctrl) & 1;
2108 val = ioread32(&bp->nmea_out->status);
2109 seq_printf(s, "%7s: %s, error: %d\n", "NMEA",
2110 on ? " ON" : "OFF", val);
2113 /* compute src for PPS1, used below. */
2114 if (bp->pps_select) {
2115 val = ioread32(&bp->pps_select->gpio1);
2117 src = gpio_map(sma_in, 0, "sma1", "sma2", "----");
2118 else if (val & 0x02)
2120 else if (val & 0x04)
2128 /* assumes automatic switchover/selection */
2129 val = ioread32(&bp->reg->select);
2130 switch (val >> 16) {
2132 sprintf(buf, "----");
2135 sprintf(buf, "IRIG");
2138 sprintf(buf, "%s via PPS1", src);
2141 sprintf(buf, "DCF");
2144 strcpy(buf, "unknown");
2147 val = ioread32(&bp->reg->status);
2148 seq_printf(s, "%7s: %s, state: %s\n", "PHC src", buf,
2149 val & OCP_STATUS_IN_SYNC ? "sync" : "unsynced");
2151 /* reuses PPS1 src from earlier */
2152 seq_printf(s, "MAC PPS1 src: %s\n", src);
2154 src = gpio_map(sma_in, 1, "sma1", "sma2", "GNSS2");
2155 seq_printf(s, "MAC PPS2 src: %s\n", src);
2157 if (!ptp_ocp_gettimex(&bp->ptp_info, &ts, &sts)) {
2158 struct timespec64 sys_ts;
2159 s64 pre_ns, post_ns, ns;
2161 pre_ns = timespec64_to_ns(&sts.pre_ts);
2162 post_ns = timespec64_to_ns(&sts.post_ts);
2163 ns = (pre_ns + post_ns) / 2;
2164 ns += (s64)bp->utc_tai_offset * NSEC_PER_SEC;
2165 sys_ts = ns_to_timespec64(ns);
2167 seq_printf(s, "%7s: %lld.%ld == %ptT TAI\n", "PHC",
2168 ts.tv_sec, ts.tv_nsec, &ts);
2169 seq_printf(s, "%7s: %lld.%ld == %ptT UTC offset %d\n", "SYS",
2170 sys_ts.tv_sec, sys_ts.tv_nsec, &sys_ts,
2171 bp->utc_tai_offset);
2172 seq_printf(s, "%7s: PHC:SYS offset: %lld window: %lld\n", "",
2173 timespec64_to_ns(&ts) - ns,
2177 free_page((unsigned long)buf);
2180 DEFINE_SHOW_ATTRIBUTE(ptp_ocp_summary);
2182 static struct dentry *ptp_ocp_debugfs_root;
2185 ptp_ocp_debugfs_add_device(struct ptp_ocp *bp)
2189 d = debugfs_create_dir(dev_name(&bp->dev), ptp_ocp_debugfs_root);
2191 debugfs_create_file("summary", 0444, bp->debug_root,
2192 &bp->dev, &ptp_ocp_summary_fops);
2196 ptp_ocp_debugfs_remove_device(struct ptp_ocp *bp)
2198 debugfs_remove_recursive(bp->debug_root);
2202 ptp_ocp_debugfs_init(void)
2204 ptp_ocp_debugfs_root = debugfs_create_dir("timecard", NULL);
2208 ptp_ocp_debugfs_fini(void)
2210 debugfs_remove_recursive(ptp_ocp_debugfs_root);
2214 ptp_ocp_dev_release(struct device *dev)
2216 struct ptp_ocp *bp = dev_get_drvdata(dev);
2218 mutex_lock(&ptp_ocp_lock);
2219 idr_remove(&ptp_ocp_idr, bp->id);
2220 mutex_unlock(&ptp_ocp_lock);
2224 ptp_ocp_device_init(struct ptp_ocp *bp, struct pci_dev *pdev)
2228 mutex_lock(&ptp_ocp_lock);
2229 err = idr_alloc(&ptp_ocp_idr, bp, 0, 0, GFP_KERNEL);
2230 mutex_unlock(&ptp_ocp_lock);
2232 dev_err(&pdev->dev, "idr_alloc failed: %d\n", err);
2237 bp->ptp_info = ptp_ocp_clock_info;
2238 spin_lock_init(&bp->lock);
2240 bp->gnss2_port = -1;
2245 device_initialize(&bp->dev);
2246 dev_set_name(&bp->dev, "ocp%d", bp->id);
2247 bp->dev.class = &timecard_class;
2248 bp->dev.parent = &pdev->dev;
2249 bp->dev.release = ptp_ocp_dev_release;
2250 dev_set_drvdata(&bp->dev, bp);
2252 err = device_add(&bp->dev);
2254 dev_err(&bp->dev, "device add failed: %d\n", err);
2258 pci_set_drvdata(pdev, bp);
2263 ptp_ocp_dev_release(&bp->dev);
2264 put_device(&bp->dev);
2269 ptp_ocp_symlink(struct ptp_ocp *bp, struct device *child, const char *link)
2271 struct device *dev = &bp->dev;
2273 if (sysfs_create_link(&dev->kobj, &child->kobj, link))
2274 dev_err(dev, "%s symlink failed\n", link);
2278 ptp_ocp_link_child(struct ptp_ocp *bp, const char *name, const char *link)
2280 struct device *dev, *child;
2282 dev = &bp->pdev->dev;
2284 child = device_find_child_by_name(dev, name);
2286 dev_err(dev, "Could not find device %s\n", name);
2290 ptp_ocp_symlink(bp, child, link);
2295 ptp_ocp_complete(struct ptp_ocp *bp)
2297 struct pps_device *pps;
2300 if (bp->gnss_port != -1) {
2301 sprintf(buf, "ttyS%d", bp->gnss_port);
2302 ptp_ocp_link_child(bp, buf, "ttyGNSS");
2304 if (bp->gnss2_port != -1) {
2305 sprintf(buf, "ttyS%d", bp->gnss2_port);
2306 ptp_ocp_link_child(bp, buf, "ttyGNSS2");
2308 if (bp->mac_port != -1) {
2309 sprintf(buf, "ttyS%d", bp->mac_port);
2310 ptp_ocp_link_child(bp, buf, "ttyMAC");
2312 if (bp->nmea_port != -1) {
2313 sprintf(buf, "ttyS%d", bp->nmea_port);
2314 ptp_ocp_link_child(bp, buf, "ttyNMEA");
2316 sprintf(buf, "ptp%d", ptp_clock_index(bp->ptp));
2317 ptp_ocp_link_child(bp, buf, "ptp");
2319 pps = pps_lookup_dev(bp->ptp);
2321 ptp_ocp_symlink(bp, pps->dev, "pps");
2323 if (device_add_groups(&bp->dev, timecard_groups))
2324 pr_err("device add groups failed\n");
2326 ptp_ocp_debugfs_add_device(bp);
2332 ptp_ocp_phc_info(struct ptp_ocp *bp)
2334 struct timespec64 ts;
2335 u32 version, select;
2338 version = ioread32(&bp->reg->version);
2339 select = ioread32(&bp->reg->select);
2340 dev_info(&bp->pdev->dev, "Version %d.%d.%d, clock %s, device ptp%d\n",
2341 version >> 24, (version >> 16) & 0xff, version & 0xffff,
2342 ptp_ocp_select_name_from_val(ptp_ocp_clock, select >> 16),
2343 ptp_clock_index(bp->ptp));
2345 sync = ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC;
2346 if (!ptp_ocp_gettimex(&bp->ptp_info, &ts, NULL))
2347 dev_info(&bp->pdev->dev, "Time: %lld.%ld, %s\n",
2348 ts.tv_sec, ts.tv_nsec,
2349 sync ? "in-sync" : "UNSYNCED");
2353 ptp_ocp_serial_info(struct device *dev, const char *name, int port, int baud)
2356 dev_info(dev, "%5s: /dev/ttyS%-2d @ %6d\n", name, port, baud);
2360 ptp_ocp_info(struct ptp_ocp *bp)
2362 static int nmea_baud[] = {
2363 1200, 2400, 4800, 9600, 19200, 38400,
2364 57600, 115200, 230400, 460800, 921600,
2367 struct device *dev = &bp->pdev->dev;
2370 ptp_ocp_phc_info(bp);
2372 ptp_ocp_tod_info(bp);
2375 u32 ver = ioread32(&bp->image->version);
2377 dev_info(dev, "version %x\n", ver);
2379 dev_info(dev, "regular image, version %d\n",
2382 dev_info(dev, "golden image, version %d\n",
2385 ptp_ocp_serial_info(dev, "GNSS", bp->gnss_port, 115200);
2386 ptp_ocp_serial_info(dev, "GNSS2", bp->gnss2_port, 115200);
2387 ptp_ocp_serial_info(dev, "MAC", bp->mac_port, 57600);
2388 if (bp->nmea_out && bp->nmea_port != -1) {
2391 reg = ioread32(&bp->nmea_out->uart_baud);
2392 if (reg < ARRAY_SIZE(nmea_baud))
2393 baud = nmea_baud[reg];
2394 ptp_ocp_serial_info(dev, "NMEA", bp->nmea_port, baud);
2399 ptp_ocp_detach_sysfs(struct ptp_ocp *bp)
2401 struct device *dev = &bp->dev;
2403 sysfs_remove_link(&dev->kobj, "ttyGNSS");
2404 sysfs_remove_link(&dev->kobj, "ttyMAC");
2405 sysfs_remove_link(&dev->kobj, "ptp");
2406 sysfs_remove_link(&dev->kobj, "pps");
2407 device_remove_groups(dev, timecard_groups);
2411 ptp_ocp_detach(struct ptp_ocp *bp)
2413 ptp_ocp_debugfs_remove_device(bp);
2414 ptp_ocp_detach_sysfs(bp);
2415 if (timer_pending(&bp->watchdog))
2416 del_timer_sync(&bp->watchdog);
2418 ptp_ocp_unregister_ext(bp->ts0);
2420 ptp_ocp_unregister_ext(bp->ts1);
2422 ptp_ocp_unregister_ext(bp->ts2);
2424 ptp_ocp_unregister_ext(bp->pps);
2425 if (bp->gnss_port != -1)
2426 serial8250_unregister_port(bp->gnss_port);
2427 if (bp->gnss2_port != -1)
2428 serial8250_unregister_port(bp->gnss2_port);
2429 if (bp->mac_port != -1)
2430 serial8250_unregister_port(bp->mac_port);
2431 if (bp->nmea_port != -1)
2432 serial8250_unregister_port(bp->nmea_port);
2434 platform_device_unregister(bp->spi_flash);
2436 platform_device_unregister(bp->i2c_ctrl);
2438 clk_hw_unregister_fixed_rate(bp->i2c_clk);
2440 pci_free_irq_vectors(bp->pdev);
2442 ptp_clock_unregister(bp->ptp);
2443 device_unregister(&bp->dev);
2447 ptp_ocp_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2449 struct devlink *devlink;
2453 devlink = devlink_alloc(&ptp_ocp_devlink_ops, sizeof(*bp), &pdev->dev);
2455 dev_err(&pdev->dev, "devlink_alloc failed\n");
2459 err = pci_enable_device(pdev);
2461 dev_err(&pdev->dev, "pci_enable_device\n");
2462 goto out_unregister;
2465 bp = devlink_priv(devlink);
2466 err = ptp_ocp_device_init(bp, pdev);
2471 * Older FPGA firmware only returns 2 irq's.
2472 * allow this - if not all of the IRQ's are returned, skip the
2473 * extra devices and just register the clock.
2475 err = pci_alloc_irq_vectors(pdev, 1, 11, PCI_IRQ_MSI | PCI_IRQ_MSIX);
2477 dev_err(&pdev->dev, "alloc_irq_vectors err: %d\n", err);
2481 pci_set_master(pdev);
2483 err = ptp_ocp_register_resources(bp, id->driver_data);
2487 bp->ptp = ptp_clock_register(&bp->ptp_info, &pdev->dev);
2488 if (IS_ERR(bp->ptp)) {
2489 err = PTR_ERR(bp->ptp);
2490 dev_err(&pdev->dev, "ptp_clock_register: %d\n", err);
2495 err = ptp_ocp_complete(bp);
2500 devlink_register(devlink);
2505 pci_set_drvdata(pdev, NULL);
2507 pci_disable_device(pdev);
2509 devlink_free(devlink);
2514 ptp_ocp_remove(struct pci_dev *pdev)
2516 struct ptp_ocp *bp = pci_get_drvdata(pdev);
2517 struct devlink *devlink = priv_to_devlink(bp);
2519 devlink_unregister(devlink);
2521 pci_set_drvdata(pdev, NULL);
2522 pci_disable_device(pdev);
2524 devlink_free(devlink);
2527 static struct pci_driver ptp_ocp_driver = {
2528 .name = KBUILD_MODNAME,
2529 .id_table = ptp_ocp_pcidev_id,
2530 .probe = ptp_ocp_probe,
2531 .remove = ptp_ocp_remove,
2535 ptp_ocp_i2c_notifier_call(struct notifier_block *nb,
2536 unsigned long action, void *data)
2538 struct device *dev, *child = data;
2543 case BUS_NOTIFY_ADD_DEVICE:
2544 case BUS_NOTIFY_DEL_DEVICE:
2545 add = action == BUS_NOTIFY_ADD_DEVICE;
2551 if (!i2c_verify_adapter(child))
2555 while ((dev = dev->parent))
2556 if (dev->driver && !strcmp(dev->driver->name, KBUILD_MODNAME))
2561 bp = dev_get_drvdata(dev);
2563 ptp_ocp_symlink(bp, child, "i2c");
2565 sysfs_remove_link(&bp->dev.kobj, "i2c");
2570 static struct notifier_block ptp_ocp_i2c_notifier = {
2571 .notifier_call = ptp_ocp_i2c_notifier_call,
2580 ptp_ocp_debugfs_init();
2582 what = "timecard class";
2583 err = class_register(&timecard_class);
2587 what = "i2c notifier";
2588 err = bus_register_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
2592 what = "ptp_ocp driver";
2593 err = pci_register_driver(&ptp_ocp_driver);
2600 bus_unregister_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
2602 class_unregister(&timecard_class);
2604 ptp_ocp_debugfs_fini();
2605 pr_err(KBUILD_MODNAME ": failed to register %s: %d\n", what, err);
2612 bus_unregister_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
2613 pci_unregister_driver(&ptp_ocp_driver);
2614 class_unregister(&timecard_class);
2615 ptp_ocp_debugfs_fini();
2618 module_init(ptp_ocp_init);
2619 module_exit(ptp_ocp_fini);
2621 MODULE_DESCRIPTION("OpenCompute TimeCard driver");
2622 MODULE_LICENSE("GPL v2");