drivers/pwm/pwm-lpss.c

   1 /*
   2  * Intel Low Power Subsystem PWM controller driver
   3  *
   4  * Copyright (C) 2014, Intel Corporation
   5  * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
   6  * Author: Chew Kean Ho <kean.ho.chew@intel.com>
   7  * Author: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
   8  * Author: Chew Chiau Ee <chiau.ee.chew@intel.com>
   9  * Author: Alan Cox <alan@linux.intel.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include <linux/delay.h>
  17 #include <linux/io.h>
  18 #include <linux/iopoll.h>
  19 #include <linux/kernel.h>
  20 #include <linux/module.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/time.h>
  23
  24 #include "pwm-lpss.h"
  25
  26 #define PWM                             0x00000000
  27 #define PWM_ENABLE                      BIT(31)
  28 #define PWM_SW_UPDATE                   BIT(30)
  29 #define PWM_BASE_UNIT_SHIFT             8
  30 #define PWM_ON_TIME_DIV_MASK            0x000000ff
  31
  32 /* Size of each PWM register space if multiple */
  33 #define PWM_SIZE                        0x400
  34
  35 static inline struct pwm_lpss_chip *to_lpwm(struct pwm_chip *chip)
  36 {
  37         return container_of(chip, struct pwm_lpss_chip, chip);
  38 }
  39
  40 static inline u32 pwm_lpss_read(const struct pwm_device *pwm)
  41 {
  42         struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
  43
  44         return readl(lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
  45 }
  46
  47 static inline void pwm_lpss_write(const struct pwm_device *pwm, u32 value)
  48 {
  49         struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
  50
  51         writel(value, lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
  52 }
  53
  54 static int pwm_lpss_wait_for_update(struct pwm_device *pwm)
  55 {
  56         struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
  57         const void __iomem *addr = lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM;
  58         const unsigned int ms = 500 * USEC_PER_MSEC;
  59         u32 val;
  60         int err;
  61
  62         /*
  63          * PWM Configuration register has SW_UPDATE bit that is set when a new
  64          * configuration is written to the register. The bit is automatically
  65          * cleared at the start of the next output cycle by the IP block.
  66          *
  67          * If one writes a new configuration to the register while it still has
  68          * the bit enabled, PWM may freeze. That is, while one can still write
  69          * to the register, it won't have an effect. Thus, we try to sleep long
  70          * enough that the bit gets cleared and make sure the bit is not
  71          * enabled while we update the configuration.
  72          */
  73         err = readl_poll_timeout(addr, val, !(val & PWM_SW_UPDATE), 40, ms);
  74         if (err)
  75                 dev_err(pwm->chip->dev, "PWM_SW_UPDATE was not cleared\n");
  76
  77         return err;
  78 }
  79
  80 static inline int pwm_lpss_is_updating(struct pwm_device *pwm)
  81 {
  82         return (pwm_lpss_read(pwm) & PWM_SW_UPDATE) ? -EBUSY : 0;
  83 }
  84
  85 static void pwm_lpss_prepare(struct pwm_lpss_chip *lpwm, struct pwm_device *pwm,
  86                              int duty_ns, int period_ns)
  87 {
  88         unsigned long long on_time_div;
  89         unsigned long c = lpwm->info->clk_rate, base_unit_range;
  90         unsigned long long base_unit, freq = NSEC_PER_SEC;
  91         u32 ctrl;
  92
  93         do_div(freq, period_ns);
  94
  95         /*
  96          * The equation is:
  97          * base_unit = round(base_unit_range * freq / c)
  98          */
  99         base_unit_range = BIT(lpwm->info->base_unit_bits) - 1;
 100         freq *= base_unit_range;
 101
 102         base_unit = DIV_ROUND_CLOSEST_ULL(freq, c);
 103
 104         on_time_div = 255ULL * duty_ns;
 105         do_div(on_time_div, period_ns);
 106         on_time_div = 255ULL - on_time_div;
 107
 108         ctrl = pwm_lpss_read(pwm);
 109         ctrl &= ~PWM_ON_TIME_DIV_MASK;
 110         ctrl &= ~(base_unit_range << PWM_BASE_UNIT_SHIFT);
 111         base_unit &= base_unit_range;
 112         ctrl |= (u32) base_unit << PWM_BASE_UNIT_SHIFT;
 113         ctrl |= on_time_div;
 114         pwm_lpss_write(pwm, ctrl);
 115 }
 116
 117 static inline void pwm_lpss_cond_enable(struct pwm_device *pwm, bool cond)
 118 {
 119         if (cond)
 120                 pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_ENABLE);
 121 }
 122
 123 static int pwm_lpss_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 124                           struct pwm_state *state)
 125 {
 126         struct pwm_lpss_chip *lpwm = to_lpwm(chip);
 127         int ret;
 128
 129         if (state->enabled) {
 130                 if (!pwm_is_enabled(pwm)) {
 131                         pm_runtime_get_sync(chip->dev);
 132                         ret = pwm_lpss_is_updating(pwm);
 133                         if (ret) {
 134                                 pm_runtime_put(chip->dev);
 135                                 return ret;
 136                         }
 137                         pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, state->period);
 138                         pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_SW_UPDATE);
 139                         pwm_lpss_cond_enable(pwm, lpwm->info->bypass == false);
 140                         ret = pwm_lpss_wait_for_update(pwm);
 141                         if (ret) {
 142                                 pm_runtime_put(chip->dev);
 143                                 return ret;
 144                         }
 145                         pwm_lpss_cond_enable(pwm, lpwm->info->bypass == true);
 146                 } else {
 147                         ret = pwm_lpss_is_updating(pwm);
 148                         if (ret)
 149                                 return ret;
 150                         pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, state->period);
 151                         pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_SW_UPDATE);
 152                         return pwm_lpss_wait_for_update(pwm);
 153                 }
 154         } else if (pwm_is_enabled(pwm)) {
 155                 pwm_lpss_write(pwm, pwm_lpss_read(pwm) & ~PWM_ENABLE);
 156                 pm_runtime_put(chip->dev);
 157         }
 158
 159         return 0;
 160 }
 161
 162 /* This function gets called once from pwmchip_add to get the initial state */
 163 static void pwm_lpss_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
 164                                struct pwm_state *state)
 165 {
 166         struct pwm_lpss_chip *lpwm = to_lpwm(chip);
 167         unsigned long base_unit_range;
 168         unsigned long long base_unit, freq, on_time_div;
 169         u32 ctrl;
 170
 171         base_unit_range = BIT(lpwm->info->base_unit_bits);
 172
 173         ctrl = pwm_lpss_read(pwm);
 174         on_time_div = 255 - (ctrl & PWM_ON_TIME_DIV_MASK);
 175         base_unit = (ctrl >> PWM_BASE_UNIT_SHIFT) & (base_unit_range - 1);
 176
 177         freq = base_unit * lpwm->info->clk_rate;
 178         do_div(freq, base_unit_range);
 179         if (freq == 0)
 180                 state->period = NSEC_PER_SEC;
 181         else
 182                 state->period = NSEC_PER_SEC / (unsigned long)freq;
 183
 184         on_time_div *= state->period;
 185         do_div(on_time_div, 255);
 186         state->duty_cycle = on_time_div;
 187
 188         state->polarity = PWM_POLARITY_NORMAL;
 189         state->enabled = !!(ctrl & PWM_ENABLE);
 190
 191         if (state->enabled)
 192                 pm_runtime_get(chip->dev);
 193 }
 194
 195 static const struct pwm_ops pwm_lpss_ops = {
 196         .apply = pwm_lpss_apply,
 197         .get_state = pwm_lpss_get_state,
 198         .owner = THIS_MODULE,
 199 };
 200
 201 struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, struct resource *r,
 202                                      const struct pwm_lpss_boardinfo *info)
 203 {
 204         struct pwm_lpss_chip *lpwm;
 205         unsigned long c;
 206         int ret;
 207
 208         if (WARN_ON(info->npwm > MAX_PWMS))
 209                 return ERR_PTR(-ENODEV);
 210
 211         lpwm = devm_kzalloc(dev, sizeof(*lpwm), GFP_KERNEL);
 212         if (!lpwm)
 213                 return ERR_PTR(-ENOMEM);
 214
 215         lpwm->regs = devm_ioremap_resource(dev, r);
 216         if (IS_ERR(lpwm->regs))
 217                 return ERR_CAST(lpwm->regs);
 218
 219         lpwm->info = info;
 220
 221         c = lpwm->info->clk_rate;
 222         if (!c)
 223                 return ERR_PTR(-EINVAL);
 224
 225         lpwm->chip.dev = dev;
 226         lpwm->chip.ops = &pwm_lpss_ops;
 227         lpwm->chip.base = -1;
 228         lpwm->chip.npwm = info->npwm;
 229
 230         ret = pwmchip_add(&lpwm->chip);
 231         if (ret) {
 232                 dev_err(dev, "failed to add PWM chip: %d\n", ret);
 233                 return ERR_PTR(ret);
 234         }
 235
 236         return lpwm;
 237 }
 238 EXPORT_SYMBOL_GPL(pwm_lpss_probe);
 239
 240 int pwm_lpss_remove(struct pwm_lpss_chip *lpwm)
 241 {
 242         int i;
 243
 244         for (i = 0; i < lpwm->info->npwm; i++) {
 245                 if (pwm_is_enabled(&lpwm->chip.pwms[i]))
 246                         pm_runtime_put(lpwm->chip.dev);
 247         }
 248         return pwmchip_remove(&lpwm->chip);
 249 }
 250 EXPORT_SYMBOL_GPL(pwm_lpss_remove);
 251
 252 int pwm_lpss_suspend(struct device *dev)
 253 {
 254         struct pwm_lpss_chip *lpwm = dev_get_drvdata(dev);
 255         int i;
 256
 257         for (i = 0; i < lpwm->info->npwm; i++)
 258                 lpwm->saved_ctrl[i] = readl(lpwm->regs + i * PWM_SIZE + PWM);
 259
 260         return 0;
 261 }
 262 EXPORT_SYMBOL_GPL(pwm_lpss_suspend);
 263
 264 int pwm_lpss_resume(struct device *dev)
 265 {
 266         struct pwm_lpss_chip *lpwm = dev_get_drvdata(dev);
 267         int i;
 268
 269         for (i = 0; i < lpwm->info->npwm; i++)
 270                 writel(lpwm->saved_ctrl[i], lpwm->regs + i * PWM_SIZE + PWM);
 271
 272         return 0;
 273 }
 274 EXPORT_SYMBOL_GPL(pwm_lpss_resume);
 275
 276 MODULE_DESCRIPTION("PWM driver for Intel LPSS");
 277 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
 278 MODULE_LICENSE("GPL v2");