drivers/remoteproc/qcom_wcnss.c

   1 /*
   2  * Qualcomm Wireless Connectivity Subsystem Peripheral Image Loader
   3  *
   4  * Copyright (C) 2016 Linaro Ltd
   5  * Copyright (C) 2014 Sony Mobile Communications AB
   6  * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * version 2 as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/clk.h>
  19 #include <linux/delay.h>
  20 #include <linux/firmware.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/io.h>
  25 #include <linux/of_address.h>
  26 #include <linux/of_device.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/qcom_scm.h>
  29 #include <linux/regulator/consumer.h>
  30 #include <linux/remoteproc.h>
  31 #include <linux/soc/qcom/smem.h>
  32 #include <linux/soc/qcom/smem_state.h>
  33
  34 #include "qcom_mdt_loader.h"
  35 #include "remoteproc_internal.h"
  36 #include "qcom_wcnss.h"
  37
  38 #define WCNSS_CRASH_REASON_SMEM         422
  39 #define WCNSS_FIRMWARE_NAME             "wcnss.mdt"
  40 #define WCNSS_PAS_ID                    6
  41
  42 #define WCNSS_SPARE_NVBIN_DLND          BIT(25)
  43
  44 #define WCNSS_PMU_IRIS_XO_CFG           BIT(3)
  45 #define WCNSS_PMU_IRIS_XO_EN            BIT(4)
  46 #define WCNSS_PMU_GC_BUS_MUX_SEL_TOP    BIT(5)
  47 #define WCNSS_PMU_IRIS_XO_CFG_STS       BIT(6) /* 1: in progress, 0: done */
  48
  49 #define WCNSS_PMU_IRIS_RESET            BIT(7)
  50 #define WCNSS_PMU_IRIS_RESET_STS        BIT(8) /* 1: in progress, 0: done */
  51 #define WCNSS_PMU_IRIS_XO_READ          BIT(9)
  52 #define WCNSS_PMU_IRIS_XO_READ_STS      BIT(10)
  53
  54 #define WCNSS_PMU_XO_MODE_MASK          GENMASK(2, 1)
  55 #define WCNSS_PMU_XO_MODE_19p2          0
  56 #define WCNSS_PMU_XO_MODE_48            3
  57
  58 struct wcnss_data {
  59         size_t pmu_offset;
  60         size_t spare_offset;
  61
  62         const struct wcnss_vreg_info *vregs;
  63         size_t num_vregs;
  64 };
  65
  66 struct qcom_wcnss {
  67         struct device *dev;
  68         struct rproc *rproc;
  69
  70         void __iomem *pmu_cfg;
  71         void __iomem *spare_out;
  72
  73         bool use_48mhz_xo;
  74
  75         int wdog_irq;
  76         int fatal_irq;
  77         int ready_irq;
  78         int handover_irq;
  79         int stop_ack_irq;
  80
  81         struct qcom_smem_state *state;
  82         unsigned stop_bit;
  83
  84         struct mutex iris_lock;
  85         struct qcom_iris *iris;
  86
  87         struct regulator_bulk_data *vregs;
  88         size_t num_vregs;
  89
  90         struct completion start_done;
  91         struct completion stop_done;
  92
  93         phys_addr_t mem_phys;
  94         phys_addr_t mem_reloc;
  95         void *mem_region;
  96         size_t mem_size;
  97 };
  98
  99 static const struct wcnss_data riva_data = {
 100         .pmu_offset = 0x28,
 101         .spare_offset = 0xb4,
 102
 103         .vregs = (struct wcnss_vreg_info[]) {
 104                 { "vddmx",  1050000, 1150000, 0 },
 105                 { "vddcx",  1050000, 1150000, 0 },
 106                 { "vddpx",  1800000, 1800000, 0 },
 107         },
 108         .num_vregs = 3,
 109 };
 110
 111 static const struct wcnss_data pronto_v1_data = {
 112         .pmu_offset = 0x1004,
 113         .spare_offset = 0x1088,
 114
 115         .vregs = (struct wcnss_vreg_info[]) {
 116                 { "vddmx", 950000, 1150000, 0 },
 117                 { "vddcx", .super_turbo = true},
 118                 { "vddpx", 1800000, 1800000, 0 },
 119         },
 120         .num_vregs = 3,
 121 };
 122
 123 static const struct wcnss_data pronto_v2_data = {
 124         .pmu_offset = 0x1004,
 125         .spare_offset = 0x1088,
 126
 127         .vregs = (struct wcnss_vreg_info[]) {
 128                 { "vddmx", 1287500, 1287500, 0 },
 129                 { "vddcx", .super_turbo = true },
 130                 { "vddpx", 1800000, 1800000, 0 },
 131         },
 132         .num_vregs = 3,
 133 };
 134
 135 void qcom_wcnss_assign_iris(struct qcom_wcnss *wcnss,
 136                             struct qcom_iris *iris,
 137                             bool use_48mhz_xo)
 138 {
 139         mutex_lock(&wcnss->iris_lock);
 140
 141         wcnss->iris = iris;
 142         wcnss->use_48mhz_xo = use_48mhz_xo;
 143
 144         mutex_unlock(&wcnss->iris_lock);
 145 }
 146
 147 static int wcnss_load(struct rproc *rproc, const struct firmware *fw)
 148 {
 149         struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
 150         phys_addr_t fw_addr;
 151         size_t fw_size;
 152         bool relocate;
 153         int ret;
 154
 155         ret = qcom_scm_pas_init_image(WCNSS_PAS_ID, fw->data, fw->size);
 156         if (ret) {
 157                 dev_err(&rproc->dev, "invalid firmware metadata\n");
 158                 return ret;
 159         }
 160
 161         ret = qcom_mdt_parse(fw, &fw_addr, &fw_size, &relocate);
 162         if (ret) {
 163                 dev_err(&rproc->dev, "failed to parse mdt header\n");
 164                 return ret;
 165         }
 166
 167         if (relocate) {
 168                 wcnss->mem_reloc = fw_addr;
 169
 170                 ret = qcom_scm_pas_mem_setup(WCNSS_PAS_ID, wcnss->mem_phys, fw_size);
 171                 if (ret) {
 172                         dev_err(&rproc->dev, "unable to setup memory for image\n");
 173                         return ret;
 174                 }
 175         }
 176
 177         return qcom_mdt_load(rproc, fw, rproc->firmware);
 178 }
 179
 180 static const struct rproc_fw_ops wcnss_fw_ops = {
 181         .find_rsc_table = qcom_mdt_find_rsc_table,
 182         .load = wcnss_load,
 183 };
 184
 185 static void wcnss_indicate_nv_download(struct qcom_wcnss *wcnss)
 186 {
 187         u32 val;
 188
 189         /* Indicate NV download capability */
 190         val = readl(wcnss->spare_out);
 191         val |= WCNSS_SPARE_NVBIN_DLND;
 192         writel(val, wcnss->spare_out);
 193 }
 194
 195 static void wcnss_configure_iris(struct qcom_wcnss *wcnss)
 196 {
 197         u32 val;
 198
 199         /* Clear PMU cfg register */
 200         writel(0, wcnss->pmu_cfg);
 201
 202         val = WCNSS_PMU_GC_BUS_MUX_SEL_TOP | WCNSS_PMU_IRIS_XO_EN;
 203         writel(val, wcnss->pmu_cfg);
 204
 205         /* Clear XO_MODE */
 206         val &= ~WCNSS_PMU_XO_MODE_MASK;
 207         if (wcnss->use_48mhz_xo)
 208                 val |= WCNSS_PMU_XO_MODE_48 << 1;
 209         else
 210                 val |= WCNSS_PMU_XO_MODE_19p2 << 1;
 211         writel(val, wcnss->pmu_cfg);
 212
 213         /* Reset IRIS */
 214         val |= WCNSS_PMU_IRIS_RESET;
 215         writel(val, wcnss->pmu_cfg);
 216
 217         /* Wait for PMU.iris_reg_reset_sts */
 218         while (readl(wcnss->pmu_cfg) & WCNSS_PMU_IRIS_RESET_STS)
 219                 cpu_relax();
 220
 221         /* Clear IRIS reset */
 222         val &= ~WCNSS_PMU_IRIS_RESET;
 223         writel(val, wcnss->pmu_cfg);
 224
 225         /* Start IRIS XO configuration */
 226         val |= WCNSS_PMU_IRIS_XO_CFG;
 227         writel(val, wcnss->pmu_cfg);
 228
 229         /* Wait for XO configuration to finish */
 230         while (readl(wcnss->pmu_cfg) & WCNSS_PMU_IRIS_XO_CFG_STS)
 231                 cpu_relax();
 232
 233         /* Stop IRIS XO configuration */
 234         val &= ~WCNSS_PMU_GC_BUS_MUX_SEL_TOP;
 235         val &= ~WCNSS_PMU_IRIS_XO_CFG;
 236         writel(val, wcnss->pmu_cfg);
 237
 238         /* Add some delay for XO to settle */
 239         msleep(20);
 240 }
 241
 242 static int wcnss_start(struct rproc *rproc)
 243 {
 244         struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
 245         int ret;
 246
 247         mutex_lock(&wcnss->iris_lock);
 248         if (!wcnss->iris) {
 249                 dev_err(wcnss->dev, "no iris registered\n");
 250                 ret = -EINVAL;
 251                 goto release_iris_lock;
 252         }
 253
 254         ret = regulator_bulk_enable(wcnss->num_vregs, wcnss->vregs);
 255         if (ret)
 256                 goto release_iris_lock;
 257
 258         ret = qcom_iris_enable(wcnss->iris);
 259         if (ret)
 260                 goto disable_regulators;
 261
 262         wcnss_indicate_nv_download(wcnss);
 263         wcnss_configure_iris(wcnss);
 264
 265         ret = qcom_scm_pas_auth_and_reset(WCNSS_PAS_ID);
 266         if (ret) {
 267                 dev_err(wcnss->dev,
 268                         "failed to authenticate image and release reset\n");
 269                 goto disable_iris;
 270         }
 271
 272         ret = wait_for_completion_timeout(&wcnss->start_done,
 273                                           msecs_to_jiffies(5000));
 274         if (wcnss->ready_irq > 0 && ret == 0) {
 275                 /* We have a ready_irq, but it didn't fire in time. */
 276                 dev_err(wcnss->dev, "start timed out\n");
 277                 qcom_scm_pas_shutdown(WCNSS_PAS_ID);
 278                 ret = -ETIMEDOUT;
 279                 goto disable_iris;
 280         }
 281
 282         ret = 0;
 283
 284 disable_iris:
 285         qcom_iris_disable(wcnss->iris);
 286 disable_regulators:
 287         regulator_bulk_disable(wcnss->num_vregs, wcnss->vregs);
 288 release_iris_lock:
 289         mutex_unlock(&wcnss->iris_lock);
 290
 291         return ret;
 292 }
 293
 294 static int wcnss_stop(struct rproc *rproc)
 295 {
 296         struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
 297         int ret;
 298
 299         if (wcnss->state) {
 300                 qcom_smem_state_update_bits(wcnss->state,
 301                                             BIT(wcnss->stop_bit),
 302                                             BIT(wcnss->stop_bit));
 303
 304                 ret = wait_for_completion_timeout(&wcnss->stop_done,
 305                                                   msecs_to_jiffies(5000));
 306                 if (ret == 0)
 307                         dev_err(wcnss->dev, "timed out on wait\n");
 308
 309                 qcom_smem_state_update_bits(wcnss->state,
 310                                             BIT(wcnss->stop_bit),
 311                                             0);
 312         }
 313
 314         ret = qcom_scm_pas_shutdown(WCNSS_PAS_ID);
 315         if (ret)
 316                 dev_err(wcnss->dev, "failed to shutdown: %d\n", ret);
 317
 318         return ret;
 319 }
 320
 321 static void *wcnss_da_to_va(struct rproc *rproc, u64 da, int len)
 322 {
 323         struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
 324         int offset;
 325
 326         offset = da - wcnss->mem_reloc;
 327         if (offset < 0 || offset + len > wcnss->mem_size)
 328                 return NULL;
 329
 330         return wcnss->mem_region + offset;
 331 }
 332
 333 static const struct rproc_ops wcnss_ops = {
 334         .start = wcnss_start,
 335         .stop = wcnss_stop,
 336         .da_to_va = wcnss_da_to_va,
 337 };
 338
 339 static irqreturn_t wcnss_wdog_interrupt(int irq, void *dev)
 340 {
 341         struct qcom_wcnss *wcnss = dev;
 342
 343         rproc_report_crash(wcnss->rproc, RPROC_WATCHDOG);
 344
 345         return IRQ_HANDLED;
 346 }
 347
 348 static irqreturn_t wcnss_fatal_interrupt(int irq, void *dev)
 349 {
 350         struct qcom_wcnss *wcnss = dev;
 351         size_t len;
 352         char *msg;
 353
 354         msg = qcom_smem_get(QCOM_SMEM_HOST_ANY, WCNSS_CRASH_REASON_SMEM, &len);
 355         if (!IS_ERR(msg) && len > 0 && msg[0])
 356                 dev_err(wcnss->dev, "fatal error received: %s\n", msg);
 357
 358         rproc_report_crash(wcnss->rproc, RPROC_FATAL_ERROR);
 359
 360         if (!IS_ERR(msg))
 361                 msg[0] = '\0';
 362
 363         return IRQ_HANDLED;
 364 }
 365
 366 static irqreturn_t wcnss_ready_interrupt(int irq, void *dev)
 367 {
 368         struct qcom_wcnss *wcnss = dev;
 369
 370         complete(&wcnss->start_done);
 371
 372         return IRQ_HANDLED;
 373 }
 374
 375 static irqreturn_t wcnss_handover_interrupt(int irq, void *dev)
 376 {
 377         /*
 378          * XXX: At this point we're supposed to release the resources that we
 379          * have been holding on behalf of the WCNSS. Unfortunately this
 380          * interrupt comes way before the other side seems to be done.
 381          *
 382          * So we're currently relying on the ready interrupt firing later then
 383          * this and we just disable the resources at the end of wcnss_start().
 384          */
 385
 386         return IRQ_HANDLED;
 387 }
 388
 389 static irqreturn_t wcnss_stop_ack_interrupt(int irq, void *dev)
 390 {
 391         struct qcom_wcnss *wcnss = dev;
 392
 393         complete(&wcnss->stop_done);
 394
 395         return IRQ_HANDLED;
 396 }
 397
 398 static int wcnss_init_regulators(struct qcom_wcnss *wcnss,
 399                                  const struct wcnss_vreg_info *info,
 400                                  int num_vregs)
 401 {
 402         struct regulator_bulk_data *bulk;
 403         int ret;
 404         int i;
 405
 406         bulk = devm_kcalloc(wcnss->dev,
 407                             num_vregs, sizeof(struct regulator_bulk_data),
 408                             GFP_KERNEL);
 409         if (!bulk)
 410                 return -ENOMEM;
 411
 412         for (i = 0; i < num_vregs; i++)
 413                 bulk[i].supply = info[i].name;
 414
 415         ret = devm_regulator_bulk_get(wcnss->dev, num_vregs, bulk);
 416         if (ret)
 417                 return ret;
 418
 419         for (i = 0; i < num_vregs; i++) {
 420                 if (info[i].max_voltage)
 421                         regulator_set_voltage(bulk[i].consumer,
 422                                               info[i].min_voltage,
 423                                               info[i].max_voltage);
 424
 425                 if (info[i].load_uA)
 426                         regulator_set_load(bulk[i].consumer, info[i].load_uA);
 427         }
 428
 429         wcnss->vregs = bulk;
 430         wcnss->num_vregs = num_vregs;
 431
 432         return 0;
 433 }
 434
 435 static int wcnss_request_irq(struct qcom_wcnss *wcnss,
 436                              struct platform_device *pdev,
 437                              const char *name,
 438                              bool optional,
 439                              irq_handler_t thread_fn)
 440 {
 441         int ret;
 442
 443         ret = platform_get_irq_byname(pdev, name);
 444         if (ret < 0 && optional) {
 445                 dev_dbg(&pdev->dev, "no %s IRQ defined, ignoring\n", name);
 446                 return 0;
 447         } else if (ret < 0) {
 448                 dev_err(&pdev->dev, "no %s IRQ defined\n", name);
 449                 return ret;
 450         }
 451
 452         ret = devm_request_threaded_irq(&pdev->dev, ret,
 453                                         NULL, thread_fn,
 454                                         IRQF_TRIGGER_RISING | IRQF_ONESHOT,
 455                                         "wcnss", wcnss);
 456         if (ret)
 457                 dev_err(&pdev->dev, "request %s IRQ failed\n", name);
 458
 459         return ret;
 460 }
 461
 462 static int wcnss_alloc_memory_region(struct qcom_wcnss *wcnss)
 463 {
 464         struct device_node *node;
 465         struct resource r;
 466         int ret;
 467
 468         node = of_parse_phandle(wcnss->dev->of_node, "memory-region", 0);
 469         if (!node) {
 470                 dev_err(wcnss->dev, "no memory-region specified\n");
 471                 return -EINVAL;
 472         }
 473
 474         ret = of_address_to_resource(node, 0, &r);
 475         if (ret)
 476                 return ret;
 477
 478         wcnss->mem_phys = wcnss->mem_reloc = r.start;
 479         wcnss->mem_size = resource_size(&r);
 480         wcnss->mem_region = devm_ioremap_wc(wcnss->dev, wcnss->mem_phys, wcnss->mem_size);
 481         if (!wcnss->mem_region) {
 482                 dev_err(wcnss->dev, "unable to map memory region: %pa+%zx\n",
 483                         &r.start, wcnss->mem_size);
 484                 return -EBUSY;
 485         }
 486
 487         return 0;
 488 }
 489
 490 static int wcnss_probe(struct platform_device *pdev)
 491 {
 492         const struct wcnss_data *data;
 493         struct qcom_wcnss *wcnss;
 494         struct resource *res;
 495         struct rproc *rproc;
 496         void __iomem *mmio;
 497         int ret;
 498
 499         data = of_device_get_match_data(&pdev->dev);
 500
 501         if (!qcom_scm_is_available())
 502                 return -EPROBE_DEFER;
 503
 504         if (!qcom_scm_pas_supported(WCNSS_PAS_ID)) {
 505                 dev_err(&pdev->dev, "PAS is not available for WCNSS\n");
 506                 return -ENXIO;
 507         }
 508
 509         rproc = rproc_alloc(&pdev->dev, pdev->name, &wcnss_ops,
 510                             WCNSS_FIRMWARE_NAME, sizeof(*wcnss));
 511         if (!rproc) {
 512                 dev_err(&pdev->dev, "unable to allocate remoteproc\n");
 513                 return -ENOMEM;
 514         }
 515
 516         rproc->fw_ops = &wcnss_fw_ops;
 517
 518         wcnss = (struct qcom_wcnss *)rproc->priv;
 519         wcnss->dev = &pdev->dev;
 520         wcnss->rproc = rproc;
 521         platform_set_drvdata(pdev, wcnss);
 522
 523         init_completion(&wcnss->start_done);
 524         init_completion(&wcnss->stop_done);
 525
 526         mutex_init(&wcnss->iris_lock);
 527
 528         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pmu");
 529         mmio = devm_ioremap_resource(&pdev->dev, res);
 530         if (IS_ERR(mmio)) {
 531                 ret = PTR_ERR(mmio);
 532                 goto free_rproc;
 533         };
 534
 535         ret = wcnss_alloc_memory_region(wcnss);
 536         if (ret)
 537                 goto free_rproc;
 538
 539         wcnss->pmu_cfg = mmio + data->pmu_offset;
 540         wcnss->spare_out = mmio + data->spare_offset;
 541
 542         ret = wcnss_init_regulators(wcnss, data->vregs, data->num_vregs);
 543         if (ret)
 544                 goto free_rproc;
 545
 546         ret = wcnss_request_irq(wcnss, pdev, "wdog", false, wcnss_wdog_interrupt);
 547         if (ret < 0)
 548                 goto free_rproc;
 549         wcnss->wdog_irq = ret;
 550
 551         ret = wcnss_request_irq(wcnss, pdev, "fatal", false, wcnss_fatal_interrupt);
 552         if (ret < 0)
 553                 goto free_rproc;
 554         wcnss->fatal_irq = ret;
 555
 556         ret = wcnss_request_irq(wcnss, pdev, "ready", true, wcnss_ready_interrupt);
 557         if (ret < 0)
 558                 goto free_rproc;
 559         wcnss->ready_irq = ret;
 560
 561         ret = wcnss_request_irq(wcnss, pdev, "handover", true, wcnss_handover_interrupt);
 562         if (ret < 0)
 563                 goto free_rproc;
 564         wcnss->handover_irq = ret;
 565
 566         ret = wcnss_request_irq(wcnss, pdev, "stop-ack", true, wcnss_stop_ack_interrupt);
 567         if (ret < 0)
 568                 goto free_rproc;
 569         wcnss->stop_ack_irq = ret;
 570
 571         if (wcnss->stop_ack_irq) {
 572                 wcnss->state = qcom_smem_state_get(&pdev->dev, "stop",
 573                                                    &wcnss->stop_bit);
 574                 if (IS_ERR(wcnss->state)) {
 575                         ret = PTR_ERR(wcnss->state);
 576                         goto free_rproc;
 577                 }
 578         }
 579
 580         ret = rproc_add(rproc);
 581         if (ret)
 582                 goto free_rproc;
 583
 584         return of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
 585
 586 free_rproc:
 587         rproc_free(rproc);
 588
 589         return ret;
 590 }
 591
 592 static int wcnss_remove(struct platform_device *pdev)
 593 {
 594         struct qcom_wcnss *wcnss = platform_get_drvdata(pdev);
 595
 596         of_platform_depopulate(&pdev->dev);
 597
 598         qcom_smem_state_put(wcnss->state);
 599         rproc_del(wcnss->rproc);
 600         rproc_free(wcnss->rproc);
 601
 602         return 0;
 603 }
 604
 605 static const struct of_device_id wcnss_of_match[] = {
 606         { .compatible = "qcom,riva-pil", &riva_data },
 607         { .compatible = "qcom,pronto-v1-pil", &pronto_v1_data },
 608         { .compatible = "qcom,pronto-v2-pil", &pronto_v2_data },
 609         { },
 610 };
 611
 612 static struct platform_driver wcnss_driver = {
 613         .probe = wcnss_probe,
 614         .remove = wcnss_remove,
 615         .driver = {
 616                 .name = "qcom-wcnss-pil",
 617                 .of_match_table = wcnss_of_match,
 618         },
 619 };
 620
 621 static int __init wcnss_init(void)
 622 {
 623         int ret;
 624
 625         ret = platform_driver_register(&wcnss_driver);
 626         if (ret)
 627                 return ret;
 628
 629         ret = platform_driver_register(&qcom_iris_driver);
 630         if (ret)
 631                 platform_driver_unregister(&wcnss_driver);
 632
 633         return ret;
 634 }
 635 module_init(wcnss_init);
 636
 637 static void __exit wcnss_exit(void)
 638 {
 639         platform_driver_unregister(&qcom_iris_driver);
 640         platform_driver_unregister(&wcnss_driver);
 641 }
 642 module_exit(wcnss_exit);
 643
 644 MODULE_DESCRIPTION("Qualcomm Peripherial Image Loader for Wireless Subsystem");
 645 MODULE_LICENSE("GPL v2");