drivers/rtc/rtc-jz4740.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
   4  *  Copyright (C) 2010, Paul Cercueil <paul@crapouillou.net>
   5  *       JZ4740 SoC RTC driver
   6  */
   7
   8 #include <linux/clk.h>
   9 #include <linux/io.h>
  10 #include <linux/kernel.h>
  11 #include <linux/module.h>
  12 #include <linux/of_device.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/pm_wakeirq.h>
  15 #include <linux/reboot.h>
  16 #include <linux/rtc.h>
  17 #include <linux/slab.h>
  18 #include <linux/spinlock.h>
  19
  20 #define JZ_REG_RTC_CTRL         0x00
  21 #define JZ_REG_RTC_SEC          0x04
  22 #define JZ_REG_RTC_SEC_ALARM    0x08
  23 #define JZ_REG_RTC_REGULATOR    0x0C
  24 #define JZ_REG_RTC_HIBERNATE    0x20
  25 #define JZ_REG_RTC_WAKEUP_FILTER        0x24
  26 #define JZ_REG_RTC_RESET_COUNTER        0x28
  27 #define JZ_REG_RTC_SCRATCHPAD   0x34
  28
  29 /* The following are present on the jz4780 */
  30 #define JZ_REG_RTC_WENR 0x3C
  31 #define JZ_RTC_WENR_WEN BIT(31)
  32
  33 #define JZ_RTC_CTRL_WRDY        BIT(7)
  34 #define JZ_RTC_CTRL_1HZ         BIT(6)
  35 #define JZ_RTC_CTRL_1HZ_IRQ     BIT(5)
  36 #define JZ_RTC_CTRL_AF          BIT(4)
  37 #define JZ_RTC_CTRL_AF_IRQ      BIT(3)
  38 #define JZ_RTC_CTRL_AE          BIT(2)
  39 #define JZ_RTC_CTRL_ENABLE      BIT(0)
  40
  41 /* Magic value to enable writes on jz4780 */
  42 #define JZ_RTC_WENR_MAGIC       0xA55A
  43
  44 #define JZ_RTC_WAKEUP_FILTER_MASK       0x0000FFE0
  45 #define JZ_RTC_RESET_COUNTER_MASK       0x00000FE0
  46
  47 enum jz4740_rtc_type {
  48         ID_JZ4740,
  49         ID_JZ4760,
  50         ID_JZ4780,
  51 };
  52
  53 struct jz4740_rtc {
  54         void __iomem *base;
  55         enum jz4740_rtc_type type;
  56
  57         struct rtc_device *rtc;
  58         struct clk *clk;
  59
  60         int irq;
  61
  62         spinlock_t lock;
  63
  64         unsigned int min_wakeup_pin_assert_time;
  65         unsigned int reset_pin_assert_time;
  66 };
  67
  68 static struct device *dev_for_power_off;
  69
  70 static inline uint32_t jz4740_rtc_reg_read(struct jz4740_rtc *rtc, size_t reg)
  71 {
  72         return readl(rtc->base + reg);
  73 }
  74
  75 static int jz4740_rtc_wait_write_ready(struct jz4740_rtc *rtc)
  76 {
  77         uint32_t ctrl;
  78         int timeout = 10000;
  79
  80         do {
  81                 ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
  82         } while (!(ctrl & JZ_RTC_CTRL_WRDY) && --timeout);
  83
  84         return timeout ? 0 : -EIO;
  85 }
  86
  87 static inline int jz4780_rtc_enable_write(struct jz4740_rtc *rtc)
  88 {
  89         uint32_t ctrl;
  90         int ret, timeout = 10000;
  91
  92         ret = jz4740_rtc_wait_write_ready(rtc);
  93         if (ret != 0)
  94                 return ret;
  95
  96         writel(JZ_RTC_WENR_MAGIC, rtc->base + JZ_REG_RTC_WENR);
  97
  98         do {
  99                 ctrl = readl(rtc->base + JZ_REG_RTC_WENR);
 100         } while (!(ctrl & JZ_RTC_WENR_WEN) && --timeout);
 101
 102         return timeout ? 0 : -EIO;
 103 }
 104
 105 static inline int jz4740_rtc_reg_write(struct jz4740_rtc *rtc, size_t reg,
 106         uint32_t val)
 107 {
 108         int ret = 0;
 109
 110         if (rtc->type >= ID_JZ4760)
 111                 ret = jz4780_rtc_enable_write(rtc);
 112         if (ret == 0)
 113                 ret = jz4740_rtc_wait_write_ready(rtc);
 114         if (ret == 0)
 115                 writel(val, rtc->base + reg);
 116
 117         return ret;
 118 }
 119
 120 static int jz4740_rtc_ctrl_set_bits(struct jz4740_rtc *rtc, uint32_t mask,
 121         bool set)
 122 {
 123         int ret;
 124         unsigned long flags;
 125         uint32_t ctrl;
 126
 127         spin_lock_irqsave(&rtc->lock, flags);
 128
 129         ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
 130
 131         /* Don't clear interrupt flags by accident */
 132         ctrl |= JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF;
 133
 134         if (set)
 135                 ctrl |= mask;
 136         else
 137                 ctrl &= ~mask;
 138
 139         ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_CTRL, ctrl);
 140
 141         spin_unlock_irqrestore(&rtc->lock, flags);
 142
 143         return ret;
 144 }
 145
 146 static int jz4740_rtc_read_time(struct device *dev, struct rtc_time *time)
 147 {
 148         struct jz4740_rtc *rtc = dev_get_drvdata(dev);
 149         uint32_t secs, secs2;
 150         int timeout = 5;
 151
 152         if (jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SCRATCHPAD) != 0x12345678)
 153                 return -EINVAL;
 154
 155         /* If the seconds register is read while it is updated, it can contain a
 156          * bogus value. This can be avoided by making sure that two consecutive
 157          * reads have the same value.
 158          */
 159         secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
 160         secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
 161
 162         while (secs != secs2 && --timeout) {
 163                 secs = secs2;
 164                 secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
 165         }
 166
 167         if (timeout == 0)
 168                 return -EIO;
 169
 170         rtc_time64_to_tm(secs, time);
 171
 172         return 0;
 173 }
 174
 175 static int jz4740_rtc_set_time(struct device *dev, struct rtc_time *time)
 176 {
 177         struct jz4740_rtc *rtc = dev_get_drvdata(dev);
 178         int ret;
 179
 180         ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC, rtc_tm_to_time64(time));
 181         if (ret)
 182                 return ret;
 183
 184         return jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SCRATCHPAD, 0x12345678);
 185 }
 186
 187 static int jz4740_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
 188 {
 189         struct jz4740_rtc *rtc = dev_get_drvdata(dev);
 190         uint32_t secs;
 191         uint32_t ctrl;
 192
 193         secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC_ALARM);
 194
 195         ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
 196
 197         alrm->enabled = !!(ctrl & JZ_RTC_CTRL_AE);
 198         alrm->pending = !!(ctrl & JZ_RTC_CTRL_AF);
 199
 200         rtc_time64_to_tm(secs, &alrm->time);
 201
 202         return 0;
 203 }
 204
 205 static int jz4740_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
 206 {
 207         int ret;
 208         struct jz4740_rtc *rtc = dev_get_drvdata(dev);
 209         uint32_t secs = lower_32_bits(rtc_tm_to_time64(&alrm->time));
 210
 211         ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC_ALARM, secs);
 212         if (!ret)
 213                 ret = jz4740_rtc_ctrl_set_bits(rtc,
 214                         JZ_RTC_CTRL_AE | JZ_RTC_CTRL_AF_IRQ, alrm->enabled);
 215
 216         return ret;
 217 }
 218
 219 static int jz4740_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
 220 {
 221         struct jz4740_rtc *rtc = dev_get_drvdata(dev);
 222         return jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_AF_IRQ, enable);
 223 }
 224
 225 static const struct rtc_class_ops jz4740_rtc_ops = {
 226         .read_time      = jz4740_rtc_read_time,
 227         .set_time       = jz4740_rtc_set_time,
 228         .read_alarm     = jz4740_rtc_read_alarm,
 229         .set_alarm      = jz4740_rtc_set_alarm,
 230         .alarm_irq_enable = jz4740_rtc_alarm_irq_enable,
 231 };
 232
 233 static irqreturn_t jz4740_rtc_irq(int irq, void *data)
 234 {
 235         struct jz4740_rtc *rtc = data;
 236         uint32_t ctrl;
 237         unsigned long events = 0;
 238
 239         ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
 240
 241         if (ctrl & JZ_RTC_CTRL_1HZ)
 242                 events |= (RTC_UF | RTC_IRQF);
 243
 244         if (ctrl & JZ_RTC_CTRL_AF)
 245                 events |= (RTC_AF | RTC_IRQF);
 246
 247         rtc_update_irq(rtc->rtc, 1, events);
 248
 249         jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF, false);
 250
 251         return IRQ_HANDLED;
 252 }
 253
 254 static void jz4740_rtc_poweroff(struct device *dev)
 255 {
 256         struct jz4740_rtc *rtc = dev_get_drvdata(dev);
 257         jz4740_rtc_reg_write(rtc, JZ_REG_RTC_HIBERNATE, 1);
 258 }
 259
 260 static void jz4740_rtc_power_off(void)
 261 {
 262         struct jz4740_rtc *rtc = dev_get_drvdata(dev_for_power_off);
 263         unsigned long rtc_rate;
 264         unsigned long wakeup_filter_ticks;
 265         unsigned long reset_counter_ticks;
 266
 267         clk_prepare_enable(rtc->clk);
 268
 269         rtc_rate = clk_get_rate(rtc->clk);
 270
 271         /*
 272          * Set minimum wakeup pin assertion time: 100 ms.
 273          * Range is 0 to 2 sec if RTC is clocked at 32 kHz.
 274          */
 275         wakeup_filter_ticks =
 276                 (rtc->min_wakeup_pin_assert_time * rtc_rate) / 1000;
 277         if (wakeup_filter_ticks < JZ_RTC_WAKEUP_FILTER_MASK)
 278                 wakeup_filter_ticks &= JZ_RTC_WAKEUP_FILTER_MASK;
 279         else
 280                 wakeup_filter_ticks = JZ_RTC_WAKEUP_FILTER_MASK;
 281         jz4740_rtc_reg_write(rtc,
 282                              JZ_REG_RTC_WAKEUP_FILTER, wakeup_filter_ticks);
 283
 284         /*
 285          * Set reset pin low-level assertion time after wakeup: 60 ms.
 286          * Range is 0 to 125 ms if RTC is clocked at 32 kHz.
 287          */
 288         reset_counter_ticks = (rtc->reset_pin_assert_time * rtc_rate) / 1000;
 289         if (reset_counter_ticks < JZ_RTC_RESET_COUNTER_MASK)
 290                 reset_counter_ticks &= JZ_RTC_RESET_COUNTER_MASK;
 291         else
 292                 reset_counter_ticks = JZ_RTC_RESET_COUNTER_MASK;
 293         jz4740_rtc_reg_write(rtc,
 294                              JZ_REG_RTC_RESET_COUNTER, reset_counter_ticks);
 295
 296         jz4740_rtc_poweroff(dev_for_power_off);
 297         kernel_halt();
 298 }
 299
 300 static const struct of_device_id jz4740_rtc_of_match[] = {
 301         { .compatible = "ingenic,jz4740-rtc", .data = (void *)ID_JZ4740 },
 302         { .compatible = "ingenic,jz4760-rtc", .data = (void *)ID_JZ4760 },
 303         { .compatible = "ingenic,jz4780-rtc", .data = (void *)ID_JZ4780 },
 304         {},
 305 };
 306 MODULE_DEVICE_TABLE(of, jz4740_rtc_of_match);
 307
 308 static int jz4740_rtc_probe(struct platform_device *pdev)
 309 {
 310         int ret;
 311         struct jz4740_rtc *rtc;
 312         const struct platform_device_id *id = platform_get_device_id(pdev);
 313         const struct of_device_id *of_id = of_match_device(
 314                         jz4740_rtc_of_match, &pdev->dev);
 315         struct device_node *np = pdev->dev.of_node;
 316
 317         rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
 318         if (!rtc)
 319                 return -ENOMEM;
 320
 321         if (of_id)
 322                 rtc->type = (enum jz4740_rtc_type)of_id->data;
 323         else
 324                 rtc->type = id->driver_data;
 325
 326         rtc->irq = platform_get_irq(pdev, 0);
 327         if (rtc->irq < 0)
 328                 return -ENOENT;
 329
 330         rtc->base = devm_platform_ioremap_resource(pdev, 0);
 331         if (IS_ERR(rtc->base))
 332                 return PTR_ERR(rtc->base);
 333
 334         rtc->clk = devm_clk_get(&pdev->dev, "rtc");
 335         if (IS_ERR(rtc->clk)) {
 336                 dev_err(&pdev->dev, "Failed to get RTC clock\n");
 337                 return PTR_ERR(rtc->clk);
 338         }
 339
 340         spin_lock_init(&rtc->lock);
 341
 342         platform_set_drvdata(pdev, rtc);
 343
 344         device_init_wakeup(&pdev->dev, 1);
 345
 346         ret = dev_pm_set_wake_irq(&pdev->dev, rtc->irq);
 347         if (ret) {
 348                 dev_err(&pdev->dev, "Failed to set wake irq: %d\n", ret);
 349                 return ret;
 350         }
 351
 352         rtc->rtc = devm_rtc_allocate_device(&pdev->dev);
 353         if (IS_ERR(rtc->rtc)) {
 354                 ret = PTR_ERR(rtc->rtc);
 355                 dev_err(&pdev->dev, "Failed to allocate rtc device: %d\n", ret);
 356                 return ret;
 357         }
 358
 359         rtc->rtc->ops = &jz4740_rtc_ops;
 360         rtc->rtc->range_max = U32_MAX;
 361
 362         ret = rtc_register_device(rtc->rtc);
 363         if (ret)
 364                 return ret;
 365
 366         ret = devm_request_irq(&pdev->dev, rtc->irq, jz4740_rtc_irq, 0,
 367                                 pdev->name, rtc);
 368         if (ret) {
 369                 dev_err(&pdev->dev, "Failed to request rtc irq: %d\n", ret);
 370                 return ret;
 371         }
 372
 373         if (np && of_device_is_system_power_controller(np)) {
 374                 if (!pm_power_off) {
 375                         /* Default: 60ms */
 376                         rtc->reset_pin_assert_time = 60;
 377                         of_property_read_u32(np,
 378                                              "ingenic,reset-pin-assert-time-ms",
 379                                              &rtc->reset_pin_assert_time);
 380
 381                         /* Default: 100ms */
 382                         rtc->min_wakeup_pin_assert_time = 100;
 383                         of_property_read_u32(np,
 384                                              "ingenic,min-wakeup-pin-assert-time-ms",
 385                                              &rtc->min_wakeup_pin_assert_time);
 386
 387                         dev_for_power_off = &pdev->dev;
 388                         pm_power_off = jz4740_rtc_power_off;
 389                 } else {
 390                         dev_warn(&pdev->dev,
 391                                  "Poweroff handler already present!\n");
 392                 }
 393         }
 394
 395         return 0;
 396 }
 397
 398 static const struct platform_device_id jz4740_rtc_ids[] = {
 399         { "jz4740-rtc", ID_JZ4740 },
 400         { "jz4780-rtc", ID_JZ4780 },
 401         {}
 402 };
 403 MODULE_DEVICE_TABLE(platform, jz4740_rtc_ids);
 404
 405 static struct platform_driver jz4740_rtc_driver = {
 406         .probe   = jz4740_rtc_probe,
 407         .driver  = {
 408                 .name  = "jz4740-rtc",
 409                 .of_match_table = of_match_ptr(jz4740_rtc_of_match),
 410         },
 411         .id_table = jz4740_rtc_ids,
 412 };
 413
 414 module_platform_driver(jz4740_rtc_driver);
 415
 416 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
 417 MODULE_LICENSE("GPL");
 418 MODULE_DESCRIPTION("RTC driver for the JZ4740 SoC\n");
 419 MODULE_ALIAS("platform:jz4740-rtc");