drivers/scsi/megaraid/megaraid_sas.h

   1 /*
   2  *  Linux MegaRAID driver for SAS based RAID controllers
   3  *
   4  *  Copyright (c) 2003-2013  LSI Corporation
   5  *  Copyright (c) 2013-2014  Avago Technologies
   6  *
   7  *  This program is free software; you can redistribute it and/or
   8  *  modify it under the terms of the GNU General Public License
   9  *  as published by the Free Software Foundation; either version 2
  10  *  of the License, or (at your option) any later version.
  11  *
  12  *  This program is distributed in the hope that it will be useful,
  13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *  GNU General Public License for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License
  18  *  along with this program.  If not, see <http://www.gnu.org/licenses/>.
  19  *
  20  *  FILE: megaraid_sas.h
  21  *
  22  *  Authors: Avago Technologies
  23  *           Kashyap Desai <kashyap.desai@avagotech.com>
  24  *           Sumit Saxena <sumit.saxena@avagotech.com>
  25  *
  26  *  Send feedback to: megaraidlinux.pdl@avagotech.com
  27  *
  28  *  Mail to: Avago Technologies, 350 West Trimble Road, Building 90,
  29  *  San Jose, California 95131
  30  */
  31
  32 #ifndef LSI_MEGARAID_SAS_H
  33 #define LSI_MEGARAID_SAS_H
  34
  35 /*
  36  * MegaRAID SAS Driver meta data
  37  */
  38 #define MEGASAS_VERSION                         "06.807.10.00-rc1"
  39 #define MEGASAS_RELDATE                         "March 6, 2015"
  40
  41 /*
  42  * Device IDs
  43  */
  44 #define PCI_DEVICE_ID_LSI_SAS1078R              0x0060
  45 #define PCI_DEVICE_ID_LSI_SAS1078DE             0x007C
  46 #define PCI_DEVICE_ID_LSI_VERDE_ZCR             0x0413
  47 #define PCI_DEVICE_ID_LSI_SAS1078GEN2           0x0078
  48 #define PCI_DEVICE_ID_LSI_SAS0079GEN2           0x0079
  49 #define PCI_DEVICE_ID_LSI_SAS0073SKINNY         0x0073
  50 #define PCI_DEVICE_ID_LSI_SAS0071SKINNY         0x0071
  51 #define PCI_DEVICE_ID_LSI_FUSION                0x005b
  52 #define PCI_DEVICE_ID_LSI_PLASMA                0x002f
  53 #define PCI_DEVICE_ID_LSI_INVADER               0x005d
  54 #define PCI_DEVICE_ID_LSI_FURY                  0x005f
  55
  56 /*
  57  * Intel HBA SSDIDs
  58  */
  59 #define MEGARAID_INTEL_RS3DC080_SSDID           0x9360
  60 #define MEGARAID_INTEL_RS3DC040_SSDID           0x9362
  61 #define MEGARAID_INTEL_RS3SC008_SSDID           0x9380
  62 #define MEGARAID_INTEL_RS3MC044_SSDID           0x9381
  63 #define MEGARAID_INTEL_RS3WC080_SSDID           0x9341
  64 #define MEGARAID_INTEL_RS3WC040_SSDID           0x9343
  65
  66 /*
  67  * Intel HBA branding
  68  */
  69 #define MEGARAID_INTEL_RS3DC080_BRANDING        \
  70         "Intel(R) RAID Controller RS3DC080"
  71 #define MEGARAID_INTEL_RS3DC040_BRANDING        \
  72         "Intel(R) RAID Controller RS3DC040"
  73 #define MEGARAID_INTEL_RS3SC008_BRANDING        \
  74         "Intel(R) RAID Controller RS3SC008"
  75 #define MEGARAID_INTEL_RS3MC044_BRANDING        \
  76         "Intel(R) RAID Controller RS3MC044"
  77 #define MEGARAID_INTEL_RS3WC080_BRANDING        \
  78         "Intel(R) RAID Controller RS3WC080"
  79 #define MEGARAID_INTEL_RS3WC040_BRANDING        \
  80         "Intel(R) RAID Controller RS3WC040"
  81
  82 /*
  83  * =====================================
  84  * MegaRAID SAS MFI firmware definitions
  85  * =====================================
  86  */
  87
  88 /*
  89  * MFI stands for  MegaRAID SAS FW Interface. This is just a moniker for
  90  * protocol between the software and firmware. Commands are issued using
  91  * "message frames"
  92  */
  93
  94 /*
  95  * FW posts its state in upper 4 bits of outbound_msg_0 register
  96  */
  97 #define MFI_STATE_MASK                          0xF0000000
  98 #define MFI_STATE_UNDEFINED                     0x00000000
  99 #define MFI_STATE_BB_INIT                       0x10000000
 100 #define MFI_STATE_FW_INIT                       0x40000000
 101 #define MFI_STATE_WAIT_HANDSHAKE                0x60000000
 102 #define MFI_STATE_FW_INIT_2                     0x70000000
 103 #define MFI_STATE_DEVICE_SCAN                   0x80000000
 104 #define MFI_STATE_BOOT_MESSAGE_PENDING          0x90000000
 105 #define MFI_STATE_FLUSH_CACHE                   0xA0000000
 106 #define MFI_STATE_READY                         0xB0000000
 107 #define MFI_STATE_OPERATIONAL                   0xC0000000
 108 #define MFI_STATE_FAULT                         0xF0000000
 109 #define MFI_STATE_FORCE_OCR                     0x00000080
 110 #define MFI_STATE_DMADONE                       0x00000008
 111 #define MFI_STATE_CRASH_DUMP_DONE               0x00000004
 112 #define MFI_RESET_REQUIRED                      0x00000001
 113 #define MFI_RESET_ADAPTER                       0x00000002
 114 #define MEGAMFI_FRAME_SIZE                      64
 115
 116 /*
 117  * During FW init, clear pending cmds & reset state using inbound_msg_0
 118  *
 119  * ABORT        : Abort all pending cmds
 120  * READY        : Move from OPERATIONAL to READY state; discard queue info
 121  * MFIMODE      : Discard (possible) low MFA posted in 64-bit mode (??)
 122  * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
 123  * HOTPLUG      : Resume from Hotplug
 124  * MFI_STOP_ADP : Send signal to FW to stop processing
 125  */
 126 #define WRITE_SEQUENCE_OFFSET           (0x0000000FC) /* I20 */
 127 #define HOST_DIAGNOSTIC_OFFSET          (0x000000F8)  /* I20 */
 128 #define DIAG_WRITE_ENABLE                       (0x00000080)
 129 #define DIAG_RESET_ADAPTER                      (0x00000004)
 130
 131 #define MFI_ADP_RESET                           0x00000040
 132 #define MFI_INIT_ABORT                          0x00000001
 133 #define MFI_INIT_READY                          0x00000002
 134 #define MFI_INIT_MFIMODE                        0x00000004
 135 #define MFI_INIT_CLEAR_HANDSHAKE                0x00000008
 136 #define MFI_INIT_HOTPLUG                        0x00000010
 137 #define MFI_STOP_ADP                            0x00000020
 138 #define MFI_RESET_FLAGS                         MFI_INIT_READY| \
 139                                                 MFI_INIT_MFIMODE| \
 140                                                 MFI_INIT_ABORT
 141
 142 /*
 143  * MFI frame flags
 144  */
 145 #define MFI_FRAME_POST_IN_REPLY_QUEUE           0x0000
 146 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE      0x0001
 147 #define MFI_FRAME_SGL32                         0x0000
 148 #define MFI_FRAME_SGL64                         0x0002
 149 #define MFI_FRAME_SENSE32                       0x0000
 150 #define MFI_FRAME_SENSE64                       0x0004
 151 #define MFI_FRAME_DIR_NONE                      0x0000
 152 #define MFI_FRAME_DIR_WRITE                     0x0008
 153 #define MFI_FRAME_DIR_READ                      0x0010
 154 #define MFI_FRAME_DIR_BOTH                      0x0018
 155 #define MFI_FRAME_IEEE                          0x0020
 156
 157 /* Driver internal */
 158 #define DRV_DCMD_POLLED_MODE            0x1
 159
 160 /*
 161  * Definition for cmd_status
 162  */
 163 #define MFI_CMD_STATUS_POLL_MODE                0xFF
 164
 165 /*
 166  * MFI command opcodes
 167  */
 168 #define MFI_CMD_INIT                            0x00
 169 #define MFI_CMD_LD_READ                         0x01
 170 #define MFI_CMD_LD_WRITE                        0x02
 171 #define MFI_CMD_LD_SCSI_IO                      0x03
 172 #define MFI_CMD_PD_SCSI_IO                      0x04
 173 #define MFI_CMD_DCMD                            0x05
 174 #define MFI_CMD_ABORT                           0x06
 175 #define MFI_CMD_SMP                             0x07
 176 #define MFI_CMD_STP                             0x08
 177 #define MFI_CMD_INVALID                         0xff
 178
 179 #define MR_DCMD_CTRL_GET_INFO                   0x01010000
 180 #define MR_DCMD_LD_GET_LIST                     0x03010000
 181 #define MR_DCMD_LD_LIST_QUERY                   0x03010100
 182
 183 #define MR_DCMD_CTRL_CACHE_FLUSH                0x01101000
 184 #define MR_FLUSH_CTRL_CACHE                     0x01
 185 #define MR_FLUSH_DISK_CACHE                     0x02
 186
 187 #define MR_DCMD_CTRL_SHUTDOWN                   0x01050000
 188 #define MR_DCMD_HIBERNATE_SHUTDOWN              0x01060000
 189 #define MR_ENABLE_DRIVE_SPINDOWN                0x01
 190
 191 #define MR_DCMD_CTRL_EVENT_GET_INFO             0x01040100
 192 #define MR_DCMD_CTRL_EVENT_GET                  0x01040300
 193 #define MR_DCMD_CTRL_EVENT_WAIT                 0x01040500
 194 #define MR_DCMD_LD_GET_PROPERTIES               0x03030000
 195
 196 #define MR_DCMD_CLUSTER                         0x08000000
 197 #define MR_DCMD_CLUSTER_RESET_ALL               0x08010100
 198 #define MR_DCMD_CLUSTER_RESET_LD                0x08010200
 199 #define MR_DCMD_PD_LIST_QUERY                   0x02010100
 200
 201 #define MR_DCMD_CTRL_SET_CRASH_DUMP_PARAMS      0x01190100
 202 #define MR_DRIVER_SET_APP_CRASHDUMP_MODE        (0xF0010000 | 0x0600)
 203
 204 /*
 205  * Global functions
 206  */
 207 extern u8 MR_ValidateMapInfo(struct megasas_instance *instance);
 208
 209
 210 /*
 211  * MFI command completion codes
 212  */
 213 enum MFI_STAT {
 214         MFI_STAT_OK = 0x00,
 215         MFI_STAT_INVALID_CMD = 0x01,
 216         MFI_STAT_INVALID_DCMD = 0x02,
 217         MFI_STAT_INVALID_PARAMETER = 0x03,
 218         MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
 219         MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
 220         MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
 221         MFI_STAT_APP_IN_USE = 0x07,
 222         MFI_STAT_APP_NOT_INITIALIZED = 0x08,
 223         MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
 224         MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
 225         MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
 226         MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
 227         MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
 228         MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
 229         MFI_STAT_FLASH_BUSY = 0x0f,
 230         MFI_STAT_FLASH_ERROR = 0x10,
 231         MFI_STAT_FLASH_IMAGE_BAD = 0x11,
 232         MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
 233         MFI_STAT_FLASH_NOT_OPEN = 0x13,
 234         MFI_STAT_FLASH_NOT_STARTED = 0x14,
 235         MFI_STAT_FLUSH_FAILED = 0x15,
 236         MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
 237         MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
 238         MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
 239         MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
 240         MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
 241         MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
 242         MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
 243         MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
 244         MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
 245         MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
 246         MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
 247         MFI_STAT_MFC_HW_ERROR = 0x21,
 248         MFI_STAT_NO_HW_PRESENT = 0x22,
 249         MFI_STAT_NOT_FOUND = 0x23,
 250         MFI_STAT_NOT_IN_ENCL = 0x24,
 251         MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
 252         MFI_STAT_PD_TYPE_WRONG = 0x26,
 253         MFI_STAT_PR_DISABLED = 0x27,
 254         MFI_STAT_ROW_INDEX_INVALID = 0x28,
 255         MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
 256         MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
 257         MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
 258         MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
 259         MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
 260         MFI_STAT_SCSI_IO_FAILED = 0x2e,
 261         MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
 262         MFI_STAT_SHUTDOWN_FAILED = 0x30,
 263         MFI_STAT_TIME_NOT_SET = 0x31,
 264         MFI_STAT_WRONG_STATE = 0x32,
 265         MFI_STAT_LD_OFFLINE = 0x33,
 266         MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34,
 267         MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35,
 268         MFI_STAT_RESERVATION_IN_PROGRESS = 0x36,
 269         MFI_STAT_I2C_ERRORS_DETECTED = 0x37,
 270         MFI_STAT_PCI_ERRORS_DETECTED = 0x38,
 271         MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67,
 272
 273         MFI_STAT_INVALID_STATUS = 0xFF
 274 };
 275
 276 /*
 277  * Crash dump related defines
 278  */
 279 #define MAX_CRASH_DUMP_SIZE 512
 280 #define CRASH_DMA_BUF_SIZE  (1024 * 1024)
 281
 282 enum MR_FW_CRASH_DUMP_STATE {
 283         UNAVAILABLE = 0,
 284         AVAILABLE = 1,
 285         COPYING = 2,
 286         COPIED = 3,
 287         COPY_ERROR = 4,
 288 };
 289
 290 enum _MR_CRASH_BUF_STATUS {
 291         MR_CRASH_BUF_TURN_OFF = 0,
 292         MR_CRASH_BUF_TURN_ON = 1,
 293 };
 294
 295 /*
 296  * Number of mailbox bytes in DCMD message frame
 297  */
 298 #define MFI_MBOX_SIZE                           12
 299
 300 enum MR_EVT_CLASS {
 301
 302         MR_EVT_CLASS_DEBUG = -2,
 303         MR_EVT_CLASS_PROGRESS = -1,
 304         MR_EVT_CLASS_INFO = 0,
 305         MR_EVT_CLASS_WARNING = 1,
 306         MR_EVT_CLASS_CRITICAL = 2,
 307         MR_EVT_CLASS_FATAL = 3,
 308         MR_EVT_CLASS_DEAD = 4,
 309
 310 };
 311
 312 enum MR_EVT_LOCALE {
 313
 314         MR_EVT_LOCALE_LD = 0x0001,
 315         MR_EVT_LOCALE_PD = 0x0002,
 316         MR_EVT_LOCALE_ENCL = 0x0004,
 317         MR_EVT_LOCALE_BBU = 0x0008,
 318         MR_EVT_LOCALE_SAS = 0x0010,
 319         MR_EVT_LOCALE_CTRL = 0x0020,
 320         MR_EVT_LOCALE_CONFIG = 0x0040,
 321         MR_EVT_LOCALE_CLUSTER = 0x0080,
 322         MR_EVT_LOCALE_ALL = 0xffff,
 323
 324 };
 325
 326 enum MR_EVT_ARGS {
 327
 328         MR_EVT_ARGS_NONE,
 329         MR_EVT_ARGS_CDB_SENSE,
 330         MR_EVT_ARGS_LD,
 331         MR_EVT_ARGS_LD_COUNT,
 332         MR_EVT_ARGS_LD_LBA,
 333         MR_EVT_ARGS_LD_OWNER,
 334         MR_EVT_ARGS_LD_LBA_PD_LBA,
 335         MR_EVT_ARGS_LD_PROG,
 336         MR_EVT_ARGS_LD_STATE,
 337         MR_EVT_ARGS_LD_STRIP,
 338         MR_EVT_ARGS_PD,
 339         MR_EVT_ARGS_PD_ERR,
 340         MR_EVT_ARGS_PD_LBA,
 341         MR_EVT_ARGS_PD_LBA_LD,
 342         MR_EVT_ARGS_PD_PROG,
 343         MR_EVT_ARGS_PD_STATE,
 344         MR_EVT_ARGS_PCI,
 345         MR_EVT_ARGS_RATE,
 346         MR_EVT_ARGS_STR,
 347         MR_EVT_ARGS_TIME,
 348         MR_EVT_ARGS_ECC,
 349         MR_EVT_ARGS_LD_PROP,
 350         MR_EVT_ARGS_PD_SPARE,
 351         MR_EVT_ARGS_PD_INDEX,
 352         MR_EVT_ARGS_DIAG_PASS,
 353         MR_EVT_ARGS_DIAG_FAIL,
 354         MR_EVT_ARGS_PD_LBA_LBA,
 355         MR_EVT_ARGS_PORT_PHY,
 356         MR_EVT_ARGS_PD_MISSING,
 357         MR_EVT_ARGS_PD_ADDRESS,
 358         MR_EVT_ARGS_BITMAP,
 359         MR_EVT_ARGS_CONNECTOR,
 360         MR_EVT_ARGS_PD_PD,
 361         MR_EVT_ARGS_PD_FRU,
 362         MR_EVT_ARGS_PD_PATHINFO,
 363         MR_EVT_ARGS_PD_POWER_STATE,
 364         MR_EVT_ARGS_GENERIC,
 365 };
 366
 367 /*
 368  * define constants for device list query options
 369  */
 370 enum MR_PD_QUERY_TYPE {
 371         MR_PD_QUERY_TYPE_ALL                = 0,
 372         MR_PD_QUERY_TYPE_STATE              = 1,
 373         MR_PD_QUERY_TYPE_POWER_STATE        = 2,
 374         MR_PD_QUERY_TYPE_MEDIA_TYPE         = 3,
 375         MR_PD_QUERY_TYPE_SPEED              = 4,
 376         MR_PD_QUERY_TYPE_EXPOSED_TO_HOST    = 5,
 377 };
 378
 379 enum MR_LD_QUERY_TYPE {
 380         MR_LD_QUERY_TYPE_ALL             = 0,
 381         MR_LD_QUERY_TYPE_EXPOSED_TO_HOST = 1,
 382         MR_LD_QUERY_TYPE_USED_TGT_IDS    = 2,
 383         MR_LD_QUERY_TYPE_CLUSTER_ACCESS  = 3,
 384         MR_LD_QUERY_TYPE_CLUSTER_LOCALE  = 4,
 385 };
 386
 387
 388 #define MR_EVT_CFG_CLEARED                              0x0004
 389 #define MR_EVT_LD_STATE_CHANGE                          0x0051
 390 #define MR_EVT_PD_INSERTED                              0x005b
 391 #define MR_EVT_PD_REMOVED                               0x0070
 392 #define MR_EVT_LD_CREATED                               0x008a
 393 #define MR_EVT_LD_DELETED                               0x008b
 394 #define MR_EVT_FOREIGN_CFG_IMPORTED                     0x00db
 395 #define MR_EVT_LD_OFFLINE                               0x00fc
 396 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED             0x0152
 397
 398 enum MR_PD_STATE {
 399         MR_PD_STATE_UNCONFIGURED_GOOD   = 0x00,
 400         MR_PD_STATE_UNCONFIGURED_BAD    = 0x01,
 401         MR_PD_STATE_HOT_SPARE           = 0x02,
 402         MR_PD_STATE_OFFLINE             = 0x10,
 403         MR_PD_STATE_FAILED              = 0x11,
 404         MR_PD_STATE_REBUILD             = 0x14,
 405         MR_PD_STATE_ONLINE              = 0x18,
 406         MR_PD_STATE_COPYBACK            = 0x20,
 407         MR_PD_STATE_SYSTEM              = 0x40,
 408  };
 409
 410
 411  /*
 412  * defines the physical drive address structure
 413  */
 414 struct MR_PD_ADDRESS {
 415         __le16  deviceId;
 416         u16     enclDeviceId;
 417
 418         union {
 419                 struct {
 420                         u8  enclIndex;
 421                         u8  slotNumber;
 422                 } mrPdAddress;
 423                 struct {
 424                         u8  enclPosition;
 425                         u8  enclConnectorIndex;
 426                 } mrEnclAddress;
 427         };
 428         u8      scsiDevType;
 429         union {
 430                 u8      connectedPortBitmap;
 431                 u8      connectedPortNumbers;
 432         };
 433         u64     sasAddr[2];
 434 } __packed;
 435
 436 /*
 437  * defines the physical drive list structure
 438  */
 439 struct MR_PD_LIST {
 440         __le32          size;
 441         __le32          count;
 442         struct MR_PD_ADDRESS   addr[1];
 443 } __packed;
 444
 445 struct megasas_pd_list {
 446         u16             tid;
 447         u8             driveType;
 448         u8             driveState;
 449 } __packed;
 450
 451  /*
 452  * defines the logical drive reference structure
 453  */
 454 union  MR_LD_REF {
 455         struct {
 456                 u8      targetId;
 457                 u8      reserved;
 458                 __le16     seqNum;
 459         };
 460         __le32     ref;
 461 } __packed;
 462
 463 /*
 464  * defines the logical drive list structure
 465  */
 466 struct MR_LD_LIST {
 467         __le32     ldCount;
 468         __le32     reserved;
 469         struct {
 470                 union MR_LD_REF   ref;
 471                 u8          state;
 472                 u8          reserved[3];
 473                 __le64          size;
 474         } ldList[MAX_LOGICAL_DRIVES_EXT];
 475 } __packed;
 476
 477 struct MR_LD_TARGETID_LIST {
 478         __le32  size;
 479         __le32  count;
 480         u8      pad[3];
 481         u8      targetId[MAX_LOGICAL_DRIVES_EXT];
 482 };
 483
 484
 485 /*
 486  * SAS controller properties
 487  */
 488 struct megasas_ctrl_prop {
 489
 490         u16 seq_num;
 491         u16 pred_fail_poll_interval;
 492         u16 intr_throttle_count;
 493         u16 intr_throttle_timeouts;
 494         u8 rebuild_rate;
 495         u8 patrol_read_rate;
 496         u8 bgi_rate;
 497         u8 cc_rate;
 498         u8 recon_rate;
 499         u8 cache_flush_interval;
 500         u8 spinup_drv_count;
 501         u8 spinup_delay;
 502         u8 cluster_enable;
 503         u8 coercion_mode;
 504         u8 alarm_enable;
 505         u8 disable_auto_rebuild;
 506         u8 disable_battery_warn;
 507         u8 ecc_bucket_size;
 508         u16 ecc_bucket_leak_rate;
 509         u8 restore_hotspare_on_insertion;
 510         u8 expose_encl_devices;
 511         u8 maintainPdFailHistory;
 512         u8 disallowHostRequestReordering;
 513         u8 abortCCOnError;
 514         u8 loadBalanceMode;
 515         u8 disableAutoDetectBackplane;
 516
 517         u8 snapVDSpace;
 518
 519         /*
 520         * Add properties that can be controlled by
 521         * a bit in the following structure.
 522         */
 523         struct {
 524 #if   defined(__BIG_ENDIAN_BITFIELD)
 525                 u32     reserved:18;
 526                 u32     enableJBOD:1;
 527                 u32     disableSpinDownHS:1;
 528                 u32     allowBootWithPinnedCache:1;
 529                 u32     disableOnlineCtrlReset:1;
 530                 u32     enableSecretKeyControl:1;
 531                 u32     autoEnhancedImport:1;
 532                 u32     enableSpinDownUnconfigured:1;
 533                 u32     SSDPatrolReadEnabled:1;
 534                 u32     SSDSMARTerEnabled:1;
 535                 u32     disableNCQ:1;
 536                 u32     useFdeOnly:1;
 537                 u32     prCorrectUnconfiguredAreas:1;
 538                 u32     SMARTerEnabled:1;
 539                 u32     copyBackDisabled:1;
 540 #else
 541                 u32     copyBackDisabled:1;
 542                 u32     SMARTerEnabled:1;
 543                 u32     prCorrectUnconfiguredAreas:1;
 544                 u32     useFdeOnly:1;
 545                 u32     disableNCQ:1;
 546                 u32     SSDSMARTerEnabled:1;
 547                 u32     SSDPatrolReadEnabled:1;
 548                 u32     enableSpinDownUnconfigured:1;
 549                 u32     autoEnhancedImport:1;
 550                 u32     enableSecretKeyControl:1;
 551                 u32     disableOnlineCtrlReset:1;
 552                 u32     allowBootWithPinnedCache:1;
 553                 u32     disableSpinDownHS:1;
 554                 u32     enableJBOD:1;
 555                 u32     reserved:18;
 556 #endif
 557         } OnOffProperties;
 558         u8 autoSnapVDSpace;
 559         u8 viewSpace;
 560         __le16 spinDownTime;
 561         u8  reserved[24];
 562 } __packed;
 563
 564 /*
 565  * SAS controller information
 566  */
 567 struct megasas_ctrl_info {
 568
 569         /*
 570          * PCI device information
 571          */
 572         struct {
 573
 574                 __le16 vendor_id;
 575                 __le16 device_id;
 576                 __le16 sub_vendor_id;
 577                 __le16 sub_device_id;
 578                 u8 reserved[24];
 579
 580         } __attribute__ ((packed)) pci;
 581
 582         /*
 583          * Host interface information
 584          */
 585         struct {
 586
 587                 u8 PCIX:1;
 588                 u8 PCIE:1;
 589                 u8 iSCSI:1;
 590                 u8 SAS_3G:1;
 591                 u8 SRIOV:1;
 592                 u8 reserved_0:3;
 593                 u8 reserved_1[6];
 594                 u8 port_count;
 595                 u64 port_addr[8];
 596
 597         } __attribute__ ((packed)) host_interface;
 598
 599         /*
 600          * Device (backend) interface information
 601          */
 602         struct {
 603
 604                 u8 SPI:1;
 605                 u8 SAS_3G:1;
 606                 u8 SATA_1_5G:1;
 607                 u8 SATA_3G:1;
 608                 u8 reserved_0:4;
 609                 u8 reserved_1[6];
 610                 u8 port_count;
 611                 u64 port_addr[8];
 612
 613         } __attribute__ ((packed)) device_interface;
 614
 615         /*
 616          * List of components residing in flash. All str are null terminated
 617          */
 618         __le32 image_check_word;
 619         __le32 image_component_count;
 620
 621         struct {
 622
 623                 char name[8];
 624                 char version[32];
 625                 char build_date[16];
 626                 char built_time[16];
 627
 628         } __attribute__ ((packed)) image_component[8];
 629
 630         /*
 631          * List of flash components that have been flashed on the card, but
 632          * are not in use, pending reset of the adapter. This list will be
 633          * empty if a flash operation has not occurred. All stings are null
 634          * terminated
 635          */
 636         __le32 pending_image_component_count;
 637
 638         struct {
 639
 640                 char name[8];
 641                 char version[32];
 642                 char build_date[16];
 643                 char build_time[16];
 644
 645         } __attribute__ ((packed)) pending_image_component[8];
 646
 647         u8 max_arms;
 648         u8 max_spans;
 649         u8 max_arrays;
 650         u8 max_lds;
 651
 652         char product_name[80];
 653         char serial_no[32];
 654
 655         /*
 656          * Other physical/controller/operation information. Indicates the
 657          * presence of the hardware
 658          */
 659         struct {
 660
 661                 u32 bbu:1;
 662                 u32 alarm:1;
 663                 u32 nvram:1;
 664                 u32 uart:1;
 665                 u32 reserved:28;
 666
 667         } __attribute__ ((packed)) hw_present;
 668
 669         __le32 current_fw_time;
 670
 671         /*
 672          * Maximum data transfer sizes
 673          */
 674         __le16 max_concurrent_cmds;
 675         __le16 max_sge_count;
 676         __le32 max_request_size;
 677
 678         /*
 679          * Logical and physical device counts
 680          */
 681         __le16 ld_present_count;
 682         __le16 ld_degraded_count;
 683         __le16 ld_offline_count;
 684
 685         __le16 pd_present_count;
 686         __le16 pd_disk_present_count;
 687         __le16 pd_disk_pred_failure_count;
 688         __le16 pd_disk_failed_count;
 689
 690         /*
 691          * Memory size information
 692          */
 693         __le16 nvram_size;
 694         __le16 memory_size;
 695         __le16 flash_size;
 696
 697         /*
 698          * Error counters
 699          */
 700         __le16 mem_correctable_error_count;
 701         __le16 mem_uncorrectable_error_count;
 702
 703         /*
 704          * Cluster information
 705          */
 706         u8 cluster_permitted;
 707         u8 cluster_active;
 708
 709         /*
 710          * Additional max data transfer sizes
 711          */
 712         __le16 max_strips_per_io;
 713
 714         /*
 715          * Controller capabilities structures
 716          */
 717         struct {
 718
 719                 u32 raid_level_0:1;
 720                 u32 raid_level_1:1;
 721                 u32 raid_level_5:1;
 722                 u32 raid_level_1E:1;
 723                 u32 raid_level_6:1;
 724                 u32 reserved:27;
 725
 726         } __attribute__ ((packed)) raid_levels;
 727
 728         struct {
 729
 730                 u32 rbld_rate:1;
 731                 u32 cc_rate:1;
 732                 u32 bgi_rate:1;
 733                 u32 recon_rate:1;
 734                 u32 patrol_rate:1;
 735                 u32 alarm_control:1;
 736                 u32 cluster_supported:1;
 737                 u32 bbu:1;
 738                 u32 spanning_allowed:1;
 739                 u32 dedicated_hotspares:1;
 740                 u32 revertible_hotspares:1;
 741                 u32 foreign_config_import:1;
 742                 u32 self_diagnostic:1;
 743                 u32 mixed_redundancy_arr:1;
 744                 u32 global_hot_spares:1;
 745                 u32 reserved:17;
 746
 747         } __attribute__ ((packed)) adapter_operations;
 748
 749         struct {
 750
 751                 u32 read_policy:1;
 752                 u32 write_policy:1;
 753                 u32 io_policy:1;
 754                 u32 access_policy:1;
 755                 u32 disk_cache_policy:1;
 756                 u32 reserved:27;
 757
 758         } __attribute__ ((packed)) ld_operations;
 759
 760         struct {
 761
 762                 u8 min;
 763                 u8 max;
 764                 u8 reserved[2];
 765
 766         } __attribute__ ((packed)) stripe_sz_ops;
 767
 768         struct {
 769
 770                 u32 force_online:1;
 771                 u32 force_offline:1;
 772                 u32 force_rebuild:1;
 773                 u32 reserved:29;
 774
 775         } __attribute__ ((packed)) pd_operations;
 776
 777         struct {
 778
 779                 u32 ctrl_supports_sas:1;
 780                 u32 ctrl_supports_sata:1;
 781                 u32 allow_mix_in_encl:1;
 782                 u32 allow_mix_in_ld:1;
 783                 u32 allow_sata_in_cluster:1;
 784                 u32 reserved:27;
 785
 786         } __attribute__ ((packed)) pd_mix_support;
 787
 788         /*
 789          * Define ECC single-bit-error bucket information
 790          */
 791         u8 ecc_bucket_count;
 792         u8 reserved_2[11];
 793
 794         /*
 795          * Include the controller properties (changeable items)
 796          */
 797         struct megasas_ctrl_prop properties;
 798
 799         /*
 800          * Define FW pkg version (set in envt v'bles on OEM basis)
 801          */
 802         char package_version[0x60];
 803
 804
 805         /*
 806         * If adapterOperations.supportMoreThan8Phys is set,
 807         * and deviceInterface.portCount is greater than 8,
 808         * SAS Addrs for first 8 ports shall be populated in
 809         * deviceInterface.portAddr, and the rest shall be
 810         * populated in deviceInterfacePortAddr2.
 811         */
 812         __le64      deviceInterfacePortAddr2[8]; /*6a0h */
 813         u8          reserved3[128];              /*6e0h */
 814
 815         struct {                                /*760h */
 816                 u16 minPdRaidLevel_0:4;
 817                 u16 maxPdRaidLevel_0:12;
 818
 819                 u16 minPdRaidLevel_1:4;
 820                 u16 maxPdRaidLevel_1:12;
 821
 822                 u16 minPdRaidLevel_5:4;
 823                 u16 maxPdRaidLevel_5:12;
 824
 825                 u16 minPdRaidLevel_1E:4;
 826                 u16 maxPdRaidLevel_1E:12;
 827
 828                 u16 minPdRaidLevel_6:4;
 829                 u16 maxPdRaidLevel_6:12;
 830
 831                 u16 minPdRaidLevel_10:4;
 832                 u16 maxPdRaidLevel_10:12;
 833
 834                 u16 minPdRaidLevel_50:4;
 835                 u16 maxPdRaidLevel_50:12;
 836
 837                 u16 minPdRaidLevel_60:4;
 838                 u16 maxPdRaidLevel_60:12;
 839
 840                 u16 minPdRaidLevel_1E_RLQ0:4;
 841                 u16 maxPdRaidLevel_1E_RLQ0:12;
 842
 843                 u16 minPdRaidLevel_1E0_RLQ0:4;
 844                 u16 maxPdRaidLevel_1E0_RLQ0:12;
 845
 846                 u16 reserved[6];
 847         } pdsForRaidLevels;
 848
 849         __le16 maxPds;                          /*780h */
 850         __le16 maxDedHSPs;                      /*782h */
 851         __le16 maxGlobalHSP;                    /*784h */
 852         __le16 ddfSize;                         /*786h */
 853         u8  maxLdsPerArray;                     /*788h */
 854         u8  partitionsInDDF;                    /*789h */
 855         u8  lockKeyBinding;                     /*78ah */
 856         u8  maxPITsPerLd;                       /*78bh */
 857         u8  maxViewsPerLd;                      /*78ch */
 858         u8  maxTargetId;                        /*78dh */
 859         __le16 maxBvlVdSize;                    /*78eh */
 860
 861         __le16 maxConfigurableSSCSize;          /*790h */
 862         __le16 currentSSCsize;                  /*792h */
 863
 864         char    expanderFwVersion[12];          /*794h */
 865
 866         __le16 PFKTrialTimeRemaining;           /*7A0h */
 867
 868         __le16 cacheMemorySize;                 /*7A2h */
 869
 870         struct {                                /*7A4h */
 871 #if   defined(__BIG_ENDIAN_BITFIELD)
 872                 u32     reserved:5;
 873                 u32     activePassive:2;
 874                 u32     supportConfigAutoBalance:1;
 875                 u32     mpio:1;
 876                 u32     supportDataLDonSSCArray:1;
 877                 u32     supportPointInTimeProgress:1;
 878                 u32     supportUnevenSpans:1;
 879                 u32     dedicatedHotSparesLimited:1;
 880                 u32     headlessMode:1;
 881                 u32     supportEmulatedDrives:1;
 882                 u32     supportResetNow:1;
 883                 u32     realTimeScheduler:1;
 884                 u32     supportSSDPatrolRead:1;
 885                 u32     supportPerfTuning:1;
 886                 u32     disableOnlinePFKChange:1;
 887                 u32     supportJBOD:1;
 888                 u32     supportBootTimePFKChange:1;
 889                 u32     supportSetLinkSpeed:1;
 890                 u32     supportEmergencySpares:1;
 891                 u32     supportSuspendResumeBGops:1;
 892                 u32     blockSSDWriteCacheChange:1;
 893                 u32     supportShieldState:1;
 894                 u32     supportLdBBMInfo:1;
 895                 u32     supportLdPIType3:1;
 896                 u32     supportLdPIType2:1;
 897                 u32     supportLdPIType1:1;
 898                 u32     supportPIcontroller:1;
 899 #else
 900                 u32     supportPIcontroller:1;
 901                 u32     supportLdPIType1:1;
 902                 u32     supportLdPIType2:1;
 903                 u32     supportLdPIType3:1;
 904                 u32     supportLdBBMInfo:1;
 905                 u32     supportShieldState:1;
 906                 u32     blockSSDWriteCacheChange:1;
 907                 u32     supportSuspendResumeBGops:1;
 908                 u32     supportEmergencySpares:1;
 909                 u32     supportSetLinkSpeed:1;
 910                 u32     supportBootTimePFKChange:1;
 911                 u32     supportJBOD:1;
 912                 u32     disableOnlinePFKChange:1;
 913                 u32     supportPerfTuning:1;
 914                 u32     supportSSDPatrolRead:1;
 915                 u32     realTimeScheduler:1;
 916
 917                 u32     supportResetNow:1;
 918                 u32     supportEmulatedDrives:1;
 919                 u32     headlessMode:1;
 920                 u32     dedicatedHotSparesLimited:1;
 921
 922
 923                 u32     supportUnevenSpans:1;
 924                 u32     supportPointInTimeProgress:1;
 925                 u32     supportDataLDonSSCArray:1;
 926                 u32     mpio:1;
 927                 u32     supportConfigAutoBalance:1;
 928                 u32     activePassive:2;
 929                 u32     reserved:5;
 930 #endif
 931         } adapterOperations2;
 932
 933         u8  driverVersion[32];                  /*7A8h */
 934         u8  maxDAPdCountSpinup60;               /*7C8h */
 935         u8  temperatureROC;                     /*7C9h */
 936         u8  temperatureCtrl;                    /*7CAh */
 937         u8  reserved4;                          /*7CBh */
 938         __le16 maxConfigurablePds;              /*7CCh */
 939
 940
 941         u8  reserved5[2];                       /*0x7CDh */
 942
 943         /*
 944         * HA cluster information
 945         */
 946         struct {
 947 #if defined(__BIG_ENDIAN_BITFIELD)
 948                 u32     reserved:26;
 949                 u32     premiumFeatureMismatch:1;
 950                 u32     ctrlPropIncompatible:1;
 951                 u32     fwVersionMismatch:1;
 952                 u32     hwIncompatible:1;
 953                 u32     peerIsIncompatible:1;
 954                 u32     peerIsPresent:1;
 955 #else
 956                 u32     peerIsPresent:1;
 957                 u32     peerIsIncompatible:1;
 958                 u32     hwIncompatible:1;
 959                 u32     fwVersionMismatch:1;
 960                 u32     ctrlPropIncompatible:1;
 961                 u32     premiumFeatureMismatch:1;
 962                 u32     reserved:26;
 963 #endif
 964         } cluster;
 965
 966         char clusterId[16];                     /*7D4h */
 967         struct {
 968                 u8  maxVFsSupported;            /*0x7E4*/
 969                 u8  numVFsEnabled;              /*0x7E5*/
 970                 u8  requestorId;                /*0x7E6 0:PF, 1:VF1, 2:VF2*/
 971                 u8  reserved;                   /*0x7E7*/
 972         } iov;
 973
 974         struct {
 975 #if defined(__BIG_ENDIAN_BITFIELD)
 976                 u32     reserved:12;
 977                 u32     discardCacheDuringLDDelete:1;
 978                 u32     supportSecurityonJBOD:1;
 979                 u32     supportCacheBypassModes:1;
 980                 u32     supportDisableSESMonitoring:1;
 981                 u32     supportForceFlash:1;
 982                 u32     supportNVDRAM:1;
 983                 u32     supportDrvActivityLEDSetting:1;
 984                 u32     supportAllowedOpsforDrvRemoval:1;
 985                 u32     supportHOQRebuild:1;
 986                 u32     supportForceTo512e:1;
 987                 u32     supportNVCacheErase:1;
 988                 u32     supportDebugQueue:1;
 989                 u32     supportSwZone:1;
 990                 u32     supportCrashDump:1;
 991                 u32     supportMaxExtLDs:1;
 992                 u32     supportT10RebuildAssist:1;
 993                 u32     supportDisableImmediateIO:1;
 994                 u32     supportThermalPollInterval:1;
 995                 u32     supportPersonalityChange:2;
 996 #else
 997                 u32     supportPersonalityChange:2;
 998                 u32     supportThermalPollInterval:1;
 999                 u32     supportDisableImmediateIO:1;
1000                 u32     supportT10RebuildAssist:1;
1001                 u32     supportMaxExtLDs:1;
1002                 u32     supportCrashDump:1;
1003                 u32     supportSwZone:1;
1004                 u32     supportDebugQueue:1;
1005                 u32     supportNVCacheErase:1;
1006                 u32     supportForceTo512e:1;
1007                 u32     supportHOQRebuild:1;
1008                 u32     supportAllowedOpsforDrvRemoval:1;
1009                 u32     supportDrvActivityLEDSetting:1;
1010                 u32     supportNVDRAM:1;
1011                 u32     supportForceFlash:1;
1012                 u32     supportDisableSESMonitoring:1;
1013                 u32     supportCacheBypassModes:1;
1014                 u32     supportSecurityonJBOD:1;
1015                 u32     discardCacheDuringLDDelete:1;
1016                 u32     reserved:12;
1017 #endif
1018         } adapterOperations3;
1019
1020         u8          pad[0x800-0x7EC];
1021 } __packed;
1022
1023 /*
1024  * ===============================
1025  * MegaRAID SAS driver definitions
1026  * ===============================
1027  */
1028 #define MEGASAS_MAX_PD_CHANNELS                 2
1029 #define MEGASAS_MAX_LD_CHANNELS                 2
1030 #define MEGASAS_MAX_CHANNELS                    (MEGASAS_MAX_PD_CHANNELS + \
1031                                                 MEGASAS_MAX_LD_CHANNELS)
1032 #define MEGASAS_MAX_DEV_PER_CHANNEL             128
1033 #define MEGASAS_DEFAULT_INIT_ID                 -1
1034 #define MEGASAS_MAX_LUN                         8
1035 #define MEGASAS_DEFAULT_CMD_PER_LUN             256
1036 #define MEGASAS_MAX_PD                          (MEGASAS_MAX_PD_CHANNELS * \
1037                                                 MEGASAS_MAX_DEV_PER_CHANNEL)
1038 #define MEGASAS_MAX_LD_IDS                      (MEGASAS_MAX_LD_CHANNELS * \
1039                                                 MEGASAS_MAX_DEV_PER_CHANNEL)
1040
1041 #define MEGASAS_MAX_SECTORS                    (2*1024)
1042 #define MEGASAS_MAX_SECTORS_IEEE                (2*128)
1043 #define MEGASAS_DBG_LVL                         1
1044
1045 #define MEGASAS_FW_BUSY                         1
1046
1047 #define VD_EXT_DEBUG 0
1048
1049
1050 enum MR_SCSI_CMD_TYPE {
1051         READ_WRITE_LDIO = 0,
1052         NON_READ_WRITE_LDIO = 1,
1053         READ_WRITE_SYSPDIO = 2,
1054         NON_READ_WRITE_SYSPDIO = 3,
1055 };
1056
1057 /* Frame Type */
1058 #define IO_FRAME                                0
1059 #define PTHRU_FRAME                             1
1060
1061 /*
1062  * When SCSI mid-layer calls driver's reset routine, driver waits for
1063  * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note
1064  * that the driver cannot _actually_ abort or reset pending commands. While
1065  * it is waiting for the commands to complete, it prints a diagnostic message
1066  * every MEGASAS_RESET_NOTICE_INTERVAL seconds
1067  */
1068 #define MEGASAS_RESET_WAIT_TIME                 180
1069 #define MEGASAS_INTERNAL_CMD_WAIT_TIME          180
1070 #define MEGASAS_RESET_NOTICE_INTERVAL           5
1071 #define MEGASAS_IOCTL_CMD                       0
1072 #define MEGASAS_DEFAULT_CMD_TIMEOUT             90
1073 #define MEGASAS_THROTTLE_QUEUE_DEPTH            16
1074 #define MEGASAS_BLOCKED_CMD_TIMEOUT             60
1075 /*
1076  * FW reports the maximum of number of commands that it can accept (maximum
1077  * commands that can be outstanding) at any time. The driver must report a
1078  * lower number to the mid layer because it can issue a few internal commands
1079  * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs
1080  * is shown below
1081  */
1082 #define MEGASAS_INT_CMDS                        32
1083 #define MEGASAS_SKINNY_INT_CMDS                 5
1084 #define MEGASAS_FUSION_INTERNAL_CMDS            5
1085 #define MEGASAS_FUSION_IOCTL_CMDS               3
1086 #define MEGASAS_MFI_IOCTL_CMDS                  27
1087
1088 #define MEGASAS_MAX_MSIX_QUEUES                 128
1089 /*
1090  * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
1091  * SGLs based on the size of dma_addr_t
1092  */
1093 #define IS_DMA64                                (sizeof(dma_addr_t) == 8)
1094
1095 #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT                0x00000001
1096
1097 #define MFI_INTR_FLAG_REPLY_MESSAGE                     0x00000001
1098 #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE             0x00000002
1099 #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT       0x00000004
1100
1101 #define MFI_OB_INTR_STATUS_MASK                 0x00000002
1102 #define MFI_POLL_TIMEOUT_SECS                   60
1103 #define MEGASAS_SRIOV_HEARTBEAT_INTERVAL_VF     (5 * HZ)
1104 #define MEGASAS_OCR_SETTLE_TIME_VF              (1000 * 30)
1105 #define MEGASAS_ROUTINE_WAIT_TIME_VF            300
1106 #define MFI_REPLY_1078_MESSAGE_INTERRUPT        0x80000000
1107 #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT        0x00000001
1108 #define MFI_GEN2_ENABLE_INTERRUPT_MASK          (0x00000001 | 0x00000004)
1109 #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT      0x40000000
1110 #define MFI_SKINNY_ENABLE_INTERRUPT_MASK        (0x00000001)
1111
1112 #define MFI_1068_PCSR_OFFSET                    0x84
1113 #define MFI_1068_FW_HANDSHAKE_OFFSET            0x64
1114 #define MFI_1068_FW_READY                       0xDDDD0000
1115
1116 #define MR_MAX_REPLY_QUEUES_OFFSET              0X0000001F
1117 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET          0X003FC000
1118 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT    14
1119 #define MR_MAX_MSIX_REG_ARRAY                   16
1120 /*
1121 * register set for both 1068 and 1078 controllers
1122 * structure extended for 1078 registers
1123 */
1124
1125 struct megasas_register_set {
1126         u32     doorbell;                       /*0000h*/
1127         u32     fusion_seq_offset;              /*0004h*/
1128         u32     fusion_host_diag;               /*0008h*/
1129         u32     reserved_01;                    /*000Ch*/
1130
1131         u32     inbound_msg_0;                  /*0010h*/
1132         u32     inbound_msg_1;                  /*0014h*/
1133         u32     outbound_msg_0;                 /*0018h*/
1134         u32     outbound_msg_1;                 /*001Ch*/
1135
1136         u32     inbound_doorbell;               /*0020h*/
1137         u32     inbound_intr_status;            /*0024h*/
1138         u32     inbound_intr_mask;              /*0028h*/
1139
1140         u32     outbound_doorbell;              /*002Ch*/
1141         u32     outbound_intr_status;           /*0030h*/
1142         u32     outbound_intr_mask;             /*0034h*/
1143
1144         u32     reserved_1[2];                  /*0038h*/
1145
1146         u32     inbound_queue_port;             /*0040h*/
1147         u32     outbound_queue_port;            /*0044h*/
1148
1149         u32     reserved_2[9];                  /*0048h*/
1150         u32     reply_post_host_index;          /*006Ch*/
1151         u32     reserved_2_2[12];               /*0070h*/
1152
1153         u32     outbound_doorbell_clear;        /*00A0h*/
1154
1155         u32     reserved_3[3];                  /*00A4h*/
1156
1157         u32     outbound_scratch_pad ;          /*00B0h*/
1158         u32     outbound_scratch_pad_2;         /*00B4h*/
1159
1160         u32     reserved_4[2];                  /*00B8h*/
1161
1162         u32     inbound_low_queue_port ;        /*00C0h*/
1163
1164         u32     inbound_high_queue_port ;       /*00C4h*/
1165
1166         u32     reserved_5;                     /*00C8h*/
1167         u32     res_6[11];                      /*CCh*/
1168         u32     host_diag;
1169         u32     seq_offset;
1170         u32     index_registers[807];           /*00CCh*/
1171 } __attribute__ ((packed));
1172
1173 struct megasas_sge32 {
1174
1175         __le32 phys_addr;
1176         __le32 length;
1177
1178 } __attribute__ ((packed));
1179
1180 struct megasas_sge64 {
1181
1182         __le64 phys_addr;
1183         __le32 length;
1184
1185 } __attribute__ ((packed));
1186
1187 struct megasas_sge_skinny {
1188         __le64 phys_addr;
1189         __le32 length;
1190         __le32 flag;
1191 } __packed;
1192
1193 union megasas_sgl {
1194
1195         struct megasas_sge32 sge32[1];
1196         struct megasas_sge64 sge64[1];
1197         struct megasas_sge_skinny sge_skinny[1];
1198
1199 } __attribute__ ((packed));
1200
1201 struct megasas_header {
1202
1203         u8 cmd;                 /*00h */
1204         u8 sense_len;           /*01h */
1205         u8 cmd_status;          /*02h */
1206         u8 scsi_status;         /*03h */
1207
1208         u8 target_id;           /*04h */
1209         u8 lun;                 /*05h */
1210         u8 cdb_len;             /*06h */
1211         u8 sge_count;           /*07h */
1212
1213         __le32 context;         /*08h */
1214         __le32 pad_0;           /*0Ch */
1215
1216         __le16 flags;           /*10h */
1217         __le16 timeout;         /*12h */
1218         __le32 data_xferlen;    /*14h */
1219
1220 } __attribute__ ((packed));
1221
1222 union megasas_sgl_frame {
1223
1224         struct megasas_sge32 sge32[8];
1225         struct megasas_sge64 sge64[5];
1226
1227 } __attribute__ ((packed));
1228
1229 typedef union _MFI_CAPABILITIES {
1230         struct {
1231 #if   defined(__BIG_ENDIAN_BITFIELD)
1232                 u32     reserved:25;
1233                 u32     security_protocol_cmds_fw:1;
1234                 u32     support_core_affinity:1;
1235                 u32     support_ndrive_r1_lb:1;
1236                 u32     support_max_255lds:1;
1237                 u32     support_fastpath_wb:1;
1238                 u32     support_additional_msix:1;
1239                 u32     support_fp_remote_lun:1;
1240 #else
1241                 u32     support_fp_remote_lun:1;
1242                 u32     support_additional_msix:1;
1243                 u32     support_fastpath_wb:1;
1244                 u32     support_max_255lds:1;
1245                 u32     support_ndrive_r1_lb:1;
1246                 u32     support_core_affinity:1;
1247                 u32     security_protocol_cmds_fw:1;
1248                 u32     reserved:25;
1249 #endif
1250         } mfi_capabilities;
1251         __le32          reg;
1252 } MFI_CAPABILITIES;
1253
1254 struct megasas_init_frame {
1255
1256         u8 cmd;                 /*00h */
1257         u8 reserved_0;          /*01h */
1258         u8 cmd_status;          /*02h */
1259
1260         u8 reserved_1;          /*03h */
1261         MFI_CAPABILITIES driver_operations; /*04h*/
1262
1263         __le32 context;         /*08h */
1264         __le32 pad_0;           /*0Ch */
1265
1266         __le16 flags;           /*10h */
1267         __le16 reserved_3;              /*12h */
1268         __le32 data_xfer_len;   /*14h */
1269
1270         __le32 queue_info_new_phys_addr_lo;     /*18h */
1271         __le32 queue_info_new_phys_addr_hi;     /*1Ch */
1272         __le32 queue_info_old_phys_addr_lo;     /*20h */
1273         __le32 queue_info_old_phys_addr_hi;     /*24h */
1274         __le32 reserved_4[2];   /*28h */
1275         __le32 system_info_lo;      /*30h */
1276         __le32 system_info_hi;      /*34h */
1277         __le32 reserved_5[2];   /*38h */
1278
1279 } __attribute__ ((packed));
1280
1281 struct megasas_init_queue_info {
1282
1283         __le32 init_flags;              /*00h */
1284         __le32 reply_queue_entries;     /*04h */
1285
1286         __le32 reply_queue_start_phys_addr_lo;  /*08h */
1287         __le32 reply_queue_start_phys_addr_hi;  /*0Ch */
1288         __le32 producer_index_phys_addr_lo;     /*10h */
1289         __le32 producer_index_phys_addr_hi;     /*14h */
1290         __le32 consumer_index_phys_addr_lo;     /*18h */
1291         __le32 consumer_index_phys_addr_hi;     /*1Ch */
1292
1293 } __attribute__ ((packed));
1294
1295 struct megasas_io_frame {
1296
1297         u8 cmd;                 /*00h */
1298         u8 sense_len;           /*01h */
1299         u8 cmd_status;          /*02h */
1300         u8 scsi_status;         /*03h */
1301
1302         u8 target_id;           /*04h */
1303         u8 access_byte;         /*05h */
1304         u8 reserved_0;          /*06h */
1305         u8 sge_count;           /*07h */
1306
1307         __le32 context;         /*08h */
1308         __le32 pad_0;           /*0Ch */
1309
1310         __le16 flags;           /*10h */
1311         __le16 timeout;         /*12h */
1312         __le32 lba_count;       /*14h */
1313
1314         __le32 sense_buf_phys_addr_lo;  /*18h */
1315         __le32 sense_buf_phys_addr_hi;  /*1Ch */
1316
1317         __le32 start_lba_lo;    /*20h */
1318         __le32 start_lba_hi;    /*24h */
1319
1320         union megasas_sgl sgl;  /*28h */
1321
1322 } __attribute__ ((packed));
1323
1324 struct megasas_pthru_frame {
1325
1326         u8 cmd;                 /*00h */
1327         u8 sense_len;           /*01h */
1328         u8 cmd_status;          /*02h */
1329         u8 scsi_status;         /*03h */
1330
1331         u8 target_id;           /*04h */
1332         u8 lun;                 /*05h */
1333         u8 cdb_len;             /*06h */
1334         u8 sge_count;           /*07h */
1335
1336         __le32 context;         /*08h */
1337         __le32 pad_0;           /*0Ch */
1338
1339         __le16 flags;           /*10h */
1340         __le16 timeout;         /*12h */
1341         __le32 data_xfer_len;   /*14h */
1342
1343         __le32 sense_buf_phys_addr_lo;  /*18h */
1344         __le32 sense_buf_phys_addr_hi;  /*1Ch */
1345
1346         u8 cdb[16];             /*20h */
1347         union megasas_sgl sgl;  /*30h */
1348
1349 } __attribute__ ((packed));
1350
1351 struct megasas_dcmd_frame {
1352
1353         u8 cmd;                 /*00h */
1354         u8 reserved_0;          /*01h */
1355         u8 cmd_status;          /*02h */
1356         u8 reserved_1[4];       /*03h */
1357         u8 sge_count;           /*07h */
1358
1359         __le32 context;         /*08h */
1360         __le32 pad_0;           /*0Ch */
1361
1362         __le16 flags;           /*10h */
1363         __le16 timeout;         /*12h */
1364
1365         __le32 data_xfer_len;   /*14h */
1366         __le32 opcode;          /*18h */
1367
1368         union {                 /*1Ch */
1369                 u8 b[12];
1370                 __le16 s[6];
1371                 __le32 w[3];
1372         } mbox;
1373
1374         union megasas_sgl sgl;  /*28h */
1375
1376 } __attribute__ ((packed));
1377
1378 struct megasas_abort_frame {
1379
1380         u8 cmd;                 /*00h */
1381         u8 reserved_0;          /*01h */
1382         u8 cmd_status;          /*02h */
1383
1384         u8 reserved_1;          /*03h */
1385         __le32 reserved_2;      /*04h */
1386
1387         __le32 context;         /*08h */
1388         __le32 pad_0;           /*0Ch */
1389
1390         __le16 flags;           /*10h */
1391         __le16 reserved_3;      /*12h */
1392         __le32 reserved_4;      /*14h */
1393
1394         __le32 abort_context;   /*18h */
1395         __le32 pad_1;           /*1Ch */
1396
1397         __le32 abort_mfi_phys_addr_lo;  /*20h */
1398         __le32 abort_mfi_phys_addr_hi;  /*24h */
1399
1400         __le32 reserved_5[6];   /*28h */
1401
1402 } __attribute__ ((packed));
1403
1404 struct megasas_smp_frame {
1405
1406         u8 cmd;                 /*00h */
1407         u8 reserved_1;          /*01h */
1408         u8 cmd_status;          /*02h */
1409         u8 connection_status;   /*03h */
1410
1411         u8 reserved_2[3];       /*04h */
1412         u8 sge_count;           /*07h */
1413
1414         __le32 context;         /*08h */
1415         __le32 pad_0;           /*0Ch */
1416
1417         __le16 flags;           /*10h */
1418         __le16 timeout;         /*12h */
1419
1420         __le32 data_xfer_len;   /*14h */
1421         __le64 sas_addr;        /*18h */
1422
1423         union {
1424                 struct megasas_sge32 sge32[2];  /* [0]: resp [1]: req */
1425                 struct megasas_sge64 sge64[2];  /* [0]: resp [1]: req */
1426         } sgl;
1427
1428 } __attribute__ ((packed));
1429
1430 struct megasas_stp_frame {
1431
1432         u8 cmd;                 /*00h */
1433         u8 reserved_1;          /*01h */
1434         u8 cmd_status;          /*02h */
1435         u8 reserved_2;          /*03h */
1436
1437         u8 target_id;           /*04h */
1438         u8 reserved_3[2];       /*05h */
1439         u8 sge_count;           /*07h */
1440
1441         __le32 context;         /*08h */
1442         __le32 pad_0;           /*0Ch */
1443
1444         __le16 flags;           /*10h */
1445         __le16 timeout;         /*12h */
1446
1447         __le32 data_xfer_len;   /*14h */
1448
1449         __le16 fis[10];         /*18h */
1450         __le32 stp_flags;
1451
1452         union {
1453                 struct megasas_sge32 sge32[2];  /* [0]: resp [1]: data */
1454                 struct megasas_sge64 sge64[2];  /* [0]: resp [1]: data */
1455         } sgl;
1456
1457 } __attribute__ ((packed));
1458
1459 union megasas_frame {
1460
1461         struct megasas_header hdr;
1462         struct megasas_init_frame init;
1463         struct megasas_io_frame io;
1464         struct megasas_pthru_frame pthru;
1465         struct megasas_dcmd_frame dcmd;
1466         struct megasas_abort_frame abort;
1467         struct megasas_smp_frame smp;
1468         struct megasas_stp_frame stp;
1469
1470         u8 raw_bytes[64];
1471 };
1472
1473 struct megasas_cmd;
1474
1475 union megasas_evt_class_locale {
1476
1477         struct {
1478 #ifndef __BIG_ENDIAN_BITFIELD
1479                 u16 locale;
1480                 u8 reserved;
1481                 s8 class;
1482 #else
1483                 s8 class;
1484                 u8 reserved;
1485                 u16 locale;
1486 #endif
1487         } __attribute__ ((packed)) members;
1488
1489         u32 word;
1490
1491 } __attribute__ ((packed));
1492
1493 struct megasas_evt_log_info {
1494         __le32 newest_seq_num;
1495         __le32 oldest_seq_num;
1496         __le32 clear_seq_num;
1497         __le32 shutdown_seq_num;
1498         __le32 boot_seq_num;
1499
1500 } __attribute__ ((packed));
1501
1502 struct megasas_progress {
1503
1504         __le16 progress;
1505         __le16 elapsed_seconds;
1506
1507 } __attribute__ ((packed));
1508
1509 struct megasas_evtarg_ld {
1510
1511         u16 target_id;
1512         u8 ld_index;
1513         u8 reserved;
1514
1515 } __attribute__ ((packed));
1516
1517 struct megasas_evtarg_pd {
1518         u16 device_id;
1519         u8 encl_index;
1520         u8 slot_number;
1521
1522 } __attribute__ ((packed));
1523
1524 struct megasas_evt_detail {
1525
1526         __le32 seq_num;
1527         __le32 time_stamp;
1528         __le32 code;
1529         union megasas_evt_class_locale cl;
1530         u8 arg_type;
1531         u8 reserved1[15];
1532
1533         union {
1534                 struct {
1535                         struct megasas_evtarg_pd pd;
1536                         u8 cdb_length;
1537                         u8 sense_length;
1538                         u8 reserved[2];
1539                         u8 cdb[16];
1540                         u8 sense[64];
1541                 } __attribute__ ((packed)) cdbSense;
1542
1543                 struct megasas_evtarg_ld ld;
1544
1545                 struct {
1546                         struct megasas_evtarg_ld ld;
1547                         __le64 count;
1548                 } __attribute__ ((packed)) ld_count;
1549
1550                 struct {
1551                         __le64 lba;
1552                         struct megasas_evtarg_ld ld;
1553                 } __attribute__ ((packed)) ld_lba;
1554
1555                 struct {
1556                         struct megasas_evtarg_ld ld;
1557                         __le32 prevOwner;
1558                         __le32 newOwner;
1559                 } __attribute__ ((packed)) ld_owner;
1560
1561                 struct {
1562                         u64 ld_lba;
1563                         u64 pd_lba;
1564                         struct megasas_evtarg_ld ld;
1565                         struct megasas_evtarg_pd pd;
1566                 } __attribute__ ((packed)) ld_lba_pd_lba;
1567
1568                 struct {
1569                         struct megasas_evtarg_ld ld;
1570                         struct megasas_progress prog;
1571                 } __attribute__ ((packed)) ld_prog;
1572
1573                 struct {
1574                         struct megasas_evtarg_ld ld;
1575                         u32 prev_state;
1576                         u32 new_state;
1577                 } __attribute__ ((packed)) ld_state;
1578
1579                 struct {
1580                         u64 strip;
1581                         struct megasas_evtarg_ld ld;
1582                 } __attribute__ ((packed)) ld_strip;
1583
1584                 struct megasas_evtarg_pd pd;
1585
1586                 struct {
1587                         struct megasas_evtarg_pd pd;
1588                         u32 err;
1589                 } __attribute__ ((packed)) pd_err;
1590
1591                 struct {
1592                         u64 lba;
1593                         struct megasas_evtarg_pd pd;
1594                 } __attribute__ ((packed)) pd_lba;
1595
1596                 struct {
1597                         u64 lba;
1598                         struct megasas_evtarg_pd pd;
1599                         struct megasas_evtarg_ld ld;
1600                 } __attribute__ ((packed)) pd_lba_ld;
1601
1602                 struct {
1603                         struct megasas_evtarg_pd pd;
1604                         struct megasas_progress prog;
1605                 } __attribute__ ((packed)) pd_prog;
1606
1607                 struct {
1608                         struct megasas_evtarg_pd pd;
1609                         u32 prevState;
1610                         u32 newState;
1611                 } __attribute__ ((packed)) pd_state;
1612
1613                 struct {
1614                         u16 vendorId;
1615                         __le16 deviceId;
1616                         u16 subVendorId;
1617                         u16 subDeviceId;
1618                 } __attribute__ ((packed)) pci;
1619
1620                 u32 rate;
1621                 char str[96];
1622
1623                 struct {
1624                         u32 rtc;
1625                         u32 elapsedSeconds;
1626                 } __attribute__ ((packed)) time;
1627
1628                 struct {
1629                         u32 ecar;
1630                         u32 elog;
1631                         char str[64];
1632                 } __attribute__ ((packed)) ecc;
1633
1634                 u8 b[96];
1635                 __le16 s[48];
1636                 __le32 w[24];
1637                 __le64 d[12];
1638         } args;
1639
1640         char description[128];
1641
1642 } __attribute__ ((packed));
1643
1644 struct megasas_aen_event {
1645         struct delayed_work hotplug_work;
1646         struct megasas_instance *instance;
1647 };
1648
1649 struct megasas_irq_context {
1650         struct megasas_instance *instance;
1651         u32 MSIxIndex;
1652 };
1653
1654 struct MR_DRV_SYSTEM_INFO {
1655         u8      infoVersion;
1656         u8      systemIdLength;
1657         u16     reserved0;
1658         u8      systemId[64];
1659         u8      reserved[1980];
1660 };
1661
1662 struct megasas_instance {
1663
1664         __le32 *producer;
1665         dma_addr_t producer_h;
1666         __le32 *consumer;
1667         dma_addr_t consumer_h;
1668         struct MR_DRV_SYSTEM_INFO *system_info_buf;
1669         dma_addr_t system_info_h;
1670         struct MR_LD_VF_AFFILIATION *vf_affiliation;
1671         dma_addr_t vf_affiliation_h;
1672         struct MR_LD_VF_AFFILIATION_111 *vf_affiliation_111;
1673         dma_addr_t vf_affiliation_111_h;
1674         struct MR_CTRL_HB_HOST_MEM *hb_host_mem;
1675         dma_addr_t hb_host_mem_h;
1676
1677         __le32 *reply_queue;
1678         dma_addr_t reply_queue_h;
1679
1680         u32 *crash_dump_buf;
1681         dma_addr_t crash_dump_h;
1682         void *crash_buf[MAX_CRASH_DUMP_SIZE];
1683         u32 crash_buf_pages;
1684         unsigned int    fw_crash_buffer_size;
1685         unsigned int    fw_crash_state;
1686         unsigned int    fw_crash_buffer_offset;
1687         u32 drv_buf_index;
1688         u32 drv_buf_alloc;
1689         u32 crash_dump_fw_support;
1690         u32 crash_dump_drv_support;
1691         u32 crash_dump_app_support;
1692         u32 secure_jbod_support;
1693         spinlock_t crashdump_lock;
1694
1695         struct megasas_register_set __iomem *reg_set;
1696         u32 __iomem *reply_post_host_index_addr[MR_MAX_MSIX_REG_ARRAY];
1697         struct megasas_pd_list          pd_list[MEGASAS_MAX_PD];
1698         struct megasas_pd_list          local_pd_list[MEGASAS_MAX_PD];
1699         u8 ld_ids[MEGASAS_MAX_LD_IDS];
1700         s8 init_id;
1701
1702         u16 max_num_sge;
1703         u16 max_fw_cmds;
1704         u16 max_mfi_cmds;
1705         u16 max_scsi_cmds;
1706         u32 max_sectors_per_req;
1707         struct megasas_aen_event *ev;
1708
1709         struct megasas_cmd **cmd_list;
1710         struct list_head cmd_pool;
1711         /* used to sync fire the cmd to fw */
1712         spinlock_t mfi_pool_lock;
1713         /* used to sync fire the cmd to fw */
1714         spinlock_t hba_lock;
1715         /* used to synch producer, consumer ptrs in dpc */
1716         spinlock_t completion_lock;
1717         struct dma_pool *frame_dma_pool;
1718         struct dma_pool *sense_dma_pool;
1719
1720         struct megasas_evt_detail *evt_detail;
1721         dma_addr_t evt_detail_h;
1722         struct megasas_cmd *aen_cmd;
1723         struct mutex aen_mutex;
1724         struct semaphore ioctl_sem;
1725
1726         struct Scsi_Host *host;
1727
1728         wait_queue_head_t int_cmd_wait_q;
1729         wait_queue_head_t abort_cmd_wait_q;
1730
1731         struct pci_dev *pdev;
1732         u32 unique_id;
1733         u32 fw_support_ieee;
1734
1735         atomic_t fw_outstanding;
1736         atomic_t fw_reset_no_pci_access;
1737
1738         struct megasas_instance_template *instancet;
1739         struct tasklet_struct isr_tasklet;
1740         struct work_struct work_init;
1741         struct work_struct crash_init;
1742
1743         u8 flag;
1744         u8 unload;
1745         u8 flag_ieee;
1746         u8 issuepend_done;
1747         u8 disableOnlineCtrlReset;
1748         u8 UnevenSpanSupport;
1749
1750         u8 supportmax256vd;
1751         u16 fw_supported_vd_count;
1752         u16 fw_supported_pd_count;
1753
1754         u16 drv_supported_vd_count;
1755         u16 drv_supported_pd_count;
1756
1757         u8 adprecovery;
1758         unsigned long last_time;
1759         u32 mfiStatus;
1760         u32 last_seq_num;
1761
1762         struct list_head internal_reset_pending_q;
1763
1764         /* Ptr to hba specific information */
1765         void *ctrl_context;
1766         u32 ctrl_context_pages;
1767         struct megasas_ctrl_info *ctrl_info;
1768         unsigned int msix_vectors;
1769         struct msix_entry msixentry[MEGASAS_MAX_MSIX_QUEUES];
1770         struct megasas_irq_context irq_context[MEGASAS_MAX_MSIX_QUEUES];
1771         u64 map_id;
1772         struct megasas_cmd *map_update_cmd;
1773         unsigned long bar;
1774         long reset_flags;
1775         struct mutex reset_mutex;
1776         struct timer_list sriov_heartbeat_timer;
1777         char skip_heartbeat_timer_del;
1778         u8 requestorId;
1779         char PlasmaFW111;
1780         char mpio;
1781         u16 throttlequeuedepth;
1782         u8 mask_interrupts;
1783         u8 is_imr;
1784         bool dev_handle;
1785 };
1786 struct MR_LD_VF_MAP {
1787         u32 size;
1788         union MR_LD_REF ref;
1789         u8 ldVfCount;
1790         u8 reserved[6];
1791         u8 policy[1];
1792 };
1793
1794 struct MR_LD_VF_AFFILIATION {
1795         u32 size;
1796         u8 ldCount;
1797         u8 vfCount;
1798         u8 thisVf;
1799         u8 reserved[9];
1800         struct MR_LD_VF_MAP map[1];
1801 };
1802
1803 /* Plasma 1.11 FW backward compatibility structures */
1804 #define IOV_111_OFFSET 0x7CE
1805 #define MAX_VIRTUAL_FUNCTIONS 8
1806 #define MR_LD_ACCESS_HIDDEN 15
1807
1808 struct IOV_111 {
1809         u8 maxVFsSupported;
1810         u8 numVFsEnabled;
1811         u8 requestorId;
1812         u8 reserved[5];
1813 };
1814
1815 struct MR_LD_VF_MAP_111 {
1816         u8 targetId;
1817         u8 reserved[3];
1818         u8 policy[MAX_VIRTUAL_FUNCTIONS];
1819 };
1820
1821 struct MR_LD_VF_AFFILIATION_111 {
1822         u8 vdCount;
1823         u8 vfCount;
1824         u8 thisVf;
1825         u8 reserved[5];
1826         struct MR_LD_VF_MAP_111 map[MAX_LOGICAL_DRIVES];
1827 };
1828
1829 struct MR_CTRL_HB_HOST_MEM {
1830         struct {
1831                 u32 fwCounter;  /* Firmware heart beat counter */
1832                 struct {
1833                         u32 debugmode:1; /* 1=Firmware is in debug mode.
1834                                             Heart beat will not be updated. */
1835                         u32 reserved:31;
1836                 } debug;
1837                 u32 reserved_fw[6];
1838                 u32 driverCounter; /* Driver heart beat counter.  0x20 */
1839                 u32 reserved_driver[7];
1840         } HB;
1841         u8 pad[0x400-0x40];
1842 };
1843
1844 enum {
1845         MEGASAS_HBA_OPERATIONAL                 = 0,
1846         MEGASAS_ADPRESET_SM_INFAULT             = 1,
1847         MEGASAS_ADPRESET_SM_FW_RESET_SUCCESS    = 2,
1848         MEGASAS_ADPRESET_SM_OPERATIONAL         = 3,
1849         MEGASAS_HW_CRITICAL_ERROR               = 4,
1850         MEGASAS_ADPRESET_SM_POLLING             = 5,
1851         MEGASAS_ADPRESET_INPROG_SIGN            = 0xDEADDEAD,
1852 };
1853
1854 struct megasas_instance_template {
1855         void (*fire_cmd)(struct megasas_instance *, dma_addr_t, \
1856                 u32, struct megasas_register_set __iomem *);
1857
1858         void (*enable_intr)(struct megasas_instance *);
1859         void (*disable_intr)(struct megasas_instance *);
1860
1861         int (*clear_intr)(struct megasas_register_set __iomem *);
1862
1863         u32 (*read_fw_status_reg)(struct megasas_register_set __iomem *);
1864         int (*adp_reset)(struct megasas_instance *, \
1865                 struct megasas_register_set __iomem *);
1866         int (*check_reset)(struct megasas_instance *, \
1867                 struct megasas_register_set __iomem *);
1868         irqreturn_t (*service_isr)(int irq, void *devp);
1869         void (*tasklet)(unsigned long);
1870         u32 (*init_adapter)(struct megasas_instance *);
1871         u32 (*build_and_issue_cmd) (struct megasas_instance *,
1872                                     struct scsi_cmnd *);
1873         void (*issue_dcmd) (struct megasas_instance *instance,
1874                             struct megasas_cmd *cmd);
1875 };
1876
1877 #define MEGASAS_IS_LOGICAL(scp)                                         \
1878         (scp->device->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1
1879
1880 #define MEGASAS_DEV_INDEX(scp)                                          \
1881         (((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) +   \
1882         scp->device->id)
1883
1884 #define MEGASAS_PD_INDEX(scp)                                           \
1885         ((scp->device->channel * MEGASAS_MAX_DEV_PER_CHANNEL) +         \
1886         scp->device->id)
1887
1888 struct megasas_cmd {
1889
1890         union megasas_frame *frame;
1891         dma_addr_t frame_phys_addr;
1892         u8 *sense;
1893         dma_addr_t sense_phys_addr;
1894
1895         u32 index;
1896         u8 sync_cmd;
1897         u8 cmd_status;
1898         u8 abort_aen;
1899         u8 retry_for_fw_reset;
1900
1901
1902         struct list_head list;
1903         struct scsi_cmnd *scmd;
1904         u8 flags;
1905
1906         struct megasas_instance *instance;
1907         union {
1908                 struct {
1909                         u16 smid;
1910                         u16 resvd;
1911                 } context;
1912                 u32 frame_count;
1913         };
1914 };
1915
1916 #define MAX_MGMT_ADAPTERS               1024
1917 #define MAX_IOCTL_SGE                   16
1918
1919 struct megasas_iocpacket {
1920
1921         u16 host_no;
1922         u16 __pad1;
1923         u32 sgl_off;
1924         u32 sge_count;
1925         u32 sense_off;
1926         u32 sense_len;
1927         union {
1928                 u8 raw[128];
1929                 struct megasas_header hdr;
1930         } frame;
1931
1932         struct iovec sgl[MAX_IOCTL_SGE];
1933
1934 } __attribute__ ((packed));
1935
1936 struct megasas_aen {
1937         u16 host_no;
1938         u16 __pad1;
1939         u32 seq_num;
1940         u32 class_locale_word;
1941 } __attribute__ ((packed));
1942
1943 #ifdef CONFIG_COMPAT
1944 struct compat_megasas_iocpacket {
1945         u16 host_no;
1946         u16 __pad1;
1947         u32 sgl_off;
1948         u32 sge_count;
1949         u32 sense_off;
1950         u32 sense_len;
1951         union {
1952                 u8 raw[128];
1953                 struct megasas_header hdr;
1954         } frame;
1955         struct compat_iovec sgl[MAX_IOCTL_SGE];
1956 } __attribute__ ((packed));
1957
1958 #define MEGASAS_IOC_FIRMWARE32  _IOWR('M', 1, struct compat_megasas_iocpacket)
1959 #endif
1960
1961 #define MEGASAS_IOC_FIRMWARE    _IOWR('M', 1, struct megasas_iocpacket)
1962 #define MEGASAS_IOC_GET_AEN     _IOW('M', 3, struct megasas_aen)
1963
1964 struct megasas_mgmt_info {
1965
1966         u16 count;
1967         struct megasas_instance *instance[MAX_MGMT_ADAPTERS];
1968         int max_index;
1969 };
1970
1971 u8
1972 MR_BuildRaidContext(struct megasas_instance *instance,
1973                     struct IO_REQUEST_INFO *io_info,
1974                     struct RAID_CONTEXT *pRAID_Context,
1975                     struct MR_DRV_RAID_MAP_ALL *map, u8 **raidLUN);
1976 u8 MR_TargetIdToLdGet(u32 ldTgtId, struct MR_DRV_RAID_MAP_ALL *map);
1977 struct MR_LD_RAID *MR_LdRaidGet(u32 ld, struct MR_DRV_RAID_MAP_ALL *map);
1978 u16 MR_ArPdGet(u32 ar, u32 arm, struct MR_DRV_RAID_MAP_ALL *map);
1979 u16 MR_LdSpanArrayGet(u32 ld, u32 span, struct MR_DRV_RAID_MAP_ALL *map);
1980 __le16 MR_PdDevHandleGet(u32 pd, struct MR_DRV_RAID_MAP_ALL *map);
1981 u16 MR_GetLDTgtId(u32 ld, struct MR_DRV_RAID_MAP_ALL *map);
1982
1983 __le16 get_updated_dev_handle(struct megasas_instance *instance,
1984         struct LD_LOAD_BALANCE_INFO *lbInfo, struct IO_REQUEST_INFO *in_info);
1985 void mr_update_load_balance_params(struct MR_DRV_RAID_MAP_ALL *map,
1986         struct LD_LOAD_BALANCE_INFO *lbInfo);
1987 int megasas_get_ctrl_info(struct megasas_instance *instance);
1988 int megasas_set_crash_dump_params(struct megasas_instance *instance,
1989         u8 crash_buf_state);
1990 void megasas_free_host_crash_buffer(struct megasas_instance *instance);
1991 void megasas_fusion_crash_dump_wq(struct work_struct *work);
1992
1993 void megasas_return_cmd_fusion(struct megasas_instance *instance,
1994         struct megasas_cmd_fusion *cmd);
1995 int megasas_issue_blocked_cmd(struct megasas_instance *instance,
1996         struct megasas_cmd *cmd, int timeout);
1997 void __megasas_return_cmd(struct megasas_instance *instance,
1998         struct megasas_cmd *cmd);
1999
2000 void megasas_return_mfi_mpt_pthr(struct megasas_instance *instance,
2001         struct megasas_cmd *cmd_mfi, struct megasas_cmd_fusion *cmd_fusion);
2002 int megasas_cmd_type(struct scsi_cmnd *cmd);
2003
2004 #endif                          /*LSI_MEGARAID_SAS_H */