2 * This is the Fusion MPT base driver providing common API layer interface
3 * for access to MPT (Message Passing Technology) firmware.
5 * This code is based on drivers/scsi/mpt3sas/mpt3sas_base.c
6 * Copyright (C) 2012-2014 LSI Corporation
7 * Copyright (C) 2013-2014 Avago Technologies
8 * (mailto: MPT-FusionLinux.pdl@avagotech.com)
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version 2
13 * of the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
21 * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
22 * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
23 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
24 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
25 * solely responsible for determining the appropriateness of using and
26 * distributing the Program and assumes all risks associated with its
27 * exercise of rights under this Agreement, including but not limited to
28 * the risks and costs of program errors, damage to or loss of data,
29 * programs or equipment, and unavailability or interruption of operations.
31 * DISCLAIMER OF LIABILITY
32 * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
33 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34 * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
35 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
36 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
37 * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
38 * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
40 * You should have received a copy of the GNU General Public License
41 * along with this program; if not, write to the Free Software
42 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
46 #include <linux/kernel.h>
47 #include <linux/module.h>
48 #include <linux/errno.h>
49 #include <linux/init.h>
50 #include <linux/slab.h>
51 #include <linux/types.h>
52 #include <linux/pci.h>
53 #include <linux/kdev_t.h>
54 #include <linux/blkdev.h>
55 #include <linux/delay.h>
56 #include <linux/interrupt.h>
57 #include <linux/dma-mapping.h>
59 #include <linux/time.h>
60 #include <linux/ktime.h>
61 #include <linux/kthread.h>
62 #include <asm/page.h> /* To get host page size per arch */
63 #include <linux/aer.h>
66 #include "mpt3sas_base.h"
68 static MPT_CALLBACK mpt_callbacks[MPT_MAX_CALLBACKS];
71 #define FAULT_POLLING_INTERVAL 1000 /* in milliseconds */
73 /* maximum controller queue depth */
74 #define MAX_HBA_QUEUE_DEPTH 30000
75 #define MAX_CHAIN_DEPTH 100000
76 static int max_queue_depth = -1;
77 module_param(max_queue_depth, int, 0);
78 MODULE_PARM_DESC(max_queue_depth, " max controller queue depth ");
80 static int max_sgl_entries = -1;
81 module_param(max_sgl_entries, int, 0);
82 MODULE_PARM_DESC(max_sgl_entries, " max sg entries ");
84 static int msix_disable = -1;
85 module_param(msix_disable, int, 0);
86 MODULE_PARM_DESC(msix_disable, " disable msix routed interrupts (default=0)");
88 static int smp_affinity_enable = 1;
89 module_param(smp_affinity_enable, int, S_IRUGO);
90 MODULE_PARM_DESC(smp_affinity_enable, "SMP affinity feature enable/disable Default: enable(1)");
92 static int max_msix_vectors = -1;
93 module_param(max_msix_vectors, int, 0);
94 MODULE_PARM_DESC(max_msix_vectors,
97 static int mpt3sas_fwfault_debug;
98 MODULE_PARM_DESC(mpt3sas_fwfault_debug,
99 " enable detection of firmware fault and halt firmware - (default=0)");
102 _base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc);
105 * mpt3sas_base_check_cmd_timeout - Function
106 * to check timeout and command termination due
109 * @ioc: per adapter object.
110 * @status: Status of issued command.
111 * @mpi_request:mf request pointer.
112 * @sz: size of buffer.
114 * @Returns - 1/0 Reset to be done or Not
117 mpt3sas_base_check_cmd_timeout(struct MPT3SAS_ADAPTER *ioc,
118 u8 status, void *mpi_request, int sz)
122 if (!(status & MPT3_CMD_RESET))
125 ioc_err(ioc, "Command %s\n",
126 issue_reset == 0 ? "terminated due to Host Reset" : "Timeout");
127 _debug_dump_mf(mpi_request, sz);
133 * _scsih_set_fwfault_debug - global setting of ioc->fwfault_debug.
140 _scsih_set_fwfault_debug(const char *val, const struct kernel_param *kp)
142 int ret = param_set_int(val, kp);
143 struct MPT3SAS_ADAPTER *ioc;
148 /* global ioc spinlock to protect controller list on list operations */
149 pr_info("setting fwfault_debug(%d)\n", mpt3sas_fwfault_debug);
150 spin_lock(&gioc_lock);
151 list_for_each_entry(ioc, &mpt3sas_ioc_list, list)
152 ioc->fwfault_debug = mpt3sas_fwfault_debug;
153 spin_unlock(&gioc_lock);
156 module_param_call(mpt3sas_fwfault_debug, _scsih_set_fwfault_debug,
157 param_get_int, &mpt3sas_fwfault_debug, 0644);
160 * _base_readl_aero - retry readl for max three times.
161 * @addr - MPT Fusion system interface register address
163 * Retry the readl() for max three times if it gets zero value
164 * while reading the system interface register.
167 _base_readl_aero(const volatile void __iomem *addr)
172 ret_val = readl(addr);
174 } while (ret_val == 0 && i < 3);
180 _base_readl(const volatile void __iomem *addr)
186 * _base_clone_reply_to_sys_mem - copies reply to reply free iomem
189 * @ioc: per adapter object
190 * @reply: reply message frame(lower 32bit addr)
191 * @index: System request message index.
194 _base_clone_reply_to_sys_mem(struct MPT3SAS_ADAPTER *ioc, u32 reply,
198 * 256 is offset within sys register.
199 * 256 offset MPI frame starts. Max MPI frame supported is 32.
200 * 32 * 128 = 4K. From here, Clone of reply free for mcpu starts
202 u16 cmd_credit = ioc->facts.RequestCredit + 1;
203 void __iomem *reply_free_iomem = (void __iomem *)ioc->chip +
204 MPI_FRAME_START_OFFSET +
205 (cmd_credit * ioc->request_sz) + (index * sizeof(u32));
207 writel(reply, reply_free_iomem);
211 * _base_clone_mpi_to_sys_mem - Writes/copies MPI frames
212 * to system/BAR0 region.
214 * @dst_iomem: Pointer to the destination location in BAR0 space.
215 * @src: Pointer to the Source data.
216 * @size: Size of data to be copied.
219 _base_clone_mpi_to_sys_mem(void *dst_iomem, void *src, u32 size)
222 u32 *src_virt_mem = (u32 *)src;
224 for (i = 0; i < size/4; i++)
225 writel((u32)src_virt_mem[i],
226 (void __iomem *)dst_iomem + (i * 4));
230 * _base_clone_to_sys_mem - Writes/copies data to system/BAR0 region
232 * @dst_iomem: Pointer to the destination location in BAR0 space.
233 * @src: Pointer to the Source data.
234 * @size: Size of data to be copied.
237 _base_clone_to_sys_mem(void __iomem *dst_iomem, void *src, u32 size)
240 u32 *src_virt_mem = (u32 *)(src);
242 for (i = 0; i < size/4; i++)
243 writel((u32)src_virt_mem[i],
244 (void __iomem *)dst_iomem + (i * 4));
248 * _base_get_chain - Calculates and Returns virtual chain address
249 * for the provided smid in BAR0 space.
251 * @ioc: per adapter object
252 * @smid: system request message index
253 * @sge_chain_count: Scatter gather chain count.
255 * Return: the chain address.
257 static inline void __iomem*
258 _base_get_chain(struct MPT3SAS_ADAPTER *ioc, u16 smid,
261 void __iomem *base_chain, *chain_virt;
262 u16 cmd_credit = ioc->facts.RequestCredit + 1;
264 base_chain = (void __iomem *)ioc->chip + MPI_FRAME_START_OFFSET +
265 (cmd_credit * ioc->request_sz) +
266 REPLY_FREE_POOL_SIZE;
267 chain_virt = base_chain + (smid * ioc->facts.MaxChainDepth *
268 ioc->request_sz) + (sge_chain_count * ioc->request_sz);
273 * _base_get_chain_phys - Calculates and Returns physical address
274 * in BAR0 for scatter gather chains, for
277 * @ioc: per adapter object
278 * @smid: system request message index
279 * @sge_chain_count: Scatter gather chain count.
281 * Return: Physical chain address.
283 static inline phys_addr_t
284 _base_get_chain_phys(struct MPT3SAS_ADAPTER *ioc, u16 smid,
287 phys_addr_t base_chain_phys, chain_phys;
288 u16 cmd_credit = ioc->facts.RequestCredit + 1;
290 base_chain_phys = ioc->chip_phys + MPI_FRAME_START_OFFSET +
291 (cmd_credit * ioc->request_sz) +
292 REPLY_FREE_POOL_SIZE;
293 chain_phys = base_chain_phys + (smid * ioc->facts.MaxChainDepth *
294 ioc->request_sz) + (sge_chain_count * ioc->request_sz);
299 * _base_get_buffer_bar0 - Calculates and Returns BAR0 mapped Host
300 * buffer address for the provided smid.
301 * (Each smid can have 64K starts from 17024)
303 * @ioc: per adapter object
304 * @smid: system request message index
306 * Return: Pointer to buffer location in BAR0.
309 static void __iomem *
310 _base_get_buffer_bar0(struct MPT3SAS_ADAPTER *ioc, u16 smid)
312 u16 cmd_credit = ioc->facts.RequestCredit + 1;
313 // Added extra 1 to reach end of chain.
314 void __iomem *chain_end = _base_get_chain(ioc,
316 ioc->facts.MaxChainDepth);
317 return chain_end + (smid * 64 * 1024);
321 * _base_get_buffer_phys_bar0 - Calculates and Returns BAR0 mapped
322 * Host buffer Physical address for the provided smid.
323 * (Each smid can have 64K starts from 17024)
325 * @ioc: per adapter object
326 * @smid: system request message index
328 * Return: Pointer to buffer location in BAR0.
331 _base_get_buffer_phys_bar0(struct MPT3SAS_ADAPTER *ioc, u16 smid)
333 u16 cmd_credit = ioc->facts.RequestCredit + 1;
334 phys_addr_t chain_end_phys = _base_get_chain_phys(ioc,
336 ioc->facts.MaxChainDepth);
337 return chain_end_phys + (smid * 64 * 1024);
341 * _base_get_chain_buffer_dma_to_chain_buffer - Iterates chain
342 * lookup list and Provides chain_buffer
343 * address for the matching dma address.
344 * (Each smid can have 64K starts from 17024)
346 * @ioc: per adapter object
347 * @chain_buffer_dma: Chain buffer dma address.
349 * Return: Pointer to chain buffer. Or Null on Failure.
352 _base_get_chain_buffer_dma_to_chain_buffer(struct MPT3SAS_ADAPTER *ioc,
353 dma_addr_t chain_buffer_dma)
356 struct chain_tracker *ct;
358 for (index = 0; index < ioc->scsiio_depth; index++) {
359 for (j = 0; j < ioc->chains_needed_per_io; j++) {
360 ct = &ioc->chain_lookup[index].chains_per_smid[j];
361 if (ct && ct->chain_buffer_dma == chain_buffer_dma)
362 return ct->chain_buffer;
365 ioc_info(ioc, "Provided chain_buffer_dma address is not in the lookup list\n");
370 * _clone_sg_entries - MPI EP's scsiio and config requests
371 * are handled here. Base function for
372 * double buffering, before submitting
375 * @ioc: per adapter object.
376 * @mpi_request: mf request pointer.
377 * @smid: system request message index.
379 static void _clone_sg_entries(struct MPT3SAS_ADAPTER *ioc,
380 void *mpi_request, u16 smid)
382 Mpi2SGESimple32_t *sgel, *sgel_next;
383 u32 sgl_flags, sge_chain_count = 0;
386 void __iomem *buffer_iomem;
387 phys_addr_t buffer_iomem_phys;
388 void __iomem *buff_ptr;
389 phys_addr_t buff_ptr_phys;
390 void __iomem *dst_chain_addr[MCPU_MAX_CHAINS_PER_IO];
391 void *src_chain_addr[MCPU_MAX_CHAINS_PER_IO];
392 phys_addr_t dst_addr_phys;
393 MPI2RequestHeader_t *request_hdr;
394 struct scsi_cmnd *scmd;
395 struct scatterlist *sg_scmd = NULL;
396 int is_scsiio_req = 0;
398 request_hdr = (MPI2RequestHeader_t *) mpi_request;
400 if (request_hdr->Function == MPI2_FUNCTION_SCSI_IO_REQUEST) {
401 Mpi25SCSIIORequest_t *scsiio_request =
402 (Mpi25SCSIIORequest_t *)mpi_request;
403 sgel = (Mpi2SGESimple32_t *) &scsiio_request->SGL;
405 } else if (request_hdr->Function == MPI2_FUNCTION_CONFIG) {
406 Mpi2ConfigRequest_t *config_req =
407 (Mpi2ConfigRequest_t *)mpi_request;
408 sgel = (Mpi2SGESimple32_t *) &config_req->PageBufferSGE;
412 /* From smid we can get scsi_cmd, once we have sg_scmd,
413 * we just need to get sg_virt and sg_next to get virual
414 * address associated with sgel->Address.
418 /* Get scsi_cmd using smid */
419 scmd = mpt3sas_scsih_scsi_lookup_get(ioc, smid);
421 ioc_err(ioc, "scmd is NULL\n");
425 /* Get sg_scmd from scmd provided */
426 sg_scmd = scsi_sglist(scmd);
430 * 0 - 255 System register
431 * 256 - 4352 MPI Frame. (This is based on maxCredit 32)
432 * 4352 - 4864 Reply_free pool (512 byte is reserved
433 * considering maxCredit 32. Reply need extra
434 * room, for mCPU case kept four times of
436 * 4864 - 17152 SGE chain element. (32cmd * 3 chain of
437 * 128 byte size = 12288)
438 * 17152 - x Host buffer mapped with smid.
439 * (Each smid can have 64K Max IO.)
440 * BAR0+Last 1K MSIX Addr and Data
441 * Total size in use 2113664 bytes of 4MB BAR0
444 buffer_iomem = _base_get_buffer_bar0(ioc, smid);
445 buffer_iomem_phys = _base_get_buffer_phys_bar0(ioc, smid);
447 buff_ptr = buffer_iomem;
448 buff_ptr_phys = buffer_iomem_phys;
449 WARN_ON(buff_ptr_phys > U32_MAX);
451 if (le32_to_cpu(sgel->FlagsLength) &
452 (MPI2_SGE_FLAGS_HOST_TO_IOC << MPI2_SGE_FLAGS_SHIFT))
455 for (i = 0; i < MPT_MIN_PHYS_SEGMENTS + ioc->facts.MaxChainDepth; i++) {
458 (le32_to_cpu(sgel->FlagsLength) >> MPI2_SGE_FLAGS_SHIFT);
460 switch (sgl_flags & MPI2_SGE_FLAGS_ELEMENT_MASK) {
461 case MPI2_SGE_FLAGS_CHAIN_ELEMENT:
463 * Helper function which on passing
464 * chain_buffer_dma returns chain_buffer. Get
465 * the virtual address for sgel->Address
468 _base_get_chain_buffer_dma_to_chain_buffer(ioc,
469 le32_to_cpu(sgel->Address));
470 if (sgel_next == NULL)
473 * This is coping 128 byte chain
474 * frame (not a host buffer)
476 dst_chain_addr[sge_chain_count] =
478 smid, sge_chain_count);
479 src_chain_addr[sge_chain_count] =
481 dst_addr_phys = _base_get_chain_phys(ioc,
482 smid, sge_chain_count);
483 WARN_ON(dst_addr_phys > U32_MAX);
485 cpu_to_le32(lower_32_bits(dst_addr_phys));
489 case MPI2_SGE_FLAGS_SIMPLE_ELEMENT:
492 _base_clone_to_sys_mem(buff_ptr,
494 (le32_to_cpu(sgel->FlagsLength) &
497 * FIXME: this relies on a a zero
501 cpu_to_le32((u32)buff_ptr_phys);
503 _base_clone_to_sys_mem(buff_ptr,
505 (le32_to_cpu(sgel->FlagsLength) &
508 cpu_to_le32((u32)buff_ptr_phys);
511 buff_ptr += (le32_to_cpu(sgel->FlagsLength) &
513 buff_ptr_phys += (le32_to_cpu(sgel->FlagsLength) &
515 if ((le32_to_cpu(sgel->FlagsLength) &
516 (MPI2_SGE_FLAGS_END_OF_BUFFER
517 << MPI2_SGE_FLAGS_SHIFT)))
518 goto eob_clone_chain;
521 * Every single element in MPT will have
522 * associated sg_next. Better to sanity that
523 * sg_next is not NULL, but it will be a bug
527 sg_scmd = sg_next(sg_scmd);
531 goto eob_clone_chain;
539 for (i = 0; i < sge_chain_count; i++) {
541 _base_clone_to_sys_mem(dst_chain_addr[i],
542 src_chain_addr[i], ioc->request_sz);
547 * mpt3sas_remove_dead_ioc_func - kthread context to remove dead ioc
548 * @arg: input argument, used to derive ioc
551 * 0 if controller is removed from pci subsystem.
554 static int mpt3sas_remove_dead_ioc_func(void *arg)
556 struct MPT3SAS_ADAPTER *ioc = (struct MPT3SAS_ADAPTER *)arg;
557 struct pci_dev *pdev;
565 pci_stop_and_remove_bus_device_locked(pdev);
570 * _base_fault_reset_work - workq handling ioc fault conditions
571 * @work: input argument, used to derive ioc
576 _base_fault_reset_work(struct work_struct *work)
578 struct MPT3SAS_ADAPTER *ioc =
579 container_of(work, struct MPT3SAS_ADAPTER, fault_reset_work.work);
583 struct task_struct *p;
586 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
587 if (ioc->shost_recovery || ioc->pci_error_recovery)
589 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
591 doorbell = mpt3sas_base_get_iocstate(ioc, 0);
592 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_MASK) {
593 ioc_err(ioc, "SAS host is non-operational !!!!\n");
595 /* It may be possible that EEH recovery can resolve some of
596 * pci bus failure issues rather removing the dead ioc function
597 * by considering controller is in a non-operational state. So
598 * here priority is given to the EEH recovery. If it doesn't
599 * not resolve this issue, mpt3sas driver will consider this
600 * controller to non-operational state and remove the dead ioc
603 if (ioc->non_operational_loop++ < 5) {
604 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock,
610 * Call _scsih_flush_pending_cmds callback so that we flush all
611 * pending commands back to OS. This call is required to aovid
612 * deadlock at block layer. Dead IOC will fail to do diag reset,
613 * and this call is safe since dead ioc will never return any
614 * command back from HW.
616 ioc->schedule_dead_ioc_flush_running_cmds(ioc);
618 * Set remove_host flag early since kernel thread will
619 * take some time to execute.
621 ioc->remove_host = 1;
622 /*Remove the Dead Host */
623 p = kthread_run(mpt3sas_remove_dead_ioc_func, ioc,
624 "%s_dead_ioc_%d", ioc->driver_name, ioc->id);
626 ioc_err(ioc, "%s: Running mpt3sas_dead_ioc thread failed !!!!\n",
629 ioc_err(ioc, "%s: Running mpt3sas_dead_ioc thread success !!!!\n",
631 return; /* don't rearm timer */
634 ioc->non_operational_loop = 0;
636 if ((doorbell & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL) {
637 rc = mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER);
638 ioc_warn(ioc, "%s: hard reset: %s\n",
639 __func__, rc == 0 ? "success" : "failed");
640 doorbell = mpt3sas_base_get_iocstate(ioc, 0);
641 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
642 mpt3sas_base_fault_info(ioc, doorbell &
643 MPI2_DOORBELL_DATA_MASK);
644 if (rc && (doorbell & MPI2_IOC_STATE_MASK) !=
645 MPI2_IOC_STATE_OPERATIONAL)
646 return; /* don't rearm timer */
649 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
651 if (ioc->fault_reset_work_q)
652 queue_delayed_work(ioc->fault_reset_work_q,
653 &ioc->fault_reset_work,
654 msecs_to_jiffies(FAULT_POLLING_INTERVAL));
655 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
659 * mpt3sas_base_start_watchdog - start the fault_reset_work_q
660 * @ioc: per adapter object
665 mpt3sas_base_start_watchdog(struct MPT3SAS_ADAPTER *ioc)
669 if (ioc->fault_reset_work_q)
672 /* initialize fault polling */
674 INIT_DELAYED_WORK(&ioc->fault_reset_work, _base_fault_reset_work);
675 snprintf(ioc->fault_reset_work_q_name,
676 sizeof(ioc->fault_reset_work_q_name), "poll_%s%d_status",
677 ioc->driver_name, ioc->id);
678 ioc->fault_reset_work_q =
679 create_singlethread_workqueue(ioc->fault_reset_work_q_name);
680 if (!ioc->fault_reset_work_q) {
681 ioc_err(ioc, "%s: failed (line=%d)\n", __func__, __LINE__);
684 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
685 if (ioc->fault_reset_work_q)
686 queue_delayed_work(ioc->fault_reset_work_q,
687 &ioc->fault_reset_work,
688 msecs_to_jiffies(FAULT_POLLING_INTERVAL));
689 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
693 * mpt3sas_base_stop_watchdog - stop the fault_reset_work_q
694 * @ioc: per adapter object
699 mpt3sas_base_stop_watchdog(struct MPT3SAS_ADAPTER *ioc)
702 struct workqueue_struct *wq;
704 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
705 wq = ioc->fault_reset_work_q;
706 ioc->fault_reset_work_q = NULL;
707 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
709 if (!cancel_delayed_work_sync(&ioc->fault_reset_work))
711 destroy_workqueue(wq);
716 * mpt3sas_base_fault_info - verbose translation of firmware FAULT code
717 * @ioc: per adapter object
718 * @fault_code: fault code
721 mpt3sas_base_fault_info(struct MPT3SAS_ADAPTER *ioc , u16 fault_code)
723 ioc_err(ioc, "fault_state(0x%04x)!\n", fault_code);
727 * mpt3sas_halt_firmware - halt's mpt controller firmware
728 * @ioc: per adapter object
730 * For debugging timeout related issues. Writing 0xCOFFEE00
731 * to the doorbell register will halt controller firmware. With
732 * the purpose to stop both driver and firmware, the enduser can
733 * obtain a ring buffer from controller UART.
736 mpt3sas_halt_firmware(struct MPT3SAS_ADAPTER *ioc)
740 if (!ioc->fwfault_debug)
745 doorbell = ioc->base_readl(&ioc->chip->Doorbell);
746 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
747 mpt3sas_base_fault_info(ioc , doorbell);
749 writel(0xC0FFEE00, &ioc->chip->Doorbell);
750 ioc_err(ioc, "Firmware is halted due to command timeout\n");
753 if (ioc->fwfault_debug == 2)
757 panic("panic in %s\n", __func__);
761 * _base_sas_ioc_info - verbose translation of the ioc status
762 * @ioc: per adapter object
763 * @mpi_reply: reply mf payload returned from firmware
764 * @request_hdr: request mf
767 _base_sas_ioc_info(struct MPT3SAS_ADAPTER *ioc, MPI2DefaultReply_t *mpi_reply,
768 MPI2RequestHeader_t *request_hdr)
770 u16 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) &
774 char *func_str = NULL;
776 /* SCSI_IO, RAID_PASS are handled from _scsih_scsi_ioc_info */
777 if (request_hdr->Function == MPI2_FUNCTION_SCSI_IO_REQUEST ||
778 request_hdr->Function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH ||
779 request_hdr->Function == MPI2_FUNCTION_EVENT_NOTIFICATION)
782 if (ioc_status == MPI2_IOCSTATUS_CONFIG_INVALID_PAGE)
785 switch (ioc_status) {
787 /****************************************************************************
788 * Common IOCStatus values for all replies
789 ****************************************************************************/
791 case MPI2_IOCSTATUS_INVALID_FUNCTION:
792 desc = "invalid function";
794 case MPI2_IOCSTATUS_BUSY:
797 case MPI2_IOCSTATUS_INVALID_SGL:
798 desc = "invalid sgl";
800 case MPI2_IOCSTATUS_INTERNAL_ERROR:
801 desc = "internal error";
803 case MPI2_IOCSTATUS_INVALID_VPID:
804 desc = "invalid vpid";
806 case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES:
807 desc = "insufficient resources";
809 case MPI2_IOCSTATUS_INSUFFICIENT_POWER:
810 desc = "insufficient power";
812 case MPI2_IOCSTATUS_INVALID_FIELD:
813 desc = "invalid field";
815 case MPI2_IOCSTATUS_INVALID_STATE:
816 desc = "invalid state";
818 case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED:
819 desc = "op state not supported";
822 /****************************************************************************
823 * Config IOCStatus values
824 ****************************************************************************/
826 case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION:
827 desc = "config invalid action";
829 case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE:
830 desc = "config invalid type";
832 case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE:
833 desc = "config invalid page";
835 case MPI2_IOCSTATUS_CONFIG_INVALID_DATA:
836 desc = "config invalid data";
838 case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS:
839 desc = "config no defaults";
841 case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT:
842 desc = "config cant commit";
845 /****************************************************************************
847 ****************************************************************************/
849 case MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR:
850 case MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE:
851 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE:
852 case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN:
853 case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN:
854 case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR:
855 case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR:
856 case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED:
857 case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH:
858 case MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED:
859 case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED:
860 case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED:
863 /****************************************************************************
864 * For use by SCSI Initiator and SCSI Target end-to-end data protection
865 ****************************************************************************/
867 case MPI2_IOCSTATUS_EEDP_GUARD_ERROR:
868 desc = "eedp guard error";
870 case MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR:
871 desc = "eedp ref tag error";
873 case MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR:
874 desc = "eedp app tag error";
877 /****************************************************************************
879 ****************************************************************************/
881 case MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX:
882 desc = "target invalid io index";
884 case MPI2_IOCSTATUS_TARGET_ABORTED:
885 desc = "target aborted";
887 case MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE:
888 desc = "target no conn retryable";
890 case MPI2_IOCSTATUS_TARGET_NO_CONNECTION:
891 desc = "target no connection";
893 case MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH:
894 desc = "target xfer count mismatch";
896 case MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR:
897 desc = "target data offset error";
899 case MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA:
900 desc = "target too much write data";
902 case MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT:
903 desc = "target iu too short";
905 case MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT:
906 desc = "target ack nak timeout";
908 case MPI2_IOCSTATUS_TARGET_NAK_RECEIVED:
909 desc = "target nak received";
912 /****************************************************************************
913 * Serial Attached SCSI values
914 ****************************************************************************/
916 case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED:
917 desc = "smp request failed";
919 case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN:
920 desc = "smp data overrun";
923 /****************************************************************************
924 * Diagnostic Buffer Post / Diagnostic Release values
925 ****************************************************************************/
927 case MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED:
928 desc = "diagnostic released";
937 switch (request_hdr->Function) {
938 case MPI2_FUNCTION_CONFIG:
939 frame_sz = sizeof(Mpi2ConfigRequest_t) + ioc->sge_size;
940 func_str = "config_page";
942 case MPI2_FUNCTION_SCSI_TASK_MGMT:
943 frame_sz = sizeof(Mpi2SCSITaskManagementRequest_t);
944 func_str = "task_mgmt";
946 case MPI2_FUNCTION_SAS_IO_UNIT_CONTROL:
947 frame_sz = sizeof(Mpi2SasIoUnitControlRequest_t);
948 func_str = "sas_iounit_ctl";
950 case MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR:
951 frame_sz = sizeof(Mpi2SepRequest_t);
952 func_str = "enclosure";
954 case MPI2_FUNCTION_IOC_INIT:
955 frame_sz = sizeof(Mpi2IOCInitRequest_t);
956 func_str = "ioc_init";
958 case MPI2_FUNCTION_PORT_ENABLE:
959 frame_sz = sizeof(Mpi2PortEnableRequest_t);
960 func_str = "port_enable";
962 case MPI2_FUNCTION_SMP_PASSTHROUGH:
963 frame_sz = sizeof(Mpi2SmpPassthroughRequest_t) + ioc->sge_size;
964 func_str = "smp_passthru";
966 case MPI2_FUNCTION_NVME_ENCAPSULATED:
967 frame_sz = sizeof(Mpi26NVMeEncapsulatedRequest_t) +
969 func_str = "nvme_encapsulated";
973 func_str = "unknown";
977 ioc_warn(ioc, "ioc_status: %s(0x%04x), request(0x%p),(%s)\n",
978 desc, ioc_status, request_hdr, func_str);
980 _debug_dump_mf(request_hdr, frame_sz/4);
984 * _base_display_event_data - verbose translation of firmware asyn events
985 * @ioc: per adapter object
986 * @mpi_reply: reply mf payload returned from firmware
989 _base_display_event_data(struct MPT3SAS_ADAPTER *ioc,
990 Mpi2EventNotificationReply_t *mpi_reply)
995 if (!(ioc->logging_level & MPT_DEBUG_EVENTS))
998 event = le16_to_cpu(mpi_reply->Event);
1001 case MPI2_EVENT_LOG_DATA:
1004 case MPI2_EVENT_STATE_CHANGE:
1005 desc = "Status Change";
1007 case MPI2_EVENT_HARD_RESET_RECEIVED:
1008 desc = "Hard Reset Received";
1010 case MPI2_EVENT_EVENT_CHANGE:
1011 desc = "Event Change";
1013 case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE:
1014 desc = "Device Status Change";
1016 case MPI2_EVENT_IR_OPERATION_STATUS:
1017 if (!ioc->hide_ir_msg)
1018 desc = "IR Operation Status";
1020 case MPI2_EVENT_SAS_DISCOVERY:
1022 Mpi2EventDataSasDiscovery_t *event_data =
1023 (Mpi2EventDataSasDiscovery_t *)mpi_reply->EventData;
1024 ioc_info(ioc, "Discovery: (%s)",
1025 event_data->ReasonCode == MPI2_EVENT_SAS_DISC_RC_STARTED ?
1027 if (event_data->DiscoveryStatus)
1028 pr_cont(" discovery_status(0x%08x)",
1029 le32_to_cpu(event_data->DiscoveryStatus));
1033 case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE:
1034 desc = "SAS Broadcast Primitive";
1036 case MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE:
1037 desc = "SAS Init Device Status Change";
1039 case MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW:
1040 desc = "SAS Init Table Overflow";
1042 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
1043 desc = "SAS Topology Change List";
1045 case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE:
1046 desc = "SAS Enclosure Device Status Change";
1048 case MPI2_EVENT_IR_VOLUME:
1049 if (!ioc->hide_ir_msg)
1052 case MPI2_EVENT_IR_PHYSICAL_DISK:
1053 if (!ioc->hide_ir_msg)
1054 desc = "IR Physical Disk";
1056 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST:
1057 if (!ioc->hide_ir_msg)
1058 desc = "IR Configuration Change List";
1060 case MPI2_EVENT_LOG_ENTRY_ADDED:
1061 if (!ioc->hide_ir_msg)
1062 desc = "Log Entry Added";
1064 case MPI2_EVENT_TEMP_THRESHOLD:
1065 desc = "Temperature Threshold";
1067 case MPI2_EVENT_ACTIVE_CABLE_EXCEPTION:
1068 desc = "Cable Event";
1070 case MPI2_EVENT_SAS_DEVICE_DISCOVERY_ERROR:
1071 desc = "SAS Device Discovery Error";
1073 case MPI2_EVENT_PCIE_DEVICE_STATUS_CHANGE:
1074 desc = "PCIE Device Status Change";
1076 case MPI2_EVENT_PCIE_ENUMERATION:
1078 Mpi26EventDataPCIeEnumeration_t *event_data =
1079 (Mpi26EventDataPCIeEnumeration_t *)mpi_reply->EventData;
1080 ioc_info(ioc, "PCIE Enumeration: (%s)",
1081 event_data->ReasonCode == MPI26_EVENT_PCIE_ENUM_RC_STARTED ?
1083 if (event_data->EnumerationStatus)
1084 pr_cont("enumeration_status(0x%08x)",
1085 le32_to_cpu(event_data->EnumerationStatus));
1089 case MPI2_EVENT_PCIE_TOPOLOGY_CHANGE_LIST:
1090 desc = "PCIE Topology Change List";
1097 ioc_info(ioc, "%s\n", desc);
1101 * _base_sas_log_info - verbose translation of firmware log info
1102 * @ioc: per adapter object
1103 * @log_info: log info
1106 _base_sas_log_info(struct MPT3SAS_ADAPTER *ioc , u32 log_info)
1108 union loginfo_type {
1117 union loginfo_type sas_loginfo;
1118 char *originator_str = NULL;
1120 sas_loginfo.loginfo = log_info;
1121 if (sas_loginfo.dw.bus_type != 3 /*SAS*/)
1124 /* each nexus loss loginfo */
1125 if (log_info == 0x31170000)
1128 /* eat the loginfos associated with task aborts */
1129 if (ioc->ignore_loginfos && (log_info == 0x30050000 || log_info ==
1130 0x31140000 || log_info == 0x31130000))
1133 switch (sas_loginfo.dw.originator) {
1135 originator_str = "IOP";
1138 originator_str = "PL";
1141 if (!ioc->hide_ir_msg)
1142 originator_str = "IR";
1144 originator_str = "WarpDrive";
1148 ioc_warn(ioc, "log_info(0x%08x): originator(%s), code(0x%02x), sub_code(0x%04x)\n",
1150 originator_str, sas_loginfo.dw.code, sas_loginfo.dw.subcode);
1154 * _base_display_reply_info -
1155 * @ioc: per adapter object
1156 * @smid: system request message index
1157 * @msix_index: MSIX table index supplied by the OS
1158 * @reply: reply message frame(lower 32bit addr)
1161 _base_display_reply_info(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
1164 MPI2DefaultReply_t *mpi_reply;
1168 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
1169 if (unlikely(!mpi_reply)) {
1170 ioc_err(ioc, "mpi_reply not valid at %s:%d/%s()!\n",
1171 __FILE__, __LINE__, __func__);
1174 ioc_status = le16_to_cpu(mpi_reply->IOCStatus);
1176 if ((ioc_status & MPI2_IOCSTATUS_MASK) &&
1177 (ioc->logging_level & MPT_DEBUG_REPLY)) {
1178 _base_sas_ioc_info(ioc , mpi_reply,
1179 mpt3sas_base_get_msg_frame(ioc, smid));
1182 if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
1183 loginfo = le32_to_cpu(mpi_reply->IOCLogInfo);
1184 _base_sas_log_info(ioc, loginfo);
1187 if (ioc_status || loginfo) {
1188 ioc_status &= MPI2_IOCSTATUS_MASK;
1189 mpt3sas_trigger_mpi(ioc, ioc_status, loginfo);
1194 * mpt3sas_base_done - base internal command completion routine
1195 * @ioc: per adapter object
1196 * @smid: system request message index
1197 * @msix_index: MSIX table index supplied by the OS
1198 * @reply: reply message frame(lower 32bit addr)
1201 * 1 meaning mf should be freed from _base_interrupt
1202 * 0 means the mf is freed from this function.
1205 mpt3sas_base_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
1208 MPI2DefaultReply_t *mpi_reply;
1210 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
1211 if (mpi_reply && mpi_reply->Function == MPI2_FUNCTION_EVENT_ACK)
1212 return mpt3sas_check_for_pending_internal_cmds(ioc, smid);
1214 if (ioc->base_cmds.status == MPT3_CMD_NOT_USED)
1217 ioc->base_cmds.status |= MPT3_CMD_COMPLETE;
1219 ioc->base_cmds.status |= MPT3_CMD_REPLY_VALID;
1220 memcpy(ioc->base_cmds.reply, mpi_reply, mpi_reply->MsgLength*4);
1222 ioc->base_cmds.status &= ~MPT3_CMD_PENDING;
1224 complete(&ioc->base_cmds.done);
1229 * _base_async_event - main callback handler for firmware asyn events
1230 * @ioc: per adapter object
1231 * @msix_index: MSIX table index supplied by the OS
1232 * @reply: reply message frame(lower 32bit addr)
1235 * 1 meaning mf should be freed from _base_interrupt
1236 * 0 means the mf is freed from this function.
1239 _base_async_event(struct MPT3SAS_ADAPTER *ioc, u8 msix_index, u32 reply)
1241 Mpi2EventNotificationReply_t *mpi_reply;
1242 Mpi2EventAckRequest_t *ack_request;
1244 struct _event_ack_list *delayed_event_ack;
1246 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
1249 if (mpi_reply->Function != MPI2_FUNCTION_EVENT_NOTIFICATION)
1252 _base_display_event_data(ioc, mpi_reply);
1254 if (!(mpi_reply->AckRequired & MPI2_EVENT_NOTIFICATION_ACK_REQUIRED))
1256 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
1258 delayed_event_ack = kzalloc(sizeof(*delayed_event_ack),
1260 if (!delayed_event_ack)
1262 INIT_LIST_HEAD(&delayed_event_ack->list);
1263 delayed_event_ack->Event = mpi_reply->Event;
1264 delayed_event_ack->EventContext = mpi_reply->EventContext;
1265 list_add_tail(&delayed_event_ack->list,
1266 &ioc->delayed_event_ack_list);
1268 ioc_info(ioc, "DELAYED: EVENT ACK: event (0x%04x)\n",
1269 le16_to_cpu(mpi_reply->Event)));
1273 ack_request = mpt3sas_base_get_msg_frame(ioc, smid);
1274 memset(ack_request, 0, sizeof(Mpi2EventAckRequest_t));
1275 ack_request->Function = MPI2_FUNCTION_EVENT_ACK;
1276 ack_request->Event = mpi_reply->Event;
1277 ack_request->EventContext = mpi_reply->EventContext;
1278 ack_request->VF_ID = 0; /* TODO */
1279 ack_request->VP_ID = 0;
1280 mpt3sas_base_put_smid_default(ioc, smid);
1284 /* scsih callback handler */
1285 mpt3sas_scsih_event_callback(ioc, msix_index, reply);
1287 /* ctl callback handler */
1288 mpt3sas_ctl_event_callback(ioc, msix_index, reply);
1293 static struct scsiio_tracker *
1294 _get_st_from_smid(struct MPT3SAS_ADAPTER *ioc, u16 smid)
1296 struct scsi_cmnd *cmd;
1298 if (WARN_ON(!smid) ||
1299 WARN_ON(smid >= ioc->hi_priority_smid))
1302 cmd = mpt3sas_scsih_scsi_lookup_get(ioc, smid);
1304 return scsi_cmd_priv(cmd);
1310 * _base_get_cb_idx - obtain the callback index
1311 * @ioc: per adapter object
1312 * @smid: system request message index
1314 * Return: callback index.
1317 _base_get_cb_idx(struct MPT3SAS_ADAPTER *ioc, u16 smid)
1320 u16 ctl_smid = ioc->scsiio_depth - INTERNAL_SCSIIO_CMDS_COUNT + 1;
1323 if (smid < ioc->hi_priority_smid) {
1324 struct scsiio_tracker *st;
1326 if (smid < ctl_smid) {
1327 st = _get_st_from_smid(ioc, smid);
1329 cb_idx = st->cb_idx;
1330 } else if (smid == ctl_smid)
1331 cb_idx = ioc->ctl_cb_idx;
1332 } else if (smid < ioc->internal_smid) {
1333 i = smid - ioc->hi_priority_smid;
1334 cb_idx = ioc->hpr_lookup[i].cb_idx;
1335 } else if (smid <= ioc->hba_queue_depth) {
1336 i = smid - ioc->internal_smid;
1337 cb_idx = ioc->internal_lookup[i].cb_idx;
1343 * _base_mask_interrupts - disable interrupts
1344 * @ioc: per adapter object
1346 * Disabling ResetIRQ, Reply and Doorbell Interrupts
1349 _base_mask_interrupts(struct MPT3SAS_ADAPTER *ioc)
1353 ioc->mask_interrupts = 1;
1354 him_register = ioc->base_readl(&ioc->chip->HostInterruptMask);
1355 him_register |= MPI2_HIM_DIM + MPI2_HIM_RIM + MPI2_HIM_RESET_IRQ_MASK;
1356 writel(him_register, &ioc->chip->HostInterruptMask);
1357 ioc->base_readl(&ioc->chip->HostInterruptMask);
1361 * _base_unmask_interrupts - enable interrupts
1362 * @ioc: per adapter object
1364 * Enabling only Reply Interrupts
1367 _base_unmask_interrupts(struct MPT3SAS_ADAPTER *ioc)
1371 him_register = ioc->base_readl(&ioc->chip->HostInterruptMask);
1372 him_register &= ~MPI2_HIM_RIM;
1373 writel(him_register, &ioc->chip->HostInterruptMask);
1374 ioc->mask_interrupts = 0;
1377 union reply_descriptor {
1386 * _base_interrupt - MPT adapter (IOC) specific interrupt handler.
1387 * @irq: irq number (not used)
1388 * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure
1390 * Return: IRQ_HANDLED if processed, else IRQ_NONE.
1393 _base_interrupt(int irq, void *bus_id)
1395 struct adapter_reply_queue *reply_q = bus_id;
1396 union reply_descriptor rd;
1398 u8 request_desript_type;
1402 u8 msix_index = reply_q->msix_index;
1403 struct MPT3SAS_ADAPTER *ioc = reply_q->ioc;
1404 Mpi2ReplyDescriptorsUnion_t *rpf;
1407 if (ioc->mask_interrupts)
1410 if (!atomic_add_unless(&reply_q->busy, 1, 1))
1413 rpf = &reply_q->reply_post_free[reply_q->reply_post_host_index];
1414 request_desript_type = rpf->Default.ReplyFlags
1415 & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
1416 if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) {
1417 atomic_dec(&reply_q->busy);
1424 rd.word = le64_to_cpu(rpf->Words);
1425 if (rd.u.low == UINT_MAX || rd.u.high == UINT_MAX)
1428 smid = le16_to_cpu(rpf->Default.DescriptorTypeDependent1);
1429 if (request_desript_type ==
1430 MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS ||
1431 request_desript_type ==
1432 MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS ||
1433 request_desript_type ==
1434 MPI26_RPY_DESCRIPT_FLAGS_PCIE_ENCAPSULATED_SUCCESS) {
1435 cb_idx = _base_get_cb_idx(ioc, smid);
1436 if ((likely(cb_idx < MPT_MAX_CALLBACKS)) &&
1437 (likely(mpt_callbacks[cb_idx] != NULL))) {
1438 rc = mpt_callbacks[cb_idx](ioc, smid,
1441 mpt3sas_base_free_smid(ioc, smid);
1443 } else if (request_desript_type ==
1444 MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) {
1445 reply = le32_to_cpu(
1446 rpf->AddressReply.ReplyFrameAddress);
1447 if (reply > ioc->reply_dma_max_address ||
1448 reply < ioc->reply_dma_min_address)
1451 cb_idx = _base_get_cb_idx(ioc, smid);
1452 if ((likely(cb_idx < MPT_MAX_CALLBACKS)) &&
1453 (likely(mpt_callbacks[cb_idx] != NULL))) {
1454 rc = mpt_callbacks[cb_idx](ioc, smid,
1457 _base_display_reply_info(ioc,
1458 smid, msix_index, reply);
1460 mpt3sas_base_free_smid(ioc,
1464 _base_async_event(ioc, msix_index, reply);
1467 /* reply free queue handling */
1469 ioc->reply_free_host_index =
1470 (ioc->reply_free_host_index ==
1471 (ioc->reply_free_queue_depth - 1)) ?
1472 0 : ioc->reply_free_host_index + 1;
1473 ioc->reply_free[ioc->reply_free_host_index] =
1475 if (ioc->is_mcpu_endpoint)
1476 _base_clone_reply_to_sys_mem(ioc,
1478 ioc->reply_free_host_index);
1479 writel(ioc->reply_free_host_index,
1480 &ioc->chip->ReplyFreeHostIndex);
1484 rpf->Words = cpu_to_le64(ULLONG_MAX);
1485 reply_q->reply_post_host_index =
1486 (reply_q->reply_post_host_index ==
1487 (ioc->reply_post_queue_depth - 1)) ? 0 :
1488 reply_q->reply_post_host_index + 1;
1489 request_desript_type =
1490 reply_q->reply_post_free[reply_q->reply_post_host_index].
1491 Default.ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
1493 /* Update the reply post host index after continuously
1494 * processing the threshold number of Reply Descriptors.
1495 * So that FW can find enough entries to post the Reply
1496 * Descriptors in the reply descriptor post queue.
1498 if (completed_cmds > ioc->hba_queue_depth/3) {
1499 if (ioc->combined_reply_queue) {
1500 writel(reply_q->reply_post_host_index |
1501 ((msix_index & 7) <<
1502 MPI2_RPHI_MSIX_INDEX_SHIFT),
1503 ioc->replyPostRegisterIndex[msix_index/8]);
1505 writel(reply_q->reply_post_host_index |
1507 MPI2_RPHI_MSIX_INDEX_SHIFT),
1508 &ioc->chip->ReplyPostHostIndex);
1512 if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED)
1514 if (!reply_q->reply_post_host_index)
1515 rpf = reply_q->reply_post_free;
1522 if (!completed_cmds) {
1523 atomic_dec(&reply_q->busy);
1527 if (ioc->is_warpdrive) {
1528 writel(reply_q->reply_post_host_index,
1529 ioc->reply_post_host_index[msix_index]);
1530 atomic_dec(&reply_q->busy);
1534 /* Update Reply Post Host Index.
1535 * For those HBA's which support combined reply queue feature
1536 * 1. Get the correct Supplemental Reply Post Host Index Register.
1537 * i.e. (msix_index / 8)th entry from Supplemental Reply Post Host
1538 * Index Register address bank i.e replyPostRegisterIndex[],
1539 * 2. Then update this register with new reply host index value
1540 * in ReplyPostIndex field and the MSIxIndex field with
1541 * msix_index value reduced to a value between 0 and 7,
1542 * using a modulo 8 operation. Since each Supplemental Reply Post
1543 * Host Index Register supports 8 MSI-X vectors.
1545 * For other HBA's just update the Reply Post Host Index register with
1546 * new reply host index value in ReplyPostIndex Field and msix_index
1547 * value in MSIxIndex field.
1549 if (ioc->combined_reply_queue)
1550 writel(reply_q->reply_post_host_index | ((msix_index & 7) <<
1551 MPI2_RPHI_MSIX_INDEX_SHIFT),
1552 ioc->replyPostRegisterIndex[msix_index/8]);
1554 writel(reply_q->reply_post_host_index | (msix_index <<
1555 MPI2_RPHI_MSIX_INDEX_SHIFT),
1556 &ioc->chip->ReplyPostHostIndex);
1557 atomic_dec(&reply_q->busy);
1562 * _base_is_controller_msix_enabled - is controller support muli-reply queues
1563 * @ioc: per adapter object
1565 * Return: Whether or not MSI/X is enabled.
1568 _base_is_controller_msix_enabled(struct MPT3SAS_ADAPTER *ioc)
1570 return (ioc->facts.IOCCapabilities &
1571 MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX) && ioc->msix_enable;
1575 * mpt3sas_base_sync_reply_irqs - flush pending MSIX interrupts
1576 * @ioc: per adapter object
1577 * Context: non ISR conext
1579 * Called when a Task Management request has completed.
1582 mpt3sas_base_sync_reply_irqs(struct MPT3SAS_ADAPTER *ioc)
1584 struct adapter_reply_queue *reply_q;
1586 /* If MSIX capability is turned off
1587 * then multi-queues are not enabled
1589 if (!_base_is_controller_msix_enabled(ioc))
1592 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
1593 if (ioc->shost_recovery || ioc->remove_host ||
1594 ioc->pci_error_recovery)
1596 /* TMs are on msix_index == 0 */
1597 if (reply_q->msix_index == 0)
1599 synchronize_irq(pci_irq_vector(ioc->pdev, reply_q->msix_index));
1604 * mpt3sas_base_release_callback_handler - clear interrupt callback handler
1605 * @cb_idx: callback index
1608 mpt3sas_base_release_callback_handler(u8 cb_idx)
1610 mpt_callbacks[cb_idx] = NULL;
1614 * mpt3sas_base_register_callback_handler - obtain index for the interrupt callback handler
1615 * @cb_func: callback function
1617 * Return: Index of @cb_func.
1620 mpt3sas_base_register_callback_handler(MPT_CALLBACK cb_func)
1624 for (cb_idx = MPT_MAX_CALLBACKS-1; cb_idx; cb_idx--)
1625 if (mpt_callbacks[cb_idx] == NULL)
1628 mpt_callbacks[cb_idx] = cb_func;
1633 * mpt3sas_base_initialize_callback_handler - initialize the interrupt callback handler
1636 mpt3sas_base_initialize_callback_handler(void)
1640 for (cb_idx = 0; cb_idx < MPT_MAX_CALLBACKS; cb_idx++)
1641 mpt3sas_base_release_callback_handler(cb_idx);
1646 * _base_build_zero_len_sge - build zero length sg entry
1647 * @ioc: per adapter object
1648 * @paddr: virtual address for SGE
1650 * Create a zero length scatter gather entry to insure the IOCs hardware has
1651 * something to use if the target device goes brain dead and tries
1652 * to send data even when none is asked for.
1655 _base_build_zero_len_sge(struct MPT3SAS_ADAPTER *ioc, void *paddr)
1657 u32 flags_length = (u32)((MPI2_SGE_FLAGS_LAST_ELEMENT |
1658 MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST |
1659 MPI2_SGE_FLAGS_SIMPLE_ELEMENT) <<
1660 MPI2_SGE_FLAGS_SHIFT);
1661 ioc->base_add_sg_single(paddr, flags_length, -1);
1665 * _base_add_sg_single_32 - Place a simple 32 bit SGE at address pAddr.
1666 * @paddr: virtual address for SGE
1667 * @flags_length: SGE flags and data transfer length
1668 * @dma_addr: Physical address
1671 _base_add_sg_single_32(void *paddr, u32 flags_length, dma_addr_t dma_addr)
1673 Mpi2SGESimple32_t *sgel = paddr;
1675 flags_length |= (MPI2_SGE_FLAGS_32_BIT_ADDRESSING |
1676 MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
1677 sgel->FlagsLength = cpu_to_le32(flags_length);
1678 sgel->Address = cpu_to_le32(dma_addr);
1683 * _base_add_sg_single_64 - Place a simple 64 bit SGE at address pAddr.
1684 * @paddr: virtual address for SGE
1685 * @flags_length: SGE flags and data transfer length
1686 * @dma_addr: Physical address
1689 _base_add_sg_single_64(void *paddr, u32 flags_length, dma_addr_t dma_addr)
1691 Mpi2SGESimple64_t *sgel = paddr;
1693 flags_length |= (MPI2_SGE_FLAGS_64_BIT_ADDRESSING |
1694 MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
1695 sgel->FlagsLength = cpu_to_le32(flags_length);
1696 sgel->Address = cpu_to_le64(dma_addr);
1700 * _base_get_chain_buffer_tracker - obtain chain tracker
1701 * @ioc: per adapter object
1702 * @scmd: SCSI commands of the IO request
1704 * Return: chain tracker from chain_lookup table using key as
1705 * smid and smid's chain_offset.
1707 static struct chain_tracker *
1708 _base_get_chain_buffer_tracker(struct MPT3SAS_ADAPTER *ioc,
1709 struct scsi_cmnd *scmd)
1711 struct chain_tracker *chain_req;
1712 struct scsiio_tracker *st = scsi_cmd_priv(scmd);
1713 u16 smid = st->smid;
1715 atomic_read(&ioc->chain_lookup[smid - 1].chain_offset);
1717 if (chain_offset == ioc->chains_needed_per_io)
1720 chain_req = &ioc->chain_lookup[smid - 1].chains_per_smid[chain_offset];
1721 atomic_inc(&ioc->chain_lookup[smid - 1].chain_offset);
1727 * _base_build_sg - build generic sg
1728 * @ioc: per adapter object
1729 * @psge: virtual address for SGE
1730 * @data_out_dma: physical address for WRITES
1731 * @data_out_sz: data xfer size for WRITES
1732 * @data_in_dma: physical address for READS
1733 * @data_in_sz: data xfer size for READS
1736 _base_build_sg(struct MPT3SAS_ADAPTER *ioc, void *psge,
1737 dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
1742 if (!data_out_sz && !data_in_sz) {
1743 _base_build_zero_len_sge(ioc, psge);
1747 if (data_out_sz && data_in_sz) {
1748 /* WRITE sgel first */
1749 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1750 MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_HOST_TO_IOC);
1751 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1752 ioc->base_add_sg_single(psge, sgl_flags |
1753 data_out_sz, data_out_dma);
1756 psge += ioc->sge_size;
1758 /* READ sgel last */
1759 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1760 MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
1761 MPI2_SGE_FLAGS_END_OF_LIST);
1762 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1763 ioc->base_add_sg_single(psge, sgl_flags |
1764 data_in_sz, data_in_dma);
1765 } else if (data_out_sz) /* WRITE */ {
1766 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1767 MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
1768 MPI2_SGE_FLAGS_END_OF_LIST | MPI2_SGE_FLAGS_HOST_TO_IOC);
1769 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1770 ioc->base_add_sg_single(psge, sgl_flags |
1771 data_out_sz, data_out_dma);
1772 } else if (data_in_sz) /* READ */ {
1773 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1774 MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
1775 MPI2_SGE_FLAGS_END_OF_LIST);
1776 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1777 ioc->base_add_sg_single(psge, sgl_flags |
1778 data_in_sz, data_in_dma);
1782 /* IEEE format sgls */
1785 * _base_build_nvme_prp - This function is called for NVMe end devices to build
1786 * a native SGL (NVMe PRP). The native SGL is built starting in the first PRP
1787 * entry of the NVMe message (PRP1). If the data buffer is small enough to be
1788 * described entirely using PRP1, then PRP2 is not used. If needed, PRP2 is
1789 * used to describe a larger data buffer. If the data buffer is too large to
1790 * describe using the two PRP entriess inside the NVMe message, then PRP1
1791 * describes the first data memory segment, and PRP2 contains a pointer to a PRP
1792 * list located elsewhere in memory to describe the remaining data memory
1793 * segments. The PRP list will be contiguous.
1795 * The native SGL for NVMe devices is a Physical Region Page (PRP). A PRP
1796 * consists of a list of PRP entries to describe a number of noncontigous
1797 * physical memory segments as a single memory buffer, just as a SGL does. Note
1798 * however, that this function is only used by the IOCTL call, so the memory
1799 * given will be guaranteed to be contiguous. There is no need to translate
1800 * non-contiguous SGL into a PRP in this case. All PRPs will describe
1801 * contiguous space that is one page size each.
1803 * Each NVMe message contains two PRP entries. The first (PRP1) either contains
1804 * a PRP list pointer or a PRP element, depending upon the command. PRP2
1805 * contains the second PRP element if the memory being described fits within 2
1806 * PRP entries, or a PRP list pointer if the PRP spans more than two entries.
1808 * A PRP list pointer contains the address of a PRP list, structured as a linear
1809 * array of PRP entries. Each PRP entry in this list describes a segment of
1812 * Each 64-bit PRP entry comprises an address and an offset field. The address
1813 * always points at the beginning of a 4KB physical memory page, and the offset
1814 * describes where within that 4KB page the memory segment begins. Only the
1815 * first element in a PRP list may contain a non-zero offest, implying that all
1816 * memory segments following the first begin at the start of a 4KB page.
1818 * Each PRP element normally describes 4KB of physical memory, with exceptions
1819 * for the first and last elements in the list. If the memory being described
1820 * by the list begins at a non-zero offset within the first 4KB page, then the
1821 * first PRP element will contain a non-zero offset indicating where the region
1822 * begins within the 4KB page. The last memory segment may end before the end
1823 * of the 4KB segment, depending upon the overall size of the memory being
1824 * described by the PRP list.
1826 * Since PRP entries lack any indication of size, the overall data buffer length
1827 * is used to determine where the end of the data memory buffer is located, and
1828 * how many PRP entries are required to describe it.
1830 * @ioc: per adapter object
1831 * @smid: system request message index for getting asscociated SGL
1832 * @nvme_encap_request: the NVMe request msg frame pointer
1833 * @data_out_dma: physical address for WRITES
1834 * @data_out_sz: data xfer size for WRITES
1835 * @data_in_dma: physical address for READS
1836 * @data_in_sz: data xfer size for READS
1839 _base_build_nvme_prp(struct MPT3SAS_ADAPTER *ioc, u16 smid,
1840 Mpi26NVMeEncapsulatedRequest_t *nvme_encap_request,
1841 dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
1844 int prp_size = NVME_PRP_SIZE;
1845 __le64 *prp_entry, *prp1_entry, *prp2_entry;
1847 dma_addr_t prp_entry_dma, prp_page_dma, dma_addr;
1848 u32 offset, entry_len;
1849 u32 page_mask_result, page_mask;
1851 struct mpt3sas_nvme_cmd *nvme_cmd =
1852 (void *)nvme_encap_request->NVMe_Command;
1855 * Not all commands require a data transfer. If no data, just return
1856 * without constructing any PRP.
1858 if (!data_in_sz && !data_out_sz)
1860 prp1_entry = &nvme_cmd->prp1;
1861 prp2_entry = &nvme_cmd->prp2;
1862 prp_entry = prp1_entry;
1864 * For the PRP entries, use the specially allocated buffer of
1865 * contiguous memory.
1867 prp_page = (__le64 *)mpt3sas_base_get_pcie_sgl(ioc, smid);
1868 prp_page_dma = mpt3sas_base_get_pcie_sgl_dma(ioc, smid);
1871 * Check if we are within 1 entry of a page boundary we don't
1872 * want our first entry to be a PRP List entry.
1874 page_mask = ioc->page_size - 1;
1875 page_mask_result = (uintptr_t)((u8 *)prp_page + prp_size) & page_mask;
1876 if (!page_mask_result) {
1877 /* Bump up to next page boundary. */
1878 prp_page = (__le64 *)((u8 *)prp_page + prp_size);
1879 prp_page_dma = prp_page_dma + prp_size;
1883 * Set PRP physical pointer, which initially points to the current PRP
1886 prp_entry_dma = prp_page_dma;
1888 /* Get physical address and length of the data buffer. */
1890 dma_addr = data_in_dma;
1891 length = data_in_sz;
1893 dma_addr = data_out_dma;
1894 length = data_out_sz;
1897 /* Loop while the length is not zero. */
1900 * Check if we need to put a list pointer here if we are at
1901 * page boundary - prp_size (8 bytes).
1903 page_mask_result = (prp_entry_dma + prp_size) & page_mask;
1904 if (!page_mask_result) {
1906 * This is the last entry in a PRP List, so we need to
1907 * put a PRP list pointer here. What this does is:
1908 * - bump the current memory pointer to the next
1909 * address, which will be the next full page.
1910 * - set the PRP Entry to point to that page. This
1911 * is now the PRP List pointer.
1912 * - bump the PRP Entry pointer the start of the
1913 * next page. Since all of this PRP memory is
1914 * contiguous, no need to get a new page - it's
1915 * just the next address.
1918 *prp_entry = cpu_to_le64(prp_entry_dma);
1922 /* Need to handle if entry will be part of a page. */
1923 offset = dma_addr & page_mask;
1924 entry_len = ioc->page_size - offset;
1926 if (prp_entry == prp1_entry) {
1928 * Must fill in the first PRP pointer (PRP1) before
1931 *prp1_entry = cpu_to_le64(dma_addr);
1934 * Now point to the second PRP entry within the
1937 prp_entry = prp2_entry;
1938 } else if (prp_entry == prp2_entry) {
1940 * Should the PRP2 entry be a PRP List pointer or just
1941 * a regular PRP pointer? If there is more than one
1942 * more page of data, must use a PRP List pointer.
1944 if (length > ioc->page_size) {
1946 * PRP2 will contain a PRP List pointer because
1947 * more PRP's are needed with this command. The
1948 * list will start at the beginning of the
1949 * contiguous buffer.
1951 *prp2_entry = cpu_to_le64(prp_entry_dma);
1954 * The next PRP Entry will be the start of the
1957 prp_entry = prp_page;
1960 * After this, the PRP Entries are complete.
1961 * This command uses 2 PRP's and no PRP list.
1963 *prp2_entry = cpu_to_le64(dma_addr);
1967 * Put entry in list and bump the addresses.
1969 * After PRP1 and PRP2 are filled in, this will fill in
1970 * all remaining PRP entries in a PRP List, one per
1971 * each time through the loop.
1973 *prp_entry = cpu_to_le64(dma_addr);
1979 * Bump the phys address of the command's data buffer by the
1982 dma_addr += entry_len;
1984 /* Decrement length accounting for last partial page. */
1985 if (entry_len > length)
1988 length -= entry_len;
1993 * base_make_prp_nvme -
1994 * Prepare PRPs(Physical Region Page)- SGLs specific to NVMe drives only
1996 * @ioc: per adapter object
1997 * @scmd: SCSI command from the mid-layer
1998 * @mpi_request: mpi request
2000 * @sge_count: scatter gather element count.
2002 * Return: true: PRPs are built
2003 * false: IEEE SGLs needs to be built
2006 base_make_prp_nvme(struct MPT3SAS_ADAPTER *ioc,
2007 struct scsi_cmnd *scmd,
2008 Mpi25SCSIIORequest_t *mpi_request,
2009 u16 smid, int sge_count)
2011 int sge_len, num_prp_in_chain = 0;
2012 Mpi25IeeeSgeChain64_t *main_chain_element, *ptr_first_sgl;
2014 dma_addr_t msg_dma, sge_addr, offset;
2015 u32 page_mask, page_mask_result;
2016 struct scatterlist *sg_scmd;
2018 int data_len = scsi_bufflen(scmd);
2021 nvme_pg_size = max_t(u32, ioc->page_size, NVME_PRP_PAGE_SIZE);
2023 * Nvme has a very convoluted prp format. One prp is required
2024 * for each page or partial page. Driver need to split up OS sg_list
2025 * entries if it is longer than one page or cross a page
2026 * boundary. Driver also have to insert a PRP list pointer entry as
2027 * the last entry in each physical page of the PRP list.
2029 * NOTE: The first PRP "entry" is actually placed in the first
2030 * SGL entry in the main message as IEEE 64 format. The 2nd
2031 * entry in the main message is the chain element, and the rest
2032 * of the PRP entries are built in the contiguous pcie buffer.
2034 page_mask = nvme_pg_size - 1;
2037 * Native SGL is needed.
2038 * Put a chain element in main message frame that points to the first
2041 * NOTE: The ChainOffset field must be 0 when using a chain pointer to
2045 /* Set main message chain element pointer */
2046 main_chain_element = (pMpi25IeeeSgeChain64_t)&mpi_request->SGL;
2048 * For NVMe the chain element needs to be the 2nd SG entry in the main
2051 main_chain_element = (Mpi25IeeeSgeChain64_t *)
2052 ((u8 *)main_chain_element + sizeof(MPI25_IEEE_SGE_CHAIN64));
2055 * For the PRP entries, use the specially allocated buffer of
2056 * contiguous memory. Normal chain buffers can't be used
2057 * because each chain buffer would need to be the size of an OS
2060 curr_buff = mpt3sas_base_get_pcie_sgl(ioc, smid);
2061 msg_dma = mpt3sas_base_get_pcie_sgl_dma(ioc, smid);
2063 main_chain_element->Address = cpu_to_le64(msg_dma);
2064 main_chain_element->NextChainOffset = 0;
2065 main_chain_element->Flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT |
2066 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR |
2067 MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP;
2069 /* Build first prp, sge need not to be page aligned*/
2070 ptr_first_sgl = (pMpi25IeeeSgeChain64_t)&mpi_request->SGL;
2071 sg_scmd = scsi_sglist(scmd);
2072 sge_addr = sg_dma_address(sg_scmd);
2073 sge_len = sg_dma_len(sg_scmd);
2075 offset = sge_addr & page_mask;
2076 first_prp_len = nvme_pg_size - offset;
2078 ptr_first_sgl->Address = cpu_to_le64(sge_addr);
2079 ptr_first_sgl->Length = cpu_to_le32(first_prp_len);
2081 data_len -= first_prp_len;
2083 if (sge_len > first_prp_len) {
2084 sge_addr += first_prp_len;
2085 sge_len -= first_prp_len;
2086 } else if (data_len && (sge_len == first_prp_len)) {
2087 sg_scmd = sg_next(sg_scmd);
2088 sge_addr = sg_dma_address(sg_scmd);
2089 sge_len = sg_dma_len(sg_scmd);
2093 offset = sge_addr & page_mask;
2095 /* Put PRP pointer due to page boundary*/
2096 page_mask_result = (uintptr_t)(curr_buff + 1) & page_mask;
2097 if (unlikely(!page_mask_result)) {
2098 scmd_printk(KERN_NOTICE,
2099 scmd, "page boundary curr_buff: 0x%p\n",
2102 *curr_buff = cpu_to_le64(msg_dma);
2107 *curr_buff = cpu_to_le64(sge_addr);
2112 sge_addr += nvme_pg_size;
2113 sge_len -= nvme_pg_size;
2114 data_len -= nvme_pg_size;
2122 sg_scmd = sg_next(sg_scmd);
2123 sge_addr = sg_dma_address(sg_scmd);
2124 sge_len = sg_dma_len(sg_scmd);
2127 main_chain_element->Length =
2128 cpu_to_le32(num_prp_in_chain * sizeof(u64));
2133 base_is_prp_possible(struct MPT3SAS_ADAPTER *ioc,
2134 struct _pcie_device *pcie_device, struct scsi_cmnd *scmd, int sge_count)
2136 u32 data_length = 0;
2137 bool build_prp = true;
2139 data_length = scsi_bufflen(scmd);
2141 /* If Datalenth is <= 16K and number of SGE’s entries are <= 2
2144 if ((data_length <= NVME_PRP_PAGE_SIZE*4) && (sge_count <= 2))
2151 * _base_check_pcie_native_sgl - This function is called for PCIe end devices to
2152 * determine if the driver needs to build a native SGL. If so, that native
2153 * SGL is built in the special contiguous buffers allocated especially for
2154 * PCIe SGL creation. If the driver will not build a native SGL, return
2155 * TRUE and a normal IEEE SGL will be built. Currently this routine
2157 * @ioc: per adapter object
2158 * @mpi_request: mf request pointer
2159 * @smid: system request message index
2160 * @scmd: scsi command
2161 * @pcie_device: points to the PCIe device's info
2163 * Return: 0 if native SGL was built, 1 if no SGL was built
2166 _base_check_pcie_native_sgl(struct MPT3SAS_ADAPTER *ioc,
2167 Mpi25SCSIIORequest_t *mpi_request, u16 smid, struct scsi_cmnd *scmd,
2168 struct _pcie_device *pcie_device)
2172 /* Get the SG list pointer and info. */
2173 sges_left = scsi_dma_map(scmd);
2174 if (sges_left < 0) {
2175 sdev_printk(KERN_ERR, scmd->device,
2176 "scsi_dma_map failed: request for %d bytes!\n",
2177 scsi_bufflen(scmd));
2181 /* Check if we need to build a native SG list. */
2182 if (base_is_prp_possible(ioc, pcie_device,
2183 scmd, sges_left) == 0) {
2184 /* We built a native SG list, just return. */
2189 * Build native NVMe PRP.
2191 base_make_prp_nvme(ioc, scmd, mpi_request,
2196 scsi_dma_unmap(scmd);
2201 * _base_add_sg_single_ieee - add sg element for IEEE format
2202 * @paddr: virtual address for SGE
2204 * @chain_offset: number of 128 byte elements from start of segment
2205 * @length: data transfer length
2206 * @dma_addr: Physical address
2209 _base_add_sg_single_ieee(void *paddr, u8 flags, u8 chain_offset, u32 length,
2210 dma_addr_t dma_addr)
2212 Mpi25IeeeSgeChain64_t *sgel = paddr;
2214 sgel->Flags = flags;
2215 sgel->NextChainOffset = chain_offset;
2216 sgel->Length = cpu_to_le32(length);
2217 sgel->Address = cpu_to_le64(dma_addr);
2221 * _base_build_zero_len_sge_ieee - build zero length sg entry for IEEE format
2222 * @ioc: per adapter object
2223 * @paddr: virtual address for SGE
2225 * Create a zero length scatter gather entry to insure the IOCs hardware has
2226 * something to use if the target device goes brain dead and tries
2227 * to send data even when none is asked for.
2230 _base_build_zero_len_sge_ieee(struct MPT3SAS_ADAPTER *ioc, void *paddr)
2232 u8 sgl_flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
2233 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR |
2234 MPI25_IEEE_SGE_FLAGS_END_OF_LIST);
2236 _base_add_sg_single_ieee(paddr, sgl_flags, 0, 0, -1);
2240 * _base_build_sg_scmd - main sg creation routine
2241 * pcie_device is unused here!
2242 * @ioc: per adapter object
2243 * @scmd: scsi command
2244 * @smid: system request message index
2245 * @unused: unused pcie_device pointer
2248 * The main routine that builds scatter gather table from a given
2249 * scsi request sent via the .queuecommand main handler.
2251 * Return: 0 success, anything else error
2254 _base_build_sg_scmd(struct MPT3SAS_ADAPTER *ioc,
2255 struct scsi_cmnd *scmd, u16 smid, struct _pcie_device *unused)
2257 Mpi2SCSIIORequest_t *mpi_request;
2258 dma_addr_t chain_dma;
2259 struct scatterlist *sg_scmd;
2260 void *sg_local, *chain;
2265 u32 sges_in_segment;
2267 u32 sgl_flags_last_element;
2268 u32 sgl_flags_end_buffer;
2269 struct chain_tracker *chain_req;
2271 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
2273 /* init scatter gather flags */
2274 sgl_flags = MPI2_SGE_FLAGS_SIMPLE_ELEMENT;
2275 if (scmd->sc_data_direction == DMA_TO_DEVICE)
2276 sgl_flags |= MPI2_SGE_FLAGS_HOST_TO_IOC;
2277 sgl_flags_last_element = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT)
2278 << MPI2_SGE_FLAGS_SHIFT;
2279 sgl_flags_end_buffer = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT |
2280 MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST)
2281 << MPI2_SGE_FLAGS_SHIFT;
2282 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
2284 sg_scmd = scsi_sglist(scmd);
2285 sges_left = scsi_dma_map(scmd);
2286 if (sges_left < 0) {
2287 sdev_printk(KERN_ERR, scmd->device,
2288 "scsi_dma_map failed: request for %d bytes!\n",
2289 scsi_bufflen(scmd));
2293 sg_local = &mpi_request->SGL;
2294 sges_in_segment = ioc->max_sges_in_main_message;
2295 if (sges_left <= sges_in_segment)
2296 goto fill_in_last_segment;
2298 mpi_request->ChainOffset = (offsetof(Mpi2SCSIIORequest_t, SGL) +
2299 (sges_in_segment * ioc->sge_size))/4;
2301 /* fill in main message segment when there is a chain following */
2302 while (sges_in_segment) {
2303 if (sges_in_segment == 1)
2304 ioc->base_add_sg_single(sg_local,
2305 sgl_flags_last_element | sg_dma_len(sg_scmd),
2306 sg_dma_address(sg_scmd));
2308 ioc->base_add_sg_single(sg_local, sgl_flags |
2309 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
2310 sg_scmd = sg_next(sg_scmd);
2311 sg_local += ioc->sge_size;
2316 /* initializing the chain flags and pointers */
2317 chain_flags = MPI2_SGE_FLAGS_CHAIN_ELEMENT << MPI2_SGE_FLAGS_SHIFT;
2318 chain_req = _base_get_chain_buffer_tracker(ioc, scmd);
2321 chain = chain_req->chain_buffer;
2322 chain_dma = chain_req->chain_buffer_dma;
2324 sges_in_segment = (sges_left <=
2325 ioc->max_sges_in_chain_message) ? sges_left :
2326 ioc->max_sges_in_chain_message;
2327 chain_offset = (sges_left == sges_in_segment) ?
2328 0 : (sges_in_segment * ioc->sge_size)/4;
2329 chain_length = sges_in_segment * ioc->sge_size;
2331 chain_offset = chain_offset <<
2332 MPI2_SGE_CHAIN_OFFSET_SHIFT;
2333 chain_length += ioc->sge_size;
2335 ioc->base_add_sg_single(sg_local, chain_flags | chain_offset |
2336 chain_length, chain_dma);
2339 goto fill_in_last_segment;
2341 /* fill in chain segments */
2342 while (sges_in_segment) {
2343 if (sges_in_segment == 1)
2344 ioc->base_add_sg_single(sg_local,
2345 sgl_flags_last_element |
2346 sg_dma_len(sg_scmd),
2347 sg_dma_address(sg_scmd));
2349 ioc->base_add_sg_single(sg_local, sgl_flags |
2350 sg_dma_len(sg_scmd),
2351 sg_dma_address(sg_scmd));
2352 sg_scmd = sg_next(sg_scmd);
2353 sg_local += ioc->sge_size;
2358 chain_req = _base_get_chain_buffer_tracker(ioc, scmd);
2361 chain = chain_req->chain_buffer;
2362 chain_dma = chain_req->chain_buffer_dma;
2366 fill_in_last_segment:
2368 /* fill the last segment */
2371 ioc->base_add_sg_single(sg_local, sgl_flags_end_buffer |
2372 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
2374 ioc->base_add_sg_single(sg_local, sgl_flags |
2375 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
2376 sg_scmd = sg_next(sg_scmd);
2377 sg_local += ioc->sge_size;
2385 * _base_build_sg_scmd_ieee - main sg creation routine for IEEE format
2386 * @ioc: per adapter object
2387 * @scmd: scsi command
2388 * @smid: system request message index
2389 * @pcie_device: Pointer to pcie_device. If set, the pcie native sgl will be
2390 * constructed on need.
2393 * The main routine that builds scatter gather table from a given
2394 * scsi request sent via the .queuecommand main handler.
2396 * Return: 0 success, anything else error
2399 _base_build_sg_scmd_ieee(struct MPT3SAS_ADAPTER *ioc,
2400 struct scsi_cmnd *scmd, u16 smid, struct _pcie_device *pcie_device)
2402 Mpi25SCSIIORequest_t *mpi_request;
2403 dma_addr_t chain_dma;
2404 struct scatterlist *sg_scmd;
2405 void *sg_local, *chain;
2409 u32 sges_in_segment;
2410 u8 simple_sgl_flags;
2411 u8 simple_sgl_flags_last;
2413 struct chain_tracker *chain_req;
2415 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
2417 /* init scatter gather flags */
2418 simple_sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
2419 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
2420 simple_sgl_flags_last = simple_sgl_flags |
2421 MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
2422 chain_sgl_flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT |
2423 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
2425 /* Check if we need to build a native SG list. */
2426 if ((pcie_device) && (_base_check_pcie_native_sgl(ioc, mpi_request,
2427 smid, scmd, pcie_device) == 0)) {
2428 /* We built a native SG list, just return. */
2432 sg_scmd = scsi_sglist(scmd);
2433 sges_left = scsi_dma_map(scmd);
2434 if (sges_left < 0) {
2435 sdev_printk(KERN_ERR, scmd->device,
2436 "scsi_dma_map failed: request for %d bytes!\n",
2437 scsi_bufflen(scmd));
2441 sg_local = &mpi_request->SGL;
2442 sges_in_segment = (ioc->request_sz -
2443 offsetof(Mpi25SCSIIORequest_t, SGL))/ioc->sge_size_ieee;
2444 if (sges_left <= sges_in_segment)
2445 goto fill_in_last_segment;
2447 mpi_request->ChainOffset = (sges_in_segment - 1 /* chain element */) +
2448 (offsetof(Mpi25SCSIIORequest_t, SGL)/ioc->sge_size_ieee);
2450 /* fill in main message segment when there is a chain following */
2451 while (sges_in_segment > 1) {
2452 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
2453 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
2454 sg_scmd = sg_next(sg_scmd);
2455 sg_local += ioc->sge_size_ieee;
2460 /* initializing the pointers */
2461 chain_req = _base_get_chain_buffer_tracker(ioc, scmd);
2464 chain = chain_req->chain_buffer;
2465 chain_dma = chain_req->chain_buffer_dma;
2467 sges_in_segment = (sges_left <=
2468 ioc->max_sges_in_chain_message) ? sges_left :
2469 ioc->max_sges_in_chain_message;
2470 chain_offset = (sges_left == sges_in_segment) ?
2471 0 : sges_in_segment;
2472 chain_length = sges_in_segment * ioc->sge_size_ieee;
2474 chain_length += ioc->sge_size_ieee;
2475 _base_add_sg_single_ieee(sg_local, chain_sgl_flags,
2476 chain_offset, chain_length, chain_dma);
2480 goto fill_in_last_segment;
2482 /* fill in chain segments */
2483 while (sges_in_segment) {
2484 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
2485 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
2486 sg_scmd = sg_next(sg_scmd);
2487 sg_local += ioc->sge_size_ieee;
2492 chain_req = _base_get_chain_buffer_tracker(ioc, scmd);
2495 chain = chain_req->chain_buffer;
2496 chain_dma = chain_req->chain_buffer_dma;
2500 fill_in_last_segment:
2502 /* fill the last segment */
2503 while (sges_left > 0) {
2505 _base_add_sg_single_ieee(sg_local,
2506 simple_sgl_flags_last, 0, sg_dma_len(sg_scmd),
2507 sg_dma_address(sg_scmd));
2509 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
2510 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
2511 sg_scmd = sg_next(sg_scmd);
2512 sg_local += ioc->sge_size_ieee;
2520 * _base_build_sg_ieee - build generic sg for IEEE format
2521 * @ioc: per adapter object
2522 * @psge: virtual address for SGE
2523 * @data_out_dma: physical address for WRITES
2524 * @data_out_sz: data xfer size for WRITES
2525 * @data_in_dma: physical address for READS
2526 * @data_in_sz: data xfer size for READS
2529 _base_build_sg_ieee(struct MPT3SAS_ADAPTER *ioc, void *psge,
2530 dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
2535 if (!data_out_sz && !data_in_sz) {
2536 _base_build_zero_len_sge_ieee(ioc, psge);
2540 if (data_out_sz && data_in_sz) {
2541 /* WRITE sgel first */
2542 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
2543 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
2544 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz,
2548 psge += ioc->sge_size_ieee;
2550 /* READ sgel last */
2551 sgl_flags |= MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
2552 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz,
2554 } else if (data_out_sz) /* WRITE */ {
2555 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
2556 MPI25_IEEE_SGE_FLAGS_END_OF_LIST |
2557 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
2558 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz,
2560 } else if (data_in_sz) /* READ */ {
2561 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
2562 MPI25_IEEE_SGE_FLAGS_END_OF_LIST |
2563 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
2564 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz,
2569 #define convert_to_kb(x) ((x) << (PAGE_SHIFT - 10))
2572 * _base_config_dma_addressing - set dma addressing
2573 * @ioc: per adapter object
2574 * @pdev: PCI device struct
2576 * Return: 0 for success, non-zero for failure.
2579 _base_config_dma_addressing(struct MPT3SAS_ADAPTER *ioc, struct pci_dev *pdev)
2581 u64 required_mask, coherent_mask;
2584 if (ioc->is_mcpu_endpoint)
2587 required_mask = dma_get_required_mask(&pdev->dev);
2588 if (sizeof(dma_addr_t) == 4 || required_mask == 32)
2592 coherent_mask = DMA_BIT_MASK(64);
2594 coherent_mask = DMA_BIT_MASK(32);
2596 if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) ||
2597 dma_set_coherent_mask(&pdev->dev, coherent_mask))
2600 ioc->base_add_sg_single = &_base_add_sg_single_64;
2601 ioc->sge_size = sizeof(Mpi2SGESimple64_t);
2606 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)))
2609 ioc->base_add_sg_single = &_base_add_sg_single_32;
2610 ioc->sge_size = sizeof(Mpi2SGESimple32_t);
2614 ioc_info(ioc, "%d BIT PCI BUS DMA ADDRESSING SUPPORTED, total mem (%ld kB)\n",
2615 ioc->dma_mask, convert_to_kb(s.totalram));
2621 _base_change_consistent_dma_mask(struct MPT3SAS_ADAPTER *ioc,
2622 struct pci_dev *pdev)
2624 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
2625 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
2632 * _base_check_enable_msix - checks MSIX capabable.
2633 * @ioc: per adapter object
2635 * Check to see if card is capable of MSIX, and set number
2636 * of available msix vectors
2639 _base_check_enable_msix(struct MPT3SAS_ADAPTER *ioc)
2642 u16 message_control;
2644 /* Check whether controller SAS2008 B0 controller,
2645 * if it is SAS2008 B0 controller use IO-APIC instead of MSIX
2647 if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 &&
2648 ioc->pdev->revision == SAS2_PCI_DEVICE_B0_REVISION) {
2652 base = pci_find_capability(ioc->pdev, PCI_CAP_ID_MSIX);
2654 dfailprintk(ioc, ioc_info(ioc, "msix not supported\n"));
2658 /* get msix vector count */
2659 /* NUMA_IO not supported for older controllers */
2660 if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2004 ||
2661 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 ||
2662 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_1 ||
2663 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_2 ||
2664 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_3 ||
2665 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_1 ||
2666 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_2)
2667 ioc->msix_vector_count = 1;
2669 pci_read_config_word(ioc->pdev, base + 2, &message_control);
2670 ioc->msix_vector_count = (message_control & 0x3FF) + 1;
2672 dinitprintk(ioc, ioc_info(ioc, "msix is supported, vector_count(%d)\n",
2673 ioc->msix_vector_count));
2678 * _base_free_irq - free irq
2679 * @ioc: per adapter object
2681 * Freeing respective reply_queue from the list.
2684 _base_free_irq(struct MPT3SAS_ADAPTER *ioc)
2686 struct adapter_reply_queue *reply_q, *next;
2688 if (list_empty(&ioc->reply_queue_list))
2691 list_for_each_entry_safe(reply_q, next, &ioc->reply_queue_list, list) {
2692 list_del(&reply_q->list);
2693 free_irq(pci_irq_vector(ioc->pdev, reply_q->msix_index),
2700 * _base_request_irq - request irq
2701 * @ioc: per adapter object
2702 * @index: msix index into vector table
2704 * Inserting respective reply_queue into the list.
2707 _base_request_irq(struct MPT3SAS_ADAPTER *ioc, u8 index)
2709 struct pci_dev *pdev = ioc->pdev;
2710 struct adapter_reply_queue *reply_q;
2713 reply_q = kzalloc(sizeof(struct adapter_reply_queue), GFP_KERNEL);
2715 ioc_err(ioc, "unable to allocate memory %zu!\n",
2716 sizeof(struct adapter_reply_queue));
2720 reply_q->msix_index = index;
2722 atomic_set(&reply_q->busy, 0);
2723 if (ioc->msix_enable)
2724 snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d-msix%d",
2725 ioc->driver_name, ioc->id, index);
2727 snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d",
2728 ioc->driver_name, ioc->id);
2729 r = request_irq(pci_irq_vector(pdev, index), _base_interrupt,
2730 IRQF_SHARED, reply_q->name, reply_q);
2732 pr_err("%s: unable to allocate interrupt %d!\n",
2733 reply_q->name, pci_irq_vector(pdev, index));
2738 INIT_LIST_HEAD(&reply_q->list);
2739 list_add_tail(&reply_q->list, &ioc->reply_queue_list);
2744 * _base_assign_reply_queues - assigning msix index for each cpu
2745 * @ioc: per adapter object
2747 * The enduser would need to set the affinity via /proc/irq/#/smp_affinity
2749 * It would nice if we could call irq_set_affinity, however it is not
2750 * an exported symbol
2753 _base_assign_reply_queues(struct MPT3SAS_ADAPTER *ioc)
2755 unsigned int cpu, nr_cpus, nr_msix, index = 0;
2756 struct adapter_reply_queue *reply_q;
2758 if (!_base_is_controller_msix_enabled(ioc))
2761 memset(ioc->cpu_msix_table, 0, ioc->cpu_msix_table_sz);
2763 nr_cpus = num_online_cpus();
2764 nr_msix = ioc->reply_queue_count = min(ioc->reply_queue_count,
2765 ioc->facts.MaxMSIxVectors);
2769 if (smp_affinity_enable) {
2770 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
2771 const cpumask_t *mask = pci_irq_get_affinity(ioc->pdev,
2772 reply_q->msix_index);
2774 ioc_warn(ioc, "no affinity for msi %x\n",
2775 reply_q->msix_index);
2779 for_each_cpu_and(cpu, mask, cpu_online_mask) {
2780 if (cpu >= ioc->cpu_msix_table_sz)
2782 ioc->cpu_msix_table[cpu] = reply_q->msix_index;
2787 cpu = cpumask_first(cpu_online_mask);
2789 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
2791 unsigned int i, group = nr_cpus / nr_msix;
2796 if (index < nr_cpus % nr_msix)
2799 for (i = 0 ; i < group ; i++) {
2800 ioc->cpu_msix_table[cpu] = reply_q->msix_index;
2801 cpu = cpumask_next(cpu, cpu_online_mask);
2808 * _base_disable_msix - disables msix
2809 * @ioc: per adapter object
2813 _base_disable_msix(struct MPT3SAS_ADAPTER *ioc)
2815 if (!ioc->msix_enable)
2817 pci_disable_msix(ioc->pdev);
2818 ioc->msix_enable = 0;
2822 * _base_enable_msix - enables msix, failback to io_apic
2823 * @ioc: per adapter object
2827 _base_enable_msix(struct MPT3SAS_ADAPTER *ioc)
2830 int i, local_max_msix_vectors;
2832 unsigned int irq_flags = PCI_IRQ_MSIX;
2834 if (msix_disable == -1 || msix_disable == 0)
2840 if (_base_check_enable_msix(ioc) != 0)
2843 ioc->reply_queue_count = min_t(int, ioc->cpu_count,
2844 ioc->msix_vector_count);
2846 ioc_info(ioc, "MSI-X vectors supported: %d, no of cores: %d, max_msix_vectors: %d\n",
2847 ioc->msix_vector_count, ioc->cpu_count, max_msix_vectors);
2849 if (!ioc->rdpq_array_enable && max_msix_vectors == -1)
2850 local_max_msix_vectors = (reset_devices) ? 1 : 8;
2852 local_max_msix_vectors = max_msix_vectors;
2854 if (local_max_msix_vectors > 0)
2855 ioc->reply_queue_count = min_t(int, local_max_msix_vectors,
2856 ioc->reply_queue_count);
2857 else if (local_max_msix_vectors == 0)
2860 if (ioc->msix_vector_count < ioc->cpu_count)
2861 smp_affinity_enable = 0;
2863 if (smp_affinity_enable)
2864 irq_flags |= PCI_IRQ_AFFINITY;
2866 r = pci_alloc_irq_vectors(ioc->pdev, 1, ioc->reply_queue_count,
2870 ioc_info(ioc, "pci_alloc_irq_vectors failed (r=%d) !!!\n",
2875 ioc->msix_enable = 1;
2876 ioc->reply_queue_count = r;
2877 for (i = 0; i < ioc->reply_queue_count; i++) {
2878 r = _base_request_irq(ioc, i);
2880 _base_free_irq(ioc);
2881 _base_disable_msix(ioc);
2888 /* failback to io_apic interrupt routing */
2891 ioc->reply_queue_count = 1;
2892 r = pci_alloc_irq_vectors(ioc->pdev, 1, 1, PCI_IRQ_LEGACY);
2895 ioc_info(ioc, "pci_alloc_irq_vector(legacy) failed (r=%d) !!!\n",
2898 r = _base_request_irq(ioc, 0);
2904 * mpt3sas_base_unmap_resources - free controller resources
2905 * @ioc: per adapter object
2908 mpt3sas_base_unmap_resources(struct MPT3SAS_ADAPTER *ioc)
2910 struct pci_dev *pdev = ioc->pdev;
2912 dexitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
2914 _base_free_irq(ioc);
2915 _base_disable_msix(ioc);
2917 kfree(ioc->replyPostRegisterIndex);
2918 ioc->replyPostRegisterIndex = NULL;
2921 if (ioc->chip_phys) {
2926 if (pci_is_enabled(pdev)) {
2927 pci_release_selected_regions(ioc->pdev, ioc->bars);
2928 pci_disable_pcie_error_reporting(pdev);
2929 pci_disable_device(pdev);
2934 * mpt3sas_base_map_resources - map in controller resources (io/irq/memap)
2935 * @ioc: per adapter object
2937 * Return: 0 for success, non-zero for failure.
2940 mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER *ioc)
2942 struct pci_dev *pdev = ioc->pdev;
2947 phys_addr_t chip_phys = 0;
2948 struct adapter_reply_queue *reply_q;
2950 dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
2952 ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
2953 if (pci_enable_device_mem(pdev)) {
2954 ioc_warn(ioc, "pci_enable_device_mem: failed\n");
2960 if (pci_request_selected_regions(pdev, ioc->bars,
2961 ioc->driver_name)) {
2962 ioc_warn(ioc, "pci_request_selected_regions: failed\n");
2968 /* AER (Advanced Error Reporting) hooks */
2969 pci_enable_pcie_error_reporting(pdev);
2971 pci_set_master(pdev);
2974 if (_base_config_dma_addressing(ioc, pdev) != 0) {
2975 ioc_warn(ioc, "no suitable DMA mask for %s\n", pci_name(pdev));
2980 for (i = 0, memap_sz = 0, pio_sz = 0; (i < DEVICE_COUNT_RESOURCE) &&
2981 (!memap_sz || !pio_sz); i++) {
2982 if (pci_resource_flags(pdev, i) & IORESOURCE_IO) {
2985 pio_chip = (u64)pci_resource_start(pdev, i);
2986 pio_sz = pci_resource_len(pdev, i);
2987 } else if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
2990 ioc->chip_phys = pci_resource_start(pdev, i);
2991 chip_phys = ioc->chip_phys;
2992 memap_sz = pci_resource_len(pdev, i);
2993 ioc->chip = ioremap(ioc->chip_phys, memap_sz);
2997 if (ioc->chip == NULL) {
2998 ioc_err(ioc, "unable to map adapter memory! or resource not found\n");
3003 _base_mask_interrupts(ioc);
3005 r = _base_get_ioc_facts(ioc);
3009 if (!ioc->rdpq_array_enable_assigned) {
3010 ioc->rdpq_array_enable = ioc->rdpq_array_capable;
3011 ioc->rdpq_array_enable_assigned = 1;
3014 r = _base_enable_msix(ioc);
3018 /* Use the Combined reply queue feature only for SAS3 C0 & higher
3019 * revision HBAs and also only when reply queue count is greater than 8
3021 if (ioc->combined_reply_queue) {
3022 /* Determine the Supplemental Reply Post Host Index Registers
3023 * Addresse. Supplemental Reply Post Host Index Registers
3024 * starts at offset MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET and
3025 * each register is at offset bytes of
3026 * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET from previous one.
3028 ioc->replyPostRegisterIndex = kcalloc(
3029 ioc->combined_reply_index_count,
3030 sizeof(resource_size_t *), GFP_KERNEL);
3031 if (!ioc->replyPostRegisterIndex) {
3033 ioc_warn(ioc, "allocation for reply Post Register Index failed!!!\n"));
3038 for (i = 0; i < ioc->combined_reply_index_count; i++) {
3039 ioc->replyPostRegisterIndex[i] = (resource_size_t *)
3040 ((u8 __force *)&ioc->chip->Doorbell +
3041 MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET +
3042 (i * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET));
3046 if (ioc->is_warpdrive) {
3047 ioc->reply_post_host_index[0] = (resource_size_t __iomem *)
3048 &ioc->chip->ReplyPostHostIndex;
3050 for (i = 1; i < ioc->cpu_msix_table_sz; i++)
3051 ioc->reply_post_host_index[i] =
3052 (resource_size_t __iomem *)
3053 ((u8 __iomem *)&ioc->chip->Doorbell + (0x4000 + ((i - 1)
3057 list_for_each_entry(reply_q, &ioc->reply_queue_list, list)
3058 pr_info("%s: %s enabled: IRQ %d\n",
3060 ioc->msix_enable ? "PCI-MSI-X" : "IO-APIC",
3061 pci_irq_vector(ioc->pdev, reply_q->msix_index));
3063 ioc_info(ioc, "iomem(%pap), mapped(0x%p), size(%d)\n",
3064 &chip_phys, ioc->chip, memap_sz);
3065 ioc_info(ioc, "ioport(0x%016llx), size(%d)\n",
3066 (unsigned long long)pio_chip, pio_sz);
3068 /* Save PCI configuration state for recovery from PCI AER/EEH errors */
3069 pci_save_state(pdev);
3073 mpt3sas_base_unmap_resources(ioc);
3078 * mpt3sas_base_get_msg_frame - obtain request mf pointer
3079 * @ioc: per adapter object
3080 * @smid: system request message index(smid zero is invalid)
3082 * Return: virt pointer to message frame.
3085 mpt3sas_base_get_msg_frame(struct MPT3SAS_ADAPTER *ioc, u16 smid)
3087 return (void *)(ioc->request + (smid * ioc->request_sz));
3091 * mpt3sas_base_get_sense_buffer - obtain a sense buffer virt addr
3092 * @ioc: per adapter object
3093 * @smid: system request message index
3095 * Return: virt pointer to sense buffer.
3098 mpt3sas_base_get_sense_buffer(struct MPT3SAS_ADAPTER *ioc, u16 smid)
3100 return (void *)(ioc->sense + ((smid - 1) * SCSI_SENSE_BUFFERSIZE));
3104 * mpt3sas_base_get_sense_buffer_dma - obtain a sense buffer dma addr
3105 * @ioc: per adapter object
3106 * @smid: system request message index
3108 * Return: phys pointer to the low 32bit address of the sense buffer.
3111 mpt3sas_base_get_sense_buffer_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid)
3113 return cpu_to_le32(ioc->sense_dma + ((smid - 1) *
3114 SCSI_SENSE_BUFFERSIZE));
3118 * mpt3sas_base_get_pcie_sgl - obtain a PCIe SGL virt addr
3119 * @ioc: per adapter object
3120 * @smid: system request message index
3122 * Return: virt pointer to a PCIe SGL.
3125 mpt3sas_base_get_pcie_sgl(struct MPT3SAS_ADAPTER *ioc, u16 smid)
3127 return (void *)(ioc->pcie_sg_lookup[smid - 1].pcie_sgl);
3131 * mpt3sas_base_get_pcie_sgl_dma - obtain a PCIe SGL dma addr
3132 * @ioc: per adapter object
3133 * @smid: system request message index
3135 * Return: phys pointer to the address of the PCIe buffer.
3138 mpt3sas_base_get_pcie_sgl_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid)
3140 return ioc->pcie_sg_lookup[smid - 1].pcie_sgl_dma;
3144 * mpt3sas_base_get_reply_virt_addr - obtain reply frames virt address
3145 * @ioc: per adapter object
3146 * @phys_addr: lower 32 physical addr of the reply
3148 * Converts 32bit lower physical addr into a virt address.
3151 mpt3sas_base_get_reply_virt_addr(struct MPT3SAS_ADAPTER *ioc, u32 phys_addr)
3155 return ioc->reply + (phys_addr - (u32)ioc->reply_dma);
3159 _base_get_msix_index(struct MPT3SAS_ADAPTER *ioc)
3161 return ioc->cpu_msix_table[raw_smp_processor_id()];
3165 * mpt3sas_base_get_smid - obtain a free smid from internal queue
3166 * @ioc: per adapter object
3167 * @cb_idx: callback index
3169 * Return: smid (zero is invalid)
3172 mpt3sas_base_get_smid(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx)
3174 unsigned long flags;
3175 struct request_tracker *request;
3178 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
3179 if (list_empty(&ioc->internal_free_list)) {
3180 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
3181 ioc_err(ioc, "%s: smid not available\n", __func__);
3185 request = list_entry(ioc->internal_free_list.next,
3186 struct request_tracker, tracker_list);
3187 request->cb_idx = cb_idx;
3188 smid = request->smid;
3189 list_del(&request->tracker_list);
3190 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
3195 * mpt3sas_base_get_smid_scsiio - obtain a free smid from scsiio queue
3196 * @ioc: per adapter object
3197 * @cb_idx: callback index
3198 * @scmd: pointer to scsi command object
3200 * Return: smid (zero is invalid)
3203 mpt3sas_base_get_smid_scsiio(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx,
3204 struct scsi_cmnd *scmd)
3206 struct scsiio_tracker *request = scsi_cmd_priv(scmd);
3207 unsigned int tag = scmd->request->tag;
3211 request->cb_idx = cb_idx;
3212 request->msix_io = _base_get_msix_index(ioc);
3213 request->smid = smid;
3214 INIT_LIST_HEAD(&request->chain_list);
3219 * mpt3sas_base_get_smid_hpr - obtain a free smid from hi-priority queue
3220 * @ioc: per adapter object
3221 * @cb_idx: callback index
3223 * Return: smid (zero is invalid)
3226 mpt3sas_base_get_smid_hpr(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx)
3228 unsigned long flags;
3229 struct request_tracker *request;
3232 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
3233 if (list_empty(&ioc->hpr_free_list)) {
3234 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
3238 request = list_entry(ioc->hpr_free_list.next,
3239 struct request_tracker, tracker_list);
3240 request->cb_idx = cb_idx;
3241 smid = request->smid;
3242 list_del(&request->tracker_list);
3243 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
3248 _base_recovery_check(struct MPT3SAS_ADAPTER *ioc)
3251 * See _wait_for_commands_to_complete() call with regards to this code.
3253 if (ioc->shost_recovery && ioc->pending_io_count) {
3254 ioc->pending_io_count = scsi_host_busy(ioc->shost);
3255 if (ioc->pending_io_count == 0)
3256 wake_up(&ioc->reset_wq);
3260 void mpt3sas_base_clear_st(struct MPT3SAS_ADAPTER *ioc,
3261 struct scsiio_tracker *st)
3263 if (WARN_ON(st->smid == 0))
3267 atomic_set(&ioc->chain_lookup[st->smid - 1].chain_offset, 0);
3272 * mpt3sas_base_free_smid - put smid back on free_list
3273 * @ioc: per adapter object
3274 * @smid: system request message index
3277 mpt3sas_base_free_smid(struct MPT3SAS_ADAPTER *ioc, u16 smid)
3279 unsigned long flags;
3282 if (smid < ioc->hi_priority_smid) {
3283 struct scsiio_tracker *st;
3285 st = _get_st_from_smid(ioc, smid);
3287 _base_recovery_check(ioc);
3290 mpt3sas_base_clear_st(ioc, st);
3291 _base_recovery_check(ioc);
3295 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
3296 if (smid < ioc->internal_smid) {
3298 i = smid - ioc->hi_priority_smid;
3299 ioc->hpr_lookup[i].cb_idx = 0xFF;
3300 list_add(&ioc->hpr_lookup[i].tracker_list, &ioc->hpr_free_list);
3301 } else if (smid <= ioc->hba_queue_depth) {
3302 /* internal queue */
3303 i = smid - ioc->internal_smid;
3304 ioc->internal_lookup[i].cb_idx = 0xFF;
3305 list_add(&ioc->internal_lookup[i].tracker_list,
3306 &ioc->internal_free_list);
3308 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
3312 * _base_mpi_ep_writeq - 32 bit write to MMIO
3314 * @addr: address in MMIO space
3315 * @writeq_lock: spin lock
3317 * This special handling for MPI EP to take care of 32 bit
3318 * environment where its not quarenteed to send the entire word
3322 _base_mpi_ep_writeq(__u64 b, volatile void __iomem *addr,
3323 spinlock_t *writeq_lock)
3325 unsigned long flags;
3327 spin_lock_irqsave(writeq_lock, flags);
3328 __raw_writel((u32)(b), addr);
3329 __raw_writel((u32)(b >> 32), (addr + 4));
3331 spin_unlock_irqrestore(writeq_lock, flags);
3335 * _base_writeq - 64 bit write to MMIO
3337 * @addr: address in MMIO space
3338 * @writeq_lock: spin lock
3340 * Glue for handling an atomic 64 bit word to MMIO. This special handling takes
3341 * care of 32 bit environment where its not quarenteed to send the entire word
3344 #if defined(writeq) && defined(CONFIG_64BIT)
3346 _base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock)
3349 __raw_writeq(b, addr);
3354 _base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock)
3356 _base_mpi_ep_writeq(b, addr, writeq_lock);
3361 * _base_put_smid_mpi_ep_scsi_io - send SCSI_IO request to firmware
3362 * @ioc: per adapter object
3363 * @smid: system request message index
3364 * @handle: device handle
3367 _base_put_smid_mpi_ep_scsi_io(struct MPT3SAS_ADAPTER *ioc, u16 smid, u16 handle)
3369 Mpi2RequestDescriptorUnion_t descriptor;
3370 u64 *request = (u64 *)&descriptor;
3371 void *mpi_req_iomem;
3372 __le32 *mfp = (__le32 *)mpt3sas_base_get_msg_frame(ioc, smid);
3374 _clone_sg_entries(ioc, (void *) mfp, smid);
3375 mpi_req_iomem = (void __force *)ioc->chip +
3376 MPI_FRAME_START_OFFSET + (smid * ioc->request_sz);
3377 _base_clone_mpi_to_sys_mem(mpi_req_iomem, (void *)mfp,
3379 descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
3380 descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc);
3381 descriptor.SCSIIO.SMID = cpu_to_le16(smid);
3382 descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
3383 descriptor.SCSIIO.LMID = 0;
3384 _base_mpi_ep_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
3385 &ioc->scsi_lookup_lock);
3389 * _base_put_smid_scsi_io - send SCSI_IO request to firmware
3390 * @ioc: per adapter object
3391 * @smid: system request message index
3392 * @handle: device handle
3395 _base_put_smid_scsi_io(struct MPT3SAS_ADAPTER *ioc, u16 smid, u16 handle)
3397 Mpi2RequestDescriptorUnion_t descriptor;
3398 u64 *request = (u64 *)&descriptor;
3401 descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
3402 descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc);
3403 descriptor.SCSIIO.SMID = cpu_to_le16(smid);
3404 descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
3405 descriptor.SCSIIO.LMID = 0;
3406 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
3407 &ioc->scsi_lookup_lock);
3411 * mpt3sas_base_put_smid_fast_path - send fast path request to firmware
3412 * @ioc: per adapter object
3413 * @smid: system request message index
3414 * @handle: device handle
3417 mpt3sas_base_put_smid_fast_path(struct MPT3SAS_ADAPTER *ioc, u16 smid,
3420 Mpi2RequestDescriptorUnion_t descriptor;
3421 u64 *request = (u64 *)&descriptor;
3423 descriptor.SCSIIO.RequestFlags =
3424 MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO;
3425 descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc);
3426 descriptor.SCSIIO.SMID = cpu_to_le16(smid);
3427 descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
3428 descriptor.SCSIIO.LMID = 0;
3429 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
3430 &ioc->scsi_lookup_lock);
3434 * mpt3sas_base_put_smid_hi_priority - send Task Management request to firmware
3435 * @ioc: per adapter object
3436 * @smid: system request message index
3437 * @msix_task: msix_task will be same as msix of IO incase of task abort else 0.
3440 mpt3sas_base_put_smid_hi_priority(struct MPT3SAS_ADAPTER *ioc, u16 smid,
3443 Mpi2RequestDescriptorUnion_t descriptor;
3444 void *mpi_req_iomem;
3447 if (ioc->is_mcpu_endpoint) {
3448 __le32 *mfp = (__le32 *)mpt3sas_base_get_msg_frame(ioc, smid);
3450 /* TBD 256 is offset within sys register. */
3451 mpi_req_iomem = (void __force *)ioc->chip
3452 + MPI_FRAME_START_OFFSET
3453 + (smid * ioc->request_sz);
3454 _base_clone_mpi_to_sys_mem(mpi_req_iomem, (void *)mfp,
3458 request = (u64 *)&descriptor;
3460 descriptor.HighPriority.RequestFlags =
3461 MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY;
3462 descriptor.HighPriority.MSIxIndex = msix_task;
3463 descriptor.HighPriority.SMID = cpu_to_le16(smid);
3464 descriptor.HighPriority.LMID = 0;
3465 descriptor.HighPriority.Reserved1 = 0;
3466 if (ioc->is_mcpu_endpoint)
3467 _base_mpi_ep_writeq(*request,
3468 &ioc->chip->RequestDescriptorPostLow,
3469 &ioc->scsi_lookup_lock);
3471 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
3472 &ioc->scsi_lookup_lock);
3476 * mpt3sas_base_put_smid_nvme_encap - send NVMe encapsulated request to
3478 * @ioc: per adapter object
3479 * @smid: system request message index
3482 mpt3sas_base_put_smid_nvme_encap(struct MPT3SAS_ADAPTER *ioc, u16 smid)
3484 Mpi2RequestDescriptorUnion_t descriptor;
3485 u64 *request = (u64 *)&descriptor;
3487 descriptor.Default.RequestFlags =
3488 MPI26_REQ_DESCRIPT_FLAGS_PCIE_ENCAPSULATED;
3489 descriptor.Default.MSIxIndex = _base_get_msix_index(ioc);
3490 descriptor.Default.SMID = cpu_to_le16(smid);
3491 descriptor.Default.LMID = 0;
3492 descriptor.Default.DescriptorTypeDependent = 0;
3493 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
3494 &ioc->scsi_lookup_lock);
3498 * mpt3sas_base_put_smid_default - Default, primarily used for config pages
3499 * @ioc: per adapter object
3500 * @smid: system request message index
3503 mpt3sas_base_put_smid_default(struct MPT3SAS_ADAPTER *ioc, u16 smid)
3505 Mpi2RequestDescriptorUnion_t descriptor;
3506 void *mpi_req_iomem;
3509 if (ioc->is_mcpu_endpoint) {
3510 __le32 *mfp = (__le32 *)mpt3sas_base_get_msg_frame(ioc, smid);
3512 _clone_sg_entries(ioc, (void *) mfp, smid);
3513 /* TBD 256 is offset within sys register */
3514 mpi_req_iomem = (void __force *)ioc->chip +
3515 MPI_FRAME_START_OFFSET + (smid * ioc->request_sz);
3516 _base_clone_mpi_to_sys_mem(mpi_req_iomem, (void *)mfp,
3519 request = (u64 *)&descriptor;
3520 descriptor.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
3521 descriptor.Default.MSIxIndex = _base_get_msix_index(ioc);
3522 descriptor.Default.SMID = cpu_to_le16(smid);
3523 descriptor.Default.LMID = 0;
3524 descriptor.Default.DescriptorTypeDependent = 0;
3525 if (ioc->is_mcpu_endpoint)
3526 _base_mpi_ep_writeq(*request,
3527 &ioc->chip->RequestDescriptorPostLow,
3528 &ioc->scsi_lookup_lock);
3530 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
3531 &ioc->scsi_lookup_lock);
3535 * _base_display_OEMs_branding - Display branding string
3536 * @ioc: per adapter object
3539 _base_display_OEMs_branding(struct MPT3SAS_ADAPTER *ioc)
3541 if (ioc->pdev->subsystem_vendor != PCI_VENDOR_ID_INTEL)
3544 switch (ioc->pdev->subsystem_vendor) {
3545 case PCI_VENDOR_ID_INTEL:
3546 switch (ioc->pdev->device) {
3547 case MPI2_MFGPAGE_DEVID_SAS2008:
3548 switch (ioc->pdev->subsystem_device) {
3549 case MPT2SAS_INTEL_RMS2LL080_SSDID:
3550 ioc_info(ioc, "%s\n",
3551 MPT2SAS_INTEL_RMS2LL080_BRANDING);
3553 case MPT2SAS_INTEL_RMS2LL040_SSDID:
3554 ioc_info(ioc, "%s\n",
3555 MPT2SAS_INTEL_RMS2LL040_BRANDING);
3557 case MPT2SAS_INTEL_SSD910_SSDID:
3558 ioc_info(ioc, "%s\n",
3559 MPT2SAS_INTEL_SSD910_BRANDING);
3562 ioc_info(ioc, "Intel(R) Controller: Subsystem ID: 0x%X\n",
3563 ioc->pdev->subsystem_device);
3567 case MPI2_MFGPAGE_DEVID_SAS2308_2:
3568 switch (ioc->pdev->subsystem_device) {
3569 case MPT2SAS_INTEL_RS25GB008_SSDID:
3570 ioc_info(ioc, "%s\n",
3571 MPT2SAS_INTEL_RS25GB008_BRANDING);
3573 case MPT2SAS_INTEL_RMS25JB080_SSDID:
3574 ioc_info(ioc, "%s\n",
3575 MPT2SAS_INTEL_RMS25JB080_BRANDING);
3577 case MPT2SAS_INTEL_RMS25JB040_SSDID:
3578 ioc_info(ioc, "%s\n",
3579 MPT2SAS_INTEL_RMS25JB040_BRANDING);
3581 case MPT2SAS_INTEL_RMS25KB080_SSDID:
3582 ioc_info(ioc, "%s\n",
3583 MPT2SAS_INTEL_RMS25KB080_BRANDING);
3585 case MPT2SAS_INTEL_RMS25KB040_SSDID:
3586 ioc_info(ioc, "%s\n",
3587 MPT2SAS_INTEL_RMS25KB040_BRANDING);
3589 case MPT2SAS_INTEL_RMS25LB040_SSDID:
3590 ioc_info(ioc, "%s\n",
3591 MPT2SAS_INTEL_RMS25LB040_BRANDING);
3593 case MPT2SAS_INTEL_RMS25LB080_SSDID:
3594 ioc_info(ioc, "%s\n",
3595 MPT2SAS_INTEL_RMS25LB080_BRANDING);
3598 ioc_info(ioc, "Intel(R) Controller: Subsystem ID: 0x%X\n",
3599 ioc->pdev->subsystem_device);
3603 case MPI25_MFGPAGE_DEVID_SAS3008:
3604 switch (ioc->pdev->subsystem_device) {
3605 case MPT3SAS_INTEL_RMS3JC080_SSDID:
3606 ioc_info(ioc, "%s\n",
3607 MPT3SAS_INTEL_RMS3JC080_BRANDING);
3610 case MPT3SAS_INTEL_RS3GC008_SSDID:
3611 ioc_info(ioc, "%s\n",
3612 MPT3SAS_INTEL_RS3GC008_BRANDING);
3614 case MPT3SAS_INTEL_RS3FC044_SSDID:
3615 ioc_info(ioc, "%s\n",
3616 MPT3SAS_INTEL_RS3FC044_BRANDING);
3618 case MPT3SAS_INTEL_RS3UC080_SSDID:
3619 ioc_info(ioc, "%s\n",
3620 MPT3SAS_INTEL_RS3UC080_BRANDING);
3623 ioc_info(ioc, "Intel(R) Controller: Subsystem ID: 0x%X\n",
3624 ioc->pdev->subsystem_device);
3629 ioc_info(ioc, "Intel(R) Controller: Subsystem ID: 0x%X\n",
3630 ioc->pdev->subsystem_device);
3634 case PCI_VENDOR_ID_DELL:
3635 switch (ioc->pdev->device) {
3636 case MPI2_MFGPAGE_DEVID_SAS2008:
3637 switch (ioc->pdev->subsystem_device) {
3638 case MPT2SAS_DELL_6GBPS_SAS_HBA_SSDID:
3639 ioc_info(ioc, "%s\n",
3640 MPT2SAS_DELL_6GBPS_SAS_HBA_BRANDING);
3642 case MPT2SAS_DELL_PERC_H200_ADAPTER_SSDID:
3643 ioc_info(ioc, "%s\n",
3644 MPT2SAS_DELL_PERC_H200_ADAPTER_BRANDING);
3646 case MPT2SAS_DELL_PERC_H200_INTEGRATED_SSDID:
3647 ioc_info(ioc, "%s\n",
3648 MPT2SAS_DELL_PERC_H200_INTEGRATED_BRANDING);
3650 case MPT2SAS_DELL_PERC_H200_MODULAR_SSDID:
3651 ioc_info(ioc, "%s\n",
3652 MPT2SAS_DELL_PERC_H200_MODULAR_BRANDING);
3654 case MPT2SAS_DELL_PERC_H200_EMBEDDED_SSDID:
3655 ioc_info(ioc, "%s\n",
3656 MPT2SAS_DELL_PERC_H200_EMBEDDED_BRANDING);
3658 case MPT2SAS_DELL_PERC_H200_SSDID:
3659 ioc_info(ioc, "%s\n",
3660 MPT2SAS_DELL_PERC_H200_BRANDING);
3662 case MPT2SAS_DELL_6GBPS_SAS_SSDID:
3663 ioc_info(ioc, "%s\n",
3664 MPT2SAS_DELL_6GBPS_SAS_BRANDING);
3667 ioc_info(ioc, "Dell 6Gbps HBA: Subsystem ID: 0x%X\n",
3668 ioc->pdev->subsystem_device);
3672 case MPI25_MFGPAGE_DEVID_SAS3008:
3673 switch (ioc->pdev->subsystem_device) {
3674 case MPT3SAS_DELL_12G_HBA_SSDID:
3675 ioc_info(ioc, "%s\n",
3676 MPT3SAS_DELL_12G_HBA_BRANDING);
3679 ioc_info(ioc, "Dell 12Gbps HBA: Subsystem ID: 0x%X\n",
3680 ioc->pdev->subsystem_device);
3685 ioc_info(ioc, "Dell HBA: Subsystem ID: 0x%X\n",
3686 ioc->pdev->subsystem_device);
3690 case PCI_VENDOR_ID_CISCO:
3691 switch (ioc->pdev->device) {
3692 case MPI25_MFGPAGE_DEVID_SAS3008:
3693 switch (ioc->pdev->subsystem_device) {
3694 case MPT3SAS_CISCO_12G_8E_HBA_SSDID:
3695 ioc_info(ioc, "%s\n",
3696 MPT3SAS_CISCO_12G_8E_HBA_BRANDING);
3698 case MPT3SAS_CISCO_12G_8I_HBA_SSDID:
3699 ioc_info(ioc, "%s\n",
3700 MPT3SAS_CISCO_12G_8I_HBA_BRANDING);
3702 case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID:
3703 ioc_info(ioc, "%s\n",
3704 MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING);
3707 ioc_info(ioc, "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n",
3708 ioc->pdev->subsystem_device);
3712 case MPI25_MFGPAGE_DEVID_SAS3108_1:
3713 switch (ioc->pdev->subsystem_device) {
3714 case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID:
3715 ioc_info(ioc, "%s\n",
3716 MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING);
3718 case MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_SSDID:
3719 ioc_info(ioc, "%s\n",
3720 MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_BRANDING);
3723 ioc_info(ioc, "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n",
3724 ioc->pdev->subsystem_device);
3729 ioc_info(ioc, "Cisco SAS HBA: Subsystem ID: 0x%X\n",
3730 ioc->pdev->subsystem_device);
3734 case MPT2SAS_HP_3PAR_SSVID:
3735 switch (ioc->pdev->device) {
3736 case MPI2_MFGPAGE_DEVID_SAS2004:
3737 switch (ioc->pdev->subsystem_device) {
3738 case MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_SSDID:
3739 ioc_info(ioc, "%s\n",
3740 MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_BRANDING);
3743 ioc_info(ioc, "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n",
3744 ioc->pdev->subsystem_device);
3748 case MPI2_MFGPAGE_DEVID_SAS2308_2:
3749 switch (ioc->pdev->subsystem_device) {
3750 case MPT2SAS_HP_2_4_INTERNAL_SSDID:
3751 ioc_info(ioc, "%s\n",
3752 MPT2SAS_HP_2_4_INTERNAL_BRANDING);
3754 case MPT2SAS_HP_2_4_EXTERNAL_SSDID:
3755 ioc_info(ioc, "%s\n",
3756 MPT2SAS_HP_2_4_EXTERNAL_BRANDING);
3758 case MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_SSDID:
3759 ioc_info(ioc, "%s\n",
3760 MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_BRANDING);
3762 case MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_SSDID:
3763 ioc_info(ioc, "%s\n",
3764 MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_BRANDING);
3767 ioc_info(ioc, "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n",
3768 ioc->pdev->subsystem_device);
3773 ioc_info(ioc, "HP SAS HBA: Subsystem ID: 0x%X\n",
3774 ioc->pdev->subsystem_device);
3783 * _base_display_fwpkg_version - sends FWUpload request to pull FWPkg
3784 * version from FW Image Header.
3785 * @ioc: per adapter object
3787 * Return: 0 for success, non-zero for failure.
3790 _base_display_fwpkg_version(struct MPT3SAS_ADAPTER *ioc)
3792 Mpi2FWImageHeader_t *FWImgHdr;
3793 Mpi25FWUploadRequest_t *mpi_request;
3794 Mpi2FWUploadReply_t mpi_reply;
3796 void *fwpkg_data = NULL;
3797 dma_addr_t fwpkg_data_dma;
3798 u16 smid, ioc_status;
3801 dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
3803 if (ioc->base_cmds.status & MPT3_CMD_PENDING) {
3804 ioc_err(ioc, "%s: internal command already in use\n", __func__);
3808 data_length = sizeof(Mpi2FWImageHeader_t);
3809 fwpkg_data = dma_alloc_coherent(&ioc->pdev->dev, data_length,
3810 &fwpkg_data_dma, GFP_KERNEL);
3812 ioc_err(ioc, "failure at %s:%d/%s()!\n",
3813 __FILE__, __LINE__, __func__);
3817 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
3819 ioc_err(ioc, "%s: failed obtaining a smid\n", __func__);
3824 ioc->base_cmds.status = MPT3_CMD_PENDING;
3825 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
3826 ioc->base_cmds.smid = smid;
3827 memset(mpi_request, 0, sizeof(Mpi25FWUploadRequest_t));
3828 mpi_request->Function = MPI2_FUNCTION_FW_UPLOAD;
3829 mpi_request->ImageType = MPI2_FW_UPLOAD_ITYPE_FW_FLASH;
3830 mpi_request->ImageSize = cpu_to_le32(data_length);
3831 ioc->build_sg(ioc, &mpi_request->SGL, 0, 0, fwpkg_data_dma,
3833 init_completion(&ioc->base_cmds.done);
3834 mpt3sas_base_put_smid_default(ioc, smid);
3835 /* Wait for 15 seconds */
3836 wait_for_completion_timeout(&ioc->base_cmds.done,
3837 FW_IMG_HDR_READ_TIMEOUT*HZ);
3838 ioc_info(ioc, "%s: complete\n", __func__);
3839 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
3840 ioc_err(ioc, "%s: timeout\n", __func__);
3841 _debug_dump_mf(mpi_request,
3842 sizeof(Mpi25FWUploadRequest_t)/4);
3845 memset(&mpi_reply, 0, sizeof(Mpi2FWUploadReply_t));
3846 if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID) {
3847 memcpy(&mpi_reply, ioc->base_cmds.reply,
3848 sizeof(Mpi2FWUploadReply_t));
3849 ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
3850 MPI2_IOCSTATUS_MASK;
3851 if (ioc_status == MPI2_IOCSTATUS_SUCCESS) {
3852 FWImgHdr = (Mpi2FWImageHeader_t *)fwpkg_data;
3853 if (FWImgHdr->PackageVersion.Word) {
3854 ioc_info(ioc, "FW Package Version (%02d.%02d.%02d.%02d)\n",
3855 FWImgHdr->PackageVersion.Struct.Major,
3856 FWImgHdr->PackageVersion.Struct.Minor,
3857 FWImgHdr->PackageVersion.Struct.Unit,
3858 FWImgHdr->PackageVersion.Struct.Dev);
3861 _debug_dump_mf(&mpi_reply,
3862 sizeof(Mpi2FWUploadReply_t)/4);
3866 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
3869 dma_free_coherent(&ioc->pdev->dev, data_length, fwpkg_data,
3875 * _base_display_ioc_capabilities - Disply IOC's capabilities.
3876 * @ioc: per adapter object
3879 _base_display_ioc_capabilities(struct MPT3SAS_ADAPTER *ioc)
3883 u32 iounit_pg1_flags;
3886 bios_version = le32_to_cpu(ioc->bios_pg3.BiosVersion);
3887 strncpy(desc, ioc->manu_pg0.ChipName, 16);
3888 ioc_info(ioc, "%s: FWVersion(%02d.%02d.%02d.%02d), ChipRevision(0x%02x), BiosVersion(%02d.%02d.%02d.%02d)\n",
3890 (ioc->facts.FWVersion.Word & 0xFF000000) >> 24,
3891 (ioc->facts.FWVersion.Word & 0x00FF0000) >> 16,
3892 (ioc->facts.FWVersion.Word & 0x0000FF00) >> 8,
3893 ioc->facts.FWVersion.Word & 0x000000FF,
3894 ioc->pdev->revision,
3895 (bios_version & 0xFF000000) >> 24,
3896 (bios_version & 0x00FF0000) >> 16,
3897 (bios_version & 0x0000FF00) >> 8,
3898 bios_version & 0x000000FF);
3900 _base_display_OEMs_branding(ioc);
3902 if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES) {
3903 pr_info("%sNVMe", i ? "," : "");
3907 ioc_info(ioc, "Protocol=(");
3909 if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR) {
3910 pr_cont("Initiator");
3914 if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET) {
3915 pr_cont("%sTarget", i ? "," : "");
3920 pr_cont("), Capabilities=(");
3922 if (!ioc->hide_ir_msg) {
3923 if (ioc->facts.IOCCapabilities &
3924 MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID) {
3930 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_TLR) {
3931 pr_cont("%sTLR", i ? "," : "");
3935 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_MULTICAST) {
3936 pr_cont("%sMulticast", i ? "," : "");
3940 if (ioc->facts.IOCCapabilities &
3941 MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET) {
3942 pr_cont("%sBIDI Target", i ? "," : "");
3946 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_EEDP) {
3947 pr_cont("%sEEDP", i ? "," : "");
3951 if (ioc->facts.IOCCapabilities &
3952 MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER) {
3953 pr_cont("%sSnapshot Buffer", i ? "," : "");
3957 if (ioc->facts.IOCCapabilities &
3958 MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER) {
3959 pr_cont("%sDiag Trace Buffer", i ? "," : "");
3963 if (ioc->facts.IOCCapabilities &
3964 MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER) {
3965 pr_cont("%sDiag Extended Buffer", i ? "," : "");
3969 if (ioc->facts.IOCCapabilities &
3970 MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING) {
3971 pr_cont("%sTask Set Full", i ? "," : "");
3975 iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
3976 if (!(iounit_pg1_flags & MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE)) {
3977 pr_cont("%sNCQ", i ? "," : "");
3985 * mpt3sas_base_update_missing_delay - change the missing delay timers
3986 * @ioc: per adapter object
3987 * @device_missing_delay: amount of time till device is reported missing
3988 * @io_missing_delay: interval IO is returned when there is a missing device
3990 * Passed on the command line, this function will modify the device missing
3991 * delay, as well as the io missing delay. This should be called at driver
3995 mpt3sas_base_update_missing_delay(struct MPT3SAS_ADAPTER *ioc,
3996 u16 device_missing_delay, u8 io_missing_delay)
3998 u16 dmd, dmd_new, dmd_orignal;
3999 u8 io_missing_delay_original;
4001 Mpi2SasIOUnitPage1_t *sas_iounit_pg1 = NULL;
4002 Mpi2ConfigReply_t mpi_reply;
4006 mpt3sas_config_get_number_hba_phys(ioc, &num_phys);
4010 sz = offsetof(Mpi2SasIOUnitPage1_t, PhyData) + (num_phys *
4011 sizeof(Mpi2SasIOUnit1PhyData_t));
4012 sas_iounit_pg1 = kzalloc(sz, GFP_KERNEL);
4013 if (!sas_iounit_pg1) {
4014 ioc_err(ioc, "failure at %s:%d/%s()!\n",
4015 __FILE__, __LINE__, __func__);
4018 if ((mpt3sas_config_get_sas_iounit_pg1(ioc, &mpi_reply,
4019 sas_iounit_pg1, sz))) {
4020 ioc_err(ioc, "failure at %s:%d/%s()!\n",
4021 __FILE__, __LINE__, __func__);
4024 ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
4025 MPI2_IOCSTATUS_MASK;
4026 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
4027 ioc_err(ioc, "failure at %s:%d/%s()!\n",
4028 __FILE__, __LINE__, __func__);
4032 /* device missing delay */
4033 dmd = sas_iounit_pg1->ReportDeviceMissingDelay;
4034 if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16)
4035 dmd = (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16;
4037 dmd = dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK;
4039 if (device_missing_delay > 0x7F) {
4040 dmd = (device_missing_delay > 0x7F0) ? 0x7F0 :
4041 device_missing_delay;
4043 dmd |= MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16;
4045 dmd = device_missing_delay;
4046 sas_iounit_pg1->ReportDeviceMissingDelay = dmd;
4048 /* io missing delay */
4049 io_missing_delay_original = sas_iounit_pg1->IODeviceMissingDelay;
4050 sas_iounit_pg1->IODeviceMissingDelay = io_missing_delay;
4052 if (!mpt3sas_config_set_sas_iounit_pg1(ioc, &mpi_reply, sas_iounit_pg1,
4054 if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16)
4056 MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16;
4059 dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK;
4060 ioc_info(ioc, "device_missing_delay: old(%d), new(%d)\n",
4061 dmd_orignal, dmd_new);
4062 ioc_info(ioc, "ioc_missing_delay: old(%d), new(%d)\n",
4063 io_missing_delay_original,
4065 ioc->device_missing_delay = dmd_new;
4066 ioc->io_missing_delay = io_missing_delay;
4070 kfree(sas_iounit_pg1);
4074 * _base_static_config_pages - static start of day config pages
4075 * @ioc: per adapter object
4078 _base_static_config_pages(struct MPT3SAS_ADAPTER *ioc)
4080 Mpi2ConfigReply_t mpi_reply;
4081 u32 iounit_pg1_flags;
4083 ioc->nvme_abort_timeout = 30;
4084 mpt3sas_config_get_manufacturing_pg0(ioc, &mpi_reply, &ioc->manu_pg0);
4085 if (ioc->ir_firmware)
4086 mpt3sas_config_get_manufacturing_pg10(ioc, &mpi_reply,
4090 * Ensure correct T10 PI operation if vendor left EEDPTagMode
4091 * flag unset in NVDATA.
4093 mpt3sas_config_get_manufacturing_pg11(ioc, &mpi_reply, &ioc->manu_pg11);
4094 if (!ioc->is_gen35_ioc && ioc->manu_pg11.EEDPTagMode == 0) {
4095 pr_err("%s: overriding NVDATA EEDPTagMode setting\n",
4097 ioc->manu_pg11.EEDPTagMode &= ~0x3;
4098 ioc->manu_pg11.EEDPTagMode |= 0x1;
4099 mpt3sas_config_set_manufacturing_pg11(ioc, &mpi_reply,
4102 if (ioc->manu_pg11.AddlFlags2 & NVME_TASK_MNGT_CUSTOM_MASK)
4103 ioc->tm_custom_handling = 1;
4105 ioc->tm_custom_handling = 0;
4106 if (ioc->manu_pg11.NVMeAbortTO < NVME_TASK_ABORT_MIN_TIMEOUT)
4107 ioc->nvme_abort_timeout = NVME_TASK_ABORT_MIN_TIMEOUT;
4108 else if (ioc->manu_pg11.NVMeAbortTO >
4109 NVME_TASK_ABORT_MAX_TIMEOUT)
4110 ioc->nvme_abort_timeout = NVME_TASK_ABORT_MAX_TIMEOUT;
4112 ioc->nvme_abort_timeout = ioc->manu_pg11.NVMeAbortTO;
4115 mpt3sas_config_get_bios_pg2(ioc, &mpi_reply, &ioc->bios_pg2);
4116 mpt3sas_config_get_bios_pg3(ioc, &mpi_reply, &ioc->bios_pg3);
4117 mpt3sas_config_get_ioc_pg8(ioc, &mpi_reply, &ioc->ioc_pg8);
4118 mpt3sas_config_get_iounit_pg0(ioc, &mpi_reply, &ioc->iounit_pg0);
4119 mpt3sas_config_get_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
4120 mpt3sas_config_get_iounit_pg8(ioc, &mpi_reply, &ioc->iounit_pg8);
4121 _base_display_ioc_capabilities(ioc);
4124 * Enable task_set_full handling in iounit_pg1 when the
4125 * facts capabilities indicate that its supported.
4127 iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
4128 if ((ioc->facts.IOCCapabilities &
4129 MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING))
4131 ~MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
4134 MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
4135 ioc->iounit_pg1.Flags = cpu_to_le32(iounit_pg1_flags);
4136 mpt3sas_config_set_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
4138 if (ioc->iounit_pg8.NumSensors)
4139 ioc->temp_sensors_count = ioc->iounit_pg8.NumSensors;
4143 * mpt3sas_free_enclosure_list - release memory
4144 * @ioc: per adapter object
4146 * Free memory allocated during encloure add.
4149 mpt3sas_free_enclosure_list(struct MPT3SAS_ADAPTER *ioc)
4151 struct _enclosure_node *enclosure_dev, *enclosure_dev_next;
4153 /* Free enclosure list */
4154 list_for_each_entry_safe(enclosure_dev,
4155 enclosure_dev_next, &ioc->enclosure_list, list) {
4156 list_del(&enclosure_dev->list);
4157 kfree(enclosure_dev);
4162 * _base_release_memory_pools - release memory
4163 * @ioc: per adapter object
4165 * Free memory allocated from _base_allocate_memory_pools.
4168 _base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc)
4172 struct chain_tracker *ct;
4173 struct reply_post_struct *rps;
4175 dexitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
4178 dma_free_coherent(&ioc->pdev->dev, ioc->request_dma_sz,
4179 ioc->request, ioc->request_dma);
4181 ioc_info(ioc, "request_pool(0x%p): free\n",
4183 ioc->request = NULL;
4187 dma_pool_free(ioc->sense_dma_pool, ioc->sense, ioc->sense_dma);
4188 dma_pool_destroy(ioc->sense_dma_pool);
4190 ioc_info(ioc, "sense_pool(0x%p): free\n",
4196 dma_pool_free(ioc->reply_dma_pool, ioc->reply, ioc->reply_dma);
4197 dma_pool_destroy(ioc->reply_dma_pool);
4199 ioc_info(ioc, "reply_pool(0x%p): free\n",
4204 if (ioc->reply_free) {
4205 dma_pool_free(ioc->reply_free_dma_pool, ioc->reply_free,
4206 ioc->reply_free_dma);
4207 dma_pool_destroy(ioc->reply_free_dma_pool);
4209 ioc_info(ioc, "reply_free_pool(0x%p): free\n",
4211 ioc->reply_free = NULL;
4214 if (ioc->reply_post) {
4216 rps = &ioc->reply_post[i];
4217 if (rps->reply_post_free) {
4219 ioc->reply_post_free_dma_pool,
4220 rps->reply_post_free,
4221 rps->reply_post_free_dma);
4223 ioc_info(ioc, "reply_post_free_pool(0x%p): free\n",
4224 rps->reply_post_free));
4225 rps->reply_post_free = NULL;
4227 } while (ioc->rdpq_array_enable &&
4228 (++i < ioc->reply_queue_count));
4229 if (ioc->reply_post_free_array &&
4230 ioc->rdpq_array_enable) {
4231 dma_pool_free(ioc->reply_post_free_array_dma_pool,
4232 ioc->reply_post_free_array,
4233 ioc->reply_post_free_array_dma);
4234 ioc->reply_post_free_array = NULL;
4236 dma_pool_destroy(ioc->reply_post_free_array_dma_pool);
4237 dma_pool_destroy(ioc->reply_post_free_dma_pool);
4238 kfree(ioc->reply_post);
4241 if (ioc->pcie_sgl_dma_pool) {
4242 for (i = 0; i < ioc->scsiio_depth; i++) {
4243 dma_pool_free(ioc->pcie_sgl_dma_pool,
4244 ioc->pcie_sg_lookup[i].pcie_sgl,
4245 ioc->pcie_sg_lookup[i].pcie_sgl_dma);
4247 if (ioc->pcie_sgl_dma_pool)
4248 dma_pool_destroy(ioc->pcie_sgl_dma_pool);
4251 if (ioc->config_page) {
4253 ioc_info(ioc, "config_page(0x%p): free\n",
4255 dma_free_coherent(&ioc->pdev->dev, ioc->config_page_sz,
4256 ioc->config_page, ioc->config_page_dma);
4259 kfree(ioc->hpr_lookup);
4260 kfree(ioc->internal_lookup);
4261 if (ioc->chain_lookup) {
4262 for (i = 0; i < ioc->scsiio_depth; i++) {
4263 for (j = ioc->chains_per_prp_buffer;
4264 j < ioc->chains_needed_per_io; j++) {
4265 ct = &ioc->chain_lookup[i].chains_per_smid[j];
4266 if (ct && ct->chain_buffer)
4267 dma_pool_free(ioc->chain_dma_pool,
4269 ct->chain_buffer_dma);
4271 kfree(ioc->chain_lookup[i].chains_per_smid);
4273 dma_pool_destroy(ioc->chain_dma_pool);
4274 kfree(ioc->chain_lookup);
4275 ioc->chain_lookup = NULL;
4280 * is_MSB_are_same - checks whether all reply queues in a set are
4281 * having same upper 32bits in their base memory address.
4282 * @reply_pool_start_address: Base address of a reply queue set
4283 * @pool_sz: Size of single Reply Descriptor Post Queues pool size
4285 * Return: 1 if reply queues in a set have a same upper 32bits in their base
4286 * memory address, else 0.
4290 is_MSB_are_same(long reply_pool_start_address, u32 pool_sz)
4292 long reply_pool_end_address;
4294 reply_pool_end_address = reply_pool_start_address + pool_sz;
4296 if (upper_32_bits(reply_pool_start_address) ==
4297 upper_32_bits(reply_pool_end_address))
4304 * _base_allocate_memory_pools - allocate start of day memory pools
4305 * @ioc: per adapter object
4307 * Return: 0 success, anything else error.
4310 _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc)
4312 struct mpt3sas_facts *facts;
4313 u16 max_sge_elements;
4314 u16 chains_needed_per_io;
4315 u32 sz, total_sz, reply_post_free_sz, reply_post_free_array_sz;
4317 u16 max_request_credit, nvme_blocks_needed;
4318 unsigned short sg_tablesize;
4321 struct chain_tracker *ct;
4323 dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
4327 facts = &ioc->facts;
4329 /* command line tunables for max sgl entries */
4330 if (max_sgl_entries != -1)
4331 sg_tablesize = max_sgl_entries;
4333 if (ioc->hba_mpi_version_belonged == MPI2_VERSION)
4334 sg_tablesize = MPT2SAS_SG_DEPTH;
4336 sg_tablesize = MPT3SAS_SG_DEPTH;
4339 /* max sgl entries <= MPT_KDUMP_MIN_PHYS_SEGMENTS in KDUMP mode */
4341 sg_tablesize = min_t(unsigned short, sg_tablesize,
4342 MPT_KDUMP_MIN_PHYS_SEGMENTS);
4344 if (ioc->is_mcpu_endpoint)
4345 ioc->shost->sg_tablesize = MPT_MIN_PHYS_SEGMENTS;
4347 if (sg_tablesize < MPT_MIN_PHYS_SEGMENTS)
4348 sg_tablesize = MPT_MIN_PHYS_SEGMENTS;
4349 else if (sg_tablesize > MPT_MAX_PHYS_SEGMENTS) {
4350 sg_tablesize = min_t(unsigned short, sg_tablesize,
4352 ioc_warn(ioc, "sg_tablesize(%u) is bigger than kernel defined SG_CHUNK_SIZE(%u)\n",
4353 sg_tablesize, MPT_MAX_PHYS_SEGMENTS);
4355 ioc->shost->sg_tablesize = sg_tablesize;
4358 ioc->internal_depth = min_t(int, (facts->HighPriorityCredit + (5)),
4359 (facts->RequestCredit / 4));
4360 if (ioc->internal_depth < INTERNAL_CMDS_COUNT) {
4361 if (facts->RequestCredit <= (INTERNAL_CMDS_COUNT +
4362 INTERNAL_SCSIIO_CMDS_COUNT)) {
4363 ioc_err(ioc, "IOC doesn't have enough Request Credits, it has just %d number of credits\n",
4364 facts->RequestCredit);
4367 ioc->internal_depth = 10;
4370 ioc->hi_priority_depth = ioc->internal_depth - (5);
4371 /* command line tunables for max controller queue depth */
4372 if (max_queue_depth != -1 && max_queue_depth != 0) {
4373 max_request_credit = min_t(u16, max_queue_depth +
4374 ioc->internal_depth, facts->RequestCredit);
4375 if (max_request_credit > MAX_HBA_QUEUE_DEPTH)
4376 max_request_credit = MAX_HBA_QUEUE_DEPTH;
4377 } else if (reset_devices)
4378 max_request_credit = min_t(u16, facts->RequestCredit,
4379 (MPT3SAS_KDUMP_SCSI_IO_DEPTH + ioc->internal_depth));
4381 max_request_credit = min_t(u16, facts->RequestCredit,
4382 MAX_HBA_QUEUE_DEPTH);
4384 /* Firmware maintains additional facts->HighPriorityCredit number of
4385 * credits for HiPriprity Request messages, so hba queue depth will be
4386 * sum of max_request_credit and high priority queue depth.
4388 ioc->hba_queue_depth = max_request_credit + ioc->hi_priority_depth;
4390 /* request frame size */
4391 ioc->request_sz = facts->IOCRequestFrameSize * 4;
4393 /* reply frame size */
4394 ioc->reply_sz = facts->ReplyFrameSize * 4;
4396 /* chain segment size */
4397 if (ioc->hba_mpi_version_belonged != MPI2_VERSION) {
4398 if (facts->IOCMaxChainSegmentSize)
4399 ioc->chain_segment_sz =
4400 facts->IOCMaxChainSegmentSize *
4403 /* set to 128 bytes size if IOCMaxChainSegmentSize is zero */
4404 ioc->chain_segment_sz = DEFAULT_NUM_FWCHAIN_ELEMTS *
4407 ioc->chain_segment_sz = ioc->request_sz;
4409 /* calculate the max scatter element size */
4410 sge_size = max_t(u16, ioc->sge_size, ioc->sge_size_ieee);
4414 /* calculate number of sg elements left over in the 1st frame */
4415 max_sge_elements = ioc->request_sz - ((sizeof(Mpi2SCSIIORequest_t) -
4416 sizeof(Mpi2SGEIOUnion_t)) + sge_size);
4417 ioc->max_sges_in_main_message = max_sge_elements/sge_size;
4419 /* now do the same for a chain buffer */
4420 max_sge_elements = ioc->chain_segment_sz - sge_size;
4421 ioc->max_sges_in_chain_message = max_sge_elements/sge_size;
4424 * MPT3SAS_SG_DEPTH = CONFIG_FUSION_MAX_SGE
4426 chains_needed_per_io = ((ioc->shost->sg_tablesize -
4427 ioc->max_sges_in_main_message)/ioc->max_sges_in_chain_message)
4429 if (chains_needed_per_io > facts->MaxChainDepth) {
4430 chains_needed_per_io = facts->MaxChainDepth;
4431 ioc->shost->sg_tablesize = min_t(u16,
4432 ioc->max_sges_in_main_message + (ioc->max_sges_in_chain_message
4433 * chains_needed_per_io), ioc->shost->sg_tablesize);
4435 ioc->chains_needed_per_io = chains_needed_per_io;
4437 /* reply free queue sizing - taking into account for 64 FW events */
4438 ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64;
4440 /* mCPU manage single counters for simplicity */
4441 if (ioc->is_mcpu_endpoint)
4442 ioc->reply_post_queue_depth = ioc->reply_free_queue_depth;
4444 /* calculate reply descriptor post queue depth */
4445 ioc->reply_post_queue_depth = ioc->hba_queue_depth +
4446 ioc->reply_free_queue_depth + 1;
4447 /* align the reply post queue on the next 16 count boundary */
4448 if (ioc->reply_post_queue_depth % 16)
4449 ioc->reply_post_queue_depth += 16 -
4450 (ioc->reply_post_queue_depth % 16);
4453 if (ioc->reply_post_queue_depth >
4454 facts->MaxReplyDescriptorPostQueueDepth) {
4455 ioc->reply_post_queue_depth =
4456 facts->MaxReplyDescriptorPostQueueDepth -
4457 (facts->MaxReplyDescriptorPostQueueDepth % 16);
4458 ioc->hba_queue_depth =
4459 ((ioc->reply_post_queue_depth - 64) / 2) - 1;
4460 ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64;
4464 ioc_info(ioc, "scatter gather: sge_in_main_msg(%d), sge_per_chain(%d), sge_per_io(%d), chains_per_io(%d)\n",
4465 ioc->max_sges_in_main_message,
4466 ioc->max_sges_in_chain_message,
4467 ioc->shost->sg_tablesize,
4468 ioc->chains_needed_per_io));
4470 /* reply post queue, 16 byte align */
4471 reply_post_free_sz = ioc->reply_post_queue_depth *
4472 sizeof(Mpi2DefaultReplyDescriptor_t);
4474 sz = reply_post_free_sz;
4475 if (_base_is_controller_msix_enabled(ioc) && !ioc->rdpq_array_enable)
4476 sz *= ioc->reply_queue_count;
4478 ioc->reply_post = kcalloc((ioc->rdpq_array_enable) ?
4479 (ioc->reply_queue_count):1,
4480 sizeof(struct reply_post_struct), GFP_KERNEL);
4482 if (!ioc->reply_post) {
4483 ioc_err(ioc, "reply_post_free pool: kcalloc failed\n");
4486 ioc->reply_post_free_dma_pool = dma_pool_create("reply_post_free pool",
4487 &ioc->pdev->dev, sz, 16, 0);
4488 if (!ioc->reply_post_free_dma_pool) {
4489 ioc_err(ioc, "reply_post_free pool: dma_pool_create failed\n");
4494 ioc->reply_post[i].reply_post_free =
4495 dma_pool_zalloc(ioc->reply_post_free_dma_pool,
4497 &ioc->reply_post[i].reply_post_free_dma);
4498 if (!ioc->reply_post[i].reply_post_free) {
4499 ioc_err(ioc, "reply_post_free pool: dma_pool_alloc failed\n");
4503 ioc_info(ioc, "reply post free pool (0x%p): depth(%d), element_size(%d), pool_size(%d kB)\n",
4504 ioc->reply_post[i].reply_post_free,
4505 ioc->reply_post_queue_depth,
4508 ioc_info(ioc, "reply_post_free_dma = (0x%llx)\n",
4509 (u64)ioc->reply_post[i].reply_post_free_dma));
4511 } while (ioc->rdpq_array_enable && (++i < ioc->reply_queue_count));
4513 if (ioc->dma_mask == 64) {
4514 if (_base_change_consistent_dma_mask(ioc, ioc->pdev) != 0) {
4515 ioc_warn(ioc, "no suitable consistent DMA mask for %s\n",
4516 pci_name(ioc->pdev));
4521 ioc->scsiio_depth = ioc->hba_queue_depth -
4522 ioc->hi_priority_depth - ioc->internal_depth;
4524 /* set the scsi host can_queue depth
4525 * with some internal commands that could be outstanding
4527 ioc->shost->can_queue = ioc->scsiio_depth - INTERNAL_SCSIIO_CMDS_COUNT;
4529 ioc_info(ioc, "scsi host: can_queue depth (%d)\n",
4530 ioc->shost->can_queue));
4533 /* contiguous pool for request and chains, 16 byte align, one extra "
4536 ioc->chain_depth = ioc->chains_needed_per_io * ioc->scsiio_depth;
4537 sz = ((ioc->scsiio_depth + 1) * ioc->request_sz);
4539 /* hi-priority queue */
4540 sz += (ioc->hi_priority_depth * ioc->request_sz);
4542 /* internal queue */
4543 sz += (ioc->internal_depth * ioc->request_sz);
4545 ioc->request_dma_sz = sz;
4546 ioc->request = dma_alloc_coherent(&ioc->pdev->dev, sz,
4547 &ioc->request_dma, GFP_KERNEL);
4548 if (!ioc->request) {
4549 ioc_err(ioc, "request pool: dma_alloc_coherent failed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), total(%d kB)\n",
4550 ioc->hba_queue_depth, ioc->chains_needed_per_io,
4551 ioc->request_sz, sz / 1024);
4552 if (ioc->scsiio_depth < MPT3SAS_SAS_QUEUE_DEPTH)
4555 ioc->hba_queue_depth -= retry_sz;
4556 _base_release_memory_pools(ioc);
4557 goto retry_allocation;
4561 ioc_err(ioc, "request pool: dma_alloc_coherent succeed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), total(%d kb)\n",
4562 ioc->hba_queue_depth, ioc->chains_needed_per_io,
4563 ioc->request_sz, sz / 1024);
4565 /* hi-priority queue */
4566 ioc->hi_priority = ioc->request + ((ioc->scsiio_depth + 1) *
4568 ioc->hi_priority_dma = ioc->request_dma + ((ioc->scsiio_depth + 1) *
4571 /* internal queue */
4572 ioc->internal = ioc->hi_priority + (ioc->hi_priority_depth *
4574 ioc->internal_dma = ioc->hi_priority_dma + (ioc->hi_priority_depth *
4578 ioc_info(ioc, "request pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n",
4579 ioc->request, ioc->hba_queue_depth,
4581 (ioc->hba_queue_depth * ioc->request_sz) / 1024));
4584 ioc_info(ioc, "request pool: dma(0x%llx)\n",
4585 (unsigned long long)ioc->request_dma));
4589 ioc_info(ioc, "scsiio(0x%p): depth(%d)\n",
4590 ioc->request, ioc->scsiio_depth));
4592 ioc->chain_depth = min_t(u32, ioc->chain_depth, MAX_CHAIN_DEPTH);
4593 sz = ioc->scsiio_depth * sizeof(struct chain_lookup);
4594 ioc->chain_lookup = kzalloc(sz, GFP_KERNEL);
4595 if (!ioc->chain_lookup) {
4596 ioc_err(ioc, "chain_lookup: __get_free_pages failed\n");
4600 sz = ioc->chains_needed_per_io * sizeof(struct chain_tracker);
4601 for (i = 0; i < ioc->scsiio_depth; i++) {
4602 ioc->chain_lookup[i].chains_per_smid = kzalloc(sz, GFP_KERNEL);
4603 if (!ioc->chain_lookup[i].chains_per_smid) {
4604 ioc_err(ioc, "chain_lookup: kzalloc failed\n");
4609 /* initialize hi-priority queue smid's */
4610 ioc->hpr_lookup = kcalloc(ioc->hi_priority_depth,
4611 sizeof(struct request_tracker), GFP_KERNEL);
4612 if (!ioc->hpr_lookup) {
4613 ioc_err(ioc, "hpr_lookup: kcalloc failed\n");
4616 ioc->hi_priority_smid = ioc->scsiio_depth + 1;
4618 ioc_info(ioc, "hi_priority(0x%p): depth(%d), start smid(%d)\n",
4620 ioc->hi_priority_depth, ioc->hi_priority_smid));
4622 /* initialize internal queue smid's */
4623 ioc->internal_lookup = kcalloc(ioc->internal_depth,
4624 sizeof(struct request_tracker), GFP_KERNEL);
4625 if (!ioc->internal_lookup) {
4626 ioc_err(ioc, "internal_lookup: kcalloc failed\n");
4629 ioc->internal_smid = ioc->hi_priority_smid + ioc->hi_priority_depth;
4631 ioc_info(ioc, "internal(0x%p): depth(%d), start smid(%d)\n",
4633 ioc->internal_depth, ioc->internal_smid));
4635 * The number of NVMe page sized blocks needed is:
4636 * (((sg_tablesize * 8) - 1) / (page_size - 8)) + 1
4637 * ((sg_tablesize * 8) - 1) is the max PRP's minus the first PRP entry
4638 * that is placed in the main message frame. 8 is the size of each PRP
4639 * entry or PRP list pointer entry. 8 is subtracted from page_size
4640 * because of the PRP list pointer entry at the end of a page, so this
4641 * is not counted as a PRP entry. The 1 added page is a round up.
4643 * To avoid allocation failures due to the amount of memory that could
4644 * be required for NVMe PRP's, only each set of NVMe blocks will be
4645 * contiguous, so a new set is allocated for each possible I/O.
4647 ioc->chains_per_prp_buffer = 0;
4648 if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES) {
4649 nvme_blocks_needed =
4650 (ioc->shost->sg_tablesize * NVME_PRP_SIZE) - 1;
4651 nvme_blocks_needed /= (ioc->page_size - NVME_PRP_SIZE);
4652 nvme_blocks_needed++;
4654 sz = sizeof(struct pcie_sg_list) * ioc->scsiio_depth;
4655 ioc->pcie_sg_lookup = kzalloc(sz, GFP_KERNEL);
4656 if (!ioc->pcie_sg_lookup) {
4657 ioc_info(ioc, "PCIe SGL lookup: kzalloc failed\n");
4660 sz = nvme_blocks_needed * ioc->page_size;
4661 ioc->pcie_sgl_dma_pool =
4662 dma_pool_create("PCIe SGL pool", &ioc->pdev->dev, sz, 16, 0);
4663 if (!ioc->pcie_sgl_dma_pool) {
4664 ioc_info(ioc, "PCIe SGL pool: dma_pool_create failed\n");
4668 ioc->chains_per_prp_buffer = sz/ioc->chain_segment_sz;
4669 ioc->chains_per_prp_buffer = min(ioc->chains_per_prp_buffer,
4670 ioc->chains_needed_per_io);
4672 for (i = 0; i < ioc->scsiio_depth; i++) {
4673 ioc->pcie_sg_lookup[i].pcie_sgl = dma_pool_alloc(
4674 ioc->pcie_sgl_dma_pool, GFP_KERNEL,
4675 &ioc->pcie_sg_lookup[i].pcie_sgl_dma);
4676 if (!ioc->pcie_sg_lookup[i].pcie_sgl) {
4677 ioc_info(ioc, "PCIe SGL pool: dma_pool_alloc failed\n");
4680 for (j = 0; j < ioc->chains_per_prp_buffer; j++) {
4681 ct = &ioc->chain_lookup[i].chains_per_smid[j];
4683 ioc->pcie_sg_lookup[i].pcie_sgl +
4684 (j * ioc->chain_segment_sz);
4685 ct->chain_buffer_dma =
4686 ioc->pcie_sg_lookup[i].pcie_sgl_dma +
4687 (j * ioc->chain_segment_sz);
4692 ioc_info(ioc, "PCIe sgl pool depth(%d), element_size(%d), pool_size(%d kB)\n",
4693 ioc->scsiio_depth, sz,
4694 (sz * ioc->scsiio_depth) / 1024));
4696 ioc_info(ioc, "Number of chains can fit in a PRP page(%d)\n",
4697 ioc->chains_per_prp_buffer));
4698 total_sz += sz * ioc->scsiio_depth;
4701 ioc->chain_dma_pool = dma_pool_create("chain pool", &ioc->pdev->dev,
4702 ioc->chain_segment_sz, 16, 0);
4703 if (!ioc->chain_dma_pool) {
4704 ioc_err(ioc, "chain_dma_pool: dma_pool_create failed\n");
4707 for (i = 0; i < ioc->scsiio_depth; i++) {
4708 for (j = ioc->chains_per_prp_buffer;
4709 j < ioc->chains_needed_per_io; j++) {
4710 ct = &ioc->chain_lookup[i].chains_per_smid[j];
4711 ct->chain_buffer = dma_pool_alloc(
4712 ioc->chain_dma_pool, GFP_KERNEL,
4713 &ct->chain_buffer_dma);
4714 if (!ct->chain_buffer) {
4715 ioc_err(ioc, "chain_lookup: pci_pool_alloc failed\n");
4716 _base_release_memory_pools(ioc);
4720 total_sz += ioc->chain_segment_sz;
4724 ioc_info(ioc, "chain pool depth(%d), frame_size(%d), pool_size(%d kB)\n",
4725 ioc->chain_depth, ioc->chain_segment_sz,
4726 (ioc->chain_depth * ioc->chain_segment_sz) / 1024));
4728 /* sense buffers, 4 byte align */
4729 sz = ioc->scsiio_depth * SCSI_SENSE_BUFFERSIZE;
4730 ioc->sense_dma_pool = dma_pool_create("sense pool", &ioc->pdev->dev, sz,
4732 if (!ioc->sense_dma_pool) {
4733 ioc_err(ioc, "sense pool: dma_pool_create failed\n");
4736 ioc->sense = dma_pool_alloc(ioc->sense_dma_pool, GFP_KERNEL,
4739 ioc_err(ioc, "sense pool: dma_pool_alloc failed\n");
4742 /* sense buffer requires to be in same 4 gb region.
4743 * Below function will check the same.
4744 * In case of failure, new pci pool will be created with updated
4745 * alignment. Older allocation and pool will be destroyed.
4746 * Alignment will be used such a way that next allocation if
4747 * success, will always meet same 4gb region requirement.
4748 * Actual requirement is not alignment, but we need start and end of
4749 * DMA address must have same upper 32 bit address.
4751 if (!is_MSB_are_same((long)ioc->sense, sz)) {
4752 //Release Sense pool & Reallocate
4753 dma_pool_free(ioc->sense_dma_pool, ioc->sense, ioc->sense_dma);
4754 dma_pool_destroy(ioc->sense_dma_pool);
4757 ioc->sense_dma_pool =
4758 dma_pool_create("sense pool", &ioc->pdev->dev, sz,
4759 roundup_pow_of_two(sz), 0);
4760 if (!ioc->sense_dma_pool) {
4761 ioc_err(ioc, "sense pool: pci_pool_create failed\n");
4764 ioc->sense = dma_pool_alloc(ioc->sense_dma_pool, GFP_KERNEL,
4767 ioc_err(ioc, "sense pool: pci_pool_alloc failed\n");
4772 ioc_info(ioc, "sense pool(0x%p): depth(%d), element_size(%d), pool_size(%d kB)\n",
4773 ioc->sense, ioc->scsiio_depth,
4774 SCSI_SENSE_BUFFERSIZE, sz / 1024));
4776 ioc_info(ioc, "sense_dma(0x%llx)\n",
4777 (unsigned long long)ioc->sense_dma));
4780 /* reply pool, 4 byte align */
4781 sz = ioc->reply_free_queue_depth * ioc->reply_sz;
4782 ioc->reply_dma_pool = dma_pool_create("reply pool", &ioc->pdev->dev, sz,
4784 if (!ioc->reply_dma_pool) {
4785 ioc_err(ioc, "reply pool: dma_pool_create failed\n");
4788 ioc->reply = dma_pool_alloc(ioc->reply_dma_pool, GFP_KERNEL,
4791 ioc_err(ioc, "reply pool: dma_pool_alloc failed\n");
4794 ioc->reply_dma_min_address = (u32)(ioc->reply_dma);
4795 ioc->reply_dma_max_address = (u32)(ioc->reply_dma) + sz;
4797 ioc_info(ioc, "reply pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n",
4798 ioc->reply, ioc->reply_free_queue_depth,
4799 ioc->reply_sz, sz / 1024));
4801 ioc_info(ioc, "reply_dma(0x%llx)\n",
4802 (unsigned long long)ioc->reply_dma));
4805 /* reply free queue, 16 byte align */
4806 sz = ioc->reply_free_queue_depth * 4;
4807 ioc->reply_free_dma_pool = dma_pool_create("reply_free pool",
4808 &ioc->pdev->dev, sz, 16, 0);
4809 if (!ioc->reply_free_dma_pool) {
4810 ioc_err(ioc, "reply_free pool: dma_pool_create failed\n");
4813 ioc->reply_free = dma_pool_zalloc(ioc->reply_free_dma_pool, GFP_KERNEL,
4814 &ioc->reply_free_dma);
4815 if (!ioc->reply_free) {
4816 ioc_err(ioc, "reply_free pool: dma_pool_alloc failed\n");
4820 ioc_info(ioc, "reply_free pool(0x%p): depth(%d), element_size(%d), pool_size(%d kB)\n",
4821 ioc->reply_free, ioc->reply_free_queue_depth,
4824 ioc_info(ioc, "reply_free_dma (0x%llx)\n",
4825 (unsigned long long)ioc->reply_free_dma));
4828 if (ioc->rdpq_array_enable) {
4829 reply_post_free_array_sz = ioc->reply_queue_count *
4830 sizeof(Mpi2IOCInitRDPQArrayEntry);
4831 ioc->reply_post_free_array_dma_pool =
4832 dma_pool_create("reply_post_free_array pool",
4833 &ioc->pdev->dev, reply_post_free_array_sz, 16, 0);
4834 if (!ioc->reply_post_free_array_dma_pool) {
4836 ioc_info(ioc, "reply_post_free_array pool: dma_pool_create failed\n"));
4839 ioc->reply_post_free_array =
4840 dma_pool_alloc(ioc->reply_post_free_array_dma_pool,
4841 GFP_KERNEL, &ioc->reply_post_free_array_dma);
4842 if (!ioc->reply_post_free_array) {
4844 ioc_info(ioc, "reply_post_free_array pool: dma_pool_alloc failed\n"));
4848 ioc->config_page_sz = 512;
4849 ioc->config_page = dma_alloc_coherent(&ioc->pdev->dev,
4850 ioc->config_page_sz, &ioc->config_page_dma, GFP_KERNEL);
4851 if (!ioc->config_page) {
4852 ioc_err(ioc, "config page: dma_pool_alloc failed\n");
4856 ioc_info(ioc, "config page(0x%p): size(%d)\n",
4857 ioc->config_page, ioc->config_page_sz));
4859 ioc_info(ioc, "config_page_dma(0x%llx)\n",
4860 (unsigned long long)ioc->config_page_dma));
4861 total_sz += ioc->config_page_sz;
4863 ioc_info(ioc, "Allocated physical memory: size(%d kB)\n",
4865 ioc_info(ioc, "Current Controller Queue Depth(%d),Max Controller Queue Depth(%d)\n",
4866 ioc->shost->can_queue, facts->RequestCredit);
4867 ioc_info(ioc, "Scatter Gather Elements per IO(%d)\n",
4868 ioc->shost->sg_tablesize);
4876 * mpt3sas_base_get_iocstate - Get the current state of a MPT adapter.
4877 * @ioc: Pointer to MPT_ADAPTER structure
4878 * @cooked: Request raw or cooked IOC state
4880 * Return: all IOC Doorbell register bits if cooked==0, else just the
4881 * Doorbell bits in MPI_IOC_STATE_MASK.
4884 mpt3sas_base_get_iocstate(struct MPT3SAS_ADAPTER *ioc, int cooked)
4888 s = ioc->base_readl(&ioc->chip->Doorbell);
4889 sc = s & MPI2_IOC_STATE_MASK;
4890 return cooked ? sc : s;
4894 * _base_wait_on_iocstate - waiting on a particular ioc state
4896 * @ioc_state: controller state { READY, OPERATIONAL, or RESET }
4897 * @timeout: timeout in second
4899 * Return: 0 for success, non-zero for failure.
4902 _base_wait_on_iocstate(struct MPT3SAS_ADAPTER *ioc, u32 ioc_state, int timeout)
4908 cntdn = 1000 * timeout;
4910 current_state = mpt3sas_base_get_iocstate(ioc, 1);
4911 if (current_state == ioc_state)
4913 if (count && current_state == MPI2_IOC_STATE_FAULT)
4916 usleep_range(1000, 1500);
4920 return current_state;
4924 * _base_wait_for_doorbell_int - waiting for controller interrupt(generated by
4925 * a write to the doorbell)
4926 * @ioc: per adapter object
4928 * Return: 0 for success, non-zero for failure.
4930 * Notes: MPI2_HIS_IOC2SYS_DB_STATUS - set to one when IOC writes to doorbell.
4933 _base_diag_reset(struct MPT3SAS_ADAPTER *ioc);
4936 _base_wait_for_doorbell_int(struct MPT3SAS_ADAPTER *ioc, int timeout)
4942 cntdn = 1000 * timeout;
4944 int_status = ioc->base_readl(&ioc->chip->HostInterruptStatus);
4945 if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
4947 ioc_info(ioc, "%s: successful count(%d), timeout(%d)\n",
4948 __func__, count, timeout));
4952 usleep_range(1000, 1500);
4956 ioc_err(ioc, "%s: failed due to timeout count(%d), int_status(%x)!\n",
4957 __func__, count, int_status);
4962 _base_spin_on_doorbell_int(struct MPT3SAS_ADAPTER *ioc, int timeout)
4968 cntdn = 2000 * timeout;
4970 int_status = ioc->base_readl(&ioc->chip->HostInterruptStatus);
4971 if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
4973 ioc_info(ioc, "%s: successful count(%d), timeout(%d)\n",
4974 __func__, count, timeout));
4982 ioc_err(ioc, "%s: failed due to timeout count(%d), int_status(%x)!\n",
4983 __func__, count, int_status);
4989 * _base_wait_for_doorbell_ack - waiting for controller to read the doorbell.
4990 * @ioc: per adapter object
4991 * @timeout: timeout in second
4993 * Return: 0 for success, non-zero for failure.
4995 * Notes: MPI2_HIS_SYS2IOC_DB_STATUS - set to one when host writes to
4999 _base_wait_for_doorbell_ack(struct MPT3SAS_ADAPTER *ioc, int timeout)
5006 cntdn = 1000 * timeout;
5008 int_status = ioc->base_readl(&ioc->chip->HostInterruptStatus);
5009 if (!(int_status & MPI2_HIS_SYS2IOC_DB_STATUS)) {
5011 ioc_info(ioc, "%s: successful count(%d), timeout(%d)\n",
5012 __func__, count, timeout));
5014 } else if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
5015 doorbell = ioc->base_readl(&ioc->chip->Doorbell);
5016 if ((doorbell & MPI2_IOC_STATE_MASK) ==
5017 MPI2_IOC_STATE_FAULT) {
5018 mpt3sas_base_fault_info(ioc , doorbell);
5021 } else if (int_status == 0xFFFFFFFF)
5024 usleep_range(1000, 1500);
5029 ioc_err(ioc, "%s: failed due to timeout count(%d), int_status(%x)!\n",
5030 __func__, count, int_status);
5035 * _base_wait_for_doorbell_not_used - waiting for doorbell to not be in use
5036 * @ioc: per adapter object
5037 * @timeout: timeout in second
5039 * Return: 0 for success, non-zero for failure.
5042 _base_wait_for_doorbell_not_used(struct MPT3SAS_ADAPTER *ioc, int timeout)
5048 cntdn = 1000 * timeout;
5050 doorbell_reg = ioc->base_readl(&ioc->chip->Doorbell);
5051 if (!(doorbell_reg & MPI2_DOORBELL_USED)) {
5053 ioc_info(ioc, "%s: successful count(%d), timeout(%d)\n",
5054 __func__, count, timeout));
5058 usleep_range(1000, 1500);
5062 ioc_err(ioc, "%s: failed due to timeout count(%d), doorbell_reg(%x)!\n",
5063 __func__, count, doorbell_reg);
5068 * _base_send_ioc_reset - send doorbell reset
5069 * @ioc: per adapter object
5070 * @reset_type: currently only supports: MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET
5071 * @timeout: timeout in second
5073 * Return: 0 for success, non-zero for failure.
5076 _base_send_ioc_reset(struct MPT3SAS_ADAPTER *ioc, u8 reset_type, int timeout)
5081 if (reset_type != MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET) {
5082 ioc_err(ioc, "%s: unknown reset_type\n", __func__);
5086 if (!(ioc->facts.IOCCapabilities &
5087 MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY))
5090 ioc_info(ioc, "sending message unit reset !!\n");
5092 writel(reset_type << MPI2_DOORBELL_FUNCTION_SHIFT,
5093 &ioc->chip->Doorbell);
5094 if ((_base_wait_for_doorbell_ack(ioc, 15))) {
5098 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, timeout);
5100 ioc_err(ioc, "%s: failed going to ready state (ioc_state=0x%x)\n",
5101 __func__, ioc_state);
5106 ioc_info(ioc, "message unit reset: %s\n",
5107 r == 0 ? "SUCCESS" : "FAILED");
5112 * mpt3sas_wait_for_ioc - IOC's operational state is checked here.
5113 * @ioc: per adapter object
5114 * @wait_count: timeout in seconds
5116 * Return: Waits up to timeout seconds for the IOC to
5117 * become operational. Returns 0 if IOC is present
5118 * and operational; otherwise returns -EFAULT.
5122 mpt3sas_wait_for_ioc(struct MPT3SAS_ADAPTER *ioc, int timeout)
5124 int wait_state_count = 0;
5128 ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
5129 if (ioc_state == MPI2_IOC_STATE_OPERATIONAL)
5132 ioc_info(ioc, "%s: waiting for operational state(count=%d)\n",
5133 __func__, ++wait_state_count);
5134 } while (--timeout);
5136 ioc_err(ioc, "%s: failed due to ioc not operational\n", __func__);
5139 if (wait_state_count)
5140 ioc_info(ioc, "ioc is operational\n");
5145 * _base_handshake_req_reply_wait - send request thru doorbell interface
5146 * @ioc: per adapter object
5147 * @request_bytes: request length
5148 * @request: pointer having request payload
5149 * @reply_bytes: reply length
5150 * @reply: pointer to reply payload
5151 * @timeout: timeout in second
5153 * Return: 0 for success, non-zero for failure.
5156 _base_handshake_req_reply_wait(struct MPT3SAS_ADAPTER *ioc, int request_bytes,
5157 u32 *request, int reply_bytes, u16 *reply, int timeout)
5159 MPI2DefaultReply_t *default_reply = (MPI2DefaultReply_t *)reply;
5164 /* make sure doorbell is not in use */
5165 if ((ioc->base_readl(&ioc->chip->Doorbell) & MPI2_DOORBELL_USED)) {
5166 ioc_err(ioc, "doorbell is in use (line=%d)\n", __LINE__);
5170 /* clear pending doorbell interrupts from previous state changes */
5171 if (ioc->base_readl(&ioc->chip->HostInterruptStatus) &
5172 MPI2_HIS_IOC2SYS_DB_STATUS)
5173 writel(0, &ioc->chip->HostInterruptStatus);
5175 /* send message to ioc */
5176 writel(((MPI2_FUNCTION_HANDSHAKE<<MPI2_DOORBELL_FUNCTION_SHIFT) |
5177 ((request_bytes/4)<<MPI2_DOORBELL_ADD_DWORDS_SHIFT)),
5178 &ioc->chip->Doorbell);
5180 if ((_base_spin_on_doorbell_int(ioc, 5))) {
5181 ioc_err(ioc, "doorbell handshake int failed (line=%d)\n",
5185 writel(0, &ioc->chip->HostInterruptStatus);
5187 if ((_base_wait_for_doorbell_ack(ioc, 5))) {
5188 ioc_err(ioc, "doorbell handshake ack failed (line=%d)\n",
5193 /* send message 32-bits at a time */
5194 for (i = 0, failed = 0; i < request_bytes/4 && !failed; i++) {
5195 writel(cpu_to_le32(request[i]), &ioc->chip->Doorbell);
5196 if ((_base_wait_for_doorbell_ack(ioc, 5)))
5201 ioc_err(ioc, "doorbell handshake sending request failed (line=%d)\n",
5206 /* now wait for the reply */
5207 if ((_base_wait_for_doorbell_int(ioc, timeout))) {
5208 ioc_err(ioc, "doorbell handshake int failed (line=%d)\n",
5213 /* read the first two 16-bits, it gives the total length of the reply */
5214 reply[0] = le16_to_cpu(ioc->base_readl(&ioc->chip->Doorbell)
5215 & MPI2_DOORBELL_DATA_MASK);
5216 writel(0, &ioc->chip->HostInterruptStatus);
5217 if ((_base_wait_for_doorbell_int(ioc, 5))) {
5218 ioc_err(ioc, "doorbell handshake int failed (line=%d)\n",
5222 reply[1] = le16_to_cpu(ioc->base_readl(&ioc->chip->Doorbell)
5223 & MPI2_DOORBELL_DATA_MASK);
5224 writel(0, &ioc->chip->HostInterruptStatus);
5226 for (i = 2; i < default_reply->MsgLength * 2; i++) {
5227 if ((_base_wait_for_doorbell_int(ioc, 5))) {
5228 ioc_err(ioc, "doorbell handshake int failed (line=%d)\n",
5232 if (i >= reply_bytes/2) /* overflow case */
5233 ioc->base_readl(&ioc->chip->Doorbell);
5235 reply[i] = le16_to_cpu(
5236 ioc->base_readl(&ioc->chip->Doorbell)
5237 & MPI2_DOORBELL_DATA_MASK);
5238 writel(0, &ioc->chip->HostInterruptStatus);
5241 _base_wait_for_doorbell_int(ioc, 5);
5242 if (_base_wait_for_doorbell_not_used(ioc, 5) != 0) {
5244 ioc_info(ioc, "doorbell is in use (line=%d)\n",
5247 writel(0, &ioc->chip->HostInterruptStatus);
5249 if (ioc->logging_level & MPT_DEBUG_INIT) {
5250 mfp = (__le32 *)reply;
5251 pr_info("\toffset:data\n");
5252 for (i = 0; i < reply_bytes/4; i++)
5253 pr_info("\t[0x%02x]:%08x\n", i*4,
5254 le32_to_cpu(mfp[i]));
5260 * mpt3sas_base_sas_iounit_control - send sas iounit control to FW
5261 * @ioc: per adapter object
5262 * @mpi_reply: the reply payload from FW
5263 * @mpi_request: the request payload sent to FW
5265 * The SAS IO Unit Control Request message allows the host to perform low-level
5266 * operations, such as resets on the PHYs of the IO Unit, also allows the host
5267 * to obtain the IOC assigned device handles for a device if it has other
5268 * identifying information about the device, in addition allows the host to
5269 * remove IOC resources associated with the device.
5271 * Return: 0 for success, non-zero for failure.
5274 mpt3sas_base_sas_iounit_control(struct MPT3SAS_ADAPTER *ioc,
5275 Mpi2SasIoUnitControlReply_t *mpi_reply,
5276 Mpi2SasIoUnitControlRequest_t *mpi_request)
5283 dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
5285 mutex_lock(&ioc->base_cmds.mutex);
5287 if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) {
5288 ioc_err(ioc, "%s: base_cmd in use\n", __func__);
5293 rc = mpt3sas_wait_for_ioc(ioc, IOC_OPERATIONAL_WAIT_COUNT);
5297 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
5299 ioc_err(ioc, "%s: failed obtaining a smid\n", __func__);
5305 ioc->base_cmds.status = MPT3_CMD_PENDING;
5306 request = mpt3sas_base_get_msg_frame(ioc, smid);
5307 ioc->base_cmds.smid = smid;
5308 memcpy(request, mpi_request, sizeof(Mpi2SasIoUnitControlRequest_t));
5309 if (mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
5310 mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET)
5311 ioc->ioc_link_reset_in_progress = 1;
5312 init_completion(&ioc->base_cmds.done);
5313 mpt3sas_base_put_smid_default(ioc, smid);
5314 wait_for_completion_timeout(&ioc->base_cmds.done,
5315 msecs_to_jiffies(10000));
5316 if ((mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
5317 mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET) &&
5318 ioc->ioc_link_reset_in_progress)
5319 ioc->ioc_link_reset_in_progress = 0;
5320 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
5322 mpt3sas_base_check_cmd_timeout(ioc,
5323 ioc->base_cmds.status, mpi_request,
5324 sizeof(Mpi2SasIoUnitControlRequest_t)/4);
5325 goto issue_host_reset;
5327 if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID)
5328 memcpy(mpi_reply, ioc->base_cmds.reply,
5329 sizeof(Mpi2SasIoUnitControlReply_t));
5331 memset(mpi_reply, 0, sizeof(Mpi2SasIoUnitControlReply_t));
5332 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
5337 mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER);
5338 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
5341 mutex_unlock(&ioc->base_cmds.mutex);
5346 * mpt3sas_base_scsi_enclosure_processor - sending request to sep device
5347 * @ioc: per adapter object
5348 * @mpi_reply: the reply payload from FW
5349 * @mpi_request: the request payload sent to FW
5351 * The SCSI Enclosure Processor request message causes the IOC to
5352 * communicate with SES devices to control LED status signals.
5354 * Return: 0 for success, non-zero for failure.
5357 mpt3sas_base_scsi_enclosure_processor(struct MPT3SAS_ADAPTER *ioc,
5358 Mpi2SepReply_t *mpi_reply, Mpi2SepRequest_t *mpi_request)
5365 dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
5367 mutex_lock(&ioc->base_cmds.mutex);
5369 if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) {
5370 ioc_err(ioc, "%s: base_cmd in use\n", __func__);
5375 rc = mpt3sas_wait_for_ioc(ioc, IOC_OPERATIONAL_WAIT_COUNT);
5379 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
5381 ioc_err(ioc, "%s: failed obtaining a smid\n", __func__);
5387 ioc->base_cmds.status = MPT3_CMD_PENDING;
5388 request = mpt3sas_base_get_msg_frame(ioc, smid);
5389 ioc->base_cmds.smid = smid;
5390 memcpy(request, mpi_request, sizeof(Mpi2SepReply_t));
5391 init_completion(&ioc->base_cmds.done);
5392 mpt3sas_base_put_smid_default(ioc, smid);
5393 wait_for_completion_timeout(&ioc->base_cmds.done,
5394 msecs_to_jiffies(10000));
5395 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
5397 mpt3sas_base_check_cmd_timeout(ioc,
5398 ioc->base_cmds.status, mpi_request,
5399 sizeof(Mpi2SepRequest_t)/4);
5400 goto issue_host_reset;
5402 if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID)
5403 memcpy(mpi_reply, ioc->base_cmds.reply,
5404 sizeof(Mpi2SepReply_t));
5406 memset(mpi_reply, 0, sizeof(Mpi2SepReply_t));
5407 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
5412 mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER);
5413 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
5416 mutex_unlock(&ioc->base_cmds.mutex);
5421 * _base_get_port_facts - obtain port facts reply and save in ioc
5422 * @ioc: per adapter object
5425 * Return: 0 for success, non-zero for failure.
5428 _base_get_port_facts(struct MPT3SAS_ADAPTER *ioc, int port)
5430 Mpi2PortFactsRequest_t mpi_request;
5431 Mpi2PortFactsReply_t mpi_reply;
5432 struct mpt3sas_port_facts *pfacts;
5433 int mpi_reply_sz, mpi_request_sz, r;
5435 dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
5437 mpi_reply_sz = sizeof(Mpi2PortFactsReply_t);
5438 mpi_request_sz = sizeof(Mpi2PortFactsRequest_t);
5439 memset(&mpi_request, 0, mpi_request_sz);
5440 mpi_request.Function = MPI2_FUNCTION_PORT_FACTS;
5441 mpi_request.PortNumber = port;
5442 r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
5443 (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5);
5446 ioc_err(ioc, "%s: handshake failed (r=%d)\n", __func__, r);
5450 pfacts = &ioc->pfacts[port];
5451 memset(pfacts, 0, sizeof(struct mpt3sas_port_facts));
5452 pfacts->PortNumber = mpi_reply.PortNumber;
5453 pfacts->VP_ID = mpi_reply.VP_ID;
5454 pfacts->VF_ID = mpi_reply.VF_ID;
5455 pfacts->MaxPostedCmdBuffers =
5456 le16_to_cpu(mpi_reply.MaxPostedCmdBuffers);
5462 * _base_wait_for_iocstate - Wait until the card is in READY or OPERATIONAL
5463 * @ioc: per adapter object
5466 * Return: 0 for success, non-zero for failure.
5469 _base_wait_for_iocstate(struct MPT3SAS_ADAPTER *ioc, int timeout)
5474 dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
5476 if (ioc->pci_error_recovery) {
5478 ioc_info(ioc, "%s: host in pci error recovery\n",
5483 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
5485 ioc_info(ioc, "%s: ioc_state(0x%08x)\n",
5486 __func__, ioc_state));
5488 if (((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY) ||
5489 (ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL)
5492 if (ioc_state & MPI2_DOORBELL_USED) {
5493 dhsprintk(ioc, ioc_info(ioc, "unexpected doorbell active!\n"));
5494 goto issue_diag_reset;
5497 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
5498 mpt3sas_base_fault_info(ioc, ioc_state &
5499 MPI2_DOORBELL_DATA_MASK);
5500 goto issue_diag_reset;
5503 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, timeout);
5506 ioc_info(ioc, "%s: failed going to ready state (ioc_state=0x%x)\n",
5507 __func__, ioc_state));
5512 rc = _base_diag_reset(ioc);
5517 * _base_get_ioc_facts - obtain ioc facts reply and save in ioc
5518 * @ioc: per adapter object
5520 * Return: 0 for success, non-zero for failure.
5523 _base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc)
5525 Mpi2IOCFactsRequest_t mpi_request;
5526 Mpi2IOCFactsReply_t mpi_reply;
5527 struct mpt3sas_facts *facts;
5528 int mpi_reply_sz, mpi_request_sz, r;
5530 dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
5532 r = _base_wait_for_iocstate(ioc, 10);
5535 ioc_info(ioc, "%s: failed getting to correct state\n",
5539 mpi_reply_sz = sizeof(Mpi2IOCFactsReply_t);
5540 mpi_request_sz = sizeof(Mpi2IOCFactsRequest_t);
5541 memset(&mpi_request, 0, mpi_request_sz);
5542 mpi_request.Function = MPI2_FUNCTION_IOC_FACTS;
5543 r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
5544 (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5);
5547 ioc_err(ioc, "%s: handshake failed (r=%d)\n", __func__, r);
5551 facts = &ioc->facts;
5552 memset(facts, 0, sizeof(struct mpt3sas_facts));
5553 facts->MsgVersion = le16_to_cpu(mpi_reply.MsgVersion);
5554 facts->HeaderVersion = le16_to_cpu(mpi_reply.HeaderVersion);
5555 facts->VP_ID = mpi_reply.VP_ID;
5556 facts->VF_ID = mpi_reply.VF_ID;
5557 facts->IOCExceptions = le16_to_cpu(mpi_reply.IOCExceptions);
5558 facts->MaxChainDepth = mpi_reply.MaxChainDepth;
5559 facts->WhoInit = mpi_reply.WhoInit;
5560 facts->NumberOfPorts = mpi_reply.NumberOfPorts;
5561 facts->MaxMSIxVectors = mpi_reply.MaxMSIxVectors;
5562 if (ioc->msix_enable && (facts->MaxMSIxVectors <=
5563 MAX_COMBINED_MSIX_VECTORS(ioc->is_gen35_ioc)))
5564 ioc->combined_reply_queue = 0;
5565 facts->RequestCredit = le16_to_cpu(mpi_reply.RequestCredit);
5566 facts->MaxReplyDescriptorPostQueueDepth =
5567 le16_to_cpu(mpi_reply.MaxReplyDescriptorPostQueueDepth);
5568 facts->ProductID = le16_to_cpu(mpi_reply.ProductID);
5569 facts->IOCCapabilities = le32_to_cpu(mpi_reply.IOCCapabilities);
5570 if ((facts->IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID))
5571 ioc->ir_firmware = 1;
5572 if ((facts->IOCCapabilities &
5573 MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE) && (!reset_devices))
5574 ioc->rdpq_array_capable = 1;
5575 facts->FWVersion.Word = le32_to_cpu(mpi_reply.FWVersion.Word);
5576 facts->IOCRequestFrameSize =
5577 le16_to_cpu(mpi_reply.IOCRequestFrameSize);
5578 if (ioc->hba_mpi_version_belonged != MPI2_VERSION) {
5579 facts->IOCMaxChainSegmentSize =
5580 le16_to_cpu(mpi_reply.IOCMaxChainSegmentSize);
5582 facts->MaxInitiators = le16_to_cpu(mpi_reply.MaxInitiators);
5583 facts->MaxTargets = le16_to_cpu(mpi_reply.MaxTargets);
5584 ioc->shost->max_id = -1;
5585 facts->MaxSasExpanders = le16_to_cpu(mpi_reply.MaxSasExpanders);
5586 facts->MaxEnclosures = le16_to_cpu(mpi_reply.MaxEnclosures);
5587 facts->ProtocolFlags = le16_to_cpu(mpi_reply.ProtocolFlags);
5588 facts->HighPriorityCredit =
5589 le16_to_cpu(mpi_reply.HighPriorityCredit);
5590 facts->ReplyFrameSize = mpi_reply.ReplyFrameSize;
5591 facts->MaxDevHandle = le16_to_cpu(mpi_reply.MaxDevHandle);
5592 facts->CurrentHostPageSize = mpi_reply.CurrentHostPageSize;
5595 * Get the Page Size from IOC Facts. If it's 0, default to 4k.
5597 ioc->page_size = 1 << facts->CurrentHostPageSize;
5598 if (ioc->page_size == 1) {
5599 ioc_info(ioc, "CurrentHostPageSize is 0: Setting default host page size to 4k\n");
5600 ioc->page_size = 1 << MPT3SAS_HOST_PAGE_SIZE_4K;
5603 ioc_info(ioc, "CurrentHostPageSize(%d)\n",
5604 facts->CurrentHostPageSize));
5607 ioc_info(ioc, "hba queue depth(%d), max chains per io(%d)\n",
5608 facts->RequestCredit, facts->MaxChainDepth));
5610 ioc_info(ioc, "request frame size(%d), reply frame size(%d)\n",
5611 facts->IOCRequestFrameSize * 4,
5612 facts->ReplyFrameSize * 4));
5617 * _base_send_ioc_init - send ioc_init to firmware
5618 * @ioc: per adapter object
5620 * Return: 0 for success, non-zero for failure.
5623 _base_send_ioc_init(struct MPT3SAS_ADAPTER *ioc)
5625 Mpi2IOCInitRequest_t mpi_request;
5626 Mpi2IOCInitReply_t mpi_reply;
5628 ktime_t current_time;
5630 u32 reply_post_free_array_sz = 0;
5632 dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
5634 memset(&mpi_request, 0, sizeof(Mpi2IOCInitRequest_t));
5635 mpi_request.Function = MPI2_FUNCTION_IOC_INIT;
5636 mpi_request.WhoInit = MPI2_WHOINIT_HOST_DRIVER;
5637 mpi_request.VF_ID = 0; /* TODO */
5638 mpi_request.VP_ID = 0;
5639 mpi_request.MsgVersion = cpu_to_le16(ioc->hba_mpi_version_belonged);
5640 mpi_request.HeaderVersion = cpu_to_le16(MPI2_HEADER_VERSION);
5641 mpi_request.HostPageSize = MPT3SAS_HOST_PAGE_SIZE_4K;
5643 if (_base_is_controller_msix_enabled(ioc))
5644 mpi_request.HostMSIxVectors = ioc->reply_queue_count;
5645 mpi_request.SystemRequestFrameSize = cpu_to_le16(ioc->request_sz/4);
5646 mpi_request.ReplyDescriptorPostQueueDepth =
5647 cpu_to_le16(ioc->reply_post_queue_depth);
5648 mpi_request.ReplyFreeQueueDepth =
5649 cpu_to_le16(ioc->reply_free_queue_depth);
5651 mpi_request.SenseBufferAddressHigh =
5652 cpu_to_le32((u64)ioc->sense_dma >> 32);
5653 mpi_request.SystemReplyAddressHigh =
5654 cpu_to_le32((u64)ioc->reply_dma >> 32);
5655 mpi_request.SystemRequestFrameBaseAddress =
5656 cpu_to_le64((u64)ioc->request_dma);
5657 mpi_request.ReplyFreeQueueAddress =
5658 cpu_to_le64((u64)ioc->reply_free_dma);
5660 if (ioc->rdpq_array_enable) {
5661 reply_post_free_array_sz = ioc->reply_queue_count *
5662 sizeof(Mpi2IOCInitRDPQArrayEntry);
5663 memset(ioc->reply_post_free_array, 0, reply_post_free_array_sz);
5664 for (i = 0; i < ioc->reply_queue_count; i++)
5665 ioc->reply_post_free_array[i].RDPQBaseAddress =
5667 (u64)ioc->reply_post[i].reply_post_free_dma);
5668 mpi_request.MsgFlags = MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE;
5669 mpi_request.ReplyDescriptorPostQueueAddress =
5670 cpu_to_le64((u64)ioc->reply_post_free_array_dma);
5672 mpi_request.ReplyDescriptorPostQueueAddress =
5673 cpu_to_le64((u64)ioc->reply_post[0].reply_post_free_dma);
5676 /* This time stamp specifies number of milliseconds
5677 * since epoch ~ midnight January 1, 1970.
5679 current_time = ktime_get_real();
5680 mpi_request.TimeStamp = cpu_to_le64(ktime_to_ms(current_time));
5682 if (ioc->logging_level & MPT_DEBUG_INIT) {
5686 mfp = (__le32 *)&mpi_request;
5687 pr_info("\toffset:data\n");
5688 for (i = 0; i < sizeof(Mpi2IOCInitRequest_t)/4; i++)
5689 pr_info("\t[0x%02x]:%08x\n", i*4,
5690 le32_to_cpu(mfp[i]));
5693 r = _base_handshake_req_reply_wait(ioc,
5694 sizeof(Mpi2IOCInitRequest_t), (u32 *)&mpi_request,
5695 sizeof(Mpi2IOCInitReply_t), (u16 *)&mpi_reply, 10);
5698 ioc_err(ioc, "%s: handshake failed (r=%d)\n", __func__, r);
5702 ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & MPI2_IOCSTATUS_MASK;
5703 if (ioc_status != MPI2_IOCSTATUS_SUCCESS ||
5704 mpi_reply.IOCLogInfo) {
5705 ioc_err(ioc, "%s: failed\n", __func__);
5713 * mpt3sas_port_enable_done - command completion routine for port enable
5714 * @ioc: per adapter object
5715 * @smid: system request message index
5716 * @msix_index: MSIX table index supplied by the OS
5717 * @reply: reply message frame(lower 32bit addr)
5719 * Return: 1 meaning mf should be freed from _base_interrupt
5720 * 0 means the mf is freed from this function.
5723 mpt3sas_port_enable_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
5726 MPI2DefaultReply_t *mpi_reply;
5729 if (ioc->port_enable_cmds.status == MPT3_CMD_NOT_USED)
5732 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
5736 if (mpi_reply->Function != MPI2_FUNCTION_PORT_ENABLE)
5739 ioc->port_enable_cmds.status &= ~MPT3_CMD_PENDING;
5740 ioc->port_enable_cmds.status |= MPT3_CMD_COMPLETE;
5741 ioc->port_enable_cmds.status |= MPT3_CMD_REPLY_VALID;
5742 memcpy(ioc->port_enable_cmds.reply, mpi_reply, mpi_reply->MsgLength*4);
5743 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK;
5744 if (ioc_status != MPI2_IOCSTATUS_SUCCESS)
5745 ioc->port_enable_failed = 1;
5747 if (ioc->is_driver_loading) {
5748 if (ioc_status == MPI2_IOCSTATUS_SUCCESS) {
5749 mpt3sas_port_enable_complete(ioc);
5752 ioc->start_scan_failed = ioc_status;
5753 ioc->start_scan = 0;
5757 complete(&ioc->port_enable_cmds.done);
5762 * _base_send_port_enable - send port_enable(discovery stuff) to firmware
5763 * @ioc: per adapter object
5765 * Return: 0 for success, non-zero for failure.
5768 _base_send_port_enable(struct MPT3SAS_ADAPTER *ioc)
5770 Mpi2PortEnableRequest_t *mpi_request;
5771 Mpi2PortEnableReply_t *mpi_reply;
5776 ioc_info(ioc, "sending port enable !!\n");
5778 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
5779 ioc_err(ioc, "%s: internal command already in use\n", __func__);
5783 smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx);
5785 ioc_err(ioc, "%s: failed obtaining a smid\n", __func__);
5789 ioc->port_enable_cmds.status = MPT3_CMD_PENDING;
5790 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
5791 ioc->port_enable_cmds.smid = smid;
5792 memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
5793 mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
5795 init_completion(&ioc->port_enable_cmds.done);
5796 mpt3sas_base_put_smid_default(ioc, smid);
5797 wait_for_completion_timeout(&ioc->port_enable_cmds.done, 300*HZ);
5798 if (!(ioc->port_enable_cmds.status & MPT3_CMD_COMPLETE)) {
5799 ioc_err(ioc, "%s: timeout\n", __func__);
5800 _debug_dump_mf(mpi_request,
5801 sizeof(Mpi2PortEnableRequest_t)/4);
5802 if (ioc->port_enable_cmds.status & MPT3_CMD_RESET)
5809 mpi_reply = ioc->port_enable_cmds.reply;
5810 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK;
5811 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
5812 ioc_err(ioc, "%s: failed with (ioc_status=0x%08x)\n",
5813 __func__, ioc_status);
5819 ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED;
5820 ioc_info(ioc, "port enable: %s\n", r == 0 ? "SUCCESS" : "FAILED");
5825 * mpt3sas_port_enable - initiate firmware discovery (don't wait for reply)
5826 * @ioc: per adapter object
5828 * Return: 0 for success, non-zero for failure.
5831 mpt3sas_port_enable(struct MPT3SAS_ADAPTER *ioc)
5833 Mpi2PortEnableRequest_t *mpi_request;
5836 ioc_info(ioc, "sending port enable !!\n");
5838 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
5839 ioc_err(ioc, "%s: internal command already in use\n", __func__);
5843 smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx);
5845 ioc_err(ioc, "%s: failed obtaining a smid\n", __func__);
5849 ioc->port_enable_cmds.status = MPT3_CMD_PENDING;
5850 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
5851 ioc->port_enable_cmds.smid = smid;
5852 memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
5853 mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
5855 mpt3sas_base_put_smid_default(ioc, smid);
5860 * _base_determine_wait_on_discovery - desposition
5861 * @ioc: per adapter object
5863 * Decide whether to wait on discovery to complete. Used to either
5864 * locate boot device, or report volumes ahead of physical devices.
5866 * Return: 1 for wait, 0 for don't wait.
5869 _base_determine_wait_on_discovery(struct MPT3SAS_ADAPTER *ioc)
5871 /* We wait for discovery to complete if IR firmware is loaded.
5872 * The sas topology events arrive before PD events, so we need time to
5873 * turn on the bit in ioc->pd_handles to indicate PD
5874 * Also, it maybe required to report Volumes ahead of physical
5875 * devices when MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING is set.
5877 if (ioc->ir_firmware)
5880 /* if no Bios, then we don't need to wait */
5881 if (!ioc->bios_pg3.BiosVersion)
5884 /* Bios is present, then we drop down here.
5886 * If there any entries in the Bios Page 2, then we wait
5887 * for discovery to complete.
5890 /* Current Boot Device */
5891 if ((ioc->bios_pg2.CurrentBootDeviceForm &
5892 MPI2_BIOSPAGE2_FORM_MASK) ==
5893 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED &&
5894 /* Request Boot Device */
5895 (ioc->bios_pg2.ReqBootDeviceForm &
5896 MPI2_BIOSPAGE2_FORM_MASK) ==
5897 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED &&
5898 /* Alternate Request Boot Device */
5899 (ioc->bios_pg2.ReqAltBootDeviceForm &
5900 MPI2_BIOSPAGE2_FORM_MASK) ==
5901 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED)
5908 * _base_unmask_events - turn on notification for this event
5909 * @ioc: per adapter object
5910 * @event: firmware event
5912 * The mask is stored in ioc->event_masks.
5915 _base_unmask_events(struct MPT3SAS_ADAPTER *ioc, u16 event)
5922 desired_event = (1 << (event % 32));
5925 ioc->event_masks[0] &= ~desired_event;
5926 else if (event < 64)
5927 ioc->event_masks[1] &= ~desired_event;
5928 else if (event < 96)
5929 ioc->event_masks[2] &= ~desired_event;
5930 else if (event < 128)
5931 ioc->event_masks[3] &= ~desired_event;
5935 * _base_event_notification - send event notification
5936 * @ioc: per adapter object
5938 * Return: 0 for success, non-zero for failure.
5941 _base_event_notification(struct MPT3SAS_ADAPTER *ioc)
5943 Mpi2EventNotificationRequest_t *mpi_request;
5948 dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
5950 if (ioc->base_cmds.status & MPT3_CMD_PENDING) {
5951 ioc_err(ioc, "%s: internal command already in use\n", __func__);
5955 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
5957 ioc_err(ioc, "%s: failed obtaining a smid\n", __func__);
5960 ioc->base_cmds.status = MPT3_CMD_PENDING;
5961 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
5962 ioc->base_cmds.smid = smid;
5963 memset(mpi_request, 0, sizeof(Mpi2EventNotificationRequest_t));
5964 mpi_request->Function = MPI2_FUNCTION_EVENT_NOTIFICATION;
5965 mpi_request->VF_ID = 0; /* TODO */
5966 mpi_request->VP_ID = 0;
5967 for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
5968 mpi_request->EventMasks[i] =
5969 cpu_to_le32(ioc->event_masks[i]);
5970 init_completion(&ioc->base_cmds.done);
5971 mpt3sas_base_put_smid_default(ioc, smid);
5972 wait_for_completion_timeout(&ioc->base_cmds.done, 30*HZ);
5973 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
5974 ioc_err(ioc, "%s: timeout\n", __func__);
5975 _debug_dump_mf(mpi_request,
5976 sizeof(Mpi2EventNotificationRequest_t)/4);
5977 if (ioc->base_cmds.status & MPT3_CMD_RESET)
5982 dinitprintk(ioc, ioc_info(ioc, "%s: complete\n", __func__));
5983 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
5988 * mpt3sas_base_validate_event_type - validating event types
5989 * @ioc: per adapter object
5990 * @event_type: firmware event
5992 * This will turn on firmware event notification when application
5993 * ask for that event. We don't mask events that are already enabled.
5996 mpt3sas_base_validate_event_type(struct MPT3SAS_ADAPTER *ioc, u32 *event_type)
5999 u32 event_mask, desired_event;
6000 u8 send_update_to_fw;
6002 for (i = 0, send_update_to_fw = 0; i <
6003 MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) {
6004 event_mask = ~event_type[i];
6006 for (j = 0; j < 32; j++) {
6007 if (!(event_mask & desired_event) &&
6008 (ioc->event_masks[i] & desired_event)) {
6009 ioc->event_masks[i] &= ~desired_event;
6010 send_update_to_fw = 1;
6012 desired_event = (desired_event << 1);
6016 if (!send_update_to_fw)
6019 mutex_lock(&ioc->base_cmds.mutex);
6020 _base_event_notification(ioc);
6021 mutex_unlock(&ioc->base_cmds.mutex);
6025 * _base_diag_reset - the "big hammer" start of day reset
6026 * @ioc: per adapter object
6028 * Return: 0 for success, non-zero for failure.
6031 _base_diag_reset(struct MPT3SAS_ADAPTER *ioc)
6033 u32 host_diagnostic;
6038 ioc_info(ioc, "sending diag reset !!\n");
6040 drsprintk(ioc, ioc_info(ioc, "clear interrupts\n"));
6044 /* Write magic sequence to WriteSequence register
6045 * Loop until in diagnostic mode
6047 drsprintk(ioc, ioc_info(ioc, "write magic sequence\n"));
6048 writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
6049 writel(MPI2_WRSEQ_1ST_KEY_VALUE, &ioc->chip->WriteSequence);
6050 writel(MPI2_WRSEQ_2ND_KEY_VALUE, &ioc->chip->WriteSequence);
6051 writel(MPI2_WRSEQ_3RD_KEY_VALUE, &ioc->chip->WriteSequence);
6052 writel(MPI2_WRSEQ_4TH_KEY_VALUE, &ioc->chip->WriteSequence);
6053 writel(MPI2_WRSEQ_5TH_KEY_VALUE, &ioc->chip->WriteSequence);
6054 writel(MPI2_WRSEQ_6TH_KEY_VALUE, &ioc->chip->WriteSequence);
6062 host_diagnostic = ioc->base_readl(&ioc->chip->HostDiagnostic);
6064 ioc_info(ioc, "wrote magic sequence: count(%d), host_diagnostic(0x%08x)\n",
6065 count, host_diagnostic));
6067 } while ((host_diagnostic & MPI2_DIAG_DIAG_WRITE_ENABLE) == 0);
6069 hcb_size = ioc->base_readl(&ioc->chip->HCBSize);
6071 drsprintk(ioc, ioc_info(ioc, "diag reset: issued\n"));
6072 writel(host_diagnostic | MPI2_DIAG_RESET_ADAPTER,
6073 &ioc->chip->HostDiagnostic);
6075 /*This delay allows the chip PCIe hardware time to finish reset tasks*/
6076 msleep(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000);
6078 /* Approximately 300 second max wait */
6079 for (count = 0; count < (300000000 /
6080 MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC); count++) {
6082 host_diagnostic = ioc->base_readl(&ioc->chip->HostDiagnostic);
6084 if (host_diagnostic == 0xFFFFFFFF)
6086 if (!(host_diagnostic & MPI2_DIAG_RESET_ADAPTER))
6089 msleep(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC / 1000);
6092 if (host_diagnostic & MPI2_DIAG_HCB_MODE) {
6095 ioc_info(ioc, "restart the adapter assuming the HCB Address points to good F/W\n"));
6096 host_diagnostic &= ~MPI2_DIAG_BOOT_DEVICE_SELECT_MASK;
6097 host_diagnostic |= MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW;
6098 writel(host_diagnostic, &ioc->chip->HostDiagnostic);
6100 drsprintk(ioc, ioc_info(ioc, "re-enable the HCDW\n"));
6101 writel(hcb_size | MPI2_HCB_SIZE_HCB_ENABLE,
6102 &ioc->chip->HCBSize);
6105 drsprintk(ioc, ioc_info(ioc, "restart the adapter\n"));
6106 writel(host_diagnostic & ~MPI2_DIAG_HOLD_IOC_RESET,
6107 &ioc->chip->HostDiagnostic);
6110 ioc_info(ioc, "disable writes to the diagnostic register\n"));
6111 writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
6113 drsprintk(ioc, ioc_info(ioc, "Wait for FW to go to the READY state\n"));
6114 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, 20);
6116 ioc_err(ioc, "%s: failed going to ready state (ioc_state=0x%x)\n",
6117 __func__, ioc_state);
6121 ioc_info(ioc, "diag reset: SUCCESS\n");
6125 ioc_err(ioc, "diag reset: FAILED\n");
6130 * _base_make_ioc_ready - put controller in READY state
6131 * @ioc: per adapter object
6132 * @type: FORCE_BIG_HAMMER or SOFT_RESET
6134 * Return: 0 for success, non-zero for failure.
6137 _base_make_ioc_ready(struct MPT3SAS_ADAPTER *ioc, enum reset_type type)
6143 dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
6145 if (ioc->pci_error_recovery)
6148 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
6150 ioc_info(ioc, "%s: ioc_state(0x%08x)\n",
6151 __func__, ioc_state));
6153 /* if in RESET state, it should move to READY state shortly */
6155 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_RESET) {
6156 while ((ioc_state & MPI2_IOC_STATE_MASK) !=
6157 MPI2_IOC_STATE_READY) {
6158 if (count++ == 10) {
6159 ioc_err(ioc, "%s: failed going to ready state (ioc_state=0x%x)\n",
6160 __func__, ioc_state);
6164 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
6168 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY)
6171 if (ioc_state & MPI2_DOORBELL_USED) {
6172 dhsprintk(ioc, ioc_info(ioc, "unexpected doorbell active!\n"));
6173 goto issue_diag_reset;
6176 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
6177 mpt3sas_base_fault_info(ioc, ioc_state &
6178 MPI2_DOORBELL_DATA_MASK);
6179 goto issue_diag_reset;
6182 if (type == FORCE_BIG_HAMMER)
6183 goto issue_diag_reset;
6185 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL)
6186 if (!(_base_send_ioc_reset(ioc,
6187 MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET, 15))) {
6192 rc = _base_diag_reset(ioc);
6197 * _base_make_ioc_operational - put controller in OPERATIONAL state
6198 * @ioc: per adapter object
6200 * Return: 0 for success, non-zero for failure.
6203 _base_make_ioc_operational(struct MPT3SAS_ADAPTER *ioc)
6206 unsigned long flags;
6209 struct _tr_list *delayed_tr, *delayed_tr_next;
6210 struct _sc_list *delayed_sc, *delayed_sc_next;
6211 struct _event_ack_list *delayed_event_ack, *delayed_event_ack_next;
6213 struct adapter_reply_queue *reply_q;
6214 Mpi2ReplyDescriptorsUnion_t *reply_post_free_contig;
6216 dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
6218 /* clean the delayed target reset list */
6219 list_for_each_entry_safe(delayed_tr, delayed_tr_next,
6220 &ioc->delayed_tr_list, list) {
6221 list_del(&delayed_tr->list);
6226 list_for_each_entry_safe(delayed_tr, delayed_tr_next,
6227 &ioc->delayed_tr_volume_list, list) {
6228 list_del(&delayed_tr->list);
6232 list_for_each_entry_safe(delayed_sc, delayed_sc_next,
6233 &ioc->delayed_sc_list, list) {
6234 list_del(&delayed_sc->list);
6238 list_for_each_entry_safe(delayed_event_ack, delayed_event_ack_next,
6239 &ioc->delayed_event_ack_list, list) {
6240 list_del(&delayed_event_ack->list);
6241 kfree(delayed_event_ack);
6244 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
6246 /* hi-priority queue */
6247 INIT_LIST_HEAD(&ioc->hpr_free_list);
6248 smid = ioc->hi_priority_smid;
6249 for (i = 0; i < ioc->hi_priority_depth; i++, smid++) {
6250 ioc->hpr_lookup[i].cb_idx = 0xFF;
6251 ioc->hpr_lookup[i].smid = smid;
6252 list_add_tail(&ioc->hpr_lookup[i].tracker_list,
6253 &ioc->hpr_free_list);
6256 /* internal queue */
6257 INIT_LIST_HEAD(&ioc->internal_free_list);
6258 smid = ioc->internal_smid;
6259 for (i = 0; i < ioc->internal_depth; i++, smid++) {
6260 ioc->internal_lookup[i].cb_idx = 0xFF;
6261 ioc->internal_lookup[i].smid = smid;
6262 list_add_tail(&ioc->internal_lookup[i].tracker_list,
6263 &ioc->internal_free_list);
6266 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
6268 /* initialize Reply Free Queue */
6269 for (i = 0, reply_address = (u32)ioc->reply_dma ;
6270 i < ioc->reply_free_queue_depth ; i++, reply_address +=
6272 ioc->reply_free[i] = cpu_to_le32(reply_address);
6273 if (ioc->is_mcpu_endpoint)
6274 _base_clone_reply_to_sys_mem(ioc,
6278 /* initialize reply queues */
6279 if (ioc->is_driver_loading)
6280 _base_assign_reply_queues(ioc);
6282 /* initialize Reply Post Free Queue */
6284 reply_post_free_contig = ioc->reply_post[0].reply_post_free;
6285 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
6287 * If RDPQ is enabled, switch to the next allocation.
6288 * Otherwise advance within the contiguous region.
6290 if (ioc->rdpq_array_enable) {
6291 reply_q->reply_post_free =
6292 ioc->reply_post[index++].reply_post_free;
6294 reply_q->reply_post_free = reply_post_free_contig;
6295 reply_post_free_contig += ioc->reply_post_queue_depth;
6298 reply_q->reply_post_host_index = 0;
6299 for (i = 0; i < ioc->reply_post_queue_depth; i++)
6300 reply_q->reply_post_free[i].Words =
6301 cpu_to_le64(ULLONG_MAX);
6302 if (!_base_is_controller_msix_enabled(ioc))
6303 goto skip_init_reply_post_free_queue;
6305 skip_init_reply_post_free_queue:
6307 r = _base_send_ioc_init(ioc);
6311 /* initialize reply free host index */
6312 ioc->reply_free_host_index = ioc->reply_free_queue_depth - 1;
6313 writel(ioc->reply_free_host_index, &ioc->chip->ReplyFreeHostIndex);
6315 /* initialize reply post host index */
6316 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
6317 if (ioc->combined_reply_queue)
6318 writel((reply_q->msix_index & 7)<<
6319 MPI2_RPHI_MSIX_INDEX_SHIFT,
6320 ioc->replyPostRegisterIndex[reply_q->msix_index/8]);
6322 writel(reply_q->msix_index <<
6323 MPI2_RPHI_MSIX_INDEX_SHIFT,
6324 &ioc->chip->ReplyPostHostIndex);
6326 if (!_base_is_controller_msix_enabled(ioc))
6327 goto skip_init_reply_post_host_index;
6330 skip_init_reply_post_host_index:
6332 _base_unmask_interrupts(ioc);
6334 if (ioc->hba_mpi_version_belonged != MPI2_VERSION) {
6335 r = _base_display_fwpkg_version(ioc);
6340 _base_static_config_pages(ioc);
6341 r = _base_event_notification(ioc);
6345 if (ioc->is_driver_loading) {
6347 if (ioc->is_warpdrive && ioc->manu_pg10.OEMIdentifier
6350 le32_to_cpu(ioc->manu_pg10.OEMSpecificFlags0) &
6351 MFG_PAGE10_HIDE_SSDS_MASK);
6352 if (hide_flag != MFG_PAGE10_HIDE_SSDS_MASK)
6353 ioc->mfg_pg10_hide_flag = hide_flag;
6356 ioc->wait_for_discovery_to_complete =
6357 _base_determine_wait_on_discovery(ioc);
6359 return r; /* scan_start and scan_finished support */
6362 r = _base_send_port_enable(ioc);
6370 * mpt3sas_base_free_resources - free resources controller resources
6371 * @ioc: per adapter object
6374 mpt3sas_base_free_resources(struct MPT3SAS_ADAPTER *ioc)
6376 dexitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
6378 /* synchronizing freeing resource with pci_access_mutex lock */
6379 mutex_lock(&ioc->pci_access_mutex);
6380 if (ioc->chip_phys && ioc->chip) {
6381 _base_mask_interrupts(ioc);
6382 ioc->shost_recovery = 1;
6383 _base_make_ioc_ready(ioc, SOFT_RESET);
6384 ioc->shost_recovery = 0;
6387 mpt3sas_base_unmap_resources(ioc);
6388 mutex_unlock(&ioc->pci_access_mutex);
6393 * mpt3sas_base_attach - attach controller instance
6394 * @ioc: per adapter object
6396 * Return: 0 for success, non-zero for failure.
6399 mpt3sas_base_attach(struct MPT3SAS_ADAPTER *ioc)
6402 int cpu_id, last_cpu_id = 0;
6404 dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
6406 /* setup cpu_msix_table */
6407 ioc->cpu_count = num_online_cpus();
6408 for_each_online_cpu(cpu_id)
6409 last_cpu_id = cpu_id;
6410 ioc->cpu_msix_table_sz = last_cpu_id + 1;
6411 ioc->cpu_msix_table = kzalloc(ioc->cpu_msix_table_sz, GFP_KERNEL);
6412 ioc->reply_queue_count = 1;
6413 if (!ioc->cpu_msix_table) {
6415 ioc_info(ioc, "allocation for cpu_msix_table failed!!!\n"));
6417 goto out_free_resources;
6420 if (ioc->is_warpdrive) {
6421 ioc->reply_post_host_index = kcalloc(ioc->cpu_msix_table_sz,
6422 sizeof(resource_size_t *), GFP_KERNEL);
6423 if (!ioc->reply_post_host_index) {
6425 ioc_info(ioc, "allocation for reply_post_host_index failed!!!\n"));
6427 goto out_free_resources;
6431 ioc->rdpq_array_enable_assigned = 0;
6433 if (ioc->is_aero_ioc)
6434 ioc->base_readl = &_base_readl_aero;
6436 ioc->base_readl = &_base_readl;
6437 r = mpt3sas_base_map_resources(ioc);
6439 goto out_free_resources;
6441 pci_set_drvdata(ioc->pdev, ioc->shost);
6442 r = _base_get_ioc_facts(ioc);
6444 goto out_free_resources;
6446 switch (ioc->hba_mpi_version_belonged) {
6448 ioc->build_sg_scmd = &_base_build_sg_scmd;
6449 ioc->build_sg = &_base_build_sg;
6450 ioc->build_zero_len_sge = &_base_build_zero_len_sge;
6456 * SCSI_IO, SMP_PASSTHRU, SATA_PASSTHRU, Target Assist, and
6457 * Target Status - all require the IEEE formated scatter gather
6460 ioc->build_sg_scmd = &_base_build_sg_scmd_ieee;
6461 ioc->build_sg = &_base_build_sg_ieee;
6462 ioc->build_nvme_prp = &_base_build_nvme_prp;
6463 ioc->build_zero_len_sge = &_base_build_zero_len_sge_ieee;
6464 ioc->sge_size_ieee = sizeof(Mpi2IeeeSgeSimple64_t);
6469 if (ioc->is_mcpu_endpoint)
6470 ioc->put_smid_scsi_io = &_base_put_smid_mpi_ep_scsi_io;
6472 ioc->put_smid_scsi_io = &_base_put_smid_scsi_io;
6475 * These function pointers for other requests that don't
6476 * the require IEEE scatter gather elements.
6478 * For example Configuration Pages and SAS IOUNIT Control don't.
6480 ioc->build_sg_mpi = &_base_build_sg;
6481 ioc->build_zero_len_sge_mpi = &_base_build_zero_len_sge;
6483 r = _base_make_ioc_ready(ioc, SOFT_RESET);
6485 goto out_free_resources;
6487 ioc->pfacts = kcalloc(ioc->facts.NumberOfPorts,
6488 sizeof(struct mpt3sas_port_facts), GFP_KERNEL);
6491 goto out_free_resources;
6494 for (i = 0 ; i < ioc->facts.NumberOfPorts; i++) {
6495 r = _base_get_port_facts(ioc, i);
6497 goto out_free_resources;
6500 r = _base_allocate_memory_pools(ioc);
6502 goto out_free_resources;
6504 init_waitqueue_head(&ioc->reset_wq);
6506 /* allocate memory pd handle bitmask list */
6507 ioc->pd_handles_sz = (ioc->facts.MaxDevHandle / 8);
6508 if (ioc->facts.MaxDevHandle % 8)
6509 ioc->pd_handles_sz++;
6510 ioc->pd_handles = kzalloc(ioc->pd_handles_sz,
6512 if (!ioc->pd_handles) {
6514 goto out_free_resources;
6516 ioc->blocking_handles = kzalloc(ioc->pd_handles_sz,
6518 if (!ioc->blocking_handles) {
6520 goto out_free_resources;
6523 /* allocate memory for pending OS device add list */
6524 ioc->pend_os_device_add_sz = (ioc->facts.MaxDevHandle / 8);
6525 if (ioc->facts.MaxDevHandle % 8)
6526 ioc->pend_os_device_add_sz++;
6527 ioc->pend_os_device_add = kzalloc(ioc->pend_os_device_add_sz,
6529 if (!ioc->pend_os_device_add)
6530 goto out_free_resources;
6532 ioc->device_remove_in_progress_sz = ioc->pend_os_device_add_sz;
6533 ioc->device_remove_in_progress =
6534 kzalloc(ioc->device_remove_in_progress_sz, GFP_KERNEL);
6535 if (!ioc->device_remove_in_progress)
6536 goto out_free_resources;
6538 ioc->fwfault_debug = mpt3sas_fwfault_debug;
6540 /* base internal command bits */
6541 mutex_init(&ioc->base_cmds.mutex);
6542 ioc->base_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
6543 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
6545 /* port_enable command bits */
6546 ioc->port_enable_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
6547 ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED;
6549 /* transport internal command bits */
6550 ioc->transport_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
6551 ioc->transport_cmds.status = MPT3_CMD_NOT_USED;
6552 mutex_init(&ioc->transport_cmds.mutex);
6554 /* scsih internal command bits */
6555 ioc->scsih_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
6556 ioc->scsih_cmds.status = MPT3_CMD_NOT_USED;
6557 mutex_init(&ioc->scsih_cmds.mutex);
6559 /* task management internal command bits */
6560 ioc->tm_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
6561 ioc->tm_cmds.status = MPT3_CMD_NOT_USED;
6562 mutex_init(&ioc->tm_cmds.mutex);
6564 /* config page internal command bits */
6565 ioc->config_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
6566 ioc->config_cmds.status = MPT3_CMD_NOT_USED;
6567 mutex_init(&ioc->config_cmds.mutex);
6569 /* ctl module internal command bits */
6570 ioc->ctl_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
6571 ioc->ctl_cmds.sense = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL);
6572 ioc->ctl_cmds.status = MPT3_CMD_NOT_USED;
6573 mutex_init(&ioc->ctl_cmds.mutex);
6575 if (!ioc->base_cmds.reply || !ioc->port_enable_cmds.reply ||
6576 !ioc->transport_cmds.reply || !ioc->scsih_cmds.reply ||
6577 !ioc->tm_cmds.reply || !ioc->config_cmds.reply ||
6578 !ioc->ctl_cmds.reply || !ioc->ctl_cmds.sense) {
6580 goto out_free_resources;
6583 for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
6584 ioc->event_masks[i] = -1;
6586 /* here we enable the events we care about */
6587 _base_unmask_events(ioc, MPI2_EVENT_SAS_DISCOVERY);
6588 _base_unmask_events(ioc, MPI2_EVENT_SAS_BROADCAST_PRIMITIVE);
6589 _base_unmask_events(ioc, MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST);
6590 _base_unmask_events(ioc, MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE);
6591 _base_unmask_events(ioc, MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE);
6592 _base_unmask_events(ioc, MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST);
6593 _base_unmask_events(ioc, MPI2_EVENT_IR_VOLUME);
6594 _base_unmask_events(ioc, MPI2_EVENT_IR_PHYSICAL_DISK);
6595 _base_unmask_events(ioc, MPI2_EVENT_IR_OPERATION_STATUS);
6596 _base_unmask_events(ioc, MPI2_EVENT_LOG_ENTRY_ADDED);
6597 _base_unmask_events(ioc, MPI2_EVENT_TEMP_THRESHOLD);
6598 _base_unmask_events(ioc, MPI2_EVENT_ACTIVE_CABLE_EXCEPTION);
6599 _base_unmask_events(ioc, MPI2_EVENT_SAS_DEVICE_DISCOVERY_ERROR);
6600 if (ioc->hba_mpi_version_belonged == MPI26_VERSION) {
6601 if (ioc->is_gen35_ioc) {
6602 _base_unmask_events(ioc,
6603 MPI2_EVENT_PCIE_DEVICE_STATUS_CHANGE);
6604 _base_unmask_events(ioc, MPI2_EVENT_PCIE_ENUMERATION);
6605 _base_unmask_events(ioc,
6606 MPI2_EVENT_PCIE_TOPOLOGY_CHANGE_LIST);
6609 r = _base_make_ioc_operational(ioc);
6611 goto out_free_resources;
6613 ioc->non_operational_loop = 0;
6614 ioc->got_task_abort_from_ioctl = 0;
6619 ioc->remove_host = 1;
6621 mpt3sas_base_free_resources(ioc);
6622 _base_release_memory_pools(ioc);
6623 pci_set_drvdata(ioc->pdev, NULL);
6624 kfree(ioc->cpu_msix_table);
6625 if (ioc->is_warpdrive)
6626 kfree(ioc->reply_post_host_index);
6627 kfree(ioc->pd_handles);
6628 kfree(ioc->blocking_handles);
6629 kfree(ioc->device_remove_in_progress);
6630 kfree(ioc->pend_os_device_add);
6631 kfree(ioc->tm_cmds.reply);
6632 kfree(ioc->transport_cmds.reply);
6633 kfree(ioc->scsih_cmds.reply);
6634 kfree(ioc->config_cmds.reply);
6635 kfree(ioc->base_cmds.reply);
6636 kfree(ioc->port_enable_cmds.reply);
6637 kfree(ioc->ctl_cmds.reply);
6638 kfree(ioc->ctl_cmds.sense);
6640 ioc->ctl_cmds.reply = NULL;
6641 ioc->base_cmds.reply = NULL;
6642 ioc->tm_cmds.reply = NULL;
6643 ioc->scsih_cmds.reply = NULL;
6644 ioc->transport_cmds.reply = NULL;
6645 ioc->config_cmds.reply = NULL;
6652 * mpt3sas_base_detach - remove controller instance
6653 * @ioc: per adapter object
6656 mpt3sas_base_detach(struct MPT3SAS_ADAPTER *ioc)
6658 dexitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
6660 mpt3sas_base_stop_watchdog(ioc);
6661 mpt3sas_base_free_resources(ioc);
6662 _base_release_memory_pools(ioc);
6663 mpt3sas_free_enclosure_list(ioc);
6664 pci_set_drvdata(ioc->pdev, NULL);
6665 kfree(ioc->cpu_msix_table);
6666 if (ioc->is_warpdrive)
6667 kfree(ioc->reply_post_host_index);
6668 kfree(ioc->pd_handles);
6669 kfree(ioc->blocking_handles);
6670 kfree(ioc->device_remove_in_progress);
6671 kfree(ioc->pend_os_device_add);
6673 kfree(ioc->ctl_cmds.reply);
6674 kfree(ioc->ctl_cmds.sense);
6675 kfree(ioc->base_cmds.reply);
6676 kfree(ioc->port_enable_cmds.reply);
6677 kfree(ioc->tm_cmds.reply);
6678 kfree(ioc->transport_cmds.reply);
6679 kfree(ioc->scsih_cmds.reply);
6680 kfree(ioc->config_cmds.reply);
6684 * _base_pre_reset_handler - pre reset handler
6685 * @ioc: per adapter object
6687 static void _base_pre_reset_handler(struct MPT3SAS_ADAPTER *ioc)
6689 mpt3sas_scsih_pre_reset_handler(ioc);
6690 mpt3sas_ctl_pre_reset_handler(ioc);
6691 dtmprintk(ioc, ioc_info(ioc, "%s: MPT3_IOC_PRE_RESET\n", __func__));
6695 * _base_after_reset_handler - after reset handler
6696 * @ioc: per adapter object
6698 static void _base_after_reset_handler(struct MPT3SAS_ADAPTER *ioc)
6700 mpt3sas_scsih_after_reset_handler(ioc);
6701 mpt3sas_ctl_after_reset_handler(ioc);
6702 dtmprintk(ioc, ioc_info(ioc, "%s: MPT3_IOC_AFTER_RESET\n", __func__));
6703 if (ioc->transport_cmds.status & MPT3_CMD_PENDING) {
6704 ioc->transport_cmds.status |= MPT3_CMD_RESET;
6705 mpt3sas_base_free_smid(ioc, ioc->transport_cmds.smid);
6706 complete(&ioc->transport_cmds.done);
6708 if (ioc->base_cmds.status & MPT3_CMD_PENDING) {
6709 ioc->base_cmds.status |= MPT3_CMD_RESET;
6710 mpt3sas_base_free_smid(ioc, ioc->base_cmds.smid);
6711 complete(&ioc->base_cmds.done);
6713 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
6714 ioc->port_enable_failed = 1;
6715 ioc->port_enable_cmds.status |= MPT3_CMD_RESET;
6716 mpt3sas_base_free_smid(ioc, ioc->port_enable_cmds.smid);
6717 if (ioc->is_driver_loading) {
6718 ioc->start_scan_failed =
6719 MPI2_IOCSTATUS_INTERNAL_ERROR;
6720 ioc->start_scan = 0;
6721 ioc->port_enable_cmds.status =
6724 complete(&ioc->port_enable_cmds.done);
6727 if (ioc->config_cmds.status & MPT3_CMD_PENDING) {
6728 ioc->config_cmds.status |= MPT3_CMD_RESET;
6729 mpt3sas_base_free_smid(ioc, ioc->config_cmds.smid);
6730 ioc->config_cmds.smid = USHRT_MAX;
6731 complete(&ioc->config_cmds.done);
6736 * _base_reset_done_handler - reset done handler
6737 * @ioc: per adapter object
6739 static void _base_reset_done_handler(struct MPT3SAS_ADAPTER *ioc)
6741 mpt3sas_scsih_reset_done_handler(ioc);
6742 mpt3sas_ctl_reset_done_handler(ioc);
6743 dtmprintk(ioc, ioc_info(ioc, "%s: MPT3_IOC_DONE_RESET\n", __func__));
6747 * mpt3sas_wait_for_commands_to_complete - reset controller
6748 * @ioc: Pointer to MPT_ADAPTER structure
6750 * This function is waiting 10s for all pending commands to complete
6751 * prior to putting controller in reset.
6754 mpt3sas_wait_for_commands_to_complete(struct MPT3SAS_ADAPTER *ioc)
6758 ioc->pending_io_count = 0;
6760 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
6761 if ((ioc_state & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL)
6764 /* pending command count */
6765 ioc->pending_io_count = scsi_host_busy(ioc->shost);
6767 if (!ioc->pending_io_count)
6770 /* wait for pending commands to complete */
6771 wait_event_timeout(ioc->reset_wq, ioc->pending_io_count == 0, 10 * HZ);
6775 * mpt3sas_base_hard_reset_handler - reset controller
6776 * @ioc: Pointer to MPT_ADAPTER structure
6777 * @type: FORCE_BIG_HAMMER or SOFT_RESET
6779 * Return: 0 for success, non-zero for failure.
6782 mpt3sas_base_hard_reset_handler(struct MPT3SAS_ADAPTER *ioc,
6783 enum reset_type type)
6786 unsigned long flags;
6788 u8 is_fault = 0, is_trigger = 0;
6790 dtmprintk(ioc, ioc_info(ioc, "%s: enter\n", __func__));
6792 if (ioc->pci_error_recovery) {
6793 ioc_err(ioc, "%s: pci error recovery reset\n", __func__);
6798 if (mpt3sas_fwfault_debug)
6799 mpt3sas_halt_firmware(ioc);
6801 /* wait for an active reset in progress to complete */
6802 mutex_lock(&ioc->reset_in_progress_mutex);
6804 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
6805 ioc->shost_recovery = 1;
6806 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
6808 if ((ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] &
6809 MPT3_DIAG_BUFFER_IS_REGISTERED) &&
6810 (!(ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] &
6811 MPT3_DIAG_BUFFER_IS_RELEASED))) {
6813 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
6814 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
6817 _base_pre_reset_handler(ioc);
6818 mpt3sas_wait_for_commands_to_complete(ioc);
6819 _base_mask_interrupts(ioc);
6820 r = _base_make_ioc_ready(ioc, type);
6823 _base_after_reset_handler(ioc);
6825 /* If this hard reset is called while port enable is active, then
6826 * there is no reason to call make_ioc_operational
6828 if (ioc->is_driver_loading && ioc->port_enable_failed) {
6829 ioc->remove_host = 1;
6833 r = _base_get_ioc_facts(ioc);
6837 if (ioc->rdpq_array_enable && !ioc->rdpq_array_capable)
6838 panic("%s: Issue occurred with flashing controller firmware."
6839 "Please reboot the system and ensure that the correct"
6840 " firmware version is running\n", ioc->name);
6842 r = _base_make_ioc_operational(ioc);
6844 _base_reset_done_handler(ioc);
6848 ioc_info(ioc, "%s: %s\n",
6849 __func__, r == 0 ? "SUCCESS" : "FAILED"));
6851 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
6852 ioc->shost_recovery = 0;
6853 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
6854 ioc->ioc_reset_count++;
6855 mutex_unlock(&ioc->reset_in_progress_mutex);
6858 if ((r == 0) && is_trigger) {
6860 mpt3sas_trigger_master(ioc, MASTER_TRIGGER_FW_FAULT);
6862 mpt3sas_trigger_master(ioc,
6863 MASTER_TRIGGER_ADAPTER_RESET);
6865 dtmprintk(ioc, ioc_info(ioc, "%s: exit\n", __func__));