2 * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver
4 * Copyright (c) 2008-2009 USI Co., Ltd.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
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14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
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19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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37 * POSSIBILITY OF SUCH DAMAGES.
41 #include <linux/slab.h>
42 #include "pm8001_sas.h"
43 #include "pm8001_chips.h"
44 #include "pm80xx_hwi.h"
46 static ulong logging_level = PM8001_FAIL_LOGGING | PM8001_IOERR_LOGGING;
47 module_param(logging_level, ulong, 0644);
48 MODULE_PARM_DESC(logging_level, " bits for enabling logging info.");
50 static ulong link_rate = LINKRATE_15 | LINKRATE_30 | LINKRATE_60 | LINKRATE_120;
51 module_param(link_rate, ulong, 0644);
52 MODULE_PARM_DESC(link_rate, "Enable link rate.\n"
53 " 1: Link rate 1.5G\n"
54 " 2: Link rate 3.0G\n"
55 " 4: Link rate 6.0G\n"
56 " 8: Link rate 12.0G\n");
58 static struct scsi_transport_template *pm8001_stt;
59 static int pm8001_init_ccb_tag(struct pm8001_hba_info *);
62 * chip info structure to identify chip key functionality as
63 * encryption available/not, no of ports, hw specific function ref
65 static const struct pm8001_chip_info pm8001_chips[] = {
66 [chip_8001] = {0, 8, &pm8001_8001_dispatch,},
67 [chip_8008] = {0, 8, &pm8001_80xx_dispatch,},
68 [chip_8009] = {1, 8, &pm8001_80xx_dispatch,},
69 [chip_8018] = {0, 16, &pm8001_80xx_dispatch,},
70 [chip_8019] = {1, 16, &pm8001_80xx_dispatch,},
71 [chip_8074] = {0, 8, &pm8001_80xx_dispatch,},
72 [chip_8076] = {0, 16, &pm8001_80xx_dispatch,},
73 [chip_8077] = {0, 16, &pm8001_80xx_dispatch,},
74 [chip_8006] = {0, 16, &pm8001_80xx_dispatch,},
75 [chip_8070] = {0, 8, &pm8001_80xx_dispatch,},
76 [chip_8072] = {0, 16, &pm8001_80xx_dispatch,},
82 struct workqueue_struct *pm8001_wq;
84 static void pm8001_map_queues(struct Scsi_Host *shost)
86 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
87 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
88 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT];
90 if (pm8001_ha->number_of_intr > 1)
91 blk_mq_pci_map_queues(qmap, pm8001_ha->pdev, 1);
93 return blk_mq_map_queues(qmap);
97 * The main structure which LLDD must register for scsi core.
99 static struct scsi_host_template pm8001_sht = {
100 .module = THIS_MODULE,
102 .proc_name = DRV_NAME,
103 .queuecommand = sas_queuecommand,
104 .dma_need_drain = ata_scsi_dma_need_drain,
105 .target_alloc = sas_target_alloc,
106 .slave_configure = sas_slave_configure,
107 .scan_finished = pm8001_scan_finished,
108 .scan_start = pm8001_scan_start,
109 .change_queue_depth = sas_change_queue_depth,
110 .bios_param = sas_bios_param,
113 .sg_tablesize = PM8001_MAX_DMA_SG,
114 .max_sectors = SCSI_DEFAULT_MAX_SECTORS,
115 .eh_device_reset_handler = sas_eh_device_reset_handler,
116 .eh_target_reset_handler = sas_eh_target_reset_handler,
117 .slave_alloc = sas_slave_alloc,
118 .target_destroy = sas_target_destroy,
121 .compat_ioctl = sas_ioctl,
123 .shost_groups = pm8001_host_groups,
124 .track_queue_depth = 1,
126 .map_queues = pm8001_map_queues,
130 * Sas layer call this function to execute specific task.
132 static struct sas_domain_function_template pm8001_transport_ops = {
133 .lldd_dev_found = pm8001_dev_found,
134 .lldd_dev_gone = pm8001_dev_gone,
136 .lldd_execute_task = pm8001_queue_command,
137 .lldd_control_phy = pm8001_phy_control,
139 .lldd_abort_task = pm8001_abort_task,
140 .lldd_abort_task_set = sas_abort_task_set,
141 .lldd_clear_task_set = pm8001_clear_task_set,
142 .lldd_I_T_nexus_reset = pm8001_I_T_nexus_reset,
143 .lldd_lu_reset = pm8001_lu_reset,
144 .lldd_query_task = pm8001_query_task,
145 .lldd_port_formed = pm8001_port_formed,
146 .lldd_tmf_exec_complete = pm8001_setds_completion,
147 .lldd_tmf_aborted = pm8001_tmf_aborted,
151 * pm8001_phy_init - initiate our adapter phys
152 * @pm8001_ha: our hba structure.
155 static void pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, int phy_id)
157 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
158 struct asd_sas_phy *sas_phy = &phy->sas_phy;
159 phy->phy_state = PHY_LINK_DISABLE;
160 phy->pm8001_ha = pm8001_ha;
161 phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS;
162 phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS;
163 sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0;
164 sas_phy->class = SAS;
165 sas_phy->iproto = SAS_PROTOCOL_ALL;
167 sas_phy->type = PHY_TYPE_PHYSICAL;
168 sas_phy->role = PHY_ROLE_INITIATOR;
169 sas_phy->oob_mode = OOB_NOT_CONNECTED;
170 sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
171 sas_phy->id = phy_id;
172 sas_phy->sas_addr = (u8 *)&phy->dev_sas_addr;
173 sas_phy->frame_rcvd = &phy->frame_rcvd[0];
174 sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata;
175 sas_phy->lldd_phy = phy;
179 * pm8001_free - free hba
180 * @pm8001_ha: our hba structure.
182 static void pm8001_free(struct pm8001_hba_info *pm8001_ha)
189 for (i = 0; i < USI_MAX_MEMCNT; i++) {
190 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
191 dma_free_coherent(&pm8001_ha->pdev->dev,
192 (pm8001_ha->memoryMap.region[i].total_len +
193 pm8001_ha->memoryMap.region[i].alignment),
194 pm8001_ha->memoryMap.region[i].virt_ptr,
195 pm8001_ha->memoryMap.region[i].phys_addr);
198 PM8001_CHIP_DISP->chip_iounmap(pm8001_ha);
199 flush_workqueue(pm8001_wq);
200 bitmap_free(pm8001_ha->rsvd_tags);
204 #ifdef PM8001_USE_TASKLET
207 * pm8001_tasklet() - tasklet for 64 msi-x interrupt handler
208 * @opaque: the passed general host adapter struct
209 * Note: pm8001_tasklet is common for pm8001 & pm80xx
211 static void pm8001_tasklet(unsigned long opaque)
213 struct pm8001_hba_info *pm8001_ha;
214 struct isr_param *irq_vector;
216 irq_vector = (struct isr_param *)opaque;
217 pm8001_ha = irq_vector->drv_inst;
218 if (unlikely(!pm8001_ha))
220 PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
225 * pm8001_interrupt_handler_msix - main MSIX interrupt handler.
226 * It obtains the vector number and calls the equivalent bottom
227 * half or services directly.
228 * @irq: interrupt number
229 * @opaque: the passed outbound queue/vector. Host structure is
230 * retrieved from the same.
232 static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque)
234 struct isr_param *irq_vector;
235 struct pm8001_hba_info *pm8001_ha;
236 irqreturn_t ret = IRQ_HANDLED;
237 irq_vector = (struct isr_param *)opaque;
238 pm8001_ha = irq_vector->drv_inst;
240 if (unlikely(!pm8001_ha))
242 if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha))
244 #ifdef PM8001_USE_TASKLET
245 tasklet_schedule(&pm8001_ha->tasklet[irq_vector->irq_id]);
247 ret = PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
253 * pm8001_interrupt_handler_intx - main INTx interrupt handler.
254 * @irq: interrupt number
255 * @dev_id: sas_ha structure. The HBA is retrieved from sas_ha structure.
258 static irqreturn_t pm8001_interrupt_handler_intx(int irq, void *dev_id)
260 struct pm8001_hba_info *pm8001_ha;
261 irqreturn_t ret = IRQ_HANDLED;
262 struct sas_ha_struct *sha = dev_id;
263 pm8001_ha = sha->lldd_ha;
264 if (unlikely(!pm8001_ha))
266 if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha))
269 #ifdef PM8001_USE_TASKLET
270 tasklet_schedule(&pm8001_ha->tasklet[0]);
272 ret = PM8001_CHIP_DISP->isr(pm8001_ha, 0);
277 static u32 pm8001_setup_irq(struct pm8001_hba_info *pm8001_ha);
278 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha);
281 * pm8001_alloc - initiate our hba structure and 6 DMAs area.
282 * @pm8001_ha: our hba structure.
283 * @ent: PCI device ID structure to match on
285 static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha,
286 const struct pci_device_id *ent)
288 int i, count = 0, rc = 0;
289 u32 ci_offset, ib_offset, ob_offset, pi_offset;
290 struct inbound_queue_table *ibq;
291 struct outbound_queue_table *obq;
293 spin_lock_init(&pm8001_ha->lock);
294 spin_lock_init(&pm8001_ha->bitmap_lock);
295 pm8001_dbg(pm8001_ha, INIT, "pm8001_alloc: PHY:%x\n",
296 pm8001_ha->chip->n_phy);
298 /* Setup Interrupt */
299 rc = pm8001_setup_irq(pm8001_ha);
301 pm8001_dbg(pm8001_ha, FAIL,
302 "pm8001_setup_irq failed [ret: %d]\n", rc);
305 /* Request Interrupt */
306 rc = pm8001_request_irq(pm8001_ha);
310 count = pm8001_ha->max_q_num;
311 /* Queues are chosen based on the number of cores/msix availability */
312 ib_offset = pm8001_ha->ib_offset = USI_MAX_MEMCNT_BASE;
313 ci_offset = pm8001_ha->ci_offset = ib_offset + count;
314 ob_offset = pm8001_ha->ob_offset = ci_offset + count;
315 pi_offset = pm8001_ha->pi_offset = ob_offset + count;
316 pm8001_ha->max_memcnt = pi_offset + count;
318 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
319 pm8001_phy_init(pm8001_ha, i);
320 pm8001_ha->port[i].wide_port_phymap = 0;
321 pm8001_ha->port[i].port_attached = 0;
322 pm8001_ha->port[i].port_state = 0;
323 INIT_LIST_HEAD(&pm8001_ha->port[i].list);
326 /* MPI Memory region 1 for AAP Event Log for fw */
327 pm8001_ha->memoryMap.region[AAP1].num_elements = 1;
328 pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE;
329 pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE;
330 pm8001_ha->memoryMap.region[AAP1].alignment = 32;
332 /* MPI Memory region 2 for IOP Event Log for fw */
333 pm8001_ha->memoryMap.region[IOP].num_elements = 1;
334 pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE;
335 pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE;
336 pm8001_ha->memoryMap.region[IOP].alignment = 32;
338 for (i = 0; i < count; i++) {
339 ibq = &pm8001_ha->inbnd_q_tbl[i];
340 spin_lock_init(&ibq->iq_lock);
341 /* MPI Memory region 3 for consumer Index of inbound queues */
342 pm8001_ha->memoryMap.region[ci_offset+i].num_elements = 1;
343 pm8001_ha->memoryMap.region[ci_offset+i].element_size = 4;
344 pm8001_ha->memoryMap.region[ci_offset+i].total_len = 4;
345 pm8001_ha->memoryMap.region[ci_offset+i].alignment = 4;
347 if ((ent->driver_data) != chip_8001) {
348 /* MPI Memory region 5 inbound queues */
349 pm8001_ha->memoryMap.region[ib_offset+i].num_elements =
351 pm8001_ha->memoryMap.region[ib_offset+i].element_size
353 pm8001_ha->memoryMap.region[ib_offset+i].total_len =
354 PM8001_MPI_QUEUE * 128;
355 pm8001_ha->memoryMap.region[ib_offset+i].alignment
358 pm8001_ha->memoryMap.region[ib_offset+i].num_elements =
360 pm8001_ha->memoryMap.region[ib_offset+i].element_size
362 pm8001_ha->memoryMap.region[ib_offset+i].total_len =
363 PM8001_MPI_QUEUE * 64;
364 pm8001_ha->memoryMap.region[ib_offset+i].alignment = 64;
368 for (i = 0; i < count; i++) {
369 obq = &pm8001_ha->outbnd_q_tbl[i];
370 spin_lock_init(&obq->oq_lock);
371 /* MPI Memory region 4 for producer Index of outbound queues */
372 pm8001_ha->memoryMap.region[pi_offset+i].num_elements = 1;
373 pm8001_ha->memoryMap.region[pi_offset+i].element_size = 4;
374 pm8001_ha->memoryMap.region[pi_offset+i].total_len = 4;
375 pm8001_ha->memoryMap.region[pi_offset+i].alignment = 4;
377 if (ent->driver_data != chip_8001) {
378 /* MPI Memory region 6 Outbound queues */
379 pm8001_ha->memoryMap.region[ob_offset+i].num_elements =
381 pm8001_ha->memoryMap.region[ob_offset+i].element_size
383 pm8001_ha->memoryMap.region[ob_offset+i].total_len =
384 PM8001_MPI_QUEUE * 128;
385 pm8001_ha->memoryMap.region[ob_offset+i].alignment
388 /* MPI Memory region 6 Outbound queues */
389 pm8001_ha->memoryMap.region[ob_offset+i].num_elements =
391 pm8001_ha->memoryMap.region[ob_offset+i].element_size
393 pm8001_ha->memoryMap.region[ob_offset+i].total_len =
394 PM8001_MPI_QUEUE * 64;
395 pm8001_ha->memoryMap.region[ob_offset+i].alignment = 64;
399 /* Memory region write DMA*/
400 pm8001_ha->memoryMap.region[NVMD].num_elements = 1;
401 pm8001_ha->memoryMap.region[NVMD].element_size = 4096;
402 pm8001_ha->memoryMap.region[NVMD].total_len = 4096;
404 /* Memory region for fw flash */
405 pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096;
407 pm8001_ha->memoryMap.region[FORENSIC_MEM].num_elements = 1;
408 pm8001_ha->memoryMap.region[FORENSIC_MEM].total_len = 0x10000;
409 pm8001_ha->memoryMap.region[FORENSIC_MEM].element_size = 0x10000;
410 pm8001_ha->memoryMap.region[FORENSIC_MEM].alignment = 0x10000;
411 for (i = 0; i < pm8001_ha->max_memcnt; i++) {
412 struct mpi_mem *region = &pm8001_ha->memoryMap.region[i];
414 if (pm8001_mem_alloc(pm8001_ha->pdev,
417 ®ion->phys_addr_hi,
418 ®ion->phys_addr_lo,
420 region->alignment) != 0) {
421 pm8001_dbg(pm8001_ha, FAIL, "Mem%d alloc failed\n", i);
426 /* Memory region for devices*/
427 pm8001_ha->devices = kzalloc(PM8001_MAX_DEVICES
428 * sizeof(struct pm8001_device), GFP_KERNEL);
429 if (!pm8001_ha->devices) {
433 for (i = 0; i < PM8001_MAX_DEVICES; i++) {
434 pm8001_ha->devices[i].dev_type = SAS_PHY_UNUSED;
435 pm8001_ha->devices[i].id = i;
436 pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES;
437 atomic_set(&pm8001_ha->devices[i].running_req, 0);
439 pm8001_ha->flags = PM8001F_INIT_TIME;
443 for (i = 0; i < pm8001_ha->max_memcnt; i++) {
444 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
445 dma_free_coherent(&pm8001_ha->pdev->dev,
446 (pm8001_ha->memoryMap.region[i].total_len +
447 pm8001_ha->memoryMap.region[i].alignment),
448 pm8001_ha->memoryMap.region[i].virt_ptr,
449 pm8001_ha->memoryMap.region[i].phys_addr);
457 * pm8001_ioremap - remap the pci high physical address to kernel virtual
458 * address so that we can access them.
459 * @pm8001_ha: our hba structure.
461 static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha)
465 struct pci_dev *pdev;
467 pdev = pm8001_ha->pdev;
468 /* map pci mem (PMC pci base 0-3)*/
469 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
471 ** logical BARs for SPC:
472 ** bar 0 and 1 - logical BAR0
473 ** bar 2 and 3 - logical BAR1
474 ** bar4 - logical BAR2
475 ** bar5 - logical BAR3
476 ** Skip the appropriate assignments:
478 if ((bar == 1) || (bar == 3))
480 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
481 pm8001_ha->io_mem[logicalBar].membase =
482 pci_resource_start(pdev, bar);
483 pm8001_ha->io_mem[logicalBar].memsize =
484 pci_resource_len(pdev, bar);
485 pm8001_ha->io_mem[logicalBar].memvirtaddr =
486 ioremap(pm8001_ha->io_mem[logicalBar].membase,
487 pm8001_ha->io_mem[logicalBar].memsize);
488 if (!pm8001_ha->io_mem[logicalBar].memvirtaddr) {
489 pm8001_dbg(pm8001_ha, INIT,
490 "Failed to ioremap bar %d, logicalBar %d",
494 pm8001_dbg(pm8001_ha, INIT,
495 "base addr %llx virt_addr=%llx len=%d\n",
496 (u64)pm8001_ha->io_mem[logicalBar].membase,
498 pm8001_ha->io_mem[logicalBar].memvirtaddr,
499 pm8001_ha->io_mem[logicalBar].memsize);
501 pm8001_ha->io_mem[logicalBar].membase = 0;
502 pm8001_ha->io_mem[logicalBar].memsize = 0;
503 pm8001_ha->io_mem[logicalBar].memvirtaddr = NULL;
511 * pm8001_pci_alloc - initialize our ha card structure
514 * @shost: scsi host struct which has been initialized before.
516 static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev,
517 const struct pci_device_id *ent,
518 struct Scsi_Host *shost)
521 struct pm8001_hba_info *pm8001_ha;
522 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
525 pm8001_ha = sha->lldd_ha;
529 pm8001_ha->pdev = pdev;
530 pm8001_ha->dev = &pdev->dev;
531 pm8001_ha->chip_id = ent->driver_data;
532 pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id];
533 pm8001_ha->irq = pdev->irq;
534 pm8001_ha->sas = sha;
535 pm8001_ha->shost = shost;
536 pm8001_ha->id = pm8001_id++;
537 pm8001_ha->logging_level = logging_level;
538 pm8001_ha->non_fatal_count = 0;
539 if (link_rate >= 1 && link_rate <= 15)
540 pm8001_ha->link_rate = (link_rate << 8);
542 pm8001_ha->link_rate = LINKRATE_15 | LINKRATE_30 |
543 LINKRATE_60 | LINKRATE_120;
544 pm8001_dbg(pm8001_ha, FAIL,
545 "Setting link rate to default value\n");
547 sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id);
548 /* IOMB size is 128 for 8088/89 controllers */
549 if (pm8001_ha->chip_id != chip_8001)
550 pm8001_ha->iomb_size = IOMB_SIZE_SPCV;
552 pm8001_ha->iomb_size = IOMB_SIZE_SPC;
554 #ifdef PM8001_USE_TASKLET
555 /* Tasklet for non msi-x interrupt handler */
556 if ((!pdev->msix_cap || !pci_msi_enabled())
557 || (pm8001_ha->chip_id == chip_8001))
558 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
559 (unsigned long)&(pm8001_ha->irq_vector[0]));
561 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
562 tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
563 (unsigned long)&(pm8001_ha->irq_vector[j]));
565 if (pm8001_ioremap(pm8001_ha))
566 goto failed_pci_alloc;
567 if (!pm8001_alloc(pm8001_ha, ent))
570 pm8001_free(pm8001_ha);
575 * pci_go_44 - pm8001 specified, its DMA is 44 bit rather than 64 bit
578 static int pci_go_44(struct pci_dev *pdev)
582 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44));
584 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
586 dev_printk(KERN_ERR, &pdev->dev,
587 "32-bit DMA enable failed\n");
593 * pm8001_prep_sas_ha_init - allocate memory in general hba struct && init them.
594 * @shost: scsi host which has been allocated outside.
595 * @chip_info: our ha struct.
597 static int pm8001_prep_sas_ha_init(struct Scsi_Host *shost,
598 const struct pm8001_chip_info *chip_info)
601 struct asd_sas_phy **arr_phy;
602 struct asd_sas_port **arr_port;
603 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
605 phy_nr = chip_info->n_phy;
607 memset(sha, 0x00, sizeof(*sha));
608 arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
611 arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
615 sha->sas_phy = arr_phy;
616 sha->sas_port = arr_port;
617 sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL);
621 shost->transportt = pm8001_stt;
622 shost->max_id = PM8001_MAX_DEVICES;
623 shost->unique_id = pm8001_id;
624 shost->max_cmd_len = 16;
635 * pm8001_post_sas_ha_init - initialize general hba struct defined in libsas
636 * @shost: scsi host which has been allocated outside
637 * @chip_info: our ha struct.
639 static void pm8001_post_sas_ha_init(struct Scsi_Host *shost,
640 const struct pm8001_chip_info *chip_info)
643 struct pm8001_hba_info *pm8001_ha;
644 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
646 pm8001_ha = sha->lldd_ha;
647 for (i = 0; i < chip_info->n_phy; i++) {
648 sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy;
649 sha->sas_port[i] = &pm8001_ha->port[i].sas_port;
650 sha->sas_phy[i]->sas_addr =
651 (u8 *)&pm8001_ha->phy[i].dev_sas_addr;
653 sha->sas_ha_name = DRV_NAME;
654 sha->dev = pm8001_ha->dev;
655 sha->strict_wide_ports = 1;
656 sha->lldd_module = THIS_MODULE;
657 sha->sas_addr = &pm8001_ha->sas_addr[0];
658 sha->num_phys = chip_info->n_phy;
659 sha->core.shost = shost;
663 * pm8001_init_sas_add - initialize sas address
664 * @pm8001_ha: our ha struct.
666 * Currently we just set the fixed SAS address to our HBA, for manufacture,
667 * it should read from the EEPROM
669 static void pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha)
673 #ifdef PM8001_READ_VPD
674 /* For new SPC controllers WWN is stored in flash vpd
675 * For SPC/SPCve controllers WWN is stored in EEPROM
676 * For Older SPC WWN is stored in NVMD
678 DECLARE_COMPLETION_ONSTACK(completion);
679 struct pm8001_ioctl_payload payload;
683 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
684 pm8001_ha->nvmd_completion = &completion;
686 if (pm8001_ha->chip_id == chip_8001) {
687 if (deviceid == 0x8081 || deviceid == 0x0042) {
688 payload.minor_function = 4;
689 payload.rd_length = 4096;
691 payload.minor_function = 0;
692 payload.rd_length = 128;
694 } else if ((pm8001_ha->chip_id == chip_8070 ||
695 pm8001_ha->chip_id == chip_8072) &&
696 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
697 payload.minor_function = 4;
698 payload.rd_length = 4096;
700 payload.minor_function = 1;
701 payload.rd_length = 4096;
704 payload.func_specific = kzalloc(payload.rd_length, GFP_KERNEL);
705 if (!payload.func_specific) {
706 pm8001_dbg(pm8001_ha, INIT, "mem alloc fail\n");
709 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
711 kfree(payload.func_specific);
712 pm8001_dbg(pm8001_ha, INIT, "nvmd failed\n");
715 wait_for_completion(&completion);
717 for (i = 0, j = 0; i <= 7; i++, j++) {
718 if (pm8001_ha->chip_id == chip_8001) {
719 if (deviceid == 0x8081)
720 pm8001_ha->sas_addr[j] =
721 payload.func_specific[0x704 + i];
722 else if (deviceid == 0x0042)
723 pm8001_ha->sas_addr[j] =
724 payload.func_specific[0x010 + i];
725 } else if ((pm8001_ha->chip_id == chip_8070 ||
726 pm8001_ha->chip_id == chip_8072) &&
727 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
728 pm8001_ha->sas_addr[j] =
729 payload.func_specific[0x010 + i];
731 pm8001_ha->sas_addr[j] =
732 payload.func_specific[0x804 + i];
734 memcpy(sas_add, pm8001_ha->sas_addr, SAS_ADDR_SIZE);
735 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
736 if (i && ((i % 4) == 0))
737 sas_add[7] = sas_add[7] + 4;
738 memcpy(&pm8001_ha->phy[i].dev_sas_addr,
739 sas_add, SAS_ADDR_SIZE);
740 pm8001_dbg(pm8001_ha, INIT, "phy %d sas_addr = %016llx\n", i,
741 pm8001_ha->phy[i].dev_sas_addr);
743 kfree(payload.func_specific);
745 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
746 pm8001_ha->phy[i].dev_sas_addr = 0x50010c600047f9d0ULL;
747 pm8001_ha->phy[i].dev_sas_addr =
749 (*(u64 *)&pm8001_ha->phy[i].dev_sas_addr));
751 memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr,
757 * pm8001_get_phy_settings_info : Read phy setting values.
758 * @pm8001_ha : our hba.
760 static int pm8001_get_phy_settings_info(struct pm8001_hba_info *pm8001_ha)
763 #ifdef PM8001_READ_VPD
764 /*OPTION ROM FLASH read for the SPC cards */
765 DECLARE_COMPLETION_ONSTACK(completion);
766 struct pm8001_ioctl_payload payload;
769 pm8001_ha->nvmd_completion = &completion;
770 /* SAS ADDRESS read from flash / EEPROM */
771 payload.minor_function = 6;
773 payload.rd_length = 4096;
774 payload.func_specific = kzalloc(4096, GFP_KERNEL);
775 if (!payload.func_specific)
777 /* Read phy setting values from flash */
778 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
780 kfree(payload.func_specific);
781 pm8001_dbg(pm8001_ha, INIT, "nvmd failed\n");
784 wait_for_completion(&completion);
785 pm8001_set_phy_profile(pm8001_ha, sizeof(u8), payload.func_specific);
786 kfree(payload.func_specific);
791 struct pm8001_mpi3_phy_pg_trx_config {
804 * pm8001_get_internal_phy_settings - Retrieves the internal PHY settings
805 * @pm8001_ha : our adapter
806 * @phycfg : PHY config page to populate
809 void pm8001_get_internal_phy_settings(struct pm8001_hba_info *pm8001_ha,
810 struct pm8001_mpi3_phy_pg_trx_config *phycfg)
812 phycfg->LaneLosCfg = 0x00000132;
813 phycfg->LanePgaCfg1 = 0x00203949;
814 phycfg->LanePisoCfg1 = 0x000000FF;
815 phycfg->LanePisoCfg2 = 0xFF000001;
816 phycfg->LanePisoCfg3 = 0xE7011300;
817 phycfg->LanePisoCfg4 = 0x631C40C0;
818 phycfg->LanePisoCfg5 = 0xF8102036;
819 phycfg->LanePisoCfg6 = 0xF74A1000;
820 phycfg->LaneBctCtrl = 0x00FB33F8;
824 * pm8001_get_external_phy_settings - Retrieves the external PHY settings
825 * @pm8001_ha : our adapter
826 * @phycfg : PHY config page to populate
829 void pm8001_get_external_phy_settings(struct pm8001_hba_info *pm8001_ha,
830 struct pm8001_mpi3_phy_pg_trx_config *phycfg)
832 phycfg->LaneLosCfg = 0x00000132;
833 phycfg->LanePgaCfg1 = 0x00203949;
834 phycfg->LanePisoCfg1 = 0x000000FF;
835 phycfg->LanePisoCfg2 = 0xFF000001;
836 phycfg->LanePisoCfg3 = 0xE7011300;
837 phycfg->LanePisoCfg4 = 0x63349140;
838 phycfg->LanePisoCfg5 = 0xF8102036;
839 phycfg->LanePisoCfg6 = 0xF80D9300;
840 phycfg->LaneBctCtrl = 0x00FB33F8;
844 * pm8001_get_phy_mask - Retrieves the mask that denotes if a PHY is int/ext
845 * @pm8001_ha : our adapter
846 * @phymask : The PHY mask
849 void pm8001_get_phy_mask(struct pm8001_hba_info *pm8001_ha, int *phymask)
851 switch (pm8001_ha->pdev->subsystem_device) {
852 case 0x0070: /* H1280 - 8 external 0 internal */
853 case 0x0072: /* H12F0 - 16 external 0 internal */
857 case 0x0071: /* H1208 - 0 external 8 internal */
858 case 0x0073: /* H120F - 0 external 16 internal */
862 case 0x0080: /* H1244 - 4 external 4 internal */
866 case 0x0081: /* H1248 - 4 external 8 internal */
870 case 0x0082: /* H1288 - 8 external 8 internal */
875 pm8001_dbg(pm8001_ha, INIT,
876 "Unknown subsystem device=0x%.04x\n",
877 pm8001_ha->pdev->subsystem_device);
882 * pm8001_set_phy_settings_ven_117c_12G() - Configure ATTO 12Gb PHY settings
883 * @pm8001_ha : our adapter
886 int pm8001_set_phy_settings_ven_117c_12G(struct pm8001_hba_info *pm8001_ha)
888 struct pm8001_mpi3_phy_pg_trx_config phycfg_int;
889 struct pm8001_mpi3_phy_pg_trx_config phycfg_ext;
893 memset(&phycfg_int, 0, sizeof(phycfg_int));
894 memset(&phycfg_ext, 0, sizeof(phycfg_ext));
896 pm8001_get_internal_phy_settings(pm8001_ha, &phycfg_int);
897 pm8001_get_external_phy_settings(pm8001_ha, &phycfg_ext);
898 pm8001_get_phy_mask(pm8001_ha, &phymask);
900 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
901 if (phymask & (1 << i)) {/* Internal PHY */
902 pm8001_set_phy_profile_single(pm8001_ha, i,
903 sizeof(phycfg_int) / sizeof(u32),
906 } else { /* External PHY */
907 pm8001_set_phy_profile_single(pm8001_ha, i,
908 sizeof(phycfg_ext) / sizeof(u32),
917 * pm8001_configure_phy_settings - Configures PHY settings based on vendor ID.
918 * @pm8001_ha : our hba.
920 static int pm8001_configure_phy_settings(struct pm8001_hba_info *pm8001_ha)
922 switch (pm8001_ha->pdev->subsystem_vendor) {
923 case PCI_VENDOR_ID_ATTO:
924 if (pm8001_ha->pdev->device == 0x0042) /* 6Gb */
927 return pm8001_set_phy_settings_ven_117c_12G(pm8001_ha);
929 case PCI_VENDOR_ID_ADAPTEC2:
934 return pm8001_get_phy_settings_info(pm8001_ha);
938 #ifdef PM8001_USE_MSIX
940 * pm8001_setup_msix - enable MSI-X interrupt
941 * @pm8001_ha: our ha struct.
943 static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha)
945 unsigned int allocated_irq_vectors;
948 /* SPCv controllers supports 64 msi-x */
949 if (pm8001_ha->chip_id == chip_8001) {
950 rc = pci_alloc_irq_vectors(pm8001_ha->pdev, 1, 1,
954 * Queue index #0 is used always for housekeeping, so don't
955 * include in the affinity spreading.
957 struct irq_affinity desc = {
960 rc = pci_alloc_irq_vectors_affinity(
961 pm8001_ha->pdev, 2, PM8001_MAX_MSIX_VEC,
962 PCI_IRQ_MSIX | PCI_IRQ_AFFINITY, &desc);
965 allocated_irq_vectors = rc;
969 /* Assigns the number of interrupts */
970 pm8001_ha->number_of_intr = allocated_irq_vectors;
972 /* Maximum queue number updating in HBA structure */
973 pm8001_ha->max_q_num = allocated_irq_vectors;
975 pm8001_dbg(pm8001_ha, INIT,
976 "pci_alloc_irq_vectors request ret:%d no of intr %d\n",
977 rc, pm8001_ha->number_of_intr);
981 static u32 pm8001_request_msix(struct pm8001_hba_info *pm8001_ha)
984 int flag = 0, rc = 0;
985 int nr_irqs = pm8001_ha->number_of_intr;
987 if (pm8001_ha->chip_id != chip_8001)
988 flag &= ~IRQF_SHARED;
990 pm8001_dbg(pm8001_ha, INIT,
991 "pci_enable_msix request number of intr %d\n",
992 pm8001_ha->number_of_intr);
994 if (nr_irqs > ARRAY_SIZE(pm8001_ha->intr_drvname))
995 nr_irqs = ARRAY_SIZE(pm8001_ha->intr_drvname);
997 for (i = 0; i < nr_irqs; i++) {
998 snprintf(pm8001_ha->intr_drvname[i],
999 sizeof(pm8001_ha->intr_drvname[0]),
1000 "%s-%d", pm8001_ha->name, i);
1001 pm8001_ha->irq_vector[i].irq_id = i;
1002 pm8001_ha->irq_vector[i].drv_inst = pm8001_ha;
1004 rc = request_irq(pci_irq_vector(pm8001_ha->pdev, i),
1005 pm8001_interrupt_handler_msix, flag,
1006 pm8001_ha->intr_drvname[i],
1007 &(pm8001_ha->irq_vector[i]));
1009 for (j = 0; j < i; j++) {
1010 free_irq(pci_irq_vector(pm8001_ha->pdev, i),
1011 &(pm8001_ha->irq_vector[i]));
1013 pci_free_irq_vectors(pm8001_ha->pdev);
1022 static u32 pm8001_setup_irq(struct pm8001_hba_info *pm8001_ha)
1024 struct pci_dev *pdev;
1026 pdev = pm8001_ha->pdev;
1028 #ifdef PM8001_USE_MSIX
1029 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
1030 return pm8001_setup_msix(pm8001_ha);
1031 pm8001_dbg(pm8001_ha, INIT, "MSIX not supported!!!\n");
1037 * pm8001_request_irq - register interrupt
1038 * @pm8001_ha: our ha struct.
1040 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha)
1042 struct pci_dev *pdev;
1045 pdev = pm8001_ha->pdev;
1047 #ifdef PM8001_USE_MSIX
1048 if (pdev->msix_cap && pci_msi_enabled())
1049 return pm8001_request_msix(pm8001_ha);
1051 pm8001_dbg(pm8001_ha, INIT, "MSIX not supported!!!\n");
1057 /* initialize the INT-X interrupt */
1058 pm8001_ha->irq_vector[0].irq_id = 0;
1059 pm8001_ha->irq_vector[0].drv_inst = pm8001_ha;
1060 rc = request_irq(pdev->irq, pm8001_interrupt_handler_intx, IRQF_SHARED,
1061 pm8001_ha->name, SHOST_TO_SAS_HA(pm8001_ha->shost));
1066 * pm8001_pci_probe - probe supported device
1067 * @pdev: pci device which kernel has been prepared for.
1068 * @ent: pci device id
1070 * This function is the main initialization function, when register a new
1071 * pci driver it is invoked, all struct and hardware initialization should be
1072 * done here, also, register interrupt.
1074 static int pm8001_pci_probe(struct pci_dev *pdev,
1075 const struct pci_device_id *ent)
1080 struct pm8001_hba_info *pm8001_ha;
1081 struct Scsi_Host *shost = NULL;
1082 const struct pm8001_chip_info *chip;
1083 struct sas_ha_struct *sha;
1085 dev_printk(KERN_INFO, &pdev->dev,
1086 "pm80xx: driver version %s\n", DRV_VERSION);
1087 rc = pci_enable_device(pdev);
1089 goto err_out_enable;
1090 pci_set_master(pdev);
1092 * Enable pci slot busmaster by setting pci command register.
1093 * This is required by FW for Cyclone card.
1096 pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg);
1098 pci_write_config_dword(pdev, PCI_COMMAND, pci_reg);
1099 rc = pci_request_regions(pdev, DRV_NAME);
1101 goto err_out_disable;
1102 rc = pci_go_44(pdev);
1104 goto err_out_regions;
1106 shost = scsi_host_alloc(&pm8001_sht, sizeof(void *));
1109 goto err_out_regions;
1111 chip = &pm8001_chips[ent->driver_data];
1112 sha = kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL);
1115 goto err_out_free_host;
1117 SHOST_TO_SAS_HA(shost) = sha;
1119 rc = pm8001_prep_sas_ha_init(shost, chip);
1124 pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
1125 /* ent->driver variable is used to differentiate between controllers */
1126 pm8001_ha = pm8001_pci_alloc(pdev, ent, shost);
1132 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1133 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1135 pm8001_dbg(pm8001_ha, FAIL,
1136 "chip_init failed [ret: %d]\n", rc);
1137 goto err_out_ha_free;
1140 rc = pm8001_init_ccb_tag(pm8001_ha);
1142 goto err_out_enable;
1145 PM8001_CHIP_DISP->chip_post_init(pm8001_ha);
1147 if (pm8001_ha->number_of_intr > 1) {
1148 shost->nr_hw_queues = pm8001_ha->number_of_intr - 1;
1150 * For now, ensure we're not sent too many commands by setting
1151 * host_tagset. This is also required if we start using request
1154 shost->host_tagset = 1;
1157 rc = scsi_add_host(shost, &pdev->dev);
1159 goto err_out_ha_free;
1161 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1162 if (pm8001_ha->chip_id != chip_8001) {
1163 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1164 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1165 /* setup thermal configuration. */
1166 pm80xx_set_thermal_config(pm8001_ha);
1169 pm8001_init_sas_add(pm8001_ha);
1170 /* phy setting support for motherboard controller */
1171 rc = pm8001_configure_phy_settings(pm8001_ha);
1175 pm8001_post_sas_ha_init(shost, chip);
1176 rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
1178 pm8001_dbg(pm8001_ha, FAIL,
1179 "sas_register_ha failed [ret: %d]\n", rc);
1182 list_add_tail(&pm8001_ha->list, &hba_list);
1183 pm8001_ha->flags = PM8001F_RUN_TIME;
1184 scsi_scan_host(pm8001_ha->shost);
1188 scsi_remove_host(pm8001_ha->shost);
1190 pm8001_free(pm8001_ha);
1194 scsi_host_put(shost);
1196 pci_release_regions(pdev);
1198 pci_disable_device(pdev);
1204 * pm8001_init_ccb_tag - allocate memory to CCB and tag.
1205 * @pm8001_ha: our hba card information.
1207 static int pm8001_init_ccb_tag(struct pm8001_hba_info *pm8001_ha)
1209 struct Scsi_Host *shost = pm8001_ha->shost;
1210 struct device *dev = pm8001_ha->dev;
1211 u32 max_out_io, ccb_count;
1214 max_out_io = pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io;
1215 ccb_count = min_t(int, PM8001_MAX_CCB, max_out_io);
1217 shost->can_queue = ccb_count - PM8001_RESERVE_SLOT;
1219 pm8001_ha->rsvd_tags = bitmap_zalloc(PM8001_RESERVE_SLOT, GFP_KERNEL);
1220 if (!pm8001_ha->rsvd_tags)
1223 /* Memory region for ccb_info*/
1224 pm8001_ha->ccb_count = ccb_count;
1225 pm8001_ha->ccb_info =
1226 kcalloc(ccb_count, sizeof(struct pm8001_ccb_info), GFP_KERNEL);
1227 if (!pm8001_ha->ccb_info) {
1228 pm8001_dbg(pm8001_ha, FAIL,
1229 "Unable to allocate memory for ccb\n");
1232 for (i = 0; i < ccb_count; i++) {
1233 pm8001_ha->ccb_info[i].buf_prd = dma_alloc_coherent(dev,
1234 sizeof(struct pm8001_prd) * PM8001_MAX_DMA_SG,
1235 &pm8001_ha->ccb_info[i].ccb_dma_handle,
1237 if (!pm8001_ha->ccb_info[i].buf_prd) {
1238 pm8001_dbg(pm8001_ha, FAIL,
1239 "ccb prd memory allocation error\n");
1242 pm8001_ha->ccb_info[i].task = NULL;
1243 pm8001_ha->ccb_info[i].ccb_tag = PM8001_INVALID_TAG;
1244 pm8001_ha->ccb_info[i].device = NULL;
1250 kfree(pm8001_ha->devices);
1255 static void pm8001_pci_remove(struct pci_dev *pdev)
1257 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1258 struct pm8001_hba_info *pm8001_ha;
1260 pm8001_ha = sha->lldd_ha;
1261 sas_unregister_ha(sha);
1262 sas_remove_host(pm8001_ha->shost);
1263 list_del(&pm8001_ha->list);
1264 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1265 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1267 #ifdef PM8001_USE_MSIX
1268 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1269 synchronize_irq(pci_irq_vector(pdev, i));
1270 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1271 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);
1272 pci_free_irq_vectors(pdev);
1274 free_irq(pm8001_ha->irq, sha);
1276 #ifdef PM8001_USE_TASKLET
1277 /* For non-msix and msix interrupts */
1278 if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1279 (pm8001_ha->chip_id == chip_8001))
1280 tasklet_kill(&pm8001_ha->tasklet[0]);
1282 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1283 tasklet_kill(&pm8001_ha->tasklet[j]);
1285 scsi_host_put(pm8001_ha->shost);
1287 for (i = 0; i < pm8001_ha->ccb_count; i++) {
1288 dma_free_coherent(&pm8001_ha->pdev->dev,
1289 sizeof(struct pm8001_prd) * PM8001_MAX_DMA_SG,
1290 pm8001_ha->ccb_info[i].buf_prd,
1291 pm8001_ha->ccb_info[i].ccb_dma_handle);
1293 kfree(pm8001_ha->ccb_info);
1294 kfree(pm8001_ha->devices);
1296 pm8001_free(pm8001_ha);
1297 kfree(sha->sas_phy);
1298 kfree(sha->sas_port);
1300 pci_release_regions(pdev);
1301 pci_disable_device(pdev);
1305 * pm8001_pci_suspend - power management suspend main entry point
1306 * @dev: Device struct
1308 * Return: 0 on success, anything else on error.
1310 static int __maybe_unused pm8001_pci_suspend(struct device *dev)
1312 struct pci_dev *pdev = to_pci_dev(dev);
1313 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1314 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
1316 sas_suspend_ha(sha);
1317 flush_workqueue(pm8001_wq);
1318 scsi_block_requests(pm8001_ha->shost);
1319 if (!pdev->pm_cap) {
1320 dev_err(dev, " PCI PM not supported\n");
1323 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1324 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1325 #ifdef PM8001_USE_MSIX
1326 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1327 synchronize_irq(pci_irq_vector(pdev, i));
1328 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1329 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);
1330 pci_free_irq_vectors(pdev);
1332 free_irq(pm8001_ha->irq, sha);
1334 #ifdef PM8001_USE_TASKLET
1335 /* For non-msix and msix interrupts */
1336 if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1337 (pm8001_ha->chip_id == chip_8001))
1338 tasklet_kill(&pm8001_ha->tasklet[0]);
1340 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1341 tasklet_kill(&pm8001_ha->tasklet[j]);
1343 pm8001_info(pm8001_ha, "pdev=0x%p, slot=%s, entering "
1344 "suspended state\n", pdev,
1350 * pm8001_pci_resume - power management resume main entry point
1351 * @dev: Device struct
1353 * Return: 0 on success, anything else on error.
1355 static int __maybe_unused pm8001_pci_resume(struct device *dev)
1357 struct pci_dev *pdev = to_pci_dev(dev);
1358 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1359 struct pm8001_hba_info *pm8001_ha;
1362 DECLARE_COMPLETION_ONSTACK(completion);
1364 pm8001_ha = sha->lldd_ha;
1366 pm8001_info(pm8001_ha,
1367 "pdev=0x%p, slot=%s, resuming from previous operating state [D%d]\n",
1368 pdev, pm8001_ha->name, pdev->current_state);
1370 rc = pci_go_44(pdev);
1372 goto err_out_disable;
1373 sas_prep_resume_ha(sha);
1374 /* chip soft rst only for spc */
1375 if (pm8001_ha->chip_id == chip_8001) {
1376 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1377 pm8001_dbg(pm8001_ha, INIT, "chip soft reset successful\n");
1379 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1381 goto err_out_disable;
1383 /* disable all the interrupt bits */
1384 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1386 rc = pm8001_request_irq(pm8001_ha);
1388 goto err_out_disable;
1389 #ifdef PM8001_USE_TASKLET
1390 /* Tasklet for non msi-x interrupt handler */
1391 if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1392 (pm8001_ha->chip_id == chip_8001))
1393 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
1394 (unsigned long)&(pm8001_ha->irq_vector[0]));
1396 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1397 tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
1398 (unsigned long)&(pm8001_ha->irq_vector[j]));
1400 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1401 if (pm8001_ha->chip_id != chip_8001) {
1402 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1403 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1406 /* Chip documentation for the 8070 and 8072 SPCv */
1407 /* states that a 500ms minimum delay is required */
1408 /* before issuing commands. Otherwise, the firmware */
1409 /* will enter an unrecoverable state. */
1411 if (pm8001_ha->chip_id == chip_8070 ||
1412 pm8001_ha->chip_id == chip_8072) {
1416 /* Spin up the PHYs */
1418 pm8001_ha->flags = PM8001F_RUN_TIME;
1419 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
1420 pm8001_ha->phy[i].enable_completion = &completion;
1421 PM8001_CHIP_DISP->phy_start_req(pm8001_ha, i);
1422 wait_for_completion(&completion);
1428 scsi_remove_host(pm8001_ha->shost);
1433 /* update of pci device, vendor id and driver data with
1434 * unique value for each of the controller
1436 static struct pci_device_id pm8001_pci_table[] = {
1437 { PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 },
1438 { PCI_VDEVICE(PMC_Sierra, 0x8006), chip_8006 },
1439 { PCI_VDEVICE(ADAPTEC2, 0x8006), chip_8006 },
1440 { PCI_VDEVICE(ATTO, 0x0042), chip_8001 },
1441 /* Support for SPC/SPCv/SPCve controllers */
1442 { PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 },
1443 { PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 },
1444 { PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 },
1445 { PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 },
1446 { PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 },
1447 { PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 },
1448 { PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 },
1449 { PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 },
1450 { PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 },
1451 { PCI_VDEVICE(PMC_Sierra, 0x8074), chip_8074 },
1452 { PCI_VDEVICE(ADAPTEC2, 0x8074), chip_8074 },
1453 { PCI_VDEVICE(PMC_Sierra, 0x8076), chip_8076 },
1454 { PCI_VDEVICE(ADAPTEC2, 0x8076), chip_8076 },
1455 { PCI_VDEVICE(PMC_Sierra, 0x8077), chip_8077 },
1456 { PCI_VDEVICE(ADAPTEC2, 0x8077), chip_8077 },
1457 { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1458 PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 },
1459 { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1460 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 },
1461 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1462 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 },
1463 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1464 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 },
1465 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1466 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 },
1467 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1468 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 },
1469 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1470 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 },
1471 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1472 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 },
1473 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1474 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 },
1475 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1476 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 },
1477 { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1478 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8074 },
1479 { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1480 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8076 },
1481 { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1482 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8077 },
1483 { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1484 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8074 },
1485 { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1486 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8076 },
1487 { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1488 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8077 },
1489 { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1490 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8076 },
1491 { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1492 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8077 },
1493 { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1494 PCI_VENDOR_ID_ADAPTEC2, 0x0404, 0, 0, chip_8074 },
1495 { PCI_VENDOR_ID_ATTO, 0x8070,
1496 PCI_VENDOR_ID_ATTO, 0x0070, 0, 0, chip_8070 },
1497 { PCI_VENDOR_ID_ATTO, 0x8070,
1498 PCI_VENDOR_ID_ATTO, 0x0071, 0, 0, chip_8070 },
1499 { PCI_VENDOR_ID_ATTO, 0x8072,
1500 PCI_VENDOR_ID_ATTO, 0x0072, 0, 0, chip_8072 },
1501 { PCI_VENDOR_ID_ATTO, 0x8072,
1502 PCI_VENDOR_ID_ATTO, 0x0073, 0, 0, chip_8072 },
1503 { PCI_VENDOR_ID_ATTO, 0x8070,
1504 PCI_VENDOR_ID_ATTO, 0x0080, 0, 0, chip_8070 },
1505 { PCI_VENDOR_ID_ATTO, 0x8072,
1506 PCI_VENDOR_ID_ATTO, 0x0081, 0, 0, chip_8072 },
1507 { PCI_VENDOR_ID_ATTO, 0x8072,
1508 PCI_VENDOR_ID_ATTO, 0x0082, 0, 0, chip_8072 },
1509 {} /* terminate list */
1512 static SIMPLE_DEV_PM_OPS(pm8001_pci_pm_ops,
1516 static struct pci_driver pm8001_pci_driver = {
1518 .id_table = pm8001_pci_table,
1519 .probe = pm8001_pci_probe,
1520 .remove = pm8001_pci_remove,
1521 .driver.pm = &pm8001_pci_pm_ops,
1525 * pm8001_init - initialize scsi transport template
1527 static int __init pm8001_init(void)
1531 pm8001_wq = alloc_workqueue("pm80xx", 0, 0);
1536 pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops);
1539 rc = pci_register_driver(&pm8001_pci_driver);
1545 sas_release_transport(pm8001_stt);
1547 destroy_workqueue(pm8001_wq);
1552 static void __exit pm8001_exit(void)
1554 pci_unregister_driver(&pm8001_pci_driver);
1555 sas_release_transport(pm8001_stt);
1556 destroy_workqueue(pm8001_wq);
1559 module_init(pm8001_init);
1560 module_exit(pm8001_exit);
1562 MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>");
1563 MODULE_AUTHOR("Anand Kumar Santhanam <AnandKumar.Santhanam@pmcs.com>");
1564 MODULE_AUTHOR("Sangeetha Gnanasekaran <Sangeetha.Gnanasekaran@pmcs.com>");
1565 MODULE_AUTHOR("Nikith Ganigarakoppal <Nikith.Ganigarakoppal@pmcs.com>");
1567 "PMC-Sierra PM8001/8006/8081/8088/8089/8074/8076/8077/8070/8072 "
1568 "SAS/SATA controller driver");
1569 MODULE_VERSION(DRV_VERSION);
1570 MODULE_LICENSE("GPL");
1571 MODULE_DEVICE_TABLE(pci, pm8001_pci_table);