1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
7 #include <linux/device.h>
8 #include <linux/kobject.h>
9 #include <linux/init.h>
11 #include <linux/nvmem-consumer.h>
12 #include <linux/nvmem-provider.h>
14 #include <linux/of_address.h>
15 #include <linux/platform_device.h>
16 #include <linux/slab.h>
17 #include <linux/sys_soc.h>
19 #include <soc/tegra/common.h>
20 #include <soc/tegra/fuse.h>
24 struct tegra_sku_info tegra_sku_info;
25 EXPORT_SYMBOL(tegra_sku_info);
27 static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
28 [TEGRA_REVISION_UNKNOWN] = "unknown",
29 [TEGRA_REVISION_A01] = "A01",
30 [TEGRA_REVISION_A02] = "A02",
31 [TEGRA_REVISION_A03] = "A03",
32 [TEGRA_REVISION_A03p] = "A03 prime",
33 [TEGRA_REVISION_A04] = "A04",
36 static const struct of_device_id car_match[] __initconst = {
37 { .compatible = "nvidia,tegra20-car", },
38 { .compatible = "nvidia,tegra30-car", },
39 { .compatible = "nvidia,tegra114-car", },
40 { .compatible = "nvidia,tegra124-car", },
41 { .compatible = "nvidia,tegra132-car", },
42 { .compatible = "nvidia,tegra210-car", },
46 static struct tegra_fuse *fuse = &(struct tegra_fuse) {
51 static const struct of_device_id tegra_fuse_match[] = {
52 #ifdef CONFIG_ARCH_TEGRA_186_SOC
53 { .compatible = "nvidia,tegra186-efuse", .data = &tegra186_fuse_soc },
55 #ifdef CONFIG_ARCH_TEGRA_210_SOC
56 { .compatible = "nvidia,tegra210-efuse", .data = &tegra210_fuse_soc },
58 #ifdef CONFIG_ARCH_TEGRA_132_SOC
59 { .compatible = "nvidia,tegra132-efuse", .data = &tegra124_fuse_soc },
61 #ifdef CONFIG_ARCH_TEGRA_124_SOC
62 { .compatible = "nvidia,tegra124-efuse", .data = &tegra124_fuse_soc },
64 #ifdef CONFIG_ARCH_TEGRA_114_SOC
65 { .compatible = "nvidia,tegra114-efuse", .data = &tegra114_fuse_soc },
67 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
68 { .compatible = "nvidia,tegra30-efuse", .data = &tegra30_fuse_soc },
70 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
71 { .compatible = "nvidia,tegra20-efuse", .data = &tegra20_fuse_soc },
76 static int tegra_fuse_read(void *priv, unsigned int offset, void *value,
79 unsigned int count = bytes / 4, i;
80 struct tegra_fuse *fuse = priv;
83 for (i = 0; i < count; i++)
84 buffer[i] = fuse->read(fuse, offset + i * 4);
89 static const struct nvmem_cell_info tegra_fuse_cells[] = {
91 .name = "tsensor-cpu1",
97 .name = "tsensor-cpu2",
103 .name = "tsensor-cpu0",
109 .name = "xusb-pad-calibration",
115 .name = "tsensor-cpu3",
121 .name = "sata-calibration",
127 .name = "tsensor-gpu",
133 .name = "tsensor-mem0",
139 .name = "tsensor-mem1",
145 .name = "tsensor-pllx",
151 .name = "tsensor-common",
157 .name = "tsensor-realignment",
163 .name = "gpu-calibration",
169 .name = "xusb-pad-calibration-ext",
177 static int tegra_fuse_probe(struct platform_device *pdev)
179 void __iomem *base = fuse->base;
180 struct nvmem_config nvmem;
181 struct resource *res;
184 /* take over the memory region from the early initialization */
185 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
186 fuse->phys = res->start;
187 fuse->base = devm_ioremap_resource(&pdev->dev, res);
188 if (IS_ERR(fuse->base)) {
189 err = PTR_ERR(fuse->base);
194 fuse->clk = devm_clk_get(&pdev->dev, "fuse");
195 if (IS_ERR(fuse->clk)) {
196 if (PTR_ERR(fuse->clk) != -EPROBE_DEFER)
197 dev_err(&pdev->dev, "failed to get FUSE clock: %ld",
201 return PTR_ERR(fuse->clk);
204 platform_set_drvdata(pdev, fuse);
205 fuse->dev = &pdev->dev;
207 if (fuse->soc->probe) {
208 err = fuse->soc->probe(fuse);
213 memset(&nvmem, 0, sizeof(nvmem));
214 nvmem.dev = &pdev->dev;
217 nvmem.owner = THIS_MODULE;
218 nvmem.cells = tegra_fuse_cells;
219 nvmem.ncells = ARRAY_SIZE(tegra_fuse_cells);
220 nvmem.type = NVMEM_TYPE_OTP;
221 nvmem.read_only = true;
222 nvmem.root_only = true;
223 nvmem.reg_read = tegra_fuse_read;
224 nvmem.size = fuse->soc->info->size;
229 fuse->nvmem = devm_nvmem_register(&pdev->dev, &nvmem);
230 if (IS_ERR(fuse->nvmem)) {
231 err = PTR_ERR(fuse->nvmem);
232 dev_err(&pdev->dev, "failed to register NVMEM device: %d\n",
237 /* release the early I/O memory mapping */
247 static struct platform_driver tegra_fuse_driver = {
249 .name = "tegra-fuse",
250 .of_match_table = tegra_fuse_match,
251 .suppress_bind_attrs = true,
253 .probe = tegra_fuse_probe,
255 builtin_platform_driver(tegra_fuse_driver);
257 bool __init tegra_fuse_read_spare(unsigned int spare)
259 unsigned int offset = fuse->soc->info->spare + spare * 4;
261 return fuse->read_early(fuse, offset) & 1;
264 u32 __init tegra_fuse_read_early(unsigned int offset)
266 return fuse->read_early(fuse, offset);
269 int tegra_fuse_readl(unsigned long offset, u32 *value)
271 if (!fuse->read || !fuse->clk)
272 return -EPROBE_DEFER;
274 if (IS_ERR(fuse->clk))
275 return PTR_ERR(fuse->clk);
277 *value = fuse->read(fuse, offset);
281 EXPORT_SYMBOL(tegra_fuse_readl);
283 static void tegra_enable_fuse_clk(void __iomem *base)
287 reg = readl_relaxed(base + 0x48);
289 writel(reg, base + 0x48);
292 * Enable FUSE clock. This needs to be hardcoded because the clock
293 * subsystem is not active during early boot.
295 reg = readl(base + 0x14);
297 writel(reg, base + 0x14);
300 struct device * __init tegra_soc_device_register(void)
302 struct soc_device_attribute *attr;
303 struct soc_device *dev;
305 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
309 attr->family = kasprintf(GFP_KERNEL, "Tegra");
310 attr->revision = kasprintf(GFP_KERNEL, "%d", tegra_sku_info.revision);
311 attr->soc_id = kasprintf(GFP_KERNEL, "%u", tegra_get_chip_id());
313 dev = soc_device_register(attr);
316 kfree(attr->revision);
319 return ERR_CAST(dev);
322 return soc_device_to_device(dev);
325 static int __init tegra_init_fuse(void)
327 const struct of_device_id *match;
328 struct device_node *np;
329 struct resource regs;
331 tegra_init_apbmisc();
333 np = of_find_matching_node_and_match(NULL, tegra_fuse_match, &match);
336 * Fall back to legacy initialization for 32-bit ARM only. All
337 * 64-bit ARM device tree files for Tegra are required to have
340 * This is for backwards-compatibility with old device trees
341 * that didn't contain a FUSE node.
343 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
344 u8 chip = tegra_get_chip_id();
346 regs.start = 0x7000f800;
347 regs.end = 0x7000fbff;
348 regs.flags = IORESOURCE_MEM;
351 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
353 fuse->soc = &tegra20_fuse_soc;
357 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
359 fuse->soc = &tegra30_fuse_soc;
363 #ifdef CONFIG_ARCH_TEGRA_114_SOC
365 fuse->soc = &tegra114_fuse_soc;
369 #ifdef CONFIG_ARCH_TEGRA_124_SOC
371 fuse->soc = &tegra124_fuse_soc;
376 pr_warn("Unsupported SoC: %02x\n", chip);
381 * At this point we're not running on Tegra, so play
382 * nice with multi-platform kernels.
388 * Extract information from the device tree if we've found a
391 if (of_address_to_resource(np, 0, ®s) < 0) {
392 pr_err("failed to get FUSE register\n");
396 fuse->soc = match->data;
399 np = of_find_matching_node(NULL, car_match);
401 void __iomem *base = of_iomap(np, 0);
403 tegra_enable_fuse_clk(base);
406 pr_err("failed to map clock registers\n");
411 fuse->base = ioremap(regs.start, resource_size(®s));
413 pr_err("failed to map FUSE registers\n");
417 fuse->soc->init(fuse);
419 pr_info("Tegra Revision: %s SKU: %d CPU Process: %d SoC Process: %d\n",
420 tegra_revision_name[tegra_sku_info.revision],
421 tegra_sku_info.sku_id, tegra_sku_info.cpu_process_id,
422 tegra_sku_info.soc_process_id);
423 pr_debug("Tegra CPU Speedo ID %d, SoC Speedo ID %d\n",
424 tegra_sku_info.cpu_speedo_id, tegra_sku_info.soc_speedo_id);
426 if (fuse->soc->lookups) {
427 size_t size = sizeof(*fuse->lookups) * fuse->soc->num_lookups;
429 fuse->lookups = kmemdup(fuse->soc->lookups, size, GFP_KERNEL);
433 nvmem_add_cell_lookups(fuse->lookups, fuse->soc->num_lookups);
438 early_initcall(tegra_init_fuse);
441 static int __init tegra_init_soc(void)
443 struct device_node *np;
446 /* make sure we're running on Tegra */
447 np = of_find_matching_node(NULL, tegra_fuse_match);
453 soc = tegra_soc_device_register();
455 pr_err("failed to register SoC device: %ld\n", PTR_ERR(soc));
461 device_initcall(tegra_init_soc);