2 * drivers/soc/tegra/pmc.c
4 * Copyright (c) 2010 Google, Inc
7 * Colin Cross <ccross@google.com>
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 #define pr_fmt(fmt) "tegra-pmc: " fmt
22 #include <linux/kernel.h>
23 #include <linux/clk.h>
24 #include <linux/clk/tegra.h>
25 #include <linux/debugfs.h>
26 #include <linux/delay.h>
27 #include <linux/err.h>
28 #include <linux/export.h>
29 #include <linux/init.h>
32 #include <linux/of_address.h>
33 #include <linux/platform_device.h>
34 #include <linux/reboot.h>
35 #include <linux/reset.h>
36 #include <linux/seq_file.h>
37 #include <linux/spinlock.h>
39 #include <soc/tegra/common.h>
40 #include <soc/tegra/fuse.h>
41 #include <soc/tegra/pmc.h>
44 #define PMC_CNTRL_SYSCLK_POLARITY (1 << 10) /* sys clk polarity */
45 #define PMC_CNTRL_SYSCLK_OE (1 << 11) /* system clock enable */
46 #define PMC_CNTRL_SIDE_EFFECT_LP0 (1 << 14) /* LP0 when CPU pwr gated */
47 #define PMC_CNTRL_CPU_PWRREQ_POLARITY (1 << 15) /* CPU pwr req polarity */
48 #define PMC_CNTRL_CPU_PWRREQ_OE (1 << 16) /* CPU pwr req enable */
49 #define PMC_CNTRL_INTR_POLARITY (1 << 17) /* inverts INTR polarity */
51 #define DPD_SAMPLE 0x020
52 #define DPD_SAMPLE_ENABLE (1 << 0)
53 #define DPD_SAMPLE_DISABLE (0 << 0)
55 #define PWRGATE_TOGGLE 0x30
56 #define PWRGATE_TOGGLE_START (1 << 8)
58 #define REMOVE_CLAMPING 0x34
60 #define PWRGATE_STATUS 0x38
62 #define PMC_SCRATCH0 0x50
63 #define PMC_SCRATCH0_MODE_RECOVERY (1 << 31)
64 #define PMC_SCRATCH0_MODE_BOOTLOADER (1 << 30)
65 #define PMC_SCRATCH0_MODE_RCM (1 << 1)
66 #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \
67 PMC_SCRATCH0_MODE_BOOTLOADER | \
68 PMC_SCRATCH0_MODE_RCM)
70 #define PMC_CPUPWRGOOD_TIMER 0xc8
71 #define PMC_CPUPWROFF_TIMER 0xcc
73 #define PMC_SCRATCH41 0x140
75 #define PMC_SENSOR_CTRL 0x1b0
76 #define PMC_SENSOR_CTRL_SCRATCH_WRITE (1 << 2)
77 #define PMC_SENSOR_CTRL_ENABLE_RST (1 << 1)
79 #define IO_DPD_REQ 0x1b8
80 #define IO_DPD_REQ_CODE_IDLE (0 << 30)
81 #define IO_DPD_REQ_CODE_OFF (1 << 30)
82 #define IO_DPD_REQ_CODE_ON (2 << 30)
83 #define IO_DPD_REQ_CODE_MASK (3 << 30)
85 #define IO_DPD_STATUS 0x1bc
86 #define IO_DPD2_REQ 0x1c0
87 #define IO_DPD2_STATUS 0x1c4
88 #define SEL_DPD_TIM 0x1c8
90 #define PMC_SCRATCH54 0x258
91 #define PMC_SCRATCH54_DATA_SHIFT 8
92 #define PMC_SCRATCH54_ADDR_SHIFT 0
94 #define PMC_SCRATCH55 0x25c
95 #define PMC_SCRATCH55_RESET_TEGRA (1 << 31)
96 #define PMC_SCRATCH55_CNTRL_ID_SHIFT 27
97 #define PMC_SCRATCH55_PINMUX_SHIFT 24
98 #define PMC_SCRATCH55_16BITOP (1 << 15)
99 #define PMC_SCRATCH55_CHECKSUM_SHIFT 16
100 #define PMC_SCRATCH55_I2CSLV1_SHIFT 0
102 #define GPU_RG_CNTRL 0x2d4
104 struct tegra_pmc_soc {
105 unsigned int num_powergates;
106 const char *const *powergates;
107 unsigned int num_cpu_powergates;
108 const u8 *cpu_powergates;
110 bool has_tsense_reset;
115 * struct tegra_pmc - NVIDIA Tegra PMC
116 * @base: pointer to I/O remapped register region
117 * @clk: pointer to pclk clock
118 * @rate: currently configured rate of pclk
119 * @suspend_mode: lowest suspend mode available
120 * @cpu_good_time: CPU power good time (in microseconds)
121 * @cpu_off_time: CPU power off time (in microsecends)
122 * @core_osc_time: core power good OSC time (in microseconds)
123 * @core_pmu_time: core power good PMU time (in microseconds)
124 * @core_off_time: core power off time (in microseconds)
125 * @corereq_high: core power request is active-high
126 * @sysclkreq_high: system clock request is active-high
127 * @combined_req: combined power request for CPU & core
128 * @cpu_pwr_good_en: CPU power good signal is enabled
129 * @lp0_vec_phys: physical base address of the LP0 warm boot code
130 * @lp0_vec_size: size of the LP0 warm boot code
131 * @powergates_lock: mutex for power gate register access
138 const struct tegra_pmc_soc *soc;
142 enum tegra_suspend_mode suspend_mode;
151 bool cpu_pwr_good_en;
155 struct mutex powergates_lock;
158 static struct tegra_pmc *pmc = &(struct tegra_pmc) {
160 .suspend_mode = TEGRA_SUSPEND_NONE,
163 static u32 tegra_pmc_readl(unsigned long offset)
165 return readl(pmc->base + offset);
168 static void tegra_pmc_writel(u32 value, unsigned long offset)
170 writel(value, pmc->base + offset);
174 * tegra_powergate_set() - set the state of a partition
176 * @new_state: new state of the partition
178 static int tegra_powergate_set(int id, bool new_state)
182 mutex_lock(&pmc->powergates_lock);
184 status = tegra_pmc_readl(PWRGATE_STATUS) & (1 << id);
186 if (status == new_state) {
187 mutex_unlock(&pmc->powergates_lock);
191 tegra_pmc_writel(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
193 mutex_unlock(&pmc->powergates_lock);
199 * tegra_powergate_power_on() - power on partition
202 int tegra_powergate_power_on(int id)
204 if (!pmc->soc || id < 0 || id >= pmc->soc->num_powergates)
207 return tegra_powergate_set(id, true);
211 * tegra_powergate_power_off() - power off partition
214 int tegra_powergate_power_off(int id)
216 if (!pmc->soc || id < 0 || id >= pmc->soc->num_powergates)
219 return tegra_powergate_set(id, false);
221 EXPORT_SYMBOL(tegra_powergate_power_off);
224 * tegra_powergate_is_powered() - check if partition is powered
227 int tegra_powergate_is_powered(int id)
231 if (!pmc->soc || id < 0 || id >= pmc->soc->num_powergates)
234 status = tegra_pmc_readl(PWRGATE_STATUS) & (1 << id);
239 * tegra_powergate_remove_clamping() - remove power clamps for partition
242 int tegra_powergate_remove_clamping(int id)
246 if (!pmc->soc || id < 0 || id >= pmc->soc->num_powergates)
250 * On Tegra124 and later, the clamps for the GPU are controlled by a
251 * separate register (with different semantics).
253 if (id == TEGRA_POWERGATE_3D) {
254 if (pmc->soc->has_gpu_clamps) {
255 tegra_pmc_writel(0, GPU_RG_CNTRL);
261 * Tegra 2 has a bug where PCIE and VDE clamping masks are
262 * swapped relatively to the partition ids
264 if (id == TEGRA_POWERGATE_VDEC)
265 mask = (1 << TEGRA_POWERGATE_PCIE);
266 else if (id == TEGRA_POWERGATE_PCIE)
267 mask = (1 << TEGRA_POWERGATE_VDEC);
271 tegra_pmc_writel(mask, REMOVE_CLAMPING);
275 EXPORT_SYMBOL(tegra_powergate_remove_clamping);
278 * tegra_powergate_sequence_power_up() - power up partition
280 * @clk: clock for partition
281 * @rst: reset for partition
283 * Must be called with clk disabled, and returns with clk enabled.
285 int tegra_powergate_sequence_power_up(int id, struct clk *clk,
286 struct reset_control *rst)
290 reset_control_assert(rst);
292 ret = tegra_powergate_power_on(id);
296 ret = clk_prepare_enable(clk);
300 usleep_range(10, 20);
302 ret = tegra_powergate_remove_clamping(id);
306 usleep_range(10, 20);
307 reset_control_deassert(rst);
312 clk_disable_unprepare(clk);
314 tegra_powergate_power_off(id);
318 EXPORT_SYMBOL(tegra_powergate_sequence_power_up);
322 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID
323 * @cpuid: CPU partition ID
325 * Returns the partition ID corresponding to the CPU partition ID or a
326 * negative error code on failure.
328 static int tegra_get_cpu_powergate_id(int cpuid)
330 if (pmc->soc && cpuid > 0 && cpuid < pmc->soc->num_cpu_powergates)
331 return pmc->soc->cpu_powergates[cpuid];
337 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered
338 * @cpuid: CPU partition ID
340 bool tegra_pmc_cpu_is_powered(int cpuid)
344 id = tegra_get_cpu_powergate_id(cpuid);
348 return tegra_powergate_is_powered(id);
352 * tegra_pmc_cpu_power_on() - power on CPU partition
353 * @cpuid: CPU partition ID
355 int tegra_pmc_cpu_power_on(int cpuid)
359 id = tegra_get_cpu_powergate_id(cpuid);
363 return tegra_powergate_set(id, true);
367 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition
368 * @cpuid: CPU partition ID
370 int tegra_pmc_cpu_remove_clamping(int cpuid)
374 id = tegra_get_cpu_powergate_id(cpuid);
378 return tegra_powergate_remove_clamping(id);
380 #endif /* CONFIG_SMP */
382 static int tegra_pmc_restart_notify(struct notifier_block *this,
383 unsigned long action, void *data)
385 const char *cmd = data;
388 value = tegra_pmc_readl(PMC_SCRATCH0);
389 value &= ~PMC_SCRATCH0_MODE_MASK;
392 if (strcmp(cmd, "recovery") == 0)
393 value |= PMC_SCRATCH0_MODE_RECOVERY;
395 if (strcmp(cmd, "bootloader") == 0)
396 value |= PMC_SCRATCH0_MODE_BOOTLOADER;
398 if (strcmp(cmd, "forced-recovery") == 0)
399 value |= PMC_SCRATCH0_MODE_RCM;
402 tegra_pmc_writel(value, PMC_SCRATCH0);
404 value = tegra_pmc_readl(0);
406 tegra_pmc_writel(value, 0);
411 static struct notifier_block tegra_pmc_restart_handler = {
412 .notifier_call = tegra_pmc_restart_notify,
416 static int powergate_show(struct seq_file *s, void *data)
420 seq_printf(s, " powergate powered\n");
421 seq_printf(s, "------------------\n");
423 for (i = 0; i < pmc->soc->num_powergates; i++) {
424 if (!pmc->soc->powergates[i])
427 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i],
428 tegra_powergate_is_powered(i) ? "yes" : "no");
434 static int powergate_open(struct inode *inode, struct file *file)
436 return single_open(file, powergate_show, inode->i_private);
439 static const struct file_operations powergate_fops = {
440 .open = powergate_open,
443 .release = single_release,
446 static int tegra_powergate_debugfs_init(void)
450 d = debugfs_create_file("powergate", S_IRUGO, NULL, NULL,
458 static int tegra_io_rail_prepare(int id, unsigned long *request,
459 unsigned long *status, unsigned int *bit)
461 unsigned long rate, value;
467 * There are two sets of 30 bits to select IO rails, but bits 30 and
468 * 31 are control bits rather than IO rail selection bits.
470 if (id > 63 || *bit == 30 || *bit == 31)
474 *status = IO_DPD_STATUS;
475 *request = IO_DPD_REQ;
477 *status = IO_DPD2_STATUS;
478 *request = IO_DPD2_REQ;
481 clk = clk_get_sys(NULL, "pclk");
485 rate = clk_get_rate(clk);
488 tegra_pmc_writel(DPD_SAMPLE_ENABLE, DPD_SAMPLE);
490 /* must be at least 200 ns, in APB (PCLK) clock cycles */
491 value = DIV_ROUND_UP(1000000000, rate);
492 value = DIV_ROUND_UP(200, value);
493 tegra_pmc_writel(value, SEL_DPD_TIM);
498 static int tegra_io_rail_poll(unsigned long offset, unsigned long mask,
499 unsigned long val, unsigned long timeout)
503 timeout = jiffies + msecs_to_jiffies(timeout);
505 while (time_after(timeout, jiffies)) {
506 value = tegra_pmc_readl(offset);
507 if ((value & mask) == val)
510 usleep_range(250, 1000);
516 static void tegra_io_rail_unprepare(void)
518 tegra_pmc_writel(DPD_SAMPLE_DISABLE, DPD_SAMPLE);
521 int tegra_io_rail_power_on(int id)
523 unsigned long request, status, value;
524 unsigned int bit, mask;
527 err = tegra_io_rail_prepare(id, &request, &status, &bit);
533 value = tegra_pmc_readl(request);
535 value &= ~IO_DPD_REQ_CODE_MASK;
536 value |= IO_DPD_REQ_CODE_OFF;
537 tegra_pmc_writel(value, request);
539 err = tegra_io_rail_poll(status, mask, 0, 250);
543 tegra_io_rail_unprepare();
547 EXPORT_SYMBOL(tegra_io_rail_power_on);
549 int tegra_io_rail_power_off(int id)
551 unsigned long request, status, value;
552 unsigned int bit, mask;
555 err = tegra_io_rail_prepare(id, &request, &status, &bit);
561 value = tegra_pmc_readl(request);
563 value &= ~IO_DPD_REQ_CODE_MASK;
564 value |= IO_DPD_REQ_CODE_ON;
565 tegra_pmc_writel(value, request);
567 err = tegra_io_rail_poll(status, mask, mask, 250);
571 tegra_io_rail_unprepare();
575 EXPORT_SYMBOL(tegra_io_rail_power_off);
577 #ifdef CONFIG_PM_SLEEP
578 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
580 return pmc->suspend_mode;
583 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)
585 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE)
588 pmc->suspend_mode = mode;
591 void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode)
593 unsigned long long rate = 0;
597 case TEGRA_SUSPEND_LP1:
601 case TEGRA_SUSPEND_LP2:
602 rate = clk_get_rate(pmc->clk);
609 if (WARN_ON_ONCE(rate == 0))
612 if (rate != pmc->rate) {
615 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1;
616 do_div(ticks, USEC_PER_SEC);
617 tegra_pmc_writel(ticks, PMC_CPUPWRGOOD_TIMER);
619 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1;
620 do_div(ticks, USEC_PER_SEC);
621 tegra_pmc_writel(ticks, PMC_CPUPWROFF_TIMER);
628 value = tegra_pmc_readl(PMC_CNTRL);
629 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0;
630 value |= PMC_CNTRL_CPU_PWRREQ_OE;
631 tegra_pmc_writel(value, PMC_CNTRL);
635 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np)
637 u32 value, values[2];
639 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) {
643 pmc->suspend_mode = TEGRA_SUSPEND_LP0;
647 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
651 pmc->suspend_mode = TEGRA_SUSPEND_LP2;
655 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
660 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode);
662 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value))
663 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
665 pmc->cpu_good_time = value;
667 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value))
668 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
670 pmc->cpu_off_time = value;
672 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time",
673 values, ARRAY_SIZE(values)))
674 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
676 pmc->core_osc_time = values[0];
677 pmc->core_pmu_time = values[1];
679 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value))
680 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
682 pmc->core_off_time = value;
684 pmc->corereq_high = of_property_read_bool(np,
685 "nvidia,core-power-req-active-high");
687 pmc->sysclkreq_high = of_property_read_bool(np,
688 "nvidia,sys-clock-req-active-high");
690 pmc->combined_req = of_property_read_bool(np,
691 "nvidia,combined-power-req");
693 pmc->cpu_pwr_good_en = of_property_read_bool(np,
694 "nvidia,cpu-pwr-good-en");
696 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values,
698 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0)
699 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
701 pmc->lp0_vec_phys = values[0];
702 pmc->lp0_vec_size = values[1];
707 static void tegra_pmc_init(struct tegra_pmc *pmc)
711 /* Always enable CPU power request */
712 value = tegra_pmc_readl(PMC_CNTRL);
713 value |= PMC_CNTRL_CPU_PWRREQ_OE;
714 tegra_pmc_writel(value, PMC_CNTRL);
716 value = tegra_pmc_readl(PMC_CNTRL);
718 if (pmc->sysclkreq_high)
719 value &= ~PMC_CNTRL_SYSCLK_POLARITY;
721 value |= PMC_CNTRL_SYSCLK_POLARITY;
723 /* configure the output polarity while the request is tristated */
724 tegra_pmc_writel(value, PMC_CNTRL);
726 /* now enable the request */
727 value = tegra_pmc_readl(PMC_CNTRL);
728 value |= PMC_CNTRL_SYSCLK_OE;
729 tegra_pmc_writel(value, PMC_CNTRL);
732 void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc)
734 static const char disabled[] = "emergency thermal reset disabled";
735 u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux;
736 struct device *dev = pmc->dev;
737 struct device_node *np;
740 if (!pmc->soc->has_tsense_reset)
743 np = of_find_node_by_name(pmc->dev->of_node, "i2c-thermtrip");
745 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled);
749 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) {
750 dev_err(dev, "I2C controller ID missing, %s.\n", disabled);
754 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) {
755 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled);
759 if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) {
760 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled);
764 if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) {
765 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled);
769 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux))
772 value = tegra_pmc_readl(PMC_SENSOR_CTRL);
773 value |= PMC_SENSOR_CTRL_SCRATCH_WRITE;
774 tegra_pmc_writel(value, PMC_SENSOR_CTRL);
776 value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) |
777 (reg_addr << PMC_SCRATCH54_ADDR_SHIFT);
778 tegra_pmc_writel(value, PMC_SCRATCH54);
780 value = PMC_SCRATCH55_RESET_TEGRA;
781 value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT;
782 value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT;
783 value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT;
786 * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will
787 * contain the checksum and are currently zero, so they are not added.
789 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff)
790 + ((value >> 24) & 0xff);
792 checksum = 0x100 - checksum;
794 value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT;
796 tegra_pmc_writel(value, PMC_SCRATCH55);
798 value = tegra_pmc_readl(PMC_SENSOR_CTRL);
799 value |= PMC_SENSOR_CTRL_ENABLE_RST;
800 tegra_pmc_writel(value, PMC_SENSOR_CTRL);
802 dev_info(pmc->dev, "emergency thermal reset enabled\n");
808 static int tegra_pmc_probe(struct platform_device *pdev)
810 void __iomem *base = pmc->base;
811 struct resource *res;
814 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node);
818 /* take over the memory region from the early initialization */
819 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
820 pmc->base = devm_ioremap_resource(&pdev->dev, res);
821 if (IS_ERR(pmc->base))
822 return PTR_ERR(pmc->base);
826 pmc->clk = devm_clk_get(&pdev->dev, "pclk");
827 if (IS_ERR(pmc->clk)) {
828 err = PTR_ERR(pmc->clk);
829 dev_err(&pdev->dev, "failed to get pclk: %d\n", err);
833 pmc->dev = &pdev->dev;
837 tegra_pmc_init_tsense_reset(pmc);
839 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
840 err = tegra_powergate_debugfs_init();
845 err = register_restart_handler(&tegra_pmc_restart_handler);
847 dev_err(&pdev->dev, "unable to register restart handler, %d\n",
855 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
856 static int tegra_pmc_suspend(struct device *dev)
858 tegra_pmc_writel(virt_to_phys(tegra_resume), PMC_SCRATCH41);
863 static int tegra_pmc_resume(struct device *dev)
865 tegra_pmc_writel(0x0, PMC_SCRATCH41);
870 static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume);
874 static const char * const tegra20_powergates[] = {
875 [TEGRA_POWERGATE_CPU] = "cpu",
876 [TEGRA_POWERGATE_3D] = "3d",
877 [TEGRA_POWERGATE_VENC] = "venc",
878 [TEGRA_POWERGATE_VDEC] = "vdec",
879 [TEGRA_POWERGATE_PCIE] = "pcie",
880 [TEGRA_POWERGATE_L2] = "l2",
881 [TEGRA_POWERGATE_MPE] = "mpe",
884 static const struct tegra_pmc_soc tegra20_pmc_soc = {
885 .num_powergates = ARRAY_SIZE(tegra20_powergates),
886 .powergates = tegra20_powergates,
887 .num_cpu_powergates = 0,
888 .cpu_powergates = NULL,
889 .has_tsense_reset = false,
890 .has_gpu_clamps = false,
893 static const char * const tegra30_powergates[] = {
894 [TEGRA_POWERGATE_CPU] = "cpu0",
895 [TEGRA_POWERGATE_3D] = "3d0",
896 [TEGRA_POWERGATE_VENC] = "venc",
897 [TEGRA_POWERGATE_VDEC] = "vdec",
898 [TEGRA_POWERGATE_PCIE] = "pcie",
899 [TEGRA_POWERGATE_L2] = "l2",
900 [TEGRA_POWERGATE_MPE] = "mpe",
901 [TEGRA_POWERGATE_HEG] = "heg",
902 [TEGRA_POWERGATE_SATA] = "sata",
903 [TEGRA_POWERGATE_CPU1] = "cpu1",
904 [TEGRA_POWERGATE_CPU2] = "cpu2",
905 [TEGRA_POWERGATE_CPU3] = "cpu3",
906 [TEGRA_POWERGATE_CELP] = "celp",
907 [TEGRA_POWERGATE_3D1] = "3d1",
910 static const u8 tegra30_cpu_powergates[] = {
912 TEGRA_POWERGATE_CPU1,
913 TEGRA_POWERGATE_CPU2,
914 TEGRA_POWERGATE_CPU3,
917 static const struct tegra_pmc_soc tegra30_pmc_soc = {
918 .num_powergates = ARRAY_SIZE(tegra30_powergates),
919 .powergates = tegra30_powergates,
920 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates),
921 .cpu_powergates = tegra30_cpu_powergates,
922 .has_tsense_reset = true,
923 .has_gpu_clamps = false,
926 static const char * const tegra114_powergates[] = {
927 [TEGRA_POWERGATE_CPU] = "crail",
928 [TEGRA_POWERGATE_3D] = "3d",
929 [TEGRA_POWERGATE_VENC] = "venc",
930 [TEGRA_POWERGATE_VDEC] = "vdec",
931 [TEGRA_POWERGATE_MPE] = "mpe",
932 [TEGRA_POWERGATE_HEG] = "heg",
933 [TEGRA_POWERGATE_CPU1] = "cpu1",
934 [TEGRA_POWERGATE_CPU2] = "cpu2",
935 [TEGRA_POWERGATE_CPU3] = "cpu3",
936 [TEGRA_POWERGATE_CELP] = "celp",
937 [TEGRA_POWERGATE_CPU0] = "cpu0",
938 [TEGRA_POWERGATE_C0NC] = "c0nc",
939 [TEGRA_POWERGATE_C1NC] = "c1nc",
940 [TEGRA_POWERGATE_DIS] = "dis",
941 [TEGRA_POWERGATE_DISB] = "disb",
942 [TEGRA_POWERGATE_XUSBA] = "xusba",
943 [TEGRA_POWERGATE_XUSBB] = "xusbb",
944 [TEGRA_POWERGATE_XUSBC] = "xusbc",
947 static const u8 tegra114_cpu_powergates[] = {
948 TEGRA_POWERGATE_CPU0,
949 TEGRA_POWERGATE_CPU1,
950 TEGRA_POWERGATE_CPU2,
951 TEGRA_POWERGATE_CPU3,
954 static const struct tegra_pmc_soc tegra114_pmc_soc = {
955 .num_powergates = ARRAY_SIZE(tegra114_powergates),
956 .powergates = tegra114_powergates,
957 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates),
958 .cpu_powergates = tegra114_cpu_powergates,
959 .has_tsense_reset = true,
960 .has_gpu_clamps = false,
963 static const char * const tegra124_powergates[] = {
964 [TEGRA_POWERGATE_CPU] = "crail",
965 [TEGRA_POWERGATE_3D] = "3d",
966 [TEGRA_POWERGATE_VENC] = "venc",
967 [TEGRA_POWERGATE_PCIE] = "pcie",
968 [TEGRA_POWERGATE_VDEC] = "vdec",
969 [TEGRA_POWERGATE_L2] = "l2",
970 [TEGRA_POWERGATE_MPE] = "mpe",
971 [TEGRA_POWERGATE_HEG] = "heg",
972 [TEGRA_POWERGATE_SATA] = "sata",
973 [TEGRA_POWERGATE_CPU1] = "cpu1",
974 [TEGRA_POWERGATE_CPU2] = "cpu2",
975 [TEGRA_POWERGATE_CPU3] = "cpu3",
976 [TEGRA_POWERGATE_CELP] = "celp",
977 [TEGRA_POWERGATE_CPU0] = "cpu0",
978 [TEGRA_POWERGATE_C0NC] = "c0nc",
979 [TEGRA_POWERGATE_C1NC] = "c1nc",
980 [TEGRA_POWERGATE_SOR] = "sor",
981 [TEGRA_POWERGATE_DIS] = "dis",
982 [TEGRA_POWERGATE_DISB] = "disb",
983 [TEGRA_POWERGATE_XUSBA] = "xusba",
984 [TEGRA_POWERGATE_XUSBB] = "xusbb",
985 [TEGRA_POWERGATE_XUSBC] = "xusbc",
986 [TEGRA_POWERGATE_VIC] = "vic",
987 [TEGRA_POWERGATE_IRAM] = "iram",
990 static const u8 tegra124_cpu_powergates[] = {
991 TEGRA_POWERGATE_CPU0,
992 TEGRA_POWERGATE_CPU1,
993 TEGRA_POWERGATE_CPU2,
994 TEGRA_POWERGATE_CPU3,
997 static const struct tegra_pmc_soc tegra124_pmc_soc = {
998 .num_powergates = ARRAY_SIZE(tegra124_powergates),
999 .powergates = tegra124_powergates,
1000 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates),
1001 .cpu_powergates = tegra124_cpu_powergates,
1002 .has_tsense_reset = true,
1003 .has_gpu_clamps = true,
1006 static const char * const tegra210_powergates[] = {
1007 [TEGRA_POWERGATE_CPU] = "crail",
1008 [TEGRA_POWERGATE_3D] = "3d",
1009 [TEGRA_POWERGATE_VENC] = "venc",
1010 [TEGRA_POWERGATE_PCIE] = "pcie",
1011 [TEGRA_POWERGATE_L2] = "l2",
1012 [TEGRA_POWERGATE_MPE] = "mpe",
1013 [TEGRA_POWERGATE_HEG] = "heg",
1014 [TEGRA_POWERGATE_SATA] = "sata",
1015 [TEGRA_POWERGATE_CPU1] = "cpu1",
1016 [TEGRA_POWERGATE_CPU2] = "cpu2",
1017 [TEGRA_POWERGATE_CPU3] = "cpu3",
1018 [TEGRA_POWERGATE_CELP] = "celp",
1019 [TEGRA_POWERGATE_CPU0] = "cpu0",
1020 [TEGRA_POWERGATE_C0NC] = "c0nc",
1021 [TEGRA_POWERGATE_C1NC] = "c1nc",
1022 [TEGRA_POWERGATE_SOR] = "sor",
1023 [TEGRA_POWERGATE_DIS] = "dis",
1024 [TEGRA_POWERGATE_DISB] = "disb",
1025 [TEGRA_POWERGATE_XUSBA] = "xusba",
1026 [TEGRA_POWERGATE_XUSBB] = "xusbb",
1027 [TEGRA_POWERGATE_XUSBC] = "xusbc",
1028 [TEGRA_POWERGATE_VIC] = "vic",
1029 [TEGRA_POWERGATE_IRAM] = "iram",
1030 [TEGRA_POWERGATE_NVDEC] = "nvdec",
1031 [TEGRA_POWERGATE_NVJPG] = "nvjpg",
1032 [TEGRA_POWERGATE_AUD] = "aud",
1033 [TEGRA_POWERGATE_DFD] = "dfd",
1034 [TEGRA_POWERGATE_VE2] = "ve2",
1037 static const u8 tegra210_cpu_powergates[] = {
1038 TEGRA_POWERGATE_CPU0,
1039 TEGRA_POWERGATE_CPU1,
1040 TEGRA_POWERGATE_CPU2,
1041 TEGRA_POWERGATE_CPU3,
1044 static const struct tegra_pmc_soc tegra210_pmc_soc = {
1045 .num_powergates = ARRAY_SIZE(tegra210_powergates),
1046 .powergates = tegra210_powergates,
1047 .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates),
1048 .cpu_powergates = tegra210_cpu_powergates,
1049 .has_tsense_reset = true,
1050 .has_gpu_clamps = true,
1053 static const struct of_device_id tegra_pmc_match[] = {
1054 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc },
1055 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc },
1056 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
1057 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
1058 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },
1059 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc },
1063 static struct platform_driver tegra_pmc_driver = {
1065 .name = "tegra-pmc",
1066 .suppress_bind_attrs = true,
1067 .of_match_table = tegra_pmc_match,
1068 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
1069 .pm = &tegra_pmc_pm_ops,
1072 .probe = tegra_pmc_probe,
1074 builtin_platform_driver(tegra_pmc_driver);
1077 * Early initialization to allow access to registers in the very early boot
1080 static int __init tegra_pmc_early_init(void)
1082 const struct of_device_id *match;
1083 struct device_node *np;
1084 struct resource regs;
1088 np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match);
1091 * Fall back to legacy initialization for 32-bit ARM only. All
1092 * 64-bit ARM device tree files for Tegra are required to have
1095 * This is for backwards-compatibility with old device trees
1096 * that didn't contain a PMC node. Note that in this case the
1097 * SoC data can't be matched and therefore powergating is
1100 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
1101 pr_warn("DT node not found, powergating disabled\n");
1103 regs.start = 0x7000e400;
1104 regs.end = 0x7000e7ff;
1105 regs.flags = IORESOURCE_MEM;
1107 pr_warn("Using memory region %pR\n", ®s);
1110 * At this point we're not running on Tegra, so play
1111 * nice with multi-platform kernels.
1117 * Extract information from the device tree if we've found a
1120 if (of_address_to_resource(np, 0, ®s) < 0) {
1121 pr_err("failed to get PMC registers\n");
1125 pmc->soc = match->data;
1128 pmc->base = ioremap_nocache(regs.start, resource_size(®s));
1130 pr_err("failed to map PMC registers\n");
1134 mutex_init(&pmc->powergates_lock);
1137 * Invert the interrupt polarity if a PMC device tree node exists and
1138 * contains the nvidia,invert-interrupt property.
1140 invert = of_property_read_bool(np, "nvidia,invert-interrupt");
1142 value = tegra_pmc_readl(PMC_CNTRL);
1145 value |= PMC_CNTRL_INTR_POLARITY;
1147 value &= ~PMC_CNTRL_INTR_POLARITY;
1149 tegra_pmc_writel(value, PMC_CNTRL);
1153 early_initcall(tegra_pmc_early_init);