drivers/soundwire/swr-wcd-ctrl.c

   1 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12
  13 #include <linux/irq.h>
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/slab.h>
  17 #include <linux/io.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/soundwire/soundwire.h>
  21 #include <linux/soundwire/swr-wcd.h>
  22 #include <linux/delay.h>
  23 #include <linux/kthread.h>
  24 #include <linux/clk.h>
  25 #include <linux/pm_runtime.h>
  26 #include <linux/of.h>
  27 #include <linux/debugfs.h>
  28 #include <linux/uaccess.h>
  29 #include "swrm_registers.h"
  30 #include "swr-wcd-ctrl.h"
  31
  32 #define SWR_BROADCAST_CMD_ID            0x0F
  33 #define SWR_AUTO_SUSPEND_DELAY          3 /* delay in sec */
  34 #define SWR_DEV_ID_MASK                 0xFFFFFFFF
  35 #define SWR_REG_VAL_PACK(data, dev, id, reg)    \
  36                         ((reg) | ((id) << 16) | ((dev) << 20) | ((data) << 24))
  37
  38 /* pm runtime auto suspend timer in msecs */
  39 static int auto_suspend_timer = SWR_AUTO_SUSPEND_DELAY * 1000;
  40 module_param(auto_suspend_timer, int,
  41                 S_IRUGO | S_IWUSR | S_IWGRP);
  42 MODULE_PARM_DESC(auto_suspend_timer, "timer for auto suspend");
  43
  44 static u8 mstr_ports[] = {100, 101, 102, 103, 104, 105, 106, 107};
  45 static u8 mstr_port_type[] = {SWR_DAC_PORT, SWR_COMP_PORT, SWR_BOOST_PORT,
  46                               SWR_DAC_PORT, SWR_COMP_PORT, SWR_BOOST_PORT,
  47                               SWR_VISENSE_PORT, SWR_VISENSE_PORT};
  48
  49 struct usecase uc[] = {
  50         {0, 0, 0},              /* UC0: no ports */
  51         {1, 1, 2400},           /* UC1: Spkr */
  52         {1, 4, 600},            /* UC2: Compander */
  53         {1, 2, 300},            /* UC3: Smart Boost */
  54         {1, 2, 1200},           /* UC4: VI Sense */
  55         {4, 9, 4500},           /* UC5: Spkr + Comp + SB + VI */
  56         {8, 18, 9000},          /* UC6: 2*(Spkr + Comp + SB + VI) */
  57         {2, 2, 4800},           /* UC7: 2*Spkr */
  58         {2, 5, 3000},           /* UC8: Spkr + Comp */
  59         {4, 10, 6000},          /* UC9: 2*(Spkr + Comp) */
  60         {3, 7, 3300},           /* UC10: Spkr + Comp + SB */
  61         {6, 14, 6600},          /* UC11: 2*(Spkr + Comp + SB) */
  62         {2, 3, 2700},           /* UC12: Spkr + SB */
  63         {4, 6, 5400},           /* UC13: 2*(Spkr + SB) */
  64         {3, 5, 3900},           /* UC14: Spkr + SB + VI */
  65         {6, 10, 7800},          /* UC15: 2*(Spkr + SB + VI) */
  66         {2, 3, 3600},           /* UC16: Spkr + VI */
  67         {4, 6, 7200},           /* UC17: 2*(Spkr + VI) */
  68         {3, 7, 4200},           /* UC18: Spkr + Comp + VI */
  69         {6, 14, 8400},          /* UC19: 2*(Spkr + Comp + VI) */
  70 };
  71 #define MAX_USECASE     ARRAY_SIZE(uc)
  72
  73 struct port_params pp[MAX_USECASE][SWR_MSTR_PORT_LEN] = {
  74         /* UC 0 */
  75         {
  76                 {0, 0, 0},
  77         },
  78         /* UC 1 */
  79         {
  80                 {7, 1, 0},
  81         },
  82         /* UC 2 */
  83         {
  84                 {31, 2, 0},
  85         },
  86         /* UC 3 */
  87         {
  88                 {63, 12, 31},
  89         },
  90         /* UC 4 */
  91         {
  92                 {15, 7, 0},
  93         },
  94         /* UC 5 */
  95         {
  96                 {7, 1, 0},
  97                 {31, 2, 0},
  98                 {63, 12, 31},
  99                 {15, 7, 0},
 100         },
 101         /* UC 6 */
 102         {
 103                 {7, 1, 0},
 104                 {31, 2, 0},
 105                 {63, 12, 31},
 106                 {15, 7, 0},
 107                 {7, 6, 0},
 108                 {31, 18, 0},
 109                 {63, 13, 31},
 110                 {15, 10, 0},
 111         },
 112         /* UC 7 */
 113         {
 114                 {7, 1, 0},
 115                 {7, 6, 0},
 116
 117         },
 118         /* UC 8 */
 119         {
 120                 {7, 1, 0},
 121                 {31, 2, 0},
 122         },
 123         /* UC 9 */
 124         {
 125                 {7, 1, 0},
 126                 {31, 2, 0},
 127                 {7, 6, 0},
 128                 {31, 18, 0},
 129         },
 130         /* UC 10 */
 131         {
 132                 {7, 1, 0},
 133                 {31, 2, 0},
 134                 {63, 12, 31},
 135         },
 136         /* UC 11 */
 137         {
 138                 {7, 1, 0},
 139                 {31, 2, 0},
 140                 {63, 12, 31},
 141                 {7, 6, 0},
 142                 {31, 18, 0},
 143                 {63, 13, 31},
 144         },
 145         /* UC 12 */
 146         {
 147                 {7, 1, 0},
 148                 {63, 12, 31},
 149         },
 150         /* UC 13 */
 151         {
 152                 {7, 1, 0},
 153                 {63, 12, 31},
 154                 {7, 6, 0},
 155                 {63, 13, 31},
 156         },
 157         /* UC 14 */
 158         {
 159                 {7, 1, 0},
 160                 {63, 12, 31},
 161                 {15, 7, 0},
 162         },
 163         /* UC 15 */
 164         {
 165                 {7, 1, 0},
 166                 {63, 12, 31},
 167                 {15, 7, 0},
 168                 {7, 6, 0},
 169                 {63, 13, 31},
 170                 {15, 10, 0},
 171         },
 172         /* UC 16 */
 173         {
 174                 {7, 1, 0},
 175                 {15, 7, 0},
 176         },
 177         /* UC 17 */
 178         {
 179                 {7, 1, 0},
 180                 {15, 7, 0},
 181                 {7, 6, 0},
 182                 {15, 10, 0},
 183         },
 184         /* UC 18 */
 185         {
 186                 {7, 1, 0},
 187                 {31, 2, 0},
 188                 {15, 7, 0},
 189         },
 190         /* UC 19 */
 191         {
 192                 {7, 1, 0},
 193                 {31, 2, 0},
 194                 {15, 7, 0},
 195                 {7, 6, 0},
 196                 {31, 18, 0},
 197                 {15, 10, 0},
 198         },
 199 };
 200
 201 enum {
 202         SWR_NOT_PRESENT, /* Device is detached/not present on the bus */
 203         SWR_ATTACHED_OK, /* Device is attached */
 204         SWR_ALERT,       /* Device alters master for any interrupts */
 205         SWR_RESERVED,    /* Reserved */
 206 };
 207
 208 #define SWRM_MAX_PORT_REG    40
 209 #define SWRM_MAX_INIT_REG    8
 210
 211 #define SWR_MSTR_MAX_REG_ADDR   0x1740
 212 #define SWR_MSTR_START_REG_ADDR 0x00
 213 #define SWR_MSTR_MAX_BUF_LEN     32
 214 #define BYTES_PER_LINE          12
 215 #define SWR_MSTR_RD_BUF_LEN      8
 216 #define SWR_MSTR_WR_BUF_LEN      32
 217
 218 static void swrm_copy_data_port_config(struct swr_master *master,
 219                                        u8 inactive_bank);
 220 static struct swr_mstr_ctrl *dbgswrm;
 221 static struct dentry *debugfs_swrm_dent;
 222 static struct dentry *debugfs_peek;
 223 static struct dentry *debugfs_poke;
 224 static struct dentry *debugfs_reg_dump;
 225 static unsigned int read_data;
 226
 227
 228 static bool swrm_is_msm_variant(int val)
 229 {
 230         return (val == SWRM_VERSION_1_3);
 231 }
 232
 233 static int swrm_debug_open(struct inode *inode, struct file *file)
 234 {
 235         file->private_data = inode->i_private;
 236         return 0;
 237 }
 238
 239 static int get_parameters(char *buf, u32 *param1, int num_of_par)
 240 {
 241         char *token;
 242         int base, cnt;
 243
 244         token = strsep(&buf, " ");
 245         for (cnt = 0; cnt < num_of_par; cnt++) {
 246                 if (token) {
 247                         if ((token[1] == 'x') || (token[1] == 'X'))
 248                                 base = 16;
 249                         else
 250                                 base = 10;
 251
 252                         if (kstrtou32(token, base, &param1[cnt]) != 0)
 253                                 return -EINVAL;
 254
 255                         token = strsep(&buf, " ");
 256                 } else
 257                         return -EINVAL;
 258         }
 259         return 0;
 260 }
 261
 262 static ssize_t swrm_reg_show(char __user *ubuf, size_t count,
 263                                           loff_t *ppos)
 264 {
 265         int i, reg_val, len;
 266         ssize_t total = 0;
 267         char tmp_buf[SWR_MSTR_MAX_BUF_LEN];
 268
 269         if (!ubuf || !ppos)
 270                 return 0;
 271
 272         for (i = (((int) *ppos / BYTES_PER_LINE) + SWR_MSTR_START_REG_ADDR);
 273                 i <= SWR_MSTR_MAX_REG_ADDR; i += 4) {
 274                 reg_val = dbgswrm->read(dbgswrm->handle, i);
 275                 len = snprintf(tmp_buf, 25, "0x%.3x: 0x%.2x\n", i, reg_val);
 276                 if ((total + len) >= count - 1)
 277                         break;
 278                 if (copy_to_user((ubuf + total), tmp_buf, len)) {
 279                         pr_err("%s: fail to copy reg dump\n", __func__);
 280                         total = -EFAULT;
 281                         goto copy_err;
 282                 }
 283                 *ppos += len;
 284                 total += len;
 285         }
 286
 287 copy_err:
 288         return total;
 289 }
 290
 291 static ssize_t swrm_debug_read(struct file *file, char __user *ubuf,
 292                                 size_t count, loff_t *ppos)
 293 {
 294         char lbuf[SWR_MSTR_RD_BUF_LEN];
 295         char *access_str;
 296         ssize_t ret_cnt;
 297
 298         if (!count || !file || !ppos || !ubuf)
 299                 return -EINVAL;
 300
 301         access_str = file->private_data;
 302         if (*ppos < 0)
 303                 return -EINVAL;
 304
 305         if (!strcmp(access_str, "swrm_peek")) {
 306                 snprintf(lbuf, sizeof(lbuf), "0x%x\n", read_data);
 307                 ret_cnt = simple_read_from_buffer(ubuf, count, ppos, lbuf,
 308                                                strnlen(lbuf, 7));
 309         } else if (!strcmp(access_str, "swrm_reg_dump")) {
 310                 ret_cnt = swrm_reg_show(ubuf, count, ppos);
 311         } else {
 312                 pr_err("%s: %s not permitted to read\n", __func__, access_str);
 313                 ret_cnt = -EPERM;
 314         }
 315         return ret_cnt;
 316 }
 317
 318 static ssize_t swrm_debug_write(struct file *filp,
 319         const char __user *ubuf, size_t cnt, loff_t *ppos)
 320 {
 321         char lbuf[SWR_MSTR_WR_BUF_LEN];
 322         int rc;
 323         u32 param[5];
 324         char *access_str;
 325
 326         if (!filp || !ppos || !ubuf)
 327                 return -EINVAL;
 328
 329         access_str = filp->private_data;
 330         if (cnt > sizeof(lbuf) - 1)
 331                 return -EINVAL;
 332
 333         rc = copy_from_user(lbuf, ubuf, cnt);
 334         if (rc)
 335                 return -EFAULT;
 336
 337         lbuf[cnt] = '\0';
 338         if (!strcmp(access_str, "swrm_poke")) {
 339                 /* write */
 340                 rc = get_parameters(lbuf, param, 2);
 341                 if ((param[0] <= SWR_MSTR_MAX_REG_ADDR) &&
 342                         (param[1] <= 0xFFFFFFFF) &&
 343                         (rc == 0))
 344                         rc = dbgswrm->write(dbgswrm->handle, param[0],
 345                                             param[1]);
 346                 else
 347                         rc = -EINVAL;
 348         } else if (!strcmp(access_str, "swrm_peek")) {
 349                 /* read */
 350                 rc = get_parameters(lbuf, param, 1);
 351                 if ((param[0] <= SWR_MSTR_MAX_REG_ADDR) && (rc == 0))
 352                         read_data = dbgswrm->read(dbgswrm->handle, param[0]);
 353                 else
 354                         rc = -EINVAL;
 355         }
 356         if (rc == 0)
 357                 rc = cnt;
 358         else
 359                 pr_err("%s: rc = %d\n", __func__, rc);
 360
 361         return rc;
 362 }
 363
 364 static const struct file_operations swrm_debug_ops = {
 365         .open = swrm_debug_open,
 366         .write = swrm_debug_write,
 367         .read = swrm_debug_read,
 368 };
 369
 370 static int swrm_set_ch_map(struct swr_mstr_ctrl *swrm, void *data)
 371 {
 372         struct swr_mstr_port *pinfo = (struct swr_mstr_port *)data;
 373
 374         swrm->mstr_port = kzalloc(sizeof(struct swr_mstr_port), GFP_KERNEL);
 375         if (swrm->mstr_port == NULL)
 376                 return -ENOMEM;
 377         swrm->mstr_port->num_port = pinfo->num_port;
 378         swrm->mstr_port->port = kzalloc((pinfo->num_port * sizeof(u8)),
 379                                         GFP_KERNEL);
 380         if (!swrm->mstr_port->port) {
 381                 kfree(swrm->mstr_port);
 382                 swrm->mstr_port = NULL;
 383                 return -ENOMEM;
 384         }
 385         memcpy(swrm->mstr_port->port, pinfo->port, pinfo->num_port);
 386         return 0;
 387 }
 388
 389 static bool swrm_is_port_en(struct swr_master *mstr)
 390 {
 391         return !!(mstr->num_port);
 392 }
 393
 394 static int swrm_clk_request(struct swr_mstr_ctrl *swrm, bool enable)
 395 {
 396         if (!swrm->clk || !swrm->handle)
 397                 return -EINVAL;
 398
 399         if (enable) {
 400                 swrm->clk_ref_count++;
 401                 if (swrm->clk_ref_count == 1) {
 402                         swrm->clk(swrm->handle, true);
 403                         swrm->state = SWR_MSTR_UP;
 404                 }
 405         } else if (--swrm->clk_ref_count == 0) {
 406                 swrm->clk(swrm->handle, false);
 407                 swrm->state = SWR_MSTR_DOWN;
 408         } else if (swrm->clk_ref_count < 0) {
 409                 pr_err("%s: swrm clk count mismatch\n", __func__);
 410                 swrm->clk_ref_count = 0;
 411         }
 412         return 0;
 413 }
 414
 415 static int swrm_get_port_config(struct swr_master *master)
 416 {
 417         u32 ch_rate = 0;
 418         u32 num_ch = 0;
 419         int i, uc_idx;
 420         u32 portcount = 0;
 421
 422         for (i = 0; i < SWR_MSTR_PORT_LEN; i++) {
 423                 if (master->port[i].port_en) {
 424                         ch_rate += master->port[i].ch_rate;
 425                         num_ch += master->port[i].num_ch;
 426                         portcount++;
 427                 }
 428         }
 429         for (i = 0; i < ARRAY_SIZE(uc); i++) {
 430                 if ((uc[i].num_port == portcount) &&
 431                     (uc[i].num_ch == num_ch) &&
 432                     (uc[i].chrate == ch_rate)) {
 433                         uc_idx = i;
 434                         break;
 435                 }
 436         }
 437
 438         if (i >= ARRAY_SIZE(uc)) {
 439                 dev_err(&master->dev,
 440                         "%s: usecase port:%d, num_ch:%d, chrate:%d not found\n",
 441                         __func__, master->num_port, num_ch, ch_rate);
 442                 return -EINVAL;
 443         }
 444         for (i = 0; i < SWR_MSTR_PORT_LEN; i++) {
 445                 if (master->port[i].port_en) {
 446                         master->port[i].sinterval = pp[uc_idx][i].si;
 447                         master->port[i].offset1 = pp[uc_idx][i].off1;
 448                         master->port[i].offset2 = pp[uc_idx][i].off2;
 449                 }
 450         }
 451         return 0;
 452 }
 453
 454 static int swrm_get_master_port(u8 *mstr_port_id, u8 slv_port_id)
 455 {
 456         int i;
 457
 458         for (i = 0; i < SWR_MSTR_PORT_LEN; i++) {
 459                 if (mstr_ports[i] == slv_port_id) {
 460                         *mstr_port_id = i;
 461                         return 0;
 462                 }
 463         }
 464         return -EINVAL;
 465 }
 466
 467 static u32 swrm_get_packed_reg_val(u8 *cmd_id, u8 cmd_data,
 468                                  u8 dev_addr, u16 reg_addr)
 469 {
 470         u32 val;
 471         u8 id = *cmd_id;
 472
 473         if (id != SWR_BROADCAST_CMD_ID) {
 474                 if (id < 14)
 475                         id += 1;
 476                 else
 477                         id = 0;
 478                 *cmd_id = id;
 479         }
 480         val = SWR_REG_VAL_PACK(cmd_data, dev_addr, id, reg_addr);
 481
 482         return val;
 483 }
 484
 485 static int swrm_cmd_fifo_rd_cmd(struct swr_mstr_ctrl *swrm, int *cmd_data,
 486                                  u8 dev_addr, u8 cmd_id, u16 reg_addr,
 487                                  u32 len)
 488 {
 489         u32 val;
 490         int ret = 0;
 491
 492         val = swrm_get_packed_reg_val(&swrm->rcmd_id, len, dev_addr, reg_addr);
 493         ret = swrm->write(swrm->handle, SWRM_CMD_FIFO_RD_CMD, val);
 494         if (ret < 0) {
 495                 dev_err(swrm->dev, "%s: reg 0x%x write failed, err:%d\n",
 496                         __func__, val, ret);
 497                 goto err;
 498         }
 499         *cmd_data = swrm->read(swrm->handle, SWRM_CMD_FIFO_RD_FIFO_ADDR);
 500         dev_dbg(swrm->dev,
 501                 "%s: reg: 0x%x, cmd_id: 0x%x, dev_id: 0x%x, cmd_data: 0x%x\n",
 502                 __func__, reg_addr, cmd_id, dev_addr, *cmd_data);
 503 err:
 504         return ret;
 505 }
 506
 507 static int swrm_cmd_fifo_wr_cmd(struct swr_mstr_ctrl *swrm, u8 cmd_data,
 508                                  u8 dev_addr, u8 cmd_id, u16 reg_addr)
 509 {
 510         u32 val;
 511         int ret = 0;
 512
 513         if (!cmd_id)
 514                 val = swrm_get_packed_reg_val(&swrm->wcmd_id, cmd_data,
 515                                               dev_addr, reg_addr);
 516         else
 517                 val = swrm_get_packed_reg_val(&cmd_id, cmd_data,
 518                                               dev_addr, reg_addr);
 519
 520         dev_dbg(swrm->dev,
 521                 "%s: reg: 0x%x, cmd_id: 0x%x, dev_id: 0x%x, cmd_data: 0x%x\n",
 522                 __func__, reg_addr, cmd_id, dev_addr, cmd_data);
 523         ret = swrm->write(swrm->handle, SWRM_CMD_FIFO_WR_CMD, val);
 524         if (ret < 0) {
 525                 dev_err(swrm->dev, "%s: reg 0x%x write failed, err:%d\n",
 526                         __func__, val, ret);
 527                 goto err;
 528         }
 529         if (cmd_id == 0xF) {
 530                 /*
 531                  * sleep for 10ms for MSM soundwire variant to allow broadcast
 532                  * command to complete.
 533                  */
 534                 if (swrm_is_msm_variant(swrm->version))
 535                         usleep_range(10000, 10100);
 536                 else
 537                         wait_for_completion_timeout(&swrm->broadcast,
 538                                                     (2 * HZ/10));
 539         }
 540 err:
 541         return ret;
 542 }
 543
 544 static int swrm_read(struct swr_master *master, u8 dev_num, u16 reg_addr,
 545                      void *buf, u32 len)
 546 {
 547         struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master);
 548         int ret = 0;
 549         int val = 0;
 550         u8 *reg_val = (u8 *)buf;
 551
 552         if (!swrm) {
 553                 dev_err(&master->dev, "%s: swrm is NULL\n", __func__);
 554                 return -EINVAL;
 555         }
 556
 557         if (dev_num)
 558                 ret = swrm_cmd_fifo_rd_cmd(swrm, &val, dev_num, 0, reg_addr,
 559                                            len);
 560         else
 561                 val = swrm->read(swrm->handle, reg_addr);
 562         if (ret)
 563                 return ret;
 564
 565         *reg_val = (u8)val;
 566         pm_runtime_mark_last_busy(&swrm->pdev->dev);
 567
 568         return ret;
 569 }
 570
 571 static int swrm_write(struct swr_master *master, u8 dev_num, u16 reg_addr,
 572                       const void *buf)
 573 {
 574         struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master);
 575         int ret = 0;
 576         u8 reg_val = *(u8 *)buf;
 577
 578         if (!swrm) {
 579                 dev_err(&master->dev, "%s: swrm is NULL\n", __func__);
 580                 return -EINVAL;
 581         }
 582
 583         if (dev_num)
 584                 ret = swrm_cmd_fifo_wr_cmd(swrm, reg_val, dev_num, 0, reg_addr);
 585         else
 586                 ret = swrm->write(swrm->handle, reg_addr, reg_val);
 587
 588         pm_runtime_mark_last_busy(&swrm->pdev->dev);
 589
 590         return ret;
 591 }
 592
 593 static int swrm_bulk_write(struct swr_master *master, u8 dev_num, void *reg,
 594                            const void *buf, size_t len)
 595 {
 596         struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master);
 597         int ret = 0;
 598         int i;
 599         u32 *val;
 600         u32 *swr_fifo_reg;
 601
 602         if (!swrm || !swrm->handle) {
 603                 dev_err(&master->dev, "%s: swrm is NULL\n", __func__);
 604                 return -EINVAL;
 605         }
 606         if (len <= 0)
 607                 return -EINVAL;
 608
 609         if (dev_num) {
 610                 swr_fifo_reg = kcalloc(len, sizeof(u32), GFP_KERNEL);
 611                 if (!swr_fifo_reg) {
 612                         ret = -ENOMEM;
 613                         goto err;
 614                 }
 615                 val = kcalloc(len, sizeof(u32), GFP_KERNEL);
 616                 if (!val) {
 617                         ret = -ENOMEM;
 618                         goto mem_fail;
 619                 }
 620
 621                 for (i = 0; i < len; i++) {
 622                         val[i] = swrm_get_packed_reg_val(&swrm->wcmd_id,
 623                                                          ((u8 *)buf)[i],
 624                                                          dev_num,
 625                                                          ((u16 *)reg)[i]);
 626                         swr_fifo_reg[i] = SWRM_CMD_FIFO_WR_CMD;
 627                 }
 628                 ret = swrm->bulk_write(swrm->handle, swr_fifo_reg, val, len);
 629                 if (ret) {
 630                         dev_err(&master->dev, "%s: bulk write failed\n",
 631                                 __func__);
 632                         ret = -EINVAL;
 633                 }
 634         } else {
 635                 dev_err(&master->dev,
 636                         "%s: No support of Bulk write for master regs\n",
 637                         __func__);
 638                 ret = -EINVAL;
 639                 goto err;
 640         }
 641         kfree(val);
 642 mem_fail:
 643         kfree(swr_fifo_reg);
 644 err:
 645         pm_runtime_mark_last_busy(&swrm->pdev->dev);
 646         return ret;
 647 }
 648
 649 static u8 get_inactive_bank_num(struct swr_mstr_ctrl *swrm)
 650 {
 651         return (swrm->read(swrm->handle, SWRM_MCP_STATUS) &
 652                 SWRM_MCP_STATUS_BANK_NUM_MASK) ? 0 : 1;
 653 }
 654
 655 static void enable_bank_switch(struct swr_mstr_ctrl *swrm, u8 bank,
 656                                 u8 row, u8 col)
 657 {
 658         /* apply div2 setting for inactive bank before bank switch */
 659         swrm_cmd_fifo_wr_cmd(swrm, 0x01, 0xF, 0x00,
 660                         SWRS_SCP_HOST_CLK_DIV2_CTL_BANK(bank));
 661
 662         swrm_cmd_fifo_wr_cmd(swrm, ((row << 3) | col), 0xF, 0xF,
 663                         SWRS_SCP_FRAME_CTRL_BANK(bank));
 664 }
 665
 666 static struct swr_port_info *swrm_get_port(struct swr_master *master,
 667                                            u8 port_id)
 668 {
 669         int i;
 670         struct swr_port_info *port = NULL;
 671
 672         for (i = 0; i < SWR_MSTR_PORT_LEN; i++) {
 673                 port = &master->port[i];
 674                 if (port->port_id == port_id) {
 675                         dev_dbg(&master->dev, "%s: port_id: %d, index: %d\n",
 676                                 __func__, port_id, i);
 677                         return port;
 678                 }
 679         }
 680
 681         return NULL;
 682 }
 683
 684 static struct swr_port_info *swrm_get_avail_port(struct swr_master *master)
 685 {
 686         int i;
 687         struct swr_port_info *port = NULL;
 688
 689         for (i = 0; i < SWR_MSTR_PORT_LEN; i++) {
 690                 port = &master->port[i];
 691                 if (port->port_en)
 692                         continue;
 693
 694                 dev_dbg(&master->dev, "%s: port_id: %d, index: %d\n",
 695                         __func__, port->port_id, i);
 696                 return port;
 697         }
 698
 699         return NULL;
 700 }
 701
 702 static struct swr_port_info *swrm_get_enabled_port(struct swr_master *master,
 703                                                    u8 port_id)
 704 {
 705         int i;
 706         struct swr_port_info *port = NULL;
 707
 708         for (i = 0; i < SWR_MSTR_PORT_LEN; i++) {
 709                 port = &master->port[i];
 710                 if ((port->port_id == port_id) && (port->port_en == true))
 711                         break;
 712         }
 713         if (i == SWR_MSTR_PORT_LEN)
 714                 port = NULL;
 715         return port;
 716 }
 717
 718 static bool swrm_remove_from_group(struct swr_master *master)
 719 {
 720         struct swr_device *swr_dev;
 721         struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master);
 722         bool is_removed = false;
 723
 724         if (!swrm)
 725                 goto end;
 726
 727         mutex_lock(&swrm->mlock);
 728         if ((swrm->num_rx_chs > 1) &&
 729             (swrm->num_rx_chs == swrm->num_cfg_devs)) {
 730                 list_for_each_entry(swr_dev, &master->devices,
 731                                 dev_list) {
 732                         swr_dev->group_id = SWR_GROUP_NONE;
 733                         master->gr_sid = 0;
 734                 }
 735                 is_removed = true;
 736         }
 737         mutex_unlock(&swrm->mlock);
 738
 739 end:
 740         return is_removed;
 741 }
 742
 743 static void swrm_cleanup_disabled_data_ports(struct swr_master *master,
 744                                              u8 bank)
 745 {
 746         u32 value;
 747         struct swr_port_info *port;
 748         int i;
 749         int port_type;
 750         struct swrm_mports *mport, *mport_next = NULL;
 751         int port_disable_cnt = 0;
 752         struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master);
 753
 754         if (!swrm) {
 755                 pr_err("%s: swrm is null\n", __func__);
 756                 return;
 757         }
 758
 759         dev_dbg(swrm->dev, "%s: master num_port: %d\n", __func__,
 760                 master->num_port);
 761
 762         mport = list_first_entry_or_null(&swrm->mport_list,
 763                                         struct swrm_mports,
 764                                         list);
 765         if (!mport) {
 766                 dev_err(swrm->dev, "%s: list is empty\n", __func__);
 767                 return;
 768         }
 769
 770         for (i = 0; i < master->num_port; i++) {
 771                 port = swrm_get_port(master, mstr_ports[mport->id]);
 772                 if (!port || port->ch_en)
 773                         goto inc_loop;
 774
 775                 port_disable_cnt++;
 776                 port_type = mstr_port_type[mport->id];
 777                 value = ((port->ch_en)
 778                                 << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
 779                 value |= ((port->offset2)
 780                                 << SWRM_DP_PORT_CTRL_OFFSET2_SHFT);
 781                 value |= ((port->offset1)
 782                                 << SWRM_DP_PORT_CTRL_OFFSET1_SHFT);
 783                 value |= port->sinterval;
 784
 785                 swrm->write(swrm->handle,
 786                             SWRM_DP_PORT_CTRL_BANK((mport->id+1), bank),
 787                             value);
 788                 swrm_cmd_fifo_wr_cmd(swrm, 0x00, port->dev_id, 0x00,
 789                                 SWRS_DP_CHANNEL_ENABLE_BANK(port_type, bank));
 790
 791                 dev_dbg(swrm->dev, "%s: mport :%d, reg: 0x%x, val: 0x%x\n",
 792                         __func__, mport->id,
 793                         (SWRM_DP_PORT_CTRL_BANK((mport->id+1), bank)), value);
 794
 795 inc_loop:
 796                 mport_next = list_next_entry(mport, list);
 797                 if (port && !port->ch_en) {
 798                         list_del(&mport->list);
 799                         kfree(mport);
 800                 }
 801                 if (!mport_next) {
 802                         dev_err(swrm->dev, "%s: end of list\n", __func__);
 803                         break;
 804                 }
 805                 mport = mport_next;
 806         }
 807         master->num_port -= port_disable_cnt;
 808
 809         dev_dbg(swrm->dev, "%s:disable ports: %d, active ports (rem): %d\n",
 810                 __func__, port_disable_cnt,  master->num_port);
 811 }
 812
 813 static void swrm_slvdev_datapath_control(struct swr_master *master,
 814                                          bool enable)
 815 {
 816         u8 bank;
 817         u32 value, n_col;
 818         struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master);
 819         int mask = (SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK |
 820                     SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK |
 821                     SWRM_MCP_FRAME_CTRL_BANK_SSP_PERIOD_BMSK);
 822         u8 inactive_bank;
 823
 824         if (!swrm) {
 825                 pr_err("%s: swrm is null\n", __func__);
 826                 return;
 827         }
 828
 829         bank = get_inactive_bank_num(swrm);
 830
 831         dev_dbg(swrm->dev, "%s: enable: %d, cfg_devs: %d\n",
 832                 __func__, enable, swrm->num_cfg_devs);
 833
 834         if (enable) {
 835                 /* set Row = 48 and col = 16 */
 836                 n_col = SWR_MAX_COL;
 837         } else {
 838                 /*
 839                  * Do not change to 48x2 if number of channels configured
 840                  * as stereo and if disable datapath is called for the
 841                  * first slave device
 842                  */
 843                 if (swrm->num_cfg_devs > 0)
 844                         n_col = SWR_MAX_COL;
 845                 else
 846                         n_col = SWR_MIN_COL;
 847
 848                 /*
 849                  * All ports are already disabled, no need to perform
 850                  * bank-switch and copy operation. This case can arise
 851                  * when speaker channels are enabled in stereo mode with
 852                  * BROADCAST and disabled in GROUP_NONE
 853                  */
 854                 if (master->num_port == 0)
 855                         return;
 856         }
 857
 858         value = swrm->read(swrm->handle, SWRM_MCP_FRAME_CTRL_BANK_ADDR(bank));
 859         value &= (~mask);
 860         value |= ((0 << SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_SHFT) |
 861                   (n_col << SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_SHFT) |
 862                   (0 << SWRM_MCP_FRAME_CTRL_BANK_SSP_PERIOD_SHFT));
 863         swrm->write(swrm->handle, SWRM_MCP_FRAME_CTRL_BANK_ADDR(bank), value);
 864
 865         dev_dbg(swrm->dev, "%s: regaddr: 0x%x, value: 0x%x\n", __func__,
 866                 SWRM_MCP_FRAME_CTRL_BANK_ADDR(bank), value);
 867
 868         enable_bank_switch(swrm, bank, SWR_MAX_ROW, n_col);
 869
 870         inactive_bank = bank ? 0 : 1;
 871         if (enable)
 872                 swrm_copy_data_port_config(master, inactive_bank);
 873         else
 874                 swrm_cleanup_disabled_data_ports(master, inactive_bank);
 875
 876         if (!swrm_is_port_en(master)) {
 877                 dev_dbg(&master->dev, "%s: pm_runtime auto suspend triggered\n",
 878                         __func__);
 879                 pm_runtime_mark_last_busy(&swrm->pdev->dev);
 880                 pm_runtime_put_autosuspend(&swrm->pdev->dev);
 881         }
 882 }
 883
 884 static void swrm_apply_port_config(struct swr_master *master)
 885 {
 886         u8 bank;
 887         struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master);
 888
 889         if (!swrm) {
 890                 pr_err("%s: Invalid handle to swr controller\n",
 891                         __func__);
 892                 return;
 893         }
 894
 895         bank = get_inactive_bank_num(swrm);
 896         dev_dbg(swrm->dev, "%s: enter bank: %d master_ports: %d\n",
 897                 __func__, bank, master->num_port);
 898
 899
 900         swrm_copy_data_port_config(master, bank);
 901 }
 902
 903 static void swrm_copy_data_port_config(struct swr_master *master, u8 bank)
 904 {
 905         u32 value;
 906         struct swr_port_info *port;
 907         int i;
 908         int port_type;
 909         struct swrm_mports *mport;
 910         u32 reg[SWRM_MAX_PORT_REG];
 911         u32 val[SWRM_MAX_PORT_REG];
 912         int len = 0;
 913         struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master);
 914
 915         if (!swrm) {
 916                 pr_err("%s: swrm is null\n", __func__);
 917                 return;
 918         }
 919
 920         dev_dbg(swrm->dev, "%s: master num_port: %d\n", __func__,
 921                 master->num_port);
 922
 923         mport = list_first_entry_or_null(&swrm->mport_list,
 924                                         struct swrm_mports,
 925                                         list);
 926         if (!mport) {
 927                 dev_err(swrm->dev, "%s: list is empty\n", __func__);
 928                 return;
 929         }
 930         for (i = 0; i < master->num_port; i++) {
 931
 932                 port = swrm_get_enabled_port(master, mstr_ports[mport->id]);
 933                 if (!port)
 934                         continue;
 935                 port_type = mstr_port_type[mport->id];
 936                 if (!port->dev_id || (port->dev_id > master->num_dev)) {
 937                         dev_dbg(swrm->dev, "%s: invalid device id = %d\n",
 938                                 __func__, port->dev_id);
 939                         continue;
 940                 }
 941                 value = ((port->ch_en)
 942                                 << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
 943                 value |= ((port->offset2)
 944                                 << SWRM_DP_PORT_CTRL_OFFSET2_SHFT);
 945                 value |= ((port->offset1)
 946                                 << SWRM_DP_PORT_CTRL_OFFSET1_SHFT);
 947                 value |= port->sinterval;
 948
 949                 reg[len] = SWRM_DP_PORT_CTRL_BANK((mport->id+1), bank);
 950                 val[len++] = value;
 951
 952                 dev_dbg(swrm->dev, "%s: mport :%d, reg: 0x%x, val: 0x%x\n",
 953                         __func__, mport->id,
 954                         (SWRM_DP_PORT_CTRL_BANK((mport->id+1), bank)), value);
 955
 956                 reg[len] = SWRM_CMD_FIFO_WR_CMD;
 957                 val[len++] = SWR_REG_VAL_PACK(port->ch_en, port->dev_id, 0x00,
 958                                 SWRS_DP_CHANNEL_ENABLE_BANK(port_type, bank));
 959
 960                 reg[len] = SWRM_CMD_FIFO_WR_CMD;
 961                 val[len++] = SWR_REG_VAL_PACK(port->sinterval,
 962                                 port->dev_id, 0x00,
 963                                 SWRS_DP_SAMPLE_CONTROL_1_BANK(port_type, bank));
 964
 965                 reg[len] = SWRM_CMD_FIFO_WR_CMD;
 966                 val[len++] = SWR_REG_VAL_PACK(port->offset1,
 967                                 port->dev_id, 0x00,
 968                                 SWRS_DP_OFFSET_CONTROL_1_BANK(port_type, bank));
 969
 970                 if (port_type != 0) {
 971                         reg[len] = SWRM_CMD_FIFO_WR_CMD;
 972                         val[len++] = SWR_REG_VAL_PACK(port->offset2,
 973                                         port->dev_id, 0x00,
 974                                         SWRS_DP_OFFSET_CONTROL_2_BANK(port_type,
 975                                                                         bank));
 976                 }
 977                 mport = list_next_entry(mport, list);
 978                 if (!mport) {
 979                         dev_err(swrm->dev, "%s: end of list\n", __func__);
 980                         break;
 981                 }
 982         }
 983         swrm->bulk_write(swrm->handle, reg, val, len);
 984 }
 985
 986 static int swrm_connect_port(struct swr_master *master,
 987                         struct swr_params *portinfo)
 988 {
 989         int i;
 990         struct swr_port_info *port;
 991         int ret = 0;
 992         struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master);
 993         struct swrm_mports *mport;
 994         struct list_head *ptr, *next;
 995
 996         dev_dbg(&master->dev, "%s: enter\n", __func__);
 997         if (!portinfo)
 998                 return -EINVAL;
 999
1000         if (!swrm) {
1001                 dev_err(&master->dev,
1002                         "%s: Invalid handle to swr controller\n",
1003                         __func__);
1004                 return -EINVAL;
1005         }
1006
1007         mutex_lock(&swrm->mlock);
1008         if (!swrm_is_port_en(master))
1009                 pm_runtime_get_sync(&swrm->pdev->dev);
1010
1011         for (i = 0; i < portinfo->num_port; i++) {
1012                 mport = kzalloc(sizeof(struct swrm_mports), GFP_KERNEL);
1013                 if (!mport) {
1014                         ret = -ENOMEM;
1015                         goto mem_fail;
1016                 }
1017                 ret = swrm_get_master_port(&mport->id,
1018                                                 portinfo->port_id[i]);
1019                 if (ret < 0) {
1020                         dev_err(&master->dev,
1021                                 "%s: mstr portid for slv port %d not found\n",
1022                                 __func__, portinfo->port_id[i]);
1023                         goto port_fail;
1024                 }
1025                 port = swrm_get_avail_port(master);
1026                 if (!port) {
1027                         dev_err(&master->dev,
1028                                 "%s: avail ports not found!\n", __func__);
1029                         goto port_fail;
1030                 }
1031                 list_add(&mport->list, &swrm->mport_list);
1032                 port->dev_id = portinfo->dev_id;
1033                 port->port_id = portinfo->port_id[i];
1034                 port->num_ch = portinfo->num_ch[i];
1035                 port->ch_rate = portinfo->ch_rate[i];
1036                 port->ch_en = portinfo->ch_en[i];
1037                 port->port_en = true;
1038                 dev_dbg(&master->dev,
1039                         "%s: mstr port %d, slv port %d ch_rate %d num_ch %d\n",
1040                         __func__, mport->id, port->port_id, port->ch_rate,
1041                         port->num_ch);
1042         }
1043         master->num_port += portinfo->num_port;
1044         if (master->num_port >= SWR_MSTR_PORT_LEN)
1045                 master->num_port = SWR_MSTR_PORT_LEN;
1046
1047         swrm_get_port_config(master);
1048         swr_port_response(master, portinfo->tid);
1049         swrm->num_cfg_devs += 1;
1050         dev_dbg(&master->dev, "%s: cfg_devs: %d, rx_chs: %d\n",
1051                 __func__, swrm->num_cfg_devs, swrm->num_rx_chs);
1052         if (swrm->num_rx_chs > 1) {
1053                 if (swrm->num_rx_chs == swrm->num_cfg_devs)
1054                         swrm_apply_port_config(master);
1055         } else {
1056                 swrm_apply_port_config(master);
1057         }
1058         mutex_unlock(&swrm->mlock);
1059         return 0;
1060
1061 port_fail:
1062         kfree(mport);
1063 mem_fail:
1064         list_for_each_safe(ptr, next, &swrm->mport_list) {
1065                 mport = list_entry(ptr, struct swrm_mports, list);
1066                 for (i = 0; i < portinfo->num_port; i++) {
1067                         if (portinfo->port_id[i] == mstr_ports[mport->id]) {
1068                                 port = swrm_get_port(master,
1069                                                 portinfo->port_id[i]);
1070                                 if (port)
1071                                         port->ch_en = false;
1072                                 list_del(&mport->list);
1073                                 kfree(mport);
1074                                 break;
1075                         }
1076                 }
1077         }
1078         mutex_unlock(&swrm->mlock);
1079         return ret;
1080 }
1081
1082 static int swrm_disconnect_port(struct swr_master *master,
1083                         struct swr_params *portinfo)
1084 {
1085         int i;
1086         struct swr_port_info *port;
1087         u8 bank;
1088         u32 value;
1089         int ret = 0;
1090         u8 mport_id = 0;
1091         int port_type = 0;
1092         struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master);
1093
1094         if (!swrm) {
1095                 dev_err(&master->dev,
1096                         "%s: Invalid handle to swr controller\n",
1097                         __func__);
1098                 return -EINVAL;
1099         }
1100
1101         if (!portinfo) {
1102                 dev_err(&master->dev, "%s: portinfo is NULL\n", __func__);
1103                 return -EINVAL;
1104         }
1105         mutex_lock(&swrm->mlock);
1106         bank = get_inactive_bank_num(swrm);
1107         for (i = 0; i < portinfo->num_port; i++) {
1108                 ret = swrm_get_master_port(&mport_id,
1109                                                 portinfo->port_id[i]);
1110                 if (ret < 0) {
1111                         dev_err(&master->dev,
1112                                 "%s: mstr portid for slv port %d not found\n",
1113                                 __func__, portinfo->port_id[i]);
1114                         mutex_unlock(&swrm->mlock);
1115                         return -EINVAL;
1116                 }
1117                 port = swrm_get_enabled_port(master, portinfo->port_id[i]);
1118                 if (!port) {
1119                         dev_dbg(&master->dev, "%s: port %d already disabled\n",
1120                                 __func__, portinfo->port_id[i]);
1121                         continue;
1122                 }
1123                 port_type = mstr_port_type[mport_id];
1124                 port->dev_id = portinfo->dev_id;
1125                 port->port_en = false;
1126                 port->ch_en = 0;
1127                 value = port->ch_en << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT;
1128                 value |= (port->offset2 << SWRM_DP_PORT_CTRL_OFFSET2_SHFT);
1129                 value |= (port->offset1 << SWRM_DP_PORT_CTRL_OFFSET1_SHFT);
1130                 value |= port->sinterval;
1131
1132
1133                 swrm->write(swrm->handle,
1134                             SWRM_DP_PORT_CTRL_BANK((mport_id+1), bank),
1135                             value);
1136                 swrm_cmd_fifo_wr_cmd(swrm, 0x00, port->dev_id, 0x00,
1137                                 SWRS_DP_CHANNEL_ENABLE_BANK(port_type, bank));
1138         }
1139
1140         swr_port_response(master, portinfo->tid);
1141         swrm->num_cfg_devs -= 1;
1142         dev_dbg(&master->dev, "%s: cfg_devs: %d, rx_chs: %d, active ports: %d\n",
1143                 __func__, swrm->num_cfg_devs, swrm->num_rx_chs,
1144                 master->num_port);
1145         mutex_unlock(&swrm->mlock);
1146
1147         return 0;
1148 }
1149
1150 static int swrm_check_slave_change_status(struct swr_mstr_ctrl *swrm,
1151                                         int status, u8 *devnum)
1152 {
1153         int i;
1154         int new_sts = status;
1155         int ret = SWR_NOT_PRESENT;
1156
1157         if (status != swrm->slave_status) {
1158                 for (i = 0; i < (swrm->master.num_dev + 1); i++) {
1159                         if ((status & SWRM_MCP_SLV_STATUS_MASK) !=
1160                             (swrm->slave_status & SWRM_MCP_SLV_STATUS_MASK)) {
1161                                 ret = (status & SWRM_MCP_SLV_STATUS_MASK);
1162                                 *devnum = i;
1163                                 break;
1164                         }
1165                         status >>= 2;
1166                         swrm->slave_status >>= 2;
1167                 }
1168                 swrm->slave_status = new_sts;
1169         }
1170         return ret;
1171 }
1172
1173 static irqreturn_t swr_mstr_interrupt(int irq, void *dev)
1174 {
1175         struct swr_mstr_ctrl *swrm = dev;
1176         u32 value, intr_sts;
1177         int status, chg_sts, i;
1178         u8 devnum = 0;
1179         int ret = IRQ_HANDLED;
1180
1181         mutex_lock(&swrm->reslock);
1182         swrm_clk_request(swrm, true);
1183         mutex_unlock(&swrm->reslock);
1184
1185         intr_sts = swrm->read(swrm->handle, SWRM_INTERRUPT_STATUS);
1186         intr_sts &= SWRM_INTERRUPT_STATUS_RMSK;
1187         for (i = 0; i < SWRM_INTERRUPT_MAX; i++) {
1188                 value = intr_sts & (1 << i);
1189                 if (!value)
1190                         continue;
1191
1192                 swrm->write(swrm->handle, SWRM_INTERRUPT_CLEAR, value);
1193                 switch (value) {
1194                 case SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ:
1195                         dev_dbg(swrm->dev, "SWR slave pend irq\n");
1196                         break;
1197                 case SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED:
1198                         dev_dbg(swrm->dev, "SWR new slave attached\n");
1199                         break;
1200                 case SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS:
1201                         status = swrm->read(swrm->handle, SWRM_MCP_SLV_STATUS);
1202                         if (status == swrm->slave_status) {
1203                                 dev_dbg(swrm->dev,
1204                                         "%s: No change in slave status: %d\n",
1205                                         __func__, status);
1206                                 break;
1207                         }
1208                         chg_sts = swrm_check_slave_change_status(swrm, status,
1209                                                                 &devnum);
1210                         switch (chg_sts) {
1211                         case SWR_NOT_PRESENT:
1212                                 dev_dbg(swrm->dev, "device %d got detached\n",
1213                                         devnum);
1214                                 break;
1215                         case SWR_ATTACHED_OK:
1216                                 dev_dbg(swrm->dev, "device %d got attached\n",
1217                                         devnum);
1218                                 break;
1219                         case SWR_ALERT:
1220                                 dev_dbg(swrm->dev,
1221                                         "device %d has pending interrupt\n",
1222                                         devnum);
1223                                 break;
1224                         }
1225                         break;
1226                 case SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET:
1227                         dev_err_ratelimited(swrm->dev, "SWR bus clash detected\n");
1228                         break;
1229                 case SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW:
1230                         dev_dbg(swrm->dev, "SWR read FIFO overflow\n");
1231                         break;
1232                 case SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW:
1233                         dev_dbg(swrm->dev, "SWR read FIFO underflow\n");
1234                         break;
1235                 case SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW:
1236                         dev_dbg(swrm->dev, "SWR write FIFO overflow\n");
1237                         break;
1238                 case SWRM_INTERRUPT_STATUS_CMD_ERROR:
1239                         value = swrm->read(swrm->handle, SWRM_CMD_FIFO_STATUS);
1240                         dev_err_ratelimited(swrm->dev,
1241                         "SWR CMD error, fifo status 0x%x, flushing fifo\n",
1242                                             value);
1243                         swrm->write(swrm->handle, SWRM_CMD_FIFO_CMD, 0x1);
1244                         break;
1245                 case SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION:
1246                         dev_dbg(swrm->dev, "SWR Port collision detected\n");
1247                         break;
1248                 case SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH:
1249                         dev_dbg(swrm->dev, "SWR read enable valid mismatch\n");
1250                         break;
1251                 case SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED:
1252                         complete(&swrm->broadcast);
1253                         dev_dbg(swrm->dev, "SWR cmd id finished\n");
1254                         break;
1255                 case SWRM_INTERRUPT_STATUS_NEW_SLAVE_AUTO_ENUM_FINISHED:
1256                         break;
1257                 case SWRM_INTERRUPT_STATUS_AUTO_ENUM_FAILED:
1258                         break;
1259                 case SWRM_INTERRUPT_STATUS_AUTO_ENUM_TABLE_IS_FULL:
1260                         break;
1261                 case SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED:
1262                         complete(&swrm->reset);
1263                         break;
1264                 case SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED:
1265                         break;
1266                 default:
1267                         dev_err_ratelimited(swrm->dev, "SWR unknown interrupt\n");
1268                         ret = IRQ_NONE;
1269                         break;
1270                 }
1271         }
1272
1273         mutex_lock(&swrm->reslock);
1274         swrm_clk_request(swrm, false);
1275         mutex_unlock(&swrm->reslock);
1276         return ret;
1277 }
1278
1279 static int swrm_get_device_status(struct swr_mstr_ctrl *swrm, u8 devnum)
1280 {
1281         u32 val;
1282
1283         swrm->slave_status = swrm->read(swrm->handle, SWRM_MCP_SLV_STATUS);
1284         val = (swrm->slave_status >> (devnum * 2));
1285         val &= SWRM_MCP_SLV_STATUS_MASK;
1286         return val;
1287 }
1288
1289 static int swrm_get_logical_dev_num(struct swr_master *mstr, u64 dev_id,
1290                                 u8 *dev_num)
1291 {
1292         int i;
1293         u64 id = 0;
1294         int ret = -EINVAL;
1295         struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(mstr);
1296
1297         if (!swrm) {
1298                 pr_err("%s: Invalid handle to swr controller\n",
1299                         __func__);
1300                 return ret;
1301         }
1302
1303         pm_runtime_get_sync(&swrm->pdev->dev);
1304         for (i = 1; i < (mstr->num_dev + 1); i++) {
1305                 id = ((u64)(swrm->read(swrm->handle,
1306                             SWRM_ENUMERATOR_SLAVE_DEV_ID_2(i))) << 32);
1307                 id |= swrm->read(swrm->handle,
1308                             SWRM_ENUMERATOR_SLAVE_DEV_ID_1(i));
1309                 if ((id & SWR_DEV_ID_MASK) == dev_id) {
1310                         if (swrm_get_device_status(swrm, i) == 0x01) {
1311                                 *dev_num = i;
1312                                 ret = 0;
1313                         } else {
1314                                 dev_err(swrm->dev, "%s: device is not ready\n",
1315                                          __func__);
1316                         }
1317                         goto found;
1318                 }
1319         }
1320         dev_err(swrm->dev, "%s: device id 0x%llx does not match with 0x%llx\n",
1321                 __func__, id, dev_id);
1322 found:
1323         pm_runtime_mark_last_busy(&swrm->pdev->dev);
1324         pm_runtime_put_autosuspend(&swrm->pdev->dev);
1325         return ret;
1326 }
1327 static int swrm_master_init(struct swr_mstr_ctrl *swrm)
1328 {
1329         int ret = 0;
1330         u32 val;
1331         u8 row_ctrl = SWR_MAX_ROW;
1332         u8 col_ctrl = SWR_MIN_COL;
1333         u8 ssp_period = 1;
1334         u8 retry_cmd_num = 3;
1335         u32 reg[SWRM_MAX_INIT_REG];
1336         u32 value[SWRM_MAX_INIT_REG];
1337         int len = 0;
1338
1339         /* Clear Rows and Cols */
1340         val = ((row_ctrl << SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_SHFT) |
1341                 (col_ctrl << SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_SHFT) |
1342                 (ssp_period << SWRM_MCP_FRAME_CTRL_BANK_SSP_PERIOD_SHFT));
1343
1344         reg[len] = SWRM_MCP_FRAME_CTRL_BANK_ADDR(0);
1345         value[len++] = val;
1346
1347         /* Set Auto enumeration flag */
1348         reg[len] = SWRM_ENUMERATOR_CFG_ADDR;
1349         value[len++] = 1;
1350
1351         /* Mask soundwire interrupts */
1352         reg[len] = SWRM_INTERRUPT_MASK_ADDR;
1353         value[len++] = 0x1FFFD;
1354
1355         /* Configure No pings */
1356         val = swrm->read(swrm->handle, SWRM_MCP_CFG_ADDR);
1357         val &= ~SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK;
1358         val |= (0x1f << SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_SHFT);
1359         reg[len] = SWRM_MCP_CFG_ADDR;
1360         value[len++] = val;
1361
1362         /* Configure number of retries of a read/write cmd */
1363         val = (retry_cmd_num << SWRM_CMD_FIFO_CFG_NUM_OF_CMD_RETRY_SHFT);
1364         reg[len] = SWRM_CMD_FIFO_CFG_ADDR;
1365         value[len++] = val;
1366
1367         /* Set IRQ to PULSE */
1368         reg[len] = SWRM_COMP_CFG_ADDR;
1369         value[len++] = 0x02;
1370
1371         reg[len] = SWRM_COMP_CFG_ADDR;
1372         value[len++] = 0x03;
1373
1374         reg[len] = SWRM_INTERRUPT_CLEAR;
1375         value[len++] = 0x08;
1376
1377         swrm->bulk_write(swrm->handle, reg, value, len);
1378
1379         return ret;
1380 }
1381
1382 static int swrm_probe(struct platform_device *pdev)
1383 {
1384         struct swr_mstr_ctrl *swrm;
1385         struct swr_ctrl_platform_data *pdata;
1386         int ret;
1387
1388         /* Allocate soundwire master driver structure */
1389         swrm = kzalloc(sizeof(struct swr_mstr_ctrl), GFP_KERNEL);
1390         if (!swrm) {
1391                 dev_err(&pdev->dev, "%s: no memory for swr mstr controller\n",
1392                          __func__);
1393                 ret = -ENOMEM;
1394                 goto err_memory_fail;
1395         }
1396         swrm->dev = &pdev->dev;
1397         swrm->pdev = pdev;
1398         platform_set_drvdata(pdev, swrm);
1399         swr_set_ctrl_data(&swrm->master, swrm);
1400         pdata = dev_get_platdata(&pdev->dev);
1401         if (!pdata) {
1402                 dev_err(&pdev->dev, "%s: pdata from parent is NULL\n",
1403                         __func__);
1404                 ret = -EINVAL;
1405                 goto err_pdata_fail;
1406         }
1407         swrm->handle = (void *)pdata->handle;
1408         if (!swrm->handle) {
1409                 dev_err(&pdev->dev, "%s: swrm->handle is NULL\n",
1410                         __func__);
1411                 ret = -EINVAL;
1412                 goto err_pdata_fail;
1413         }
1414         swrm->read = pdata->read;
1415         if (!swrm->read) {
1416                 dev_err(&pdev->dev, "%s: swrm->read is NULL\n",
1417                         __func__);
1418                 ret = -EINVAL;
1419                 goto err_pdata_fail;
1420         }
1421         swrm->write = pdata->write;
1422         if (!swrm->write) {
1423                 dev_err(&pdev->dev, "%s: swrm->write is NULL\n",
1424                         __func__);
1425                 ret = -EINVAL;
1426                 goto err_pdata_fail;
1427         }
1428         swrm->bulk_write = pdata->bulk_write;
1429         if (!swrm->bulk_write) {
1430                 dev_err(&pdev->dev, "%s: swrm->bulk_write is NULL\n",
1431                         __func__);
1432                 ret = -EINVAL;
1433                 goto err_pdata_fail;
1434         }
1435         swrm->clk = pdata->clk;
1436         if (!swrm->clk) {
1437                 dev_err(&pdev->dev, "%s: swrm->clk is NULL\n",
1438                         __func__);
1439                 ret = -EINVAL;
1440                 goto err_pdata_fail;
1441         }
1442         swrm->reg_irq = pdata->reg_irq;
1443         if (!swrm->reg_irq) {
1444                 dev_err(&pdev->dev, "%s: swrm->reg_irq is NULL\n",
1445                         __func__);
1446                 ret = -EINVAL;
1447                 goto err_pdata_fail;
1448         }
1449         swrm->master.read = swrm_read;
1450         swrm->master.write = swrm_write;
1451         swrm->master.bulk_write = swrm_bulk_write;
1452         swrm->master.get_logical_dev_num = swrm_get_logical_dev_num;
1453         swrm->master.connect_port = swrm_connect_port;
1454         swrm->master.disconnect_port = swrm_disconnect_port;
1455         swrm->master.slvdev_datapath_control = swrm_slvdev_datapath_control;
1456         swrm->master.remove_from_group = swrm_remove_from_group;
1457         swrm->master.dev.parent = &pdev->dev;
1458         swrm->master.dev.of_node = pdev->dev.of_node;
1459         swrm->master.num_port = 0;
1460         swrm->num_enum_slaves = 0;
1461         swrm->rcmd_id = 0;
1462         swrm->wcmd_id = 0;
1463         swrm->slave_status = 0;
1464         swrm->num_rx_chs = 0;
1465         swrm->clk_ref_count = 0;
1466         swrm->state = SWR_MSTR_RESUME;
1467         init_completion(&swrm->reset);
1468         init_completion(&swrm->broadcast);
1469         mutex_init(&swrm->mlock);
1470         INIT_LIST_HEAD(&swrm->mport_list);
1471         mutex_init(&swrm->reslock);
1472
1473         ret = swrm->reg_irq(swrm->handle, swr_mstr_interrupt, swrm,
1474                             SWR_IRQ_REGISTER);
1475         if (ret) {
1476                 dev_err(&pdev->dev, "%s: IRQ register failed ret %d\n",
1477                         __func__, ret);
1478                 goto err_irq_fail;
1479         }
1480
1481         ret = swr_register_master(&swrm->master);
1482         if (ret) {
1483                 dev_err(&pdev->dev, "%s: error adding swr master\n", __func__);
1484                 goto err_mstr_fail;
1485         }
1486
1487         /* Add devices registered with board-info as the
1488            controller will be up now
1489          */
1490         swr_master_add_boarddevices(&swrm->master);
1491         mutex_lock(&swrm->mlock);
1492         swrm_clk_request(swrm, true);
1493         ret = swrm_master_init(swrm);
1494         if (ret < 0) {
1495                 dev_err(&pdev->dev,
1496                         "%s: Error in master Initializaiton, err %d\n",
1497                         __func__, ret);
1498                 mutex_unlock(&swrm->mlock);
1499                 goto err_mstr_fail;
1500         }
1501         swrm->version = swrm->read(swrm->handle, SWRM_COMP_HW_VERSION);
1502
1503         mutex_unlock(&swrm->mlock);
1504
1505         if (pdev->dev.of_node)
1506                 of_register_swr_devices(&swrm->master);
1507
1508         dbgswrm = swrm;
1509         debugfs_swrm_dent = debugfs_create_dir(dev_name(&pdev->dev), 0);
1510         if (!IS_ERR(debugfs_swrm_dent)) {
1511                 debugfs_peek = debugfs_create_file("swrm_peek",
1512                                 S_IFREG | S_IRUGO, debugfs_swrm_dent,
1513                                 (void *) "swrm_peek", &swrm_debug_ops);
1514
1515                 debugfs_poke = debugfs_create_file("swrm_poke",
1516                                 S_IFREG | S_IRUGO, debugfs_swrm_dent,
1517                                 (void *) "swrm_poke", &swrm_debug_ops);
1518
1519                 debugfs_reg_dump = debugfs_create_file("swrm_reg_dump",
1520                                    S_IFREG | S_IRUGO, debugfs_swrm_dent,
1521                                    (void *) "swrm_reg_dump",
1522                                    &swrm_debug_ops);
1523         }
1524         pm_runtime_set_autosuspend_delay(&pdev->dev, auto_suspend_timer);
1525         pm_runtime_use_autosuspend(&pdev->dev);
1526         pm_runtime_set_active(&pdev->dev);
1527         pm_runtime_enable(&pdev->dev);
1528         pm_runtime_mark_last_busy(&pdev->dev);
1529
1530         return 0;
1531 err_mstr_fail:
1532         swrm->reg_irq(swrm->handle, swr_mstr_interrupt,
1533                         swrm, SWR_IRQ_FREE);
1534 err_irq_fail:
1535 err_pdata_fail:
1536         kfree(swrm);
1537 err_memory_fail:
1538         return ret;
1539 }
1540
1541 static int swrm_remove(struct platform_device *pdev)
1542 {
1543         struct swr_mstr_ctrl *swrm = platform_get_drvdata(pdev);
1544
1545         swrm->reg_irq(swrm->handle, swr_mstr_interrupt,
1546                         swrm, SWR_IRQ_FREE);
1547         if (swrm->mstr_port) {
1548                 kfree(swrm->mstr_port->port);
1549                 swrm->mstr_port->port = NULL;
1550                 kfree(swrm->mstr_port);
1551                 swrm->mstr_port = NULL;
1552         }
1553         pm_runtime_disable(&pdev->dev);
1554         pm_runtime_set_suspended(&pdev->dev);
1555         swr_unregister_master(&swrm->master);
1556         mutex_destroy(&swrm->mlock);
1557         mutex_destroy(&swrm->reslock);
1558         kfree(swrm);
1559         return 0;
1560 }
1561
1562 static int swrm_clk_pause(struct swr_mstr_ctrl *swrm)
1563 {
1564         u32 val;
1565
1566         dev_dbg(swrm->dev, "%s: state: %d\n", __func__, swrm->state);
1567         swrm->write(swrm->handle, SWRM_INTERRUPT_MASK_ADDR, 0x1FDFD);
1568         val = swrm->read(swrm->handle, SWRM_MCP_CFG_ADDR);
1569         val |= SWRM_MCP_CFG_BUS_CLK_PAUSE_BMSK;
1570         swrm->write(swrm->handle, SWRM_MCP_CFG_ADDR, val);
1571         swrm->state = SWR_MSTR_PAUSE;
1572
1573         return 0;
1574 }
1575
1576 #ifdef CONFIG_PM
1577 static int swrm_runtime_resume(struct device *dev)
1578 {
1579         struct platform_device *pdev = to_platform_device(dev);
1580         struct swr_mstr_ctrl *swrm = platform_get_drvdata(pdev);
1581         int ret = 0;
1582         struct swr_master *mstr = &swrm->master;
1583         struct swr_device *swr_dev;
1584
1585         dev_dbg(dev, "%s: pm_runtime: resume, state:%d\n",
1586                 __func__, swrm->state);
1587         mutex_lock(&swrm->reslock);
1588         if ((swrm->state == SWR_MSTR_PAUSE) ||
1589             (swrm->state == SWR_MSTR_DOWN)) {
1590                 if (swrm->state == SWR_MSTR_DOWN) {
1591                         if (swrm_clk_request(swrm, true))
1592                                 goto exit;
1593                 }
1594                 list_for_each_entry(swr_dev, &mstr->devices, dev_list) {
1595                         ret = swr_device_up(swr_dev);
1596                         if (ret) {
1597                                 dev_err(dev,
1598                                         "%s: failed to wakeup swr dev %d\n",
1599                                         __func__, swr_dev->dev_num);
1600                                 swrm_clk_request(swrm, false);
1601                                 goto exit;
1602                         }
1603                 }
1604                 swrm->write(swrm->handle, SWRM_COMP_SW_RESET, 0x01);
1605                 swrm->write(swrm->handle, SWRM_COMP_SW_RESET, 0x01);
1606                 swrm_master_init(swrm);
1607         }
1608 exit:
1609         pm_runtime_set_autosuspend_delay(&pdev->dev, auto_suspend_timer);
1610         mutex_unlock(&swrm->reslock);
1611         return ret;
1612 }
1613
1614 static int swrm_runtime_suspend(struct device *dev)
1615 {
1616         struct platform_device *pdev = to_platform_device(dev);
1617         struct swr_mstr_ctrl *swrm = platform_get_drvdata(pdev);
1618         int ret = 0;
1619         struct swr_master *mstr = &swrm->master;
1620         struct swr_device *swr_dev;
1621
1622         dev_dbg(dev, "%s: pm_runtime: suspend state: %d\n",
1623                 __func__, swrm->state);
1624         mutex_lock(&swrm->reslock);
1625         if ((swrm->state == SWR_MSTR_RESUME) ||
1626             (swrm->state == SWR_MSTR_UP)) {
1627                 if (swrm_is_port_en(&swrm->master)) {
1628                         dev_dbg(dev, "%s ports are enabled\n", __func__);
1629                         ret = -EBUSY;
1630                         goto exit;
1631                 }
1632                 swrm_clk_pause(swrm);
1633                 swrm->write(swrm->handle, SWRM_COMP_CFG_ADDR, 0x00);
1634                 list_for_each_entry(swr_dev, &mstr->devices, dev_list) {
1635                         ret = swr_device_down(swr_dev);
1636                         if (ret) {
1637                                 dev_err(dev,
1638                                         "%s: failed to shutdown swr dev %d\n",
1639                                         __func__, swr_dev->dev_num);
1640                                 goto exit;
1641                         }
1642                 }
1643                 swrm_clk_request(swrm, false);
1644         }
1645 exit:
1646         mutex_unlock(&swrm->reslock);
1647         return ret;
1648 }
1649 #endif /* CONFIG_PM */
1650
1651 static int swrm_device_down(struct device *dev)
1652 {
1653         struct platform_device *pdev = to_platform_device(dev);
1654         struct swr_mstr_ctrl *swrm = platform_get_drvdata(pdev);
1655         int ret = 0;
1656         struct swr_master *mstr = &swrm->master;
1657         struct swr_device *swr_dev;
1658
1659         dev_dbg(dev, "%s: swrm state: %d\n", __func__, swrm->state);
1660         mutex_lock(&swrm->reslock);
1661         if ((swrm->state == SWR_MSTR_RESUME) ||
1662             (swrm->state == SWR_MSTR_UP)) {
1663                 list_for_each_entry(swr_dev, &mstr->devices, dev_list) {
1664                         ret = swr_device_down(swr_dev);
1665                         if (ret)
1666                                 dev_err(dev,
1667                                         "%s: failed to shutdown swr dev %d\n",
1668                                         __func__, swr_dev->dev_num);
1669                 }
1670                 dev_dbg(dev, "%s: Shutting down SWRM\n", __func__);
1671                 pm_runtime_disable(dev);
1672                 pm_runtime_set_suspended(dev);
1673                 pm_runtime_enable(dev);
1674                 swrm_clk_request(swrm, false);
1675         }
1676         mutex_unlock(&swrm->reslock);
1677         return ret;
1678 }
1679
1680 /**
1681  * swrm_wcd_notify - parent device can notify to soundwire master through
1682  * this function
1683  * @pdev: pointer to platform device structure
1684  * @id: command id from parent to the soundwire master
1685  * @data: data from parent device to soundwire master
1686  */
1687 int swrm_wcd_notify(struct platform_device *pdev, u32 id, void *data)
1688 {
1689         struct swr_mstr_ctrl *swrm;
1690         int ret = 0;
1691         struct swr_master *mstr;
1692         struct swr_device *swr_dev;
1693
1694         if (!pdev) {
1695                 pr_err("%s: pdev is NULL\n", __func__);
1696                 return -EINVAL;
1697         }
1698         swrm = platform_get_drvdata(pdev);
1699         if (!swrm) {
1700                 dev_err(&pdev->dev, "%s: swrm is NULL\n", __func__);
1701                 return -EINVAL;
1702         }
1703         mstr = &swrm->master;
1704
1705         switch (id) {
1706         case SWR_CH_MAP:
1707                 if (!data) {
1708                         dev_err(swrm->dev, "%s: data is NULL\n", __func__);
1709                         ret = -EINVAL;
1710                 } else {
1711                         ret = swrm_set_ch_map(swrm, data);
1712                 }
1713                 break;
1714         case SWR_DEVICE_DOWN:
1715                 dev_dbg(swrm->dev, "%s: swr master down called\n", __func__);
1716                 mutex_lock(&swrm->mlock);
1717                 if ((swrm->state == SWR_MSTR_PAUSE) ||
1718                     (swrm->state == SWR_MSTR_DOWN))
1719                         dev_dbg(swrm->dev, "%s: SWR master is already Down: %d\n",
1720                                 __func__, swrm->state);
1721                 else
1722                         swrm_device_down(&pdev->dev);
1723                 mutex_unlock(&swrm->mlock);
1724                 break;
1725         case SWR_DEVICE_UP:
1726                 dev_dbg(swrm->dev, "%s: swr master up called\n", __func__);
1727                 mutex_lock(&swrm->mlock);
1728                 mutex_lock(&swrm->reslock);
1729                 if ((swrm->state == SWR_MSTR_RESUME) ||
1730                     (swrm->state == SWR_MSTR_UP)) {
1731                         dev_dbg(swrm->dev, "%s: SWR master is already UP: %d\n",
1732                                 __func__, swrm->state);
1733                         list_for_each_entry(swr_dev, &mstr->devices, dev_list)
1734                                 swr_reset_device(swr_dev);
1735                 } else {
1736                         pm_runtime_mark_last_busy(&pdev->dev);
1737                         mutex_unlock(&swrm->reslock);
1738                         pm_runtime_get_sync(&pdev->dev);
1739                         mutex_lock(&swrm->reslock);
1740                         list_for_each_entry(swr_dev, &mstr->devices, dev_list) {
1741                                 ret = swr_reset_device(swr_dev);
1742                                 if (ret) {
1743                                         dev_err(swrm->dev,
1744                                                 "%s: failed to reset swr device %d\n",
1745                                                 __func__, swr_dev->dev_num);
1746                                         swrm_clk_request(swrm, false);
1747                                 }
1748                         }
1749                         pm_runtime_mark_last_busy(&pdev->dev);
1750                         pm_runtime_put_autosuspend(&pdev->dev);
1751                 }
1752                 mutex_unlock(&swrm->reslock);
1753                 mutex_unlock(&swrm->mlock);
1754                 break;
1755         case SWR_SET_NUM_RX_CH:
1756                 if (!data) {
1757                         dev_err(swrm->dev, "%s: data is NULL\n", __func__);
1758                         ret = -EINVAL;
1759                 } else {
1760                         mutex_lock(&swrm->mlock);
1761                         swrm->num_rx_chs = *(int *)data;
1762                         if ((swrm->num_rx_chs > 1) && !swrm->num_cfg_devs) {
1763                                 list_for_each_entry(swr_dev, &mstr->devices,
1764                                                     dev_list) {
1765                                         ret = swr_set_device_group(swr_dev,
1766                                                                 SWR_BROADCAST);
1767                                         if (ret)
1768                                                 dev_err(swrm->dev,
1769                                                         "%s: set num ch failed\n",
1770                                                         __func__);
1771                                 }
1772                         } else {
1773                                 list_for_each_entry(swr_dev, &mstr->devices,
1774                                                     dev_list) {
1775                                         ret = swr_set_device_group(swr_dev,
1776                                                                 SWR_GROUP_NONE);
1777                                         if (ret)
1778                                                 dev_err(swrm->dev,
1779                                                         "%s: set num ch failed\n",
1780                                                         __func__);
1781                                 }
1782                         }
1783                         mutex_unlock(&swrm->mlock);
1784                 }
1785                 break;
1786         default:
1787                 dev_err(swrm->dev, "%s: swr master unknown id %d\n",
1788                         __func__, id);
1789                 break;
1790         }
1791         return ret;
1792 }
1793 EXPORT_SYMBOL(swrm_wcd_notify);
1794
1795 #ifdef CONFIG_PM_SLEEP
1796 static int swrm_suspend(struct device *dev)
1797 {
1798         int ret = -EBUSY;
1799         struct platform_device *pdev = to_platform_device(dev);
1800         struct swr_mstr_ctrl *swrm = platform_get_drvdata(pdev);
1801
1802         dev_dbg(dev, "%s: system suspend, state: %d\n", __func__, swrm->state);
1803         if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) {
1804                 ret = swrm_runtime_suspend(dev);
1805                 if (!ret) {
1806                         /*
1807                          * Synchronize runtime-pm and system-pm states:
1808                          * At this point, we are already suspended. If
1809                          * runtime-pm still thinks its active, then
1810                          * make sure its status is in sync with HW
1811                          * status. The three below calls let the
1812                          * runtime-pm know that we are suspended
1813                          * already without re-invoking the suspend
1814                          * callback
1815                          */
1816                         pm_runtime_disable(dev);
1817                         pm_runtime_set_suspended(dev);
1818                         pm_runtime_enable(dev);
1819                 }
1820         }
1821         if (ret == -EBUSY) {
1822                 /*
1823                  * There is a possibility that some audio stream is active
1824                  * during suspend. We dont want to return suspend failure in
1825                  * that case so that display and relevant components can still
1826                  * go to suspend.
1827                  * If there is some other error, then it should be passed-on
1828                  * to system level suspend
1829                  */
1830                 ret = 0;
1831         }
1832         return ret;
1833 }
1834
1835 static int swrm_resume(struct device *dev)
1836 {
1837         int ret = 0;
1838         struct platform_device *pdev = to_platform_device(dev);
1839         struct swr_mstr_ctrl *swrm = platform_get_drvdata(pdev);
1840
1841         dev_dbg(dev, "%s: system resume, state: %d\n", __func__, swrm->state);
1842         if (!pm_runtime_enabled(dev) || !pm_runtime_suspend(dev)) {
1843                 ret = swrm_runtime_resume(dev);
1844                 if (!ret) {
1845                         pm_runtime_mark_last_busy(dev);
1846                         pm_request_autosuspend(dev);
1847                 }
1848         }
1849         return ret;
1850 }
1851 #endif /* CONFIG_PM_SLEEP */
1852
1853 static const struct dev_pm_ops swrm_dev_pm_ops = {
1854         SET_SYSTEM_SLEEP_PM_OPS(
1855                 swrm_suspend,
1856                 swrm_resume
1857         )
1858         SET_RUNTIME_PM_OPS(
1859                 swrm_runtime_suspend,
1860                 swrm_runtime_resume,
1861                 NULL
1862         )
1863 };
1864
1865 static struct of_device_id swrm_dt_match[] = {
1866         {
1867                 .compatible = "qcom,swr-wcd",
1868         },
1869         {}
1870 };
1871
1872 static struct platform_driver swr_mstr_driver = {
1873         .probe = swrm_probe,
1874         .remove = swrm_remove,
1875         .driver = {
1876                 .name = SWR_WCD_NAME,
1877                 .owner = THIS_MODULE,
1878                 .pm = &swrm_dev_pm_ops,
1879                 .of_match_table = swrm_dt_match,
1880         },
1881 };
1882
1883 static int __init swrm_init(void)
1884 {
1885         return platform_driver_register(&swr_mstr_driver);
1886 }
1887 subsys_initcall(swrm_init);
1888
1889 static void __exit swrm_exit(void)
1890 {
1891         platform_driver_unregister(&swr_mstr_driver);
1892 }
1893 module_exit(swrm_exit);
1894
1895
1896 MODULE_LICENSE("GPL v2");
1897 MODULE_DESCRIPTION("WCD SoundWire Controller");
1898 MODULE_ALIAS("platform:swr-wcd");