drivers/spi/atmel-quadspi.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Driver for Atmel QSPI Controller
   4  *
   5  * Copyright (C) 2015 Atmel Corporation
   6  * Copyright (C) 2018 Cryptera A/S
   7  *
   8  * Author: Cyrille Pitchen <cyrille.pitchen@atmel.com>
   9  * Author: Piotr Bugalski <bugalski.piotr@gmail.com>
  10  *
  11  * This driver is based on drivers/mtd/spi-nor/fsl-quadspi.c from Freescale.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/delay.h>
  16 #include <linux/err.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/kernel.h>
  20 #include <linux/module.h>
  21 #include <linux/of.h>
  22 #include <linux/of_platform.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/spi/spi-mem.h>
  25
  26 /* QSPI register offsets */
  27 #define QSPI_CR      0x0000  /* Control Register */
  28 #define QSPI_MR      0x0004  /* Mode Register */
  29 #define QSPI_RD      0x0008  /* Receive Data Register */
  30 #define QSPI_TD      0x000c  /* Transmit Data Register */
  31 #define QSPI_SR      0x0010  /* Status Register */
  32 #define QSPI_IER     0x0014  /* Interrupt Enable Register */
  33 #define QSPI_IDR     0x0018  /* Interrupt Disable Register */
  34 #define QSPI_IMR     0x001c  /* Interrupt Mask Register */
  35 #define QSPI_SCR     0x0020  /* Serial Clock Register */
  36
  37 #define QSPI_IAR     0x0030  /* Instruction Address Register */
  38 #define QSPI_ICR     0x0034  /* Instruction Code Register */
  39 #define QSPI_WICR    0x0034  /* Write Instruction Code Register */
  40 #define QSPI_IFR     0x0038  /* Instruction Frame Register */
  41 #define QSPI_RICR    0x003C  /* Read Instruction Code Register */
  42
  43 #define QSPI_SMR     0x0040  /* Scrambling Mode Register */
  44 #define QSPI_SKR     0x0044  /* Scrambling Key Register */
  45
  46 #define QSPI_WPMR    0x00E4  /* Write Protection Mode Register */
  47 #define QSPI_WPSR    0x00E8  /* Write Protection Status Register */
  48
  49 #define QSPI_VERSION 0x00FC  /* Version Register */
  50
  51
  52 /* Bitfields in QSPI_CR (Control Register) */
  53 #define QSPI_CR_QSPIEN                  BIT(0)
  54 #define QSPI_CR_QSPIDIS                 BIT(1)
  55 #define QSPI_CR_SWRST                   BIT(7)
  56 #define QSPI_CR_LASTXFER                BIT(24)
  57
  58 /* Bitfields in QSPI_MR (Mode Register) */
  59 #define QSPI_MR_SMM                     BIT(0)
  60 #define QSPI_MR_LLB                     BIT(1)
  61 #define QSPI_MR_WDRBT                   BIT(2)
  62 #define QSPI_MR_SMRM                    BIT(3)
  63 #define QSPI_MR_CSMODE_MASK             GENMASK(5, 4)
  64 #define QSPI_MR_CSMODE_NOT_RELOADED     (0 << 4)
  65 #define QSPI_MR_CSMODE_LASTXFER         (1 << 4)
  66 #define QSPI_MR_CSMODE_SYSTEMATICALLY   (2 << 4)
  67 #define QSPI_MR_NBBITS_MASK             GENMASK(11, 8)
  68 #define QSPI_MR_NBBITS(n)               ((((n) - 8) << 8) & QSPI_MR_NBBITS_MASK)
  69 #define QSPI_MR_DLYBCT_MASK             GENMASK(23, 16)
  70 #define QSPI_MR_DLYBCT(n)               (((n) << 16) & QSPI_MR_DLYBCT_MASK)
  71 #define QSPI_MR_DLYCS_MASK              GENMASK(31, 24)
  72 #define QSPI_MR_DLYCS(n)                (((n) << 24) & QSPI_MR_DLYCS_MASK)
  73
  74 /* Bitfields in QSPI_SR/QSPI_IER/QSPI_IDR/QSPI_IMR  */
  75 #define QSPI_SR_RDRF                    BIT(0)
  76 #define QSPI_SR_TDRE                    BIT(1)
  77 #define QSPI_SR_TXEMPTY                 BIT(2)
  78 #define QSPI_SR_OVRES                   BIT(3)
  79 #define QSPI_SR_CSR                     BIT(8)
  80 #define QSPI_SR_CSS                     BIT(9)
  81 #define QSPI_SR_INSTRE                  BIT(10)
  82 #define QSPI_SR_QSPIENS                 BIT(24)
  83
  84 #define QSPI_SR_CMD_COMPLETED   (QSPI_SR_INSTRE | QSPI_SR_CSR)
  85
  86 /* Bitfields in QSPI_SCR (Serial Clock Register) */
  87 #define QSPI_SCR_CPOL                   BIT(0)
  88 #define QSPI_SCR_CPHA                   BIT(1)
  89 #define QSPI_SCR_SCBR_MASK              GENMASK(15, 8)
  90 #define QSPI_SCR_SCBR(n)                (((n) << 8) & QSPI_SCR_SCBR_MASK)
  91 #define QSPI_SCR_DLYBS_MASK             GENMASK(23, 16)
  92 #define QSPI_SCR_DLYBS(n)               (((n) << 16) & QSPI_SCR_DLYBS_MASK)
  93
  94 /* Bitfields in QSPI_ICR (Read/Write Instruction Code Register) */
  95 #define QSPI_ICR_INST_MASK              GENMASK(7, 0)
  96 #define QSPI_ICR_INST(inst)             (((inst) << 0) & QSPI_ICR_INST_MASK)
  97 #define QSPI_ICR_OPT_MASK               GENMASK(23, 16)
  98 #define QSPI_ICR_OPT(opt)               (((opt) << 16) & QSPI_ICR_OPT_MASK)
  99
 100 /* Bitfields in QSPI_IFR (Instruction Frame Register) */
 101 #define QSPI_IFR_WIDTH_MASK             GENMASK(2, 0)
 102 #define QSPI_IFR_WIDTH_SINGLE_BIT_SPI   (0 << 0)
 103 #define QSPI_IFR_WIDTH_DUAL_OUTPUT      (1 << 0)
 104 #define QSPI_IFR_WIDTH_QUAD_OUTPUT      (2 << 0)
 105 #define QSPI_IFR_WIDTH_DUAL_IO          (3 << 0)
 106 #define QSPI_IFR_WIDTH_QUAD_IO          (4 << 0)
 107 #define QSPI_IFR_WIDTH_DUAL_CMD         (5 << 0)
 108 #define QSPI_IFR_WIDTH_QUAD_CMD         (6 << 0)
 109 #define QSPI_IFR_INSTEN                 BIT(4)
 110 #define QSPI_IFR_ADDREN                 BIT(5)
 111 #define QSPI_IFR_OPTEN                  BIT(6)
 112 #define QSPI_IFR_DATAEN                 BIT(7)
 113 #define QSPI_IFR_OPTL_MASK              GENMASK(9, 8)
 114 #define QSPI_IFR_OPTL_1BIT              (0 << 8)
 115 #define QSPI_IFR_OPTL_2BIT              (1 << 8)
 116 #define QSPI_IFR_OPTL_4BIT              (2 << 8)
 117 #define QSPI_IFR_OPTL_8BIT              (3 << 8)
 118 #define QSPI_IFR_ADDRL                  BIT(10)
 119 #define QSPI_IFR_TFRTYP_MEM             BIT(12)
 120 #define QSPI_IFR_SAMA5D2_WRITE_TRSFR    BIT(13)
 121 #define QSPI_IFR_CRM                    BIT(14)
 122 #define QSPI_IFR_NBDUM_MASK             GENMASK(20, 16)
 123 #define QSPI_IFR_NBDUM(n)               (((n) << 16) & QSPI_IFR_NBDUM_MASK)
 124 #define QSPI_IFR_APBTFRTYP_READ         BIT(24) /* Defined in SAM9X60 */
 125
 126 /* Bitfields in QSPI_SMR (Scrambling Mode Register) */
 127 #define QSPI_SMR_SCREN                  BIT(0)
 128 #define QSPI_SMR_RVDIS                  BIT(1)
 129
 130 /* Bitfields in QSPI_WPMR (Write Protection Mode Register) */
 131 #define QSPI_WPMR_WPEN                  BIT(0)
 132 #define QSPI_WPMR_WPKEY_MASK            GENMASK(31, 8)
 133 #define QSPI_WPMR_WPKEY(wpkey)          (((wpkey) << 8) & QSPI_WPMR_WPKEY_MASK)
 134
 135 /* Bitfields in QSPI_WPSR (Write Protection Status Register) */
 136 #define QSPI_WPSR_WPVS                  BIT(0)
 137 #define QSPI_WPSR_WPVSRC_MASK           GENMASK(15, 8)
 138 #define QSPI_WPSR_WPVSRC(src)           (((src) << 8) & QSPI_WPSR_WPVSRC)
 139
 140 struct atmel_qspi_caps {
 141         bool has_qspick;
 142         bool has_ricr;
 143 };
 144
 145 struct atmel_qspi {
 146         void __iomem            *regs;
 147         void __iomem            *mem;
 148         struct clk              *pclk;
 149         struct clk              *qspick;
 150         struct platform_device  *pdev;
 151         const struct atmel_qspi_caps *caps;
 152         u32                     pending;
 153         u32                     mr;
 154         u32                     scr;
 155         struct completion       cmd_completion;
 156 };
 157
 158 struct atmel_qspi_mode {
 159         u8 cmd_buswidth;
 160         u8 addr_buswidth;
 161         u8 data_buswidth;
 162         u32 config;
 163 };
 164
 165 static const struct atmel_qspi_mode atmel_qspi_modes[] = {
 166         { 1, 1, 1, QSPI_IFR_WIDTH_SINGLE_BIT_SPI },
 167         { 1, 1, 2, QSPI_IFR_WIDTH_DUAL_OUTPUT },
 168         { 1, 1, 4, QSPI_IFR_WIDTH_QUAD_OUTPUT },
 169         { 1, 2, 2, QSPI_IFR_WIDTH_DUAL_IO },
 170         { 1, 4, 4, QSPI_IFR_WIDTH_QUAD_IO },
 171         { 2, 2, 2, QSPI_IFR_WIDTH_DUAL_CMD },
 172         { 4, 4, 4, QSPI_IFR_WIDTH_QUAD_CMD },
 173 };
 174
 175 static inline bool atmel_qspi_is_compatible(const struct spi_mem_op *op,
 176                                             const struct atmel_qspi_mode *mode)
 177 {
 178         if (op->cmd.buswidth != mode->cmd_buswidth)
 179                 return false;
 180
 181         if (op->addr.nbytes && op->addr.buswidth != mode->addr_buswidth)
 182                 return false;
 183
 184         if (op->data.nbytes && op->data.buswidth != mode->data_buswidth)
 185                 return false;
 186
 187         return true;
 188 }
 189
 190 static int atmel_qspi_find_mode(const struct spi_mem_op *op)
 191 {
 192         u32 i;
 193
 194         for (i = 0; i < ARRAY_SIZE(atmel_qspi_modes); i++)
 195                 if (atmel_qspi_is_compatible(op, &atmel_qspi_modes[i]))
 196                         return i;
 197
 198         return -ENOTSUPP;
 199 }
 200
 201 static bool atmel_qspi_supports_op(struct spi_mem *mem,
 202                                    const struct spi_mem_op *op)
 203 {
 204         if (atmel_qspi_find_mode(op) < 0)
 205                 return false;
 206
 207         /* special case not supported by hardware */
 208         if (op->addr.nbytes == 2 && op->cmd.buswidth != op->addr.buswidth &&
 209                 op->dummy.nbytes == 0)
 210                 return false;
 211
 212         return true;
 213 }
 214
 215 static int atmel_qspi_set_cfg(struct atmel_qspi *aq,
 216                               const struct spi_mem_op *op, u32 *offset)
 217 {
 218         u32 iar, icr, ifr;
 219         u32 dummy_cycles = 0;
 220         int mode;
 221
 222         iar = 0;
 223         icr = QSPI_ICR_INST(op->cmd.opcode);
 224         ifr = QSPI_IFR_INSTEN;
 225
 226         mode = atmel_qspi_find_mode(op);
 227         if (mode < 0)
 228                 return mode;
 229         ifr |= atmel_qspi_modes[mode].config;
 230
 231         if (op->dummy.buswidth && op->dummy.nbytes)
 232                 dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth;
 233
 234         /*
 235          * The controller allows 24 and 32-bit addressing while NAND-flash
 236          * requires 16-bit long. Handling 8-bit long addresses is done using
 237          * the option field. For the 16-bit addresses, the workaround depends
 238          * of the number of requested dummy bits. If there are 8 or more dummy
 239          * cycles, the address is shifted and sent with the first dummy byte.
 240          * Otherwise opcode is disabled and the first byte of the address
 241          * contains the command opcode (works only if the opcode and address
 242          * use the same buswidth). The limitation is when the 16-bit address is
 243          * used without enough dummy cycles and the opcode is using a different
 244          * buswidth than the address.
 245          */
 246         if (op->addr.buswidth) {
 247                 switch (op->addr.nbytes) {
 248                 case 0:
 249                         break;
 250                 case 1:
 251                         ifr |= QSPI_IFR_OPTEN | QSPI_IFR_OPTL_8BIT;
 252                         icr |= QSPI_ICR_OPT(op->addr.val & 0xff);
 253                         break;
 254                 case 2:
 255                         if (dummy_cycles < 8 / op->addr.buswidth) {
 256                                 ifr &= ~QSPI_IFR_INSTEN;
 257                                 ifr |= QSPI_IFR_ADDREN;
 258                                 iar = (op->cmd.opcode << 16) |
 259                                         (op->addr.val & 0xffff);
 260                         } else {
 261                                 ifr |= QSPI_IFR_ADDREN;
 262                                 iar = (op->addr.val << 8) & 0xffffff;
 263                                 dummy_cycles -= 8 / op->addr.buswidth;
 264                         }
 265                         break;
 266                 case 3:
 267                         ifr |= QSPI_IFR_ADDREN;
 268                         iar = op->addr.val & 0xffffff;
 269                         break;
 270                 case 4:
 271                         ifr |= QSPI_IFR_ADDREN | QSPI_IFR_ADDRL;
 272                         iar = op->addr.val & 0x7ffffff;
 273                         break;
 274                 default:
 275                         return -ENOTSUPP;
 276                 }
 277         }
 278
 279         /* offset of the data access in the QSPI memory space */
 280         *offset = iar;
 281
 282         /* Set number of dummy cycles */
 283         if (dummy_cycles)
 284                 ifr |= QSPI_IFR_NBDUM(dummy_cycles);
 285
 286         /* Set data enable */
 287         if (op->data.nbytes)
 288                 ifr |= QSPI_IFR_DATAEN;
 289
 290         /*
 291          * If the QSPI controller is set in regular SPI mode, set it in
 292          * Serial Memory Mode (SMM).
 293          */
 294         if (aq->mr != QSPI_MR_SMM) {
 295                 writel_relaxed(QSPI_MR_SMM, aq->regs + QSPI_MR);
 296                 aq->mr = QSPI_MR_SMM;
 297         }
 298
 299         /* Clear pending interrupts */
 300         (void)readl_relaxed(aq->regs + QSPI_SR);
 301
 302         if (aq->caps->has_ricr) {
 303                 if (!op->addr.nbytes && op->data.dir == SPI_MEM_DATA_IN)
 304                         ifr |= QSPI_IFR_APBTFRTYP_READ;
 305
 306                 /* Set QSPI Instruction Frame registers */
 307                 writel_relaxed(iar, aq->regs + QSPI_IAR);
 308                 if (op->data.dir == SPI_MEM_DATA_IN)
 309                         writel_relaxed(icr, aq->regs + QSPI_RICR);
 310                 else
 311                         writel_relaxed(icr, aq->regs + QSPI_WICR);
 312                 writel_relaxed(ifr, aq->regs + QSPI_IFR);
 313         } else {
 314                 if (op->data.dir == SPI_MEM_DATA_OUT)
 315                         ifr |= QSPI_IFR_SAMA5D2_WRITE_TRSFR;
 316
 317                 /* Set QSPI Instruction Frame registers */
 318                 writel_relaxed(iar, aq->regs + QSPI_IAR);
 319                 writel_relaxed(icr, aq->regs + QSPI_ICR);
 320                 writel_relaxed(ifr, aq->regs + QSPI_IFR);
 321         }
 322
 323         return 0;
 324 }
 325
 326 static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
 327 {
 328         struct atmel_qspi *aq = spi_controller_get_devdata(mem->spi->master);
 329         u32 sr, offset;
 330         int err;
 331
 332         err = atmel_qspi_set_cfg(aq, op, &offset);
 333         if (err)
 334                 return err;
 335
 336         /* Skip to the final steps if there is no data */
 337         if (op->data.nbytes) {
 338                 /* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */
 339                 (void)readl_relaxed(aq->regs + QSPI_IFR);
 340
 341                 /* Send/Receive data */
 342                 if (op->data.dir == SPI_MEM_DATA_IN)
 343                         _memcpy_fromio(op->data.buf.in, aq->mem + offset,
 344                                        op->data.nbytes);
 345                 else
 346                         _memcpy_toio(aq->mem + offset, op->data.buf.out,
 347                                      op->data.nbytes);
 348
 349                 /* Release the chip-select */
 350                 writel_relaxed(QSPI_CR_LASTXFER, aq->regs + QSPI_CR);
 351         }
 352
 353         /* Poll INSTRuction End status */
 354         sr = readl_relaxed(aq->regs + QSPI_SR);
 355         if ((sr & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED)
 356                 return err;
 357
 358         /* Wait for INSTRuction End interrupt */
 359         reinit_completion(&aq->cmd_completion);
 360         aq->pending = sr & QSPI_SR_CMD_COMPLETED;
 361         writel_relaxed(QSPI_SR_CMD_COMPLETED, aq->regs + QSPI_IER);
 362         if (!wait_for_completion_timeout(&aq->cmd_completion,
 363                                          msecs_to_jiffies(1000)))
 364                 err = -ETIMEDOUT;
 365         writel_relaxed(QSPI_SR_CMD_COMPLETED, aq->regs + QSPI_IDR);
 366
 367         return err;
 368 }
 369
 370 static const char *atmel_qspi_get_name(struct spi_mem *spimem)
 371 {
 372         return dev_name(spimem->spi->dev.parent);
 373 }
 374
 375 static const struct spi_controller_mem_ops atmel_qspi_mem_ops = {
 376         .supports_op = atmel_qspi_supports_op,
 377         .exec_op = atmel_qspi_exec_op,
 378         .get_name = atmel_qspi_get_name
 379 };
 380
 381 static int atmel_qspi_setup(struct spi_device *spi)
 382 {
 383         struct spi_controller *ctrl = spi->master;
 384         struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
 385         unsigned long src_rate;
 386         u32 scbr;
 387
 388         if (ctrl->busy)
 389                 return -EBUSY;
 390
 391         if (!spi->max_speed_hz)
 392                 return -EINVAL;
 393
 394         src_rate = clk_get_rate(aq->pclk);
 395         if (!src_rate)
 396                 return -EINVAL;
 397
 398         /* Compute the QSPI baudrate */
 399         scbr = DIV_ROUND_UP(src_rate, spi->max_speed_hz);
 400         if (scbr > 0)
 401                 scbr--;
 402
 403         aq->scr = QSPI_SCR_SCBR(scbr);
 404         writel_relaxed(aq->scr, aq->regs + QSPI_SCR);
 405
 406         return 0;
 407 }
 408
 409 static void atmel_qspi_init(struct atmel_qspi *aq)
 410 {
 411         /* Reset the QSPI controller */
 412         writel_relaxed(QSPI_CR_SWRST, aq->regs + QSPI_CR);
 413
 414         /* Set the QSPI controller by default in Serial Memory Mode */
 415         writel_relaxed(QSPI_MR_SMM, aq->regs + QSPI_MR);
 416         aq->mr = QSPI_MR_SMM;
 417
 418         /* Enable the QSPI controller */
 419         writel_relaxed(QSPI_CR_QSPIEN, aq->regs + QSPI_CR);
 420 }
 421
 422 static irqreturn_t atmel_qspi_interrupt(int irq, void *dev_id)
 423 {
 424         struct atmel_qspi *aq = dev_id;
 425         u32 status, mask, pending;
 426
 427         status = readl_relaxed(aq->regs + QSPI_SR);
 428         mask = readl_relaxed(aq->regs + QSPI_IMR);
 429         pending = status & mask;
 430
 431         if (!pending)
 432                 return IRQ_NONE;
 433
 434         aq->pending |= pending;
 435         if ((aq->pending & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED)
 436                 complete(&aq->cmd_completion);
 437
 438         return IRQ_HANDLED;
 439 }
 440
 441 static int atmel_qspi_probe(struct platform_device *pdev)
 442 {
 443         struct spi_controller *ctrl;
 444         struct atmel_qspi *aq;
 445         struct resource *res;
 446         int irq, err = 0;
 447
 448         ctrl = spi_alloc_master(&pdev->dev, sizeof(*aq));
 449         if (!ctrl)
 450                 return -ENOMEM;
 451
 452         ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD;
 453         ctrl->setup = atmel_qspi_setup;
 454         ctrl->bus_num = -1;
 455         ctrl->mem_ops = &atmel_qspi_mem_ops;
 456         ctrl->num_chipselect = 1;
 457         ctrl->dev.of_node = pdev->dev.of_node;
 458         platform_set_drvdata(pdev, ctrl);
 459
 460         aq = spi_controller_get_devdata(ctrl);
 461
 462         init_completion(&aq->cmd_completion);
 463         aq->pdev = pdev;
 464
 465         /* Map the registers */
 466         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
 467         aq->regs = devm_ioremap_resource(&pdev->dev, res);
 468         if (IS_ERR(aq->regs)) {
 469                 dev_err(&pdev->dev, "missing registers\n");
 470                 err = PTR_ERR(aq->regs);
 471                 goto exit;
 472         }
 473
 474         /* Map the AHB memory */
 475         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_mmap");
 476         aq->mem = devm_ioremap_resource(&pdev->dev, res);
 477         if (IS_ERR(aq->mem)) {
 478                 dev_err(&pdev->dev, "missing AHB memory\n");
 479                 err = PTR_ERR(aq->mem);
 480                 goto exit;
 481         }
 482
 483         /* Get the peripheral clock */
 484         aq->pclk = devm_clk_get(&pdev->dev, "pclk");
 485         if (IS_ERR(aq->pclk))
 486                 aq->pclk = devm_clk_get(&pdev->dev, NULL);
 487
 488         if (IS_ERR(aq->pclk)) {
 489                 dev_err(&pdev->dev, "missing peripheral clock\n");
 490                 err = PTR_ERR(aq->pclk);
 491                 goto exit;
 492         }
 493
 494         /* Enable the peripheral clock */
 495         err = clk_prepare_enable(aq->pclk);
 496         if (err) {
 497                 dev_err(&pdev->dev, "failed to enable the peripheral clock\n");
 498                 goto exit;
 499         }
 500
 501         aq->caps = of_device_get_match_data(&pdev->dev);
 502         if (!aq->caps) {
 503                 dev_err(&pdev->dev, "Could not retrieve QSPI caps\n");
 504                 err = -EINVAL;
 505                 goto exit;
 506         }
 507
 508         if (aq->caps->has_qspick) {
 509                 /* Get the QSPI system clock */
 510                 aq->qspick = devm_clk_get(&pdev->dev, "qspick");
 511                 if (IS_ERR(aq->qspick)) {
 512                         dev_err(&pdev->dev, "missing system clock\n");
 513                         err = PTR_ERR(aq->qspick);
 514                         goto disable_pclk;
 515                 }
 516
 517                 /* Enable the QSPI system clock */
 518                 err = clk_prepare_enable(aq->qspick);
 519                 if (err) {
 520                         dev_err(&pdev->dev,
 521                                 "failed to enable the QSPI system clock\n");
 522                         goto disable_pclk;
 523                 }
 524         }
 525
 526         /* Request the IRQ */
 527         irq = platform_get_irq(pdev, 0);
 528         if (irq < 0) {
 529                 err = irq;
 530                 goto disable_qspick;
 531         }
 532         err = devm_request_irq(&pdev->dev, irq, atmel_qspi_interrupt,
 533                                0, dev_name(&pdev->dev), aq);
 534         if (err)
 535                 goto disable_qspick;
 536
 537         atmel_qspi_init(aq);
 538
 539         err = spi_register_controller(ctrl);
 540         if (err)
 541                 goto disable_qspick;
 542
 543         return 0;
 544
 545 disable_qspick:
 546         clk_disable_unprepare(aq->qspick);
 547 disable_pclk:
 548         clk_disable_unprepare(aq->pclk);
 549 exit:
 550         spi_controller_put(ctrl);
 551
 552         return err;
 553 }
 554
 555 static int atmel_qspi_remove(struct platform_device *pdev)
 556 {
 557         struct spi_controller *ctrl = platform_get_drvdata(pdev);
 558         struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
 559
 560         spi_unregister_controller(ctrl);
 561         writel_relaxed(QSPI_CR_QSPIDIS, aq->regs + QSPI_CR);
 562         clk_disable_unprepare(aq->qspick);
 563         clk_disable_unprepare(aq->pclk);
 564         return 0;
 565 }
 566
 567 static int __maybe_unused atmel_qspi_suspend(struct device *dev)
 568 {
 569         struct spi_controller *ctrl = dev_get_drvdata(dev);
 570         struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
 571
 572         clk_disable_unprepare(aq->qspick);
 573         clk_disable_unprepare(aq->pclk);
 574
 575         return 0;
 576 }
 577
 578 static int __maybe_unused atmel_qspi_resume(struct device *dev)
 579 {
 580         struct spi_controller *ctrl = dev_get_drvdata(dev);
 581         struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
 582
 583         clk_prepare_enable(aq->pclk);
 584         clk_prepare_enable(aq->qspick);
 585
 586         atmel_qspi_init(aq);
 587
 588         writel_relaxed(aq->scr, aq->regs + QSPI_SCR);
 589
 590         return 0;
 591 }
 592
 593 static SIMPLE_DEV_PM_OPS(atmel_qspi_pm_ops, atmel_qspi_suspend,
 594                          atmel_qspi_resume);
 595
 596 static const struct atmel_qspi_caps atmel_sama5d2_qspi_caps = {};
 597
 598 static const struct atmel_qspi_caps atmel_sam9x60_qspi_caps = {
 599         .has_qspick = true,
 600         .has_ricr = true,
 601 };
 602
 603 static const struct of_device_id atmel_qspi_dt_ids[] = {
 604         {
 605                 .compatible = "atmel,sama5d2-qspi",
 606                 .data = &atmel_sama5d2_qspi_caps,
 607         },
 608         {
 609                 .compatible = "microchip,sam9x60-qspi",
 610                 .data = &atmel_sam9x60_qspi_caps,
 611         },
 612         { /* sentinel */ }
 613 };
 614
 615 MODULE_DEVICE_TABLE(of, atmel_qspi_dt_ids);
 616
 617 static struct platform_driver atmel_qspi_driver = {
 618         .driver = {
 619                 .name   = "atmel_qspi",
 620                 .of_match_table = atmel_qspi_dt_ids,
 621                 .pm     = &atmel_qspi_pm_ops,
 622         },
 623         .probe          = atmel_qspi_probe,
 624         .remove         = atmel_qspi_remove,
 625 };
 626 module_platform_driver(atmel_qspi_driver);
 627
 628 MODULE_AUTHOR("Cyrille Pitchen <cyrille.pitchen@atmel.com>");
 629 MODULE_AUTHOR("Piotr Bugalski <bugalski.piotr@gmail.com");
 630 MODULE_DESCRIPTION("Atmel QSPI Controller driver");
 631 MODULE_LICENSE("GPL v2");