1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for Broadcom BRCMSTB, NSP, NS2, Cygnus SPI Controllers
5 * Copyright 2016 Broadcom
9 #include <linux/delay.h>
10 #include <linux/device.h>
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
14 #include <linux/ioport.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
18 #include <linux/of_irq.h>
19 #include <linux/platform_device.h>
20 #include <linux/slab.h>
21 #include <linux/spi/spi.h>
22 #include <linux/spi/spi-mem.h>
23 #include <linux/sysfs.h>
24 #include <linux/types.h>
25 #include "spi-bcm-qspi.h"
27 #define DRIVER_NAME "bcm_qspi"
30 /* BSPI register offsets */
31 #define BSPI_REVISION_ID 0x000
32 #define BSPI_SCRATCH 0x004
33 #define BSPI_MAST_N_BOOT_CTRL 0x008
34 #define BSPI_BUSY_STATUS 0x00c
35 #define BSPI_INTR_STATUS 0x010
36 #define BSPI_B0_STATUS 0x014
37 #define BSPI_B0_CTRL 0x018
38 #define BSPI_B1_STATUS 0x01c
39 #define BSPI_B1_CTRL 0x020
40 #define BSPI_STRAP_OVERRIDE_CTRL 0x024
41 #define BSPI_FLEX_MODE_ENABLE 0x028
42 #define BSPI_BITS_PER_CYCLE 0x02c
43 #define BSPI_BITS_PER_PHASE 0x030
44 #define BSPI_CMD_AND_MODE_BYTE 0x034
45 #define BSPI_BSPI_FLASH_UPPER_ADDR_BYTE 0x038
46 #define BSPI_BSPI_XOR_VALUE 0x03c
47 #define BSPI_BSPI_XOR_ENABLE 0x040
48 #define BSPI_BSPI_PIO_MODE_ENABLE 0x044
49 #define BSPI_BSPI_PIO_IODIR 0x048
50 #define BSPI_BSPI_PIO_DATA 0x04c
52 /* RAF register offsets */
53 #define BSPI_RAF_START_ADDR 0x100
54 #define BSPI_RAF_NUM_WORDS 0x104
55 #define BSPI_RAF_CTRL 0x108
56 #define BSPI_RAF_FULLNESS 0x10c
57 #define BSPI_RAF_WATERMARK 0x110
58 #define BSPI_RAF_STATUS 0x114
59 #define BSPI_RAF_READ_DATA 0x118
60 #define BSPI_RAF_WORD_CNT 0x11c
61 #define BSPI_RAF_CURR_ADDR 0x120
63 /* Override mode masks */
64 #define BSPI_STRAP_OVERRIDE_CTRL_OVERRIDE BIT(0)
65 #define BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL BIT(1)
66 #define BSPI_STRAP_OVERRIDE_CTRL_ADDR_4BYTE BIT(2)
67 #define BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD BIT(3)
68 #define BSPI_STRAP_OVERRIDE_CTRL_ENDAIN_MODE BIT(4)
70 #define BSPI_ADDRLEN_3BYTES 3
71 #define BSPI_ADDRLEN_4BYTES 4
73 #define BSPI_RAF_STATUS_FIFO_EMPTY_MASK BIT(1)
75 #define BSPI_RAF_CTRL_START_MASK BIT(0)
76 #define BSPI_RAF_CTRL_CLEAR_MASK BIT(1)
78 #define BSPI_BPP_MODE_SELECT_MASK BIT(8)
79 #define BSPI_BPP_ADDR_SELECT_MASK BIT(16)
81 #define BSPI_READ_LENGTH 256
83 /* MSPI register offsets */
84 #define MSPI_SPCR0_LSB 0x000
85 #define MSPI_SPCR0_MSB 0x004
86 #define MSPI_SPCR1_LSB 0x008
87 #define MSPI_SPCR1_MSB 0x00c
88 #define MSPI_NEWQP 0x010
89 #define MSPI_ENDQP 0x014
90 #define MSPI_SPCR2 0x018
91 #define MSPI_MSPI_STATUS 0x020
92 #define MSPI_CPTQP 0x024
93 #define MSPI_SPCR3 0x028
94 #define MSPI_TXRAM 0x040
95 #define MSPI_RXRAM 0x0c0
96 #define MSPI_CDRAM 0x140
97 #define MSPI_WRITE_LOCK 0x180
99 #define MSPI_MASTER_BIT BIT(7)
101 #define MSPI_NUM_CDRAM 16
102 #define MSPI_CDRAM_CONT_BIT BIT(7)
103 #define MSPI_CDRAM_BITSE_BIT BIT(6)
104 #define MSPI_CDRAM_PCS 0xf
106 #define MSPI_SPCR2_SPE BIT(6)
107 #define MSPI_SPCR2_CONT_AFTER_CMD BIT(7)
109 #define MSPI_MSPI_STATUS_SPIF BIT(0)
111 #define INTR_BASE_BIT_SHIFT 0x02
112 #define INTR_COUNT 0x07
114 #define NUM_CHIPSELECT 4
115 #define QSPI_SPBR_MIN 8U
116 #define QSPI_SPBR_MAX 255U
118 #define OPCODE_DIOR 0xBB
119 #define OPCODE_QIOR 0xEB
120 #define OPCODE_DIOR_4B 0xBC
121 #define OPCODE_QIOR_4B 0xEC
123 #define MAX_CMD_SIZE 6
125 #define ADDR_4MB_MASK GENMASK(22, 0)
127 /* stop at end of transfer, no other reason */
128 #define TRANS_STATUS_BREAK_NONE 0
129 /* stop at end of spi_message */
130 #define TRANS_STATUS_BREAK_EOM 1
131 /* stop at end of spi_transfer if delay */
132 #define TRANS_STATUS_BREAK_DELAY 2
133 /* stop at end of spi_transfer if cs_change */
134 #define TRANS_STATUS_BREAK_CS_CHANGE 4
135 /* stop if we run out of bytes */
136 #define TRANS_STATUS_BREAK_NO_BYTES 8
138 /* events that make us stop filling TX slots */
139 #define TRANS_STATUS_BREAK_TX (TRANS_STATUS_BREAK_EOM | \
140 TRANS_STATUS_BREAK_DELAY | \
141 TRANS_STATUS_BREAK_CS_CHANGE)
143 /* events that make us deassert CS */
144 #define TRANS_STATUS_BREAK_DESELECT (TRANS_STATUS_BREAK_EOM | \
145 TRANS_STATUS_BREAK_CS_CHANGE)
147 struct bcm_qspi_parms {
153 struct bcm_xfer_mode {
156 unsigned int addrlen;
172 struct bcm_qspi_irq {
173 const char *irq_name;
174 const irq_handler_t irq_handler;
179 struct bcm_qspi_dev_id {
180 const struct bcm_qspi_irq *irqp;
186 struct spi_transfer *trans;
188 bool mspi_last_trans;
192 struct platform_device *pdev;
193 struct spi_master *master;
197 void __iomem *base[BASEMAX];
199 /* Some SoCs provide custom interrupt status register(s) */
200 struct bcm_qspi_soc_intc *soc_intc;
202 struct bcm_qspi_parms last_parms;
203 struct qspi_trans trans_pos;
208 const struct spi_mem_op *bspi_rf_op;
211 u32 bspi_rf_op_status;
212 struct bcm_xfer_mode xfer_mode;
213 u32 s3_strap_override_ctrl;
217 struct bcm_qspi_dev_id *dev_ids;
218 struct completion mspi_done;
219 struct completion bspi_done;
222 static inline bool has_bspi(struct bcm_qspi *qspi)
224 return qspi->bspi_mode;
227 /* Read qspi controller register*/
228 static inline u32 bcm_qspi_read(struct bcm_qspi *qspi, enum base_type type,
231 return bcm_qspi_readl(qspi->big_endian, qspi->base[type] + offset);
234 /* Write qspi controller register*/
235 static inline void bcm_qspi_write(struct bcm_qspi *qspi, enum base_type type,
236 unsigned int offset, unsigned int data)
238 bcm_qspi_writel(qspi->big_endian, data, qspi->base[type] + offset);
242 static int bcm_qspi_bspi_busy_poll(struct bcm_qspi *qspi)
246 /* this should normally finish within 10us */
247 for (i = 0; i < 1000; i++) {
248 if (!(bcm_qspi_read(qspi, BSPI, BSPI_BUSY_STATUS) & 1))
252 dev_warn(&qspi->pdev->dev, "timeout waiting for !busy_status\n");
256 static inline bool bcm_qspi_bspi_ver_three(struct bcm_qspi *qspi)
258 if (qspi->bspi_maj_rev < 4)
263 static void bcm_qspi_bspi_flush_prefetch_buffers(struct bcm_qspi *qspi)
265 bcm_qspi_bspi_busy_poll(qspi);
266 /* Force rising edge for the b0/b1 'flush' field */
267 bcm_qspi_write(qspi, BSPI, BSPI_B0_CTRL, 1);
268 bcm_qspi_write(qspi, BSPI, BSPI_B1_CTRL, 1);
269 bcm_qspi_write(qspi, BSPI, BSPI_B0_CTRL, 0);
270 bcm_qspi_write(qspi, BSPI, BSPI_B1_CTRL, 0);
273 static int bcm_qspi_bspi_lr_is_fifo_empty(struct bcm_qspi *qspi)
275 return (bcm_qspi_read(qspi, BSPI, BSPI_RAF_STATUS) &
276 BSPI_RAF_STATUS_FIFO_EMPTY_MASK);
279 static inline u32 bcm_qspi_bspi_lr_read_fifo(struct bcm_qspi *qspi)
281 u32 data = bcm_qspi_read(qspi, BSPI, BSPI_RAF_READ_DATA);
283 /* BSPI v3 LR is LE only, convert data to host endianness */
284 if (bcm_qspi_bspi_ver_three(qspi))
285 data = le32_to_cpu(data);
290 static inline void bcm_qspi_bspi_lr_start(struct bcm_qspi *qspi)
292 bcm_qspi_bspi_busy_poll(qspi);
293 bcm_qspi_write(qspi, BSPI, BSPI_RAF_CTRL,
294 BSPI_RAF_CTRL_START_MASK);
297 static inline void bcm_qspi_bspi_lr_clear(struct bcm_qspi *qspi)
299 bcm_qspi_write(qspi, BSPI, BSPI_RAF_CTRL,
300 BSPI_RAF_CTRL_CLEAR_MASK);
301 bcm_qspi_bspi_flush_prefetch_buffers(qspi);
304 static void bcm_qspi_bspi_lr_data_read(struct bcm_qspi *qspi)
306 u32 *buf = (u32 *)qspi->bspi_rf_op->data.buf.in;
309 dev_dbg(&qspi->pdev->dev, "xfer %p rx %p rxlen %d\n", qspi->bspi_rf_op,
310 qspi->bspi_rf_op->data.buf.in, qspi->bspi_rf_op_len);
311 while (!bcm_qspi_bspi_lr_is_fifo_empty(qspi)) {
312 data = bcm_qspi_bspi_lr_read_fifo(qspi);
313 if (likely(qspi->bspi_rf_op_len >= 4) &&
314 IS_ALIGNED((uintptr_t)buf, 4)) {
315 buf[qspi->bspi_rf_op_idx++] = data;
316 qspi->bspi_rf_op_len -= 4;
318 /* Read out remaining bytes, make sure*/
319 u8 *cbuf = (u8 *)&buf[qspi->bspi_rf_op_idx];
321 data = cpu_to_le32(data);
322 while (qspi->bspi_rf_op_len) {
325 qspi->bspi_rf_op_len--;
331 static void bcm_qspi_bspi_set_xfer_params(struct bcm_qspi *qspi, u8 cmd_byte,
332 int bpp, int bpc, int flex_mode)
334 bcm_qspi_write(qspi, BSPI, BSPI_FLEX_MODE_ENABLE, 0);
335 bcm_qspi_write(qspi, BSPI, BSPI_BITS_PER_CYCLE, bpc);
336 bcm_qspi_write(qspi, BSPI, BSPI_BITS_PER_PHASE, bpp);
337 bcm_qspi_write(qspi, BSPI, BSPI_CMD_AND_MODE_BYTE, cmd_byte);
338 bcm_qspi_write(qspi, BSPI, BSPI_FLEX_MODE_ENABLE, flex_mode);
341 static int bcm_qspi_bspi_set_flex_mode(struct bcm_qspi *qspi,
342 const struct spi_mem_op *op, int hp)
344 int bpc = 0, bpp = 0;
345 u8 command = op->cmd.opcode;
346 int width = op->data.buswidth ? op->data.buswidth : SPI_NBITS_SINGLE;
347 int addrlen = op->addr.nbytes;
350 dev_dbg(&qspi->pdev->dev, "set flex mode w %x addrlen %x hp %d\n",
353 if (addrlen == BSPI_ADDRLEN_4BYTES)
354 bpp = BSPI_BPP_ADDR_SELECT_MASK;
356 bpp |= (op->dummy.nbytes * 8) / op->dummy.buswidth;
359 case SPI_NBITS_SINGLE:
360 if (addrlen == BSPI_ADDRLEN_3BYTES)
361 /* default mode, does not need flex_cmd */
367 bpc |= 0x00010100; /* address and mode are 2-bit */
368 bpp = BSPI_BPP_MODE_SELECT_MASK;
374 bpc |= 0x00020200; /* address and mode are 4-bit */
375 bpp |= BSPI_BPP_MODE_SELECT_MASK;
382 bcm_qspi_bspi_set_xfer_params(qspi, command, bpp, bpc, flex_mode);
387 static int bcm_qspi_bspi_set_override(struct bcm_qspi *qspi,
388 const struct spi_mem_op *op, int hp)
390 int width = op->data.buswidth ? op->data.buswidth : SPI_NBITS_SINGLE;
391 int addrlen = op->addr.nbytes;
392 u32 data = bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL);
394 dev_dbg(&qspi->pdev->dev, "set override mode w %x addrlen %x hp %d\n",
398 case SPI_NBITS_SINGLE:
399 /* clear quad/dual mode */
400 data &= ~(BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD |
401 BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL);
404 /* clear dual mode and set quad mode */
405 data &= ~BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL;
406 data |= BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD;
409 /* clear quad mode set dual mode */
410 data &= ~BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD;
411 data |= BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL;
417 if (addrlen == BSPI_ADDRLEN_4BYTES)
419 data |= BSPI_STRAP_OVERRIDE_CTRL_ADDR_4BYTE;
421 /* clear 4 byte mode */
422 data &= ~BSPI_STRAP_OVERRIDE_CTRL_ADDR_4BYTE;
424 /* set the override mode */
425 data |= BSPI_STRAP_OVERRIDE_CTRL_OVERRIDE;
426 bcm_qspi_write(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL, data);
427 bcm_qspi_bspi_set_xfer_params(qspi, op->cmd.opcode, 0, 0, 0);
432 static int bcm_qspi_bspi_set_mode(struct bcm_qspi *qspi,
433 const struct spi_mem_op *op, int hp)
436 int width = op->data.buswidth ? op->data.buswidth : SPI_NBITS_SINGLE;
437 int addrlen = op->addr.nbytes;
440 qspi->xfer_mode.flex_mode = true;
442 if (!bcm_qspi_bspi_ver_three(qspi)) {
445 val = bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL);
446 mask = BSPI_STRAP_OVERRIDE_CTRL_OVERRIDE;
447 if (val & mask || qspi->s3_strap_override_ctrl & mask) {
448 qspi->xfer_mode.flex_mode = false;
449 bcm_qspi_write(qspi, BSPI, BSPI_FLEX_MODE_ENABLE, 0);
450 error = bcm_qspi_bspi_set_override(qspi, op, hp);
454 if (qspi->xfer_mode.flex_mode)
455 error = bcm_qspi_bspi_set_flex_mode(qspi, op, hp);
458 dev_warn(&qspi->pdev->dev,
459 "INVALID COMBINATION: width=%d addrlen=%d hp=%d\n",
461 } else if (qspi->xfer_mode.width != width ||
462 qspi->xfer_mode.addrlen != addrlen ||
463 qspi->xfer_mode.hp != hp) {
464 qspi->xfer_mode.width = width;
465 qspi->xfer_mode.addrlen = addrlen;
466 qspi->xfer_mode.hp = hp;
467 dev_dbg(&qspi->pdev->dev,
468 "cs:%d %d-lane output, %d-byte address%s\n",
470 qspi->xfer_mode.width,
471 qspi->xfer_mode.addrlen,
472 qspi->xfer_mode.hp != -1 ? ", hp mode" : "");
478 static void bcm_qspi_enable_bspi(struct bcm_qspi *qspi)
483 qspi->bspi_enabled = 1;
484 if ((bcm_qspi_read(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL) & 1) == 0)
487 bcm_qspi_bspi_flush_prefetch_buffers(qspi);
489 bcm_qspi_write(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL, 0);
493 static void bcm_qspi_disable_bspi(struct bcm_qspi *qspi)
498 qspi->bspi_enabled = 0;
499 if ((bcm_qspi_read(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL) & 1))
502 bcm_qspi_bspi_busy_poll(qspi);
503 bcm_qspi_write(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL, 1);
507 static void bcm_qspi_chip_select(struct bcm_qspi *qspi, int cs)
512 if (qspi->base[CHIP_SELECT]) {
513 rd = bcm_qspi_read(qspi, CHIP_SELECT, 0);
514 wr = (rd & ~0xff) | (1 << cs);
517 bcm_qspi_write(qspi, CHIP_SELECT, 0, wr);
518 usleep_range(10, 20);
521 dev_dbg(&qspi->pdev->dev, "using cs:%d\n", cs);
526 static void bcm_qspi_hw_set_parms(struct bcm_qspi *qspi,
527 const struct bcm_qspi_parms *xp)
532 spbr = qspi->base_clk / (2 * xp->speed_hz);
534 spcr = clamp_val(spbr, QSPI_SPBR_MIN, QSPI_SPBR_MAX);
535 bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_LSB, spcr);
537 spcr = MSPI_MASTER_BIT;
538 /* for 16 bit the data should be zero */
539 if (xp->bits_per_word != 16)
540 spcr |= xp->bits_per_word << 2;
541 spcr |= xp->mode & 3;
542 bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_MSB, spcr);
544 qspi->last_parms = *xp;
547 static void bcm_qspi_update_parms(struct bcm_qspi *qspi,
548 struct spi_device *spi,
549 struct spi_transfer *trans)
551 struct bcm_qspi_parms xp;
553 xp.speed_hz = trans->speed_hz;
554 xp.bits_per_word = trans->bits_per_word;
557 bcm_qspi_hw_set_parms(qspi, &xp);
560 static int bcm_qspi_setup(struct spi_device *spi)
562 struct bcm_qspi_parms *xp;
564 if (spi->bits_per_word > 16)
567 xp = spi_get_ctldata(spi);
569 xp = kzalloc(sizeof(*xp), GFP_KERNEL);
572 spi_set_ctldata(spi, xp);
574 xp->speed_hz = spi->max_speed_hz;
575 xp->mode = spi->mode;
577 if (spi->bits_per_word)
578 xp->bits_per_word = spi->bits_per_word;
580 xp->bits_per_word = 8;
585 static bool bcm_qspi_mspi_transfer_is_last(struct bcm_qspi *qspi,
586 struct qspi_trans *qt)
588 if (qt->mspi_last_trans &&
589 spi_transfer_is_last(qspi->master, qt->trans))
595 static int update_qspi_trans_byte_count(struct bcm_qspi *qspi,
596 struct qspi_trans *qt, int flags)
598 int ret = TRANS_STATUS_BREAK_NONE;
600 /* count the last transferred bytes */
601 if (qt->trans->bits_per_word <= 8)
606 if (qt->byte >= qt->trans->len) {
607 /* we're at the end of the spi_transfer */
608 /* in TX mode, need to pause for a delay or CS change */
609 if (qt->trans->delay_usecs &&
610 (flags & TRANS_STATUS_BREAK_DELAY))
611 ret |= TRANS_STATUS_BREAK_DELAY;
612 if (qt->trans->cs_change &&
613 (flags & TRANS_STATUS_BREAK_CS_CHANGE))
614 ret |= TRANS_STATUS_BREAK_CS_CHANGE;
616 if (bcm_qspi_mspi_transfer_is_last(qspi, qt))
617 ret |= TRANS_STATUS_BREAK_EOM;
619 ret |= TRANS_STATUS_BREAK_NO_BYTES;
624 dev_dbg(&qspi->pdev->dev, "trans %p len %d byte %d ret %x\n",
625 qt->trans, qt->trans ? qt->trans->len : 0, qt->byte, ret);
629 static inline u8 read_rxram_slot_u8(struct bcm_qspi *qspi, int slot)
631 u32 slot_offset = MSPI_RXRAM + (slot << 3) + 0x4;
633 /* mask out reserved bits */
634 return bcm_qspi_read(qspi, MSPI, slot_offset) & 0xff;
637 static inline u16 read_rxram_slot_u16(struct bcm_qspi *qspi, int slot)
639 u32 reg_offset = MSPI_RXRAM;
640 u32 lsb_offset = reg_offset + (slot << 3) + 0x4;
641 u32 msb_offset = reg_offset + (slot << 3);
643 return (bcm_qspi_read(qspi, MSPI, lsb_offset) & 0xff) |
644 ((bcm_qspi_read(qspi, MSPI, msb_offset) & 0xff) << 8);
647 static void read_from_hw(struct bcm_qspi *qspi, int slots)
649 struct qspi_trans tp;
652 bcm_qspi_disable_bspi(qspi);
654 if (slots > MSPI_NUM_CDRAM) {
655 /* should never happen */
656 dev_err(&qspi->pdev->dev, "%s: too many slots!\n", __func__);
660 tp = qspi->trans_pos;
662 for (slot = 0; slot < slots; slot++) {
663 if (tp.trans->bits_per_word <= 8) {
664 u8 *buf = tp.trans->rx_buf;
667 buf[tp.byte] = read_rxram_slot_u8(qspi, slot);
668 dev_dbg(&qspi->pdev->dev, "RD %02x\n",
669 buf ? buf[tp.byte] : 0x0);
671 u16 *buf = tp.trans->rx_buf;
674 buf[tp.byte / 2] = read_rxram_slot_u16(qspi,
676 dev_dbg(&qspi->pdev->dev, "RD %04x\n",
677 buf ? buf[tp.byte / 2] : 0x0);
680 update_qspi_trans_byte_count(qspi, &tp,
681 TRANS_STATUS_BREAK_NONE);
684 qspi->trans_pos = tp;
687 static inline void write_txram_slot_u8(struct bcm_qspi *qspi, int slot,
690 u32 reg_offset = MSPI_TXRAM + (slot << 3);
692 /* mask out reserved bits */
693 bcm_qspi_write(qspi, MSPI, reg_offset, val);
696 static inline void write_txram_slot_u16(struct bcm_qspi *qspi, int slot,
699 u32 reg_offset = MSPI_TXRAM;
700 u32 msb_offset = reg_offset + (slot << 3);
701 u32 lsb_offset = reg_offset + (slot << 3) + 0x4;
703 bcm_qspi_write(qspi, MSPI, msb_offset, (val >> 8));
704 bcm_qspi_write(qspi, MSPI, lsb_offset, (val & 0xff));
707 static inline u32 read_cdram_slot(struct bcm_qspi *qspi, int slot)
709 return bcm_qspi_read(qspi, MSPI, MSPI_CDRAM + (slot << 2));
712 static inline void write_cdram_slot(struct bcm_qspi *qspi, int slot, u32 val)
714 bcm_qspi_write(qspi, MSPI, (MSPI_CDRAM + (slot << 2)), val);
717 /* Return number of slots written */
718 static int write_to_hw(struct bcm_qspi *qspi, struct spi_device *spi)
720 struct qspi_trans tp;
721 int slot = 0, tstatus = 0;
724 bcm_qspi_disable_bspi(qspi);
725 tp = qspi->trans_pos;
726 bcm_qspi_update_parms(qspi, spi, tp.trans);
728 /* Run until end of transfer or reached the max data */
729 while (!tstatus && slot < MSPI_NUM_CDRAM) {
730 if (tp.trans->bits_per_word <= 8) {
731 const u8 *buf = tp.trans->tx_buf;
732 u8 val = buf ? buf[tp.byte] : 0x00;
734 write_txram_slot_u8(qspi, slot, val);
735 dev_dbg(&qspi->pdev->dev, "WR %02x\n", val);
737 const u16 *buf = tp.trans->tx_buf;
738 u16 val = buf ? buf[tp.byte / 2] : 0x0000;
740 write_txram_slot_u16(qspi, slot, val);
741 dev_dbg(&qspi->pdev->dev, "WR %04x\n", val);
743 mspi_cdram = MSPI_CDRAM_CONT_BIT;
748 mspi_cdram |= (~(1 << spi->chip_select) &
751 mspi_cdram |= ((tp.trans->bits_per_word <= 8) ? 0 :
752 MSPI_CDRAM_BITSE_BIT);
754 write_cdram_slot(qspi, slot, mspi_cdram);
756 tstatus = update_qspi_trans_byte_count(qspi, &tp,
757 TRANS_STATUS_BREAK_TX);
762 dev_err(&qspi->pdev->dev, "%s: no data to send?", __func__);
766 dev_dbg(&qspi->pdev->dev, "submitting %d slots\n", slot);
767 bcm_qspi_write(qspi, MSPI, MSPI_NEWQP, 0);
768 bcm_qspi_write(qspi, MSPI, MSPI_ENDQP, slot - 1);
771 * case 1) EOM =1, cs_change =0: SSb inactive
772 * case 2) EOM =1, cs_change =1: SSb stay active
773 * case 3) EOM =0, cs_change =0: SSb stay active
774 * case 4) EOM =0, cs_change =1: SSb inactive
776 if (((tstatus & TRANS_STATUS_BREAK_DESELECT)
777 == TRANS_STATUS_BREAK_CS_CHANGE) ||
778 ((tstatus & TRANS_STATUS_BREAK_DESELECT)
779 == TRANS_STATUS_BREAK_EOM)) {
780 mspi_cdram = read_cdram_slot(qspi, slot - 1) &
781 ~MSPI_CDRAM_CONT_BIT;
782 write_cdram_slot(qspi, slot - 1, mspi_cdram);
786 bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 1);
788 /* Must flush previous writes before starting MSPI operation */
790 /* Set cont | spe | spifie */
791 bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0xe0);
797 static int bcm_qspi_bspi_exec_mem_op(struct spi_device *spi,
798 const struct spi_mem_op *op)
800 struct bcm_qspi *qspi = spi_master_get_devdata(spi->master);
801 u32 addr = 0, len, rdlen, len_words, from = 0;
803 unsigned long timeo = msecs_to_jiffies(100);
804 struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
806 if (bcm_qspi_bspi_ver_three(qspi))
807 if (op->addr.nbytes == BSPI_ADDRLEN_4BYTES)
812 bcm_qspi_chip_select(qspi, spi->chip_select);
813 bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 0);
816 * when using flex mode we need to send
817 * the upper address byte to bspi
819 if (bcm_qspi_bspi_ver_three(qspi) == false) {
820 addr = from & 0xff000000;
821 bcm_qspi_write(qspi, BSPI,
822 BSPI_BSPI_FLASH_UPPER_ADDR_BYTE, addr);
825 if (!qspi->xfer_mode.flex_mode)
828 addr = from & 0x00ffffff;
830 if (bcm_qspi_bspi_ver_three(qspi) == true)
831 addr = (addr + 0xc00000) & 0xffffff;
834 * read into the entire buffer by breaking the reads
835 * into RAF buffer read lengths
837 len = op->data.nbytes;
838 qspi->bspi_rf_op_idx = 0;
841 if (len > BSPI_READ_LENGTH)
842 rdlen = BSPI_READ_LENGTH;
846 reinit_completion(&qspi->bspi_done);
847 bcm_qspi_enable_bspi(qspi);
848 len_words = (rdlen + 3) >> 2;
849 qspi->bspi_rf_op = op;
850 qspi->bspi_rf_op_status = 0;
851 qspi->bspi_rf_op_len = rdlen;
852 dev_dbg(&qspi->pdev->dev,
853 "bspi xfr addr 0x%x len 0x%x", addr, rdlen);
854 bcm_qspi_write(qspi, BSPI, BSPI_RAF_START_ADDR, addr);
855 bcm_qspi_write(qspi, BSPI, BSPI_RAF_NUM_WORDS, len_words);
856 bcm_qspi_write(qspi, BSPI, BSPI_RAF_WATERMARK, 0);
857 if (qspi->soc_intc) {
859 * clear soc MSPI and BSPI interrupts and enable
862 soc_intc->bcm_qspi_int_ack(soc_intc, MSPI_BSPI_DONE);
863 soc_intc->bcm_qspi_int_set(soc_intc, BSPI_DONE, true);
866 /* Must flush previous writes before starting BSPI operation */
868 bcm_qspi_bspi_lr_start(qspi);
869 if (!wait_for_completion_timeout(&qspi->bspi_done, timeo)) {
870 dev_err(&qspi->pdev->dev, "timeout waiting for BSPI\n");
875 /* set msg return length */
883 static int bcm_qspi_transfer_one(struct spi_master *master,
884 struct spi_device *spi,
885 struct spi_transfer *trans)
887 struct bcm_qspi *qspi = spi_master_get_devdata(master);
889 unsigned long timeo = msecs_to_jiffies(100);
892 bcm_qspi_chip_select(qspi, spi->chip_select);
893 qspi->trans_pos.trans = trans;
894 qspi->trans_pos.byte = 0;
896 while (qspi->trans_pos.byte < trans->len) {
897 reinit_completion(&qspi->mspi_done);
899 slots = write_to_hw(qspi, spi);
900 if (!wait_for_completion_timeout(&qspi->mspi_done, timeo)) {
901 dev_err(&qspi->pdev->dev, "timeout waiting for MSPI\n");
905 read_from_hw(qspi, slots);
907 bcm_qspi_enable_bspi(qspi);
912 static int bcm_qspi_mspi_exec_mem_op(struct spi_device *spi,
913 const struct spi_mem_op *op)
915 struct spi_master *master = spi->master;
916 struct bcm_qspi *qspi = spi_master_get_devdata(master);
917 struct spi_transfer t[2];
921 memset(cmd, 0, sizeof(cmd));
922 memset(t, 0, sizeof(t));
925 /* opcode is in cmd[0] */
926 cmd[0] = op->cmd.opcode;
927 for (i = 0; i < op->addr.nbytes; i++)
928 cmd[1 + i] = op->addr.val >> (8 * (op->addr.nbytes - i - 1));
931 t[0].len = op->addr.nbytes + op->dummy.nbytes + 1;
932 t[0].bits_per_word = spi->bits_per_word;
933 t[0].tx_nbits = op->cmd.buswidth;
934 /* lets mspi know that this is not last transfer */
935 qspi->trans_pos.mspi_last_trans = false;
936 ret = bcm_qspi_transfer_one(master, spi, &t[0]);
939 qspi->trans_pos.mspi_last_trans = true;
942 t[1].rx_buf = op->data.buf.in;
943 t[1].len = op->data.nbytes;
944 t[1].rx_nbits = op->data.buswidth;
945 t[1].bits_per_word = spi->bits_per_word;
946 ret = bcm_qspi_transfer_one(master, spi, &t[1]);
952 static int bcm_qspi_exec_mem_op(struct spi_mem *mem,
953 const struct spi_mem_op *op)
955 struct spi_device *spi = mem->spi;
956 struct bcm_qspi *qspi = spi_master_get_devdata(spi->master);
958 bool mspi_read = false;
962 if (!op->data.nbytes || !op->addr.nbytes || op->addr.nbytes > 4 ||
963 op->data.dir != SPI_MEM_DATA_IN)
966 buf = op->data.buf.in;
968 len = op->data.nbytes;
970 if (bcm_qspi_bspi_ver_three(qspi) == true) {
972 * The address coming into this function is a raw flash offset.
973 * But for BSPI <= V3, we need to convert it to a remapped BSPI
974 * address. If it crosses a 4MB boundary, just revert back to
977 addr = (addr + 0xc00000) & 0xffffff;
979 if ((~ADDR_4MB_MASK & addr) ^
980 (~ADDR_4MB_MASK & (addr + len - 1)))
984 /* non-aligned and very short transfers are handled by MSPI */
985 if (!IS_ALIGNED((uintptr_t)addr, 4) || !IS_ALIGNED((uintptr_t)buf, 4) ||
990 return bcm_qspi_mspi_exec_mem_op(spi, op);
992 ret = bcm_qspi_bspi_set_mode(qspi, op, 0);
995 ret = bcm_qspi_bspi_exec_mem_op(spi, op);
1000 static void bcm_qspi_cleanup(struct spi_device *spi)
1002 struct bcm_qspi_parms *xp = spi_get_ctldata(spi);
1007 static irqreturn_t bcm_qspi_mspi_l2_isr(int irq, void *dev_id)
1009 struct bcm_qspi_dev_id *qspi_dev_id = dev_id;
1010 struct bcm_qspi *qspi = qspi_dev_id->dev;
1011 u32 status = bcm_qspi_read(qspi, MSPI, MSPI_MSPI_STATUS);
1013 if (status & MSPI_MSPI_STATUS_SPIF) {
1014 struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
1015 /* clear interrupt */
1016 status &= ~MSPI_MSPI_STATUS_SPIF;
1017 bcm_qspi_write(qspi, MSPI, MSPI_MSPI_STATUS, status);
1019 soc_intc->bcm_qspi_int_ack(soc_intc, MSPI_DONE);
1020 complete(&qspi->mspi_done);
1027 static irqreturn_t bcm_qspi_bspi_lr_l2_isr(int irq, void *dev_id)
1029 struct bcm_qspi_dev_id *qspi_dev_id = dev_id;
1030 struct bcm_qspi *qspi = qspi_dev_id->dev;
1031 struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
1032 u32 status = qspi_dev_id->irqp->mask;
1034 if (qspi->bspi_enabled && qspi->bspi_rf_op) {
1035 bcm_qspi_bspi_lr_data_read(qspi);
1036 if (qspi->bspi_rf_op_len == 0) {
1037 qspi->bspi_rf_op = NULL;
1038 if (qspi->soc_intc) {
1039 /* disable soc BSPI interrupt */
1040 soc_intc->bcm_qspi_int_set(soc_intc, BSPI_DONE,
1043 status = INTR_BSPI_LR_SESSION_DONE_MASK;
1046 if (qspi->bspi_rf_op_status)
1047 bcm_qspi_bspi_lr_clear(qspi);
1049 bcm_qspi_bspi_flush_prefetch_buffers(qspi);
1053 /* clear soc BSPI interrupt */
1054 soc_intc->bcm_qspi_int_ack(soc_intc, BSPI_DONE);
1057 status &= INTR_BSPI_LR_SESSION_DONE_MASK;
1058 if (qspi->bspi_enabled && status && qspi->bspi_rf_op_len == 0)
1059 complete(&qspi->bspi_done);
1064 static irqreturn_t bcm_qspi_bspi_lr_err_l2_isr(int irq, void *dev_id)
1066 struct bcm_qspi_dev_id *qspi_dev_id = dev_id;
1067 struct bcm_qspi *qspi = qspi_dev_id->dev;
1068 struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
1070 dev_err(&qspi->pdev->dev, "BSPI INT error\n");
1071 qspi->bspi_rf_op_status = -EIO;
1073 /* clear soc interrupt */
1074 soc_intc->bcm_qspi_int_ack(soc_intc, BSPI_ERR);
1076 complete(&qspi->bspi_done);
1080 static irqreturn_t bcm_qspi_l1_isr(int irq, void *dev_id)
1082 struct bcm_qspi_dev_id *qspi_dev_id = dev_id;
1083 struct bcm_qspi *qspi = qspi_dev_id->dev;
1084 struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
1085 irqreturn_t ret = IRQ_NONE;
1088 u32 status = soc_intc->bcm_qspi_get_int_status(soc_intc);
1090 if (status & MSPI_DONE)
1091 ret = bcm_qspi_mspi_l2_isr(irq, dev_id);
1092 else if (status & BSPI_DONE)
1093 ret = bcm_qspi_bspi_lr_l2_isr(irq, dev_id);
1094 else if (status & BSPI_ERR)
1095 ret = bcm_qspi_bspi_lr_err_l2_isr(irq, dev_id);
1101 static const struct bcm_qspi_irq qspi_irq_tab[] = {
1103 .irq_name = "spi_lr_fullness_reached",
1104 .irq_handler = bcm_qspi_bspi_lr_l2_isr,
1105 .mask = INTR_BSPI_LR_FULLNESS_REACHED_MASK,
1108 .irq_name = "spi_lr_session_aborted",
1109 .irq_handler = bcm_qspi_bspi_lr_err_l2_isr,
1110 .mask = INTR_BSPI_LR_SESSION_ABORTED_MASK,
1113 .irq_name = "spi_lr_impatient",
1114 .irq_handler = bcm_qspi_bspi_lr_err_l2_isr,
1115 .mask = INTR_BSPI_LR_IMPATIENT_MASK,
1118 .irq_name = "spi_lr_session_done",
1119 .irq_handler = bcm_qspi_bspi_lr_l2_isr,
1120 .mask = INTR_BSPI_LR_SESSION_DONE_MASK,
1122 #ifdef QSPI_INT_DEBUG
1123 /* this interrupt is for debug purposes only, dont request irq */
1125 .irq_name = "spi_lr_overread",
1126 .irq_handler = bcm_qspi_bspi_lr_err_l2_isr,
1127 .mask = INTR_BSPI_LR_OVERREAD_MASK,
1131 .irq_name = "mspi_done",
1132 .irq_handler = bcm_qspi_mspi_l2_isr,
1133 .mask = INTR_MSPI_DONE_MASK,
1136 .irq_name = "mspi_halted",
1137 .irq_handler = bcm_qspi_mspi_l2_isr,
1138 .mask = INTR_MSPI_HALTED_MASK,
1141 /* single muxed L1 interrupt source */
1142 .irq_name = "spi_l1_intr",
1143 .irq_handler = bcm_qspi_l1_isr,
1144 .irq_source = MUXED_L1,
1145 .mask = QSPI_INTERRUPTS_ALL,
1149 static void bcm_qspi_bspi_init(struct bcm_qspi *qspi)
1153 val = bcm_qspi_read(qspi, BSPI, BSPI_REVISION_ID);
1154 qspi->bspi_maj_rev = (val >> 8) & 0xff;
1155 qspi->bspi_min_rev = val & 0xff;
1156 if (!(bcm_qspi_bspi_ver_three(qspi))) {
1157 /* Force mapping of BSPI address -> flash offset */
1158 bcm_qspi_write(qspi, BSPI, BSPI_BSPI_XOR_VALUE, 0);
1159 bcm_qspi_write(qspi, BSPI, BSPI_BSPI_XOR_ENABLE, 1);
1161 qspi->bspi_enabled = 1;
1162 bcm_qspi_disable_bspi(qspi);
1163 bcm_qspi_write(qspi, BSPI, BSPI_B0_CTRL, 0);
1164 bcm_qspi_write(qspi, BSPI, BSPI_B1_CTRL, 0);
1167 static void bcm_qspi_hw_init(struct bcm_qspi *qspi)
1169 struct bcm_qspi_parms parms;
1171 bcm_qspi_write(qspi, MSPI, MSPI_SPCR1_LSB, 0);
1172 bcm_qspi_write(qspi, MSPI, MSPI_SPCR1_MSB, 0);
1173 bcm_qspi_write(qspi, MSPI, MSPI_NEWQP, 0);
1174 bcm_qspi_write(qspi, MSPI, MSPI_ENDQP, 0);
1175 bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0x20);
1177 parms.mode = SPI_MODE_3;
1178 parms.bits_per_word = 8;
1179 parms.speed_hz = qspi->max_speed_hz;
1180 bcm_qspi_hw_set_parms(qspi, &parms);
1183 bcm_qspi_bspi_init(qspi);
1186 static void bcm_qspi_hw_uninit(struct bcm_qspi *qspi)
1188 bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0);
1190 bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 0);
1194 static const struct spi_controller_mem_ops bcm_qspi_mem_ops = {
1195 .exec_op = bcm_qspi_exec_mem_op,
1198 static const struct of_device_id bcm_qspi_of_match[] = {
1199 { .compatible = "brcm,spi-bcm-qspi" },
1202 MODULE_DEVICE_TABLE(of, bcm_qspi_of_match);
1204 int bcm_qspi_probe(struct platform_device *pdev,
1205 struct bcm_qspi_soc_intc *soc_intc)
1207 struct device *dev = &pdev->dev;
1208 struct bcm_qspi *qspi;
1209 struct spi_master *master;
1210 struct resource *res;
1211 int irq, ret = 0, num_ints = 0;
1213 const char *name = NULL;
1214 int num_irqs = ARRAY_SIZE(qspi_irq_tab);
1216 /* We only support device-tree instantiation */
1220 if (!of_match_node(bcm_qspi_of_match, dev->of_node))
1223 master = spi_alloc_master(dev, sizeof(struct bcm_qspi));
1225 dev_err(dev, "error allocating spi_master\n");
1229 qspi = spi_master_get_devdata(master);
1231 qspi->clk = devm_clk_get_optional(&pdev->dev, NULL);
1232 if (IS_ERR(qspi->clk))
1233 return PTR_ERR(qspi->clk);
1236 qspi->trans_pos.trans = NULL;
1237 qspi->trans_pos.byte = 0;
1238 qspi->trans_pos.mspi_last_trans = true;
1239 qspi->master = master;
1241 master->bus_num = -1;
1242 master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_RX_DUAL | SPI_RX_QUAD;
1243 master->setup = bcm_qspi_setup;
1244 master->transfer_one = bcm_qspi_transfer_one;
1245 master->mem_ops = &bcm_qspi_mem_ops;
1246 master->cleanup = bcm_qspi_cleanup;
1247 master->dev.of_node = dev->of_node;
1248 master->num_chipselect = NUM_CHIPSELECT;
1249 master->use_gpio_descriptors = true;
1251 qspi->big_endian = of_device_is_big_endian(dev->of_node);
1253 if (!of_property_read_u32(dev->of_node, "num-cs", &val))
1254 master->num_chipselect = val;
1256 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hif_mspi");
1258 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1262 qspi->base[MSPI] = devm_ioremap_resource(dev, res);
1263 if (IS_ERR(qspi->base[MSPI])) {
1264 ret = PTR_ERR(qspi->base[MSPI]);
1265 goto qspi_resource_err;
1268 goto qspi_resource_err;
1271 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "bspi");
1273 qspi->base[BSPI] = devm_ioremap_resource(dev, res);
1274 if (IS_ERR(qspi->base[BSPI])) {
1275 ret = PTR_ERR(qspi->base[BSPI]);
1276 goto qspi_resource_err;
1278 qspi->bspi_mode = true;
1280 qspi->bspi_mode = false;
1283 dev_info(dev, "using %smspi mode\n", qspi->bspi_mode ? "bspi-" : "");
1285 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cs_reg");
1287 qspi->base[CHIP_SELECT] = devm_ioremap_resource(dev, res);
1288 if (IS_ERR(qspi->base[CHIP_SELECT])) {
1289 ret = PTR_ERR(qspi->base[CHIP_SELECT]);
1290 goto qspi_resource_err;
1294 qspi->dev_ids = kcalloc(num_irqs, sizeof(struct bcm_qspi_dev_id),
1296 if (!qspi->dev_ids) {
1298 goto qspi_resource_err;
1301 for (val = 0; val < num_irqs; val++) {
1303 name = qspi_irq_tab[val].irq_name;
1304 if (qspi_irq_tab[val].irq_source == SINGLE_L2) {
1305 /* get the l2 interrupts */
1306 irq = platform_get_irq_byname_optional(pdev, name);
1307 } else if (!num_ints && soc_intc) {
1308 /* all mspi, bspi intrs muxed to one L1 intr */
1309 irq = platform_get_irq(pdev, 0);
1313 ret = devm_request_irq(&pdev->dev, irq,
1314 qspi_irq_tab[val].irq_handler, 0,
1316 &qspi->dev_ids[val]);
1318 dev_err(&pdev->dev, "IRQ %s not found\n", name);
1319 goto qspi_probe_err;
1322 qspi->dev_ids[val].dev = qspi;
1323 qspi->dev_ids[val].irqp = &qspi_irq_tab[val];
1325 dev_dbg(&pdev->dev, "registered IRQ %s %d\n",
1326 qspi_irq_tab[val].irq_name,
1332 dev_err(&pdev->dev, "no IRQs registered, cannot init driver\n");
1334 goto qspi_probe_err;
1338 * Some SoCs integrate spi controller (e.g., its interrupt bits)
1342 qspi->soc_intc = soc_intc;
1343 soc_intc->bcm_qspi_int_set(soc_intc, MSPI_DONE, true);
1345 qspi->soc_intc = NULL;
1348 ret = clk_prepare_enable(qspi->clk);
1350 dev_err(dev, "failed to prepare clock\n");
1351 goto qspi_probe_err;
1354 qspi->base_clk = clk_get_rate(qspi->clk);
1355 qspi->max_speed_hz = qspi->base_clk / (QSPI_SPBR_MIN * 2);
1357 bcm_qspi_hw_init(qspi);
1358 init_completion(&qspi->mspi_done);
1359 init_completion(&qspi->bspi_done);
1362 platform_set_drvdata(pdev, qspi);
1364 qspi->xfer_mode.width = -1;
1365 qspi->xfer_mode.addrlen = -1;
1366 qspi->xfer_mode.hp = -1;
1368 ret = devm_spi_register_master(&pdev->dev, master);
1370 dev_err(dev, "can't register master\n");
1377 bcm_qspi_hw_uninit(qspi);
1378 clk_disable_unprepare(qspi->clk);
1380 kfree(qspi->dev_ids);
1382 spi_master_put(master);
1385 /* probe function to be called by SoC specific platform driver probe */
1386 EXPORT_SYMBOL_GPL(bcm_qspi_probe);
1388 int bcm_qspi_remove(struct platform_device *pdev)
1390 struct bcm_qspi *qspi = platform_get_drvdata(pdev);
1392 bcm_qspi_hw_uninit(qspi);
1393 clk_disable_unprepare(qspi->clk);
1394 kfree(qspi->dev_ids);
1395 spi_unregister_master(qspi->master);
1399 /* function to be called by SoC specific platform driver remove() */
1400 EXPORT_SYMBOL_GPL(bcm_qspi_remove);
1402 static int __maybe_unused bcm_qspi_suspend(struct device *dev)
1404 struct bcm_qspi *qspi = dev_get_drvdata(dev);
1406 /* store the override strap value */
1407 if (!bcm_qspi_bspi_ver_three(qspi))
1408 qspi->s3_strap_override_ctrl =
1409 bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL);
1411 spi_master_suspend(qspi->master);
1412 clk_disable_unprepare(qspi->clk);
1413 bcm_qspi_hw_uninit(qspi);
1418 static int __maybe_unused bcm_qspi_resume(struct device *dev)
1420 struct bcm_qspi *qspi = dev_get_drvdata(dev);
1423 bcm_qspi_hw_init(qspi);
1424 bcm_qspi_chip_select(qspi, qspi->curr_cs);
1426 /* enable MSPI interrupt */
1427 qspi->soc_intc->bcm_qspi_int_set(qspi->soc_intc, MSPI_DONE,
1430 ret = clk_prepare_enable(qspi->clk);
1432 spi_master_resume(qspi->master);
1437 SIMPLE_DEV_PM_OPS(bcm_qspi_pm_ops, bcm_qspi_suspend, bcm_qspi_resume);
1439 /* pm_ops to be called by SoC specific platform driver */
1440 EXPORT_SYMBOL_GPL(bcm_qspi_pm_ops);
1442 MODULE_AUTHOR("Kamal Dasu");
1443 MODULE_DESCRIPTION("Broadcom QSPI driver");
1444 MODULE_LICENSE("GPL v2");
1445 MODULE_ALIAS("platform:" DRIVER_NAME);