2 * Copyright (C) 2009 Texas Instruments.
3 * Copyright (C) 2010 EF Johnson Technologies
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/interrupt.h>
18 #include <linux/gpio.h>
19 #include <linux/module.h>
20 #include <linux/delay.h>
21 #include <linux/platform_device.h>
22 #include <linux/err.h>
23 #include <linux/clk.h>
24 #include <linux/dmaengine.h>
25 #include <linux/dma-mapping.h>
27 #include <linux/of_device.h>
28 #include <linux/of_gpio.h>
29 #include <linux/spi/spi.h>
30 #include <linux/spi/spi_bitbang.h>
31 #include <linux/slab.h>
33 #include <linux/platform_data/spi-davinci.h>
35 #define CS_DEFAULT 0xFF
37 #define SPIFMT_PHASE_MASK BIT(16)
38 #define SPIFMT_POLARITY_MASK BIT(17)
39 #define SPIFMT_DISTIMER_MASK BIT(18)
40 #define SPIFMT_SHIFTDIR_MASK BIT(20)
41 #define SPIFMT_WAITENA_MASK BIT(21)
42 #define SPIFMT_PARITYENA_MASK BIT(22)
43 #define SPIFMT_ODD_PARITY_MASK BIT(23)
44 #define SPIFMT_WDELAY_MASK 0x3f000000u
45 #define SPIFMT_WDELAY_SHIFT 24
46 #define SPIFMT_PRESCALE_SHIFT 8
49 #define SPIPC0_DIFUN_MASK BIT(11) /* MISO */
50 #define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */
51 #define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */
52 #define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */
54 #define SPIINT_MASKALL 0x0101035F
55 #define SPIINT_MASKINT 0x0000015F
56 #define SPI_INTLVL_1 0x000001FF
57 #define SPI_INTLVL_0 0x00000000
59 /* SPIDAT1 (upper 16 bit defines) */
60 #define SPIDAT1_CSHOLD_MASK BIT(12)
61 #define SPIDAT1_WDEL BIT(10)
64 #define SPIGCR1_CLKMOD_MASK BIT(1)
65 #define SPIGCR1_MASTER_MASK BIT(0)
66 #define SPIGCR1_POWERDOWN_MASK BIT(8)
67 #define SPIGCR1_LOOPBACK_MASK BIT(16)
68 #define SPIGCR1_SPIENA_MASK BIT(24)
71 #define SPIBUF_TXFULL_MASK BIT(29)
72 #define SPIBUF_RXEMPTY_MASK BIT(31)
75 #define SPIDELAY_C2TDELAY_SHIFT 24
76 #define SPIDELAY_C2TDELAY_MASK (0xFF << SPIDELAY_C2TDELAY_SHIFT)
77 #define SPIDELAY_T2CDELAY_SHIFT 16
78 #define SPIDELAY_T2CDELAY_MASK (0xFF << SPIDELAY_T2CDELAY_SHIFT)
79 #define SPIDELAY_T2EDELAY_SHIFT 8
80 #define SPIDELAY_T2EDELAY_MASK (0xFF << SPIDELAY_T2EDELAY_SHIFT)
81 #define SPIDELAY_C2EDELAY_SHIFT 0
82 #define SPIDELAY_C2EDELAY_MASK 0xFF
85 #define SPIFLG_DLEN_ERR_MASK BIT(0)
86 #define SPIFLG_TIMEOUT_MASK BIT(1)
87 #define SPIFLG_PARERR_MASK BIT(2)
88 #define SPIFLG_DESYNC_MASK BIT(3)
89 #define SPIFLG_BITERR_MASK BIT(4)
90 #define SPIFLG_OVRRUN_MASK BIT(6)
91 #define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24)
92 #define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \
93 | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \
94 | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \
97 #define SPIINT_DMA_REQ_EN BIT(16)
99 /* SPI Controller registers */
108 #define SPIDELAY 0x48
112 #define DMA_MIN_BYTES 16
114 /* SPI Controller driver's private data. */
116 struct spi_bitbang bitbang;
120 resource_size_t pbase;
123 struct completion done;
130 struct dma_chan *dma_rx;
131 struct dma_chan *dma_tx;
133 struct davinci_spi_platform_data pdata;
135 void (*get_rx)(u32 rx_data, struct davinci_spi *);
136 u32 (*get_tx)(struct davinci_spi *);
143 static struct davinci_spi_config davinci_spi_default_cfg;
145 static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *dspi)
154 static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *dspi)
163 static u32 davinci_spi_tx_buf_u8(struct davinci_spi *dspi)
168 const u8 *tx = dspi->tx;
176 static u32 davinci_spi_tx_buf_u16(struct davinci_spi *dspi)
181 const u16 *tx = dspi->tx;
189 static inline void set_io_bits(void __iomem *addr, u32 bits)
191 u32 v = ioread32(addr);
197 static inline void clear_io_bits(void __iomem *addr, u32 bits)
199 u32 v = ioread32(addr);
206 * Interface to control the chip select signal
208 static void davinci_spi_chipselect(struct spi_device *spi, int value)
210 struct davinci_spi *dspi;
211 struct davinci_spi_config *spicfg = spi->controller_data;
212 u8 chip_sel = spi->chip_select;
213 u16 spidat1 = CS_DEFAULT;
215 dspi = spi_master_get_devdata(spi->master);
217 /* program delay transfers if tx_delay is non zero */
218 if (spicfg && spicfg->wdelay)
219 spidat1 |= SPIDAT1_WDEL;
222 * Board specific chip select logic decides the polarity and cs
223 * line for the controller
225 if (spi->cs_gpio >= 0) {
226 if (value == BITBANG_CS_ACTIVE)
227 gpio_set_value(spi->cs_gpio, spi->mode & SPI_CS_HIGH);
229 gpio_set_value(spi->cs_gpio,
230 !(spi->mode & SPI_CS_HIGH));
232 if (value == BITBANG_CS_ACTIVE) {
233 if (!(spi->mode & SPI_CS_WORD))
234 spidat1 |= SPIDAT1_CSHOLD_MASK;
235 spidat1 &= ~(0x1 << chip_sel);
239 iowrite16(spidat1, dspi->base + SPIDAT1 + 2);
243 * davinci_spi_get_prescale - Calculates the correct prescale value
244 * @maxspeed_hz: the maximum rate the SPI clock can run at
246 * This function calculates the prescale value that generates a clock rate
247 * less than or equal to the specified maximum.
249 * Returns: calculated prescale value for easy programming into SPI registers
250 * or negative error number if valid prescalar cannot be updated.
252 static inline int davinci_spi_get_prescale(struct davinci_spi *dspi,
257 /* Subtract 1 to match what will be programmed into SPI register. */
258 ret = DIV_ROUND_UP(clk_get_rate(dspi->clk), max_speed_hz) - 1;
260 if (ret < dspi->prescaler_limit || ret > 255)
267 * davinci_spi_setup_transfer - This functions will determine transfer method
268 * @spi: spi device on which data transfer to be done
269 * @t: spi transfer in which transfer info is filled
271 * This function determines data transfer method (8/16/32 bit transfer).
272 * It will also set the SPI Clock Control register according to
273 * SPI slave device freq.
275 static int davinci_spi_setup_transfer(struct spi_device *spi,
276 struct spi_transfer *t)
279 struct davinci_spi *dspi;
280 struct davinci_spi_config *spicfg;
281 u8 bits_per_word = 0;
282 u32 hz = 0, spifmt = 0;
285 dspi = spi_master_get_devdata(spi->master);
286 spicfg = spi->controller_data;
288 spicfg = &davinci_spi_default_cfg;
291 bits_per_word = t->bits_per_word;
295 /* if bits_per_word is not set then set it default */
297 bits_per_word = spi->bits_per_word;
300 * Assign function pointer to appropriate transfer method
301 * 8bit, 16bit or 32bit transfer
303 if (bits_per_word <= 8) {
304 dspi->get_rx = davinci_spi_rx_buf_u8;
305 dspi->get_tx = davinci_spi_tx_buf_u8;
306 dspi->bytes_per_word[spi->chip_select] = 1;
308 dspi->get_rx = davinci_spi_rx_buf_u16;
309 dspi->get_tx = davinci_spi_tx_buf_u16;
310 dspi->bytes_per_word[spi->chip_select] = 2;
314 hz = spi->max_speed_hz;
316 /* Set up SPIFMTn register, unique to this chipselect. */
318 prescale = davinci_spi_get_prescale(dspi, hz);
322 spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f);
324 if (spi->mode & SPI_LSB_FIRST)
325 spifmt |= SPIFMT_SHIFTDIR_MASK;
327 if (spi->mode & SPI_CPOL)
328 spifmt |= SPIFMT_POLARITY_MASK;
330 if (!(spi->mode & SPI_CPHA))
331 spifmt |= SPIFMT_PHASE_MASK;
334 * Assume wdelay is used only on SPI peripherals that has this field
335 * in SPIFMTn register and when it's configured from board file or DT.
338 spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT)
339 & SPIFMT_WDELAY_MASK);
342 * Version 1 hardware supports two basic SPI modes:
343 * - Standard SPI mode uses 4 pins, with chipselect
344 * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS)
345 * (distinct from SPI_3WIRE, with just one data wire;
346 * or similar variants without MOSI or without MISO)
348 * Version 2 hardware supports an optional handshaking signal,
349 * so it can support two more modes:
350 * - 5 pin SPI variant is standard SPI plus SPI_READY
351 * - 4 pin with enable is (SPI_READY | SPI_NO_CS)
354 if (dspi->version == SPI_VERSION_2) {
358 if (spicfg->odd_parity)
359 spifmt |= SPIFMT_ODD_PARITY_MASK;
361 if (spicfg->parity_enable)
362 spifmt |= SPIFMT_PARITYENA_MASK;
364 if (spicfg->timer_disable) {
365 spifmt |= SPIFMT_DISTIMER_MASK;
367 delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT)
368 & SPIDELAY_C2TDELAY_MASK;
369 delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT)
370 & SPIDELAY_T2CDELAY_MASK;
373 if (spi->mode & SPI_READY) {
374 spifmt |= SPIFMT_WAITENA_MASK;
375 delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT)
376 & SPIDELAY_T2EDELAY_MASK;
377 delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT)
378 & SPIDELAY_C2EDELAY_MASK;
381 iowrite32(delay, dspi->base + SPIDELAY);
384 iowrite32(spifmt, dspi->base + SPIFMT0);
389 static int davinci_spi_of_setup(struct spi_device *spi)
391 struct davinci_spi_config *spicfg = spi->controller_data;
392 struct device_node *np = spi->dev.of_node;
393 struct davinci_spi *dspi = spi_master_get_devdata(spi->master);
396 if (spicfg == NULL && np) {
397 spicfg = kzalloc(sizeof(*spicfg), GFP_KERNEL);
400 *spicfg = davinci_spi_default_cfg;
401 /* override with dt configured values */
402 if (!of_property_read_u32(np, "ti,spi-wdelay", &prop))
403 spicfg->wdelay = (u8)prop;
404 spi->controller_data = spicfg;
406 if (dspi->dma_rx && dspi->dma_tx)
407 spicfg->io_type = SPI_IO_TYPE_DMA;
414 * davinci_spi_setup - This functions will set default transfer method
415 * @spi: spi device on which data transfer to be done
417 * This functions sets the default transfer method.
419 static int davinci_spi_setup(struct spi_device *spi)
422 struct davinci_spi *dspi;
423 struct spi_master *master = spi->master;
424 struct device_node *np = spi->dev.of_node;
425 bool internal_cs = true;
427 dspi = spi_master_get_devdata(spi->master);
429 if (!(spi->mode & SPI_NO_CS)) {
430 if (np && (master->cs_gpios != NULL) && (spi->cs_gpio >= 0)) {
431 retval = gpio_direction_output(
432 spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
437 dev_err(&spi->dev, "GPIO %d setup failed (%d)\n",
438 spi->cs_gpio, retval);
443 set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select);
447 if (spi->mode & SPI_READY)
448 set_io_bits(dspi->base + SPIPC0, SPIPC0_SPIENA_MASK);
450 if (spi->mode & SPI_LOOP)
451 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);
453 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);
455 return davinci_spi_of_setup(spi);
458 static void davinci_spi_cleanup(struct spi_device *spi)
460 struct davinci_spi_config *spicfg = spi->controller_data;
462 spi->controller_data = NULL;
463 if (spi->dev.of_node)
467 static bool davinci_spi_can_dma(struct spi_master *master,
468 struct spi_device *spi,
469 struct spi_transfer *xfer)
471 struct davinci_spi_config *spicfg = spi->controller_data;
472 bool can_dma = false;
475 can_dma = (spicfg->io_type == SPI_IO_TYPE_DMA) &&
476 (xfer->len >= DMA_MIN_BYTES) &&
477 !is_vmalloc_addr(xfer->rx_buf) &&
478 !is_vmalloc_addr(xfer->tx_buf);
483 static int davinci_spi_check_error(struct davinci_spi *dspi, int int_status)
485 struct device *sdev = dspi->bitbang.master->dev.parent;
487 if (int_status & SPIFLG_TIMEOUT_MASK) {
488 dev_err(sdev, "SPI Time-out Error\n");
491 if (int_status & SPIFLG_DESYNC_MASK) {
492 dev_err(sdev, "SPI Desynchronization Error\n");
495 if (int_status & SPIFLG_BITERR_MASK) {
496 dev_err(sdev, "SPI Bit error\n");
500 if (dspi->version == SPI_VERSION_2) {
501 if (int_status & SPIFLG_DLEN_ERR_MASK) {
502 dev_err(sdev, "SPI Data Length Error\n");
505 if (int_status & SPIFLG_PARERR_MASK) {
506 dev_err(sdev, "SPI Parity Error\n");
509 if (int_status & SPIFLG_OVRRUN_MASK) {
510 dev_err(sdev, "SPI Data Overrun error\n");
513 if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) {
514 dev_err(sdev, "SPI Buffer Init Active\n");
523 * davinci_spi_process_events - check for and handle any SPI controller events
524 * @dspi: the controller data
526 * This function will check the SPIFLG register and handle any events that are
529 static int davinci_spi_process_events(struct davinci_spi *dspi)
531 u32 buf, status, errors = 0, spidat1;
533 buf = ioread32(dspi->base + SPIBUF);
535 if (dspi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) {
536 dspi->get_rx(buf & 0xFFFF, dspi);
540 status = ioread32(dspi->base + SPIFLG);
542 if (unlikely(status & SPIFLG_ERROR_MASK)) {
543 errors = status & SPIFLG_ERROR_MASK;
547 if (dspi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) {
548 spidat1 = ioread32(dspi->base + SPIDAT1);
551 spidat1 |= 0xFFFF & dspi->get_tx(dspi);
552 iowrite32(spidat1, dspi->base + SPIDAT1);
559 static void davinci_spi_dma_rx_callback(void *data)
561 struct davinci_spi *dspi = (struct davinci_spi *)data;
565 if (!dspi->wcount && !dspi->rcount)
566 complete(&dspi->done);
569 static void davinci_spi_dma_tx_callback(void *data)
571 struct davinci_spi *dspi = (struct davinci_spi *)data;
575 if (!dspi->wcount && !dspi->rcount)
576 complete(&dspi->done);
580 * davinci_spi_bufs - functions which will handle transfer data
581 * @spi: spi device on which data transfer to be done
582 * @t: spi transfer in which transfer info is filled
584 * This function will put data to be transferred into data register
585 * of SPI controller and then wait until the completion will be marked
586 * by the IRQ Handler.
588 static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
590 struct davinci_spi *dspi;
591 int data_type, ret = -ENOMEM;
592 u32 tx_data, spidat1;
594 struct davinci_spi_config *spicfg;
595 struct davinci_spi_platform_data *pdata;
596 unsigned uninitialized_var(rx_buf_count);
598 dspi = spi_master_get_devdata(spi->master);
599 pdata = &dspi->pdata;
600 spicfg = (struct davinci_spi_config *)spi->controller_data;
602 spicfg = &davinci_spi_default_cfg;
604 /* convert len to words based on bits_per_word */
605 data_type = dspi->bytes_per_word[spi->chip_select];
607 dspi->tx = t->tx_buf;
608 dspi->rx = t->rx_buf;
609 dspi->wcount = t->len / data_type;
610 dspi->rcount = dspi->wcount;
612 spidat1 = ioread32(dspi->base + SPIDAT1);
614 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
615 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
617 reinit_completion(&dspi->done);
619 if (!davinci_spi_can_dma(spi->master, spi, t)) {
620 if (spicfg->io_type != SPI_IO_TYPE_POLL)
621 set_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);
622 /* start the transfer */
624 tx_data = dspi->get_tx(dspi);
625 spidat1 &= 0xFFFF0000;
626 spidat1 |= tx_data & 0xFFFF;
627 iowrite32(spidat1, dspi->base + SPIDAT1);
629 struct dma_slave_config dma_rx_conf = {
630 .direction = DMA_DEV_TO_MEM,
631 .src_addr = (unsigned long)dspi->pbase + SPIBUF,
632 .src_addr_width = data_type,
635 struct dma_slave_config dma_tx_conf = {
636 .direction = DMA_MEM_TO_DEV,
637 .dst_addr = (unsigned long)dspi->pbase + SPIDAT1,
638 .dst_addr_width = data_type,
641 struct dma_async_tx_descriptor *rxdesc;
642 struct dma_async_tx_descriptor *txdesc;
644 dmaengine_slave_config(dspi->dma_rx, &dma_rx_conf);
645 dmaengine_slave_config(dspi->dma_tx, &dma_tx_conf);
647 rxdesc = dmaengine_prep_slave_sg(dspi->dma_rx,
648 t->rx_sg.sgl, t->rx_sg.nents, DMA_DEV_TO_MEM,
649 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
654 /* To avoid errors when doing rx-only transfers with
655 * many SG entries (> 20), use the rx buffer as the
656 * dummy tx buffer so that dma reloads are done at the
657 * same time for rx and tx.
659 t->tx_sg.sgl = t->rx_sg.sgl;
660 t->tx_sg.nents = t->rx_sg.nents;
663 txdesc = dmaengine_prep_slave_sg(dspi->dma_tx,
664 t->tx_sg.sgl, t->tx_sg.nents, DMA_MEM_TO_DEV,
665 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
669 rxdesc->callback = davinci_spi_dma_rx_callback;
670 rxdesc->callback_param = (void *)dspi;
671 txdesc->callback = davinci_spi_dma_tx_callback;
672 txdesc->callback_param = (void *)dspi;
674 if (pdata->cshold_bug)
675 iowrite16(spidat1 >> 16, dspi->base + SPIDAT1 + 2);
677 dmaengine_submit(rxdesc);
678 dmaengine_submit(txdesc);
680 dma_async_issue_pending(dspi->dma_rx);
681 dma_async_issue_pending(dspi->dma_tx);
683 set_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
686 /* Wait for the transfer to complete */
687 if (spicfg->io_type != SPI_IO_TYPE_POLL) {
688 if (wait_for_completion_timeout(&dspi->done, HZ) == 0)
689 errors = SPIFLG_TIMEOUT_MASK;
691 while (dspi->rcount > 0 || dspi->wcount > 0) {
692 errors = davinci_spi_process_events(dspi);
699 clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL);
700 if (davinci_spi_can_dma(spi->master, spi, t))
701 clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
703 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
704 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
707 * Check for bit error, desync error,parity error,timeout error and
708 * receive overflow errors
711 ret = davinci_spi_check_error(dspi, errors);
712 WARN(!ret, "%s: error reported but no error found!\n",
713 dev_name(&spi->dev));
717 if (dspi->rcount != 0 || dspi->wcount != 0) {
718 dev_err(&spi->dev, "SPI data transfer error\n");
729 * dummy_thread_fn - dummy thread function
730 * @irq: IRQ number for this SPI Master
731 * @context_data: structure for SPI Master controller davinci_spi
733 * This is to satisfy the request_threaded_irq() API so that the irq
734 * handler is called in interrupt context.
736 static irqreturn_t dummy_thread_fn(s32 irq, void *data)
742 * davinci_spi_irq - Interrupt handler for SPI Master Controller
743 * @irq: IRQ number for this SPI Master
744 * @context_data: structure for SPI Master controller davinci_spi
746 * ISR will determine that interrupt arrives either for READ or WRITE command.
747 * According to command it will do the appropriate action. It will check
748 * transfer length and if it is not zero then dispatch transfer command again.
749 * If transfer length is zero then it will indicate the COMPLETION so that
750 * davinci_spi_bufs function can go ahead.
752 static irqreturn_t davinci_spi_irq(s32 irq, void *data)
754 struct davinci_spi *dspi = data;
757 status = davinci_spi_process_events(dspi);
758 if (unlikely(status != 0))
759 clear_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);
761 if ((!dspi->rcount && !dspi->wcount) || status)
762 complete(&dspi->done);
767 static int davinci_spi_request_dma(struct davinci_spi *dspi)
769 struct device *sdev = dspi->bitbang.master->dev.parent;
771 dspi->dma_rx = dma_request_chan(sdev, "rx");
772 if (IS_ERR(dspi->dma_rx))
773 return PTR_ERR(dspi->dma_rx);
775 dspi->dma_tx = dma_request_chan(sdev, "tx");
776 if (IS_ERR(dspi->dma_tx)) {
777 dma_release_channel(dspi->dma_rx);
778 return PTR_ERR(dspi->dma_tx);
784 #if defined(CONFIG_OF)
786 /* OF SPI data structure */
787 struct davinci_spi_of_data {
792 static const struct davinci_spi_of_data dm6441_spi_data = {
793 .version = SPI_VERSION_1,
794 .prescaler_limit = 2,
797 static const struct davinci_spi_of_data da830_spi_data = {
798 .version = SPI_VERSION_2,
799 .prescaler_limit = 2,
802 static const struct davinci_spi_of_data keystone_spi_data = {
803 .version = SPI_VERSION_1,
804 .prescaler_limit = 0,
807 static const struct of_device_id davinci_spi_of_match[] = {
809 .compatible = "ti,dm6441-spi",
810 .data = &dm6441_spi_data,
813 .compatible = "ti,da830-spi",
814 .data = &da830_spi_data,
817 .compatible = "ti,keystone-spi",
818 .data = &keystone_spi_data,
822 MODULE_DEVICE_TABLE(of, davinci_spi_of_match);
825 * spi_davinci_get_pdata - Get platform data from DTS binding
826 * @pdev: ptr to platform data
827 * @dspi: ptr to driver data
829 * Parses and populates pdata in dspi from device tree bindings.
831 * NOTE: Not all platform data params are supported currently.
833 static int spi_davinci_get_pdata(struct platform_device *pdev,
834 struct davinci_spi *dspi)
836 struct device_node *node = pdev->dev.of_node;
837 struct davinci_spi_of_data *spi_data;
838 struct davinci_spi_platform_data *pdata;
839 unsigned int num_cs, intr_line = 0;
840 const struct of_device_id *match;
842 pdata = &dspi->pdata;
844 match = of_match_device(davinci_spi_of_match, &pdev->dev);
848 spi_data = (struct davinci_spi_of_data *)match->data;
850 pdata->version = spi_data->version;
851 pdata->prescaler_limit = spi_data->prescaler_limit;
853 * default num_cs is 1 and all chipsel are internal to the chip
854 * indicated by chip_sel being NULL or cs_gpios being NULL or
855 * set to -ENOENT. num-cs includes internal as well as gpios.
856 * indicated by chip_sel being NULL. GPIO based CS is not
857 * supported yet in DT bindings.
860 of_property_read_u32(node, "num-cs", &num_cs);
861 pdata->num_chipselect = num_cs;
862 of_property_read_u32(node, "ti,davinci-spi-intr-line", &intr_line);
863 pdata->intr_line = intr_line;
867 static int spi_davinci_get_pdata(struct platform_device *pdev,
868 struct davinci_spi *dspi)
875 * davinci_spi_probe - probe function for SPI Master Controller
876 * @pdev: platform_device structure which contains plateform specific data
878 * According to Linux Device Model this function will be invoked by Linux
879 * with platform_device struct which contains the device specific info.
880 * This function will map the SPI controller's memory, register IRQ,
881 * Reset SPI controller and setting its registers to default value.
882 * It will invoke spi_bitbang_start to create work queue so that client driver
883 * can register transfer method to work queue.
885 static int davinci_spi_probe(struct platform_device *pdev)
887 struct spi_master *master;
888 struct davinci_spi *dspi;
889 struct davinci_spi_platform_data *pdata;
894 master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi));
895 if (master == NULL) {
900 platform_set_drvdata(pdev, master);
902 dspi = spi_master_get_devdata(master);
904 if (dev_get_platdata(&pdev->dev)) {
905 pdata = dev_get_platdata(&pdev->dev);
906 dspi->pdata = *pdata;
908 /* update dspi pdata with that from the DT */
909 ret = spi_davinci_get_pdata(pdev, dspi);
914 /* pdata in dspi is now updated and point pdata to that */
915 pdata = &dspi->pdata;
917 dspi->bytes_per_word = devm_kcalloc(&pdev->dev,
918 pdata->num_chipselect,
919 sizeof(*dspi->bytes_per_word),
921 if (dspi->bytes_per_word == NULL) {
926 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
932 dspi->pbase = r->start;
934 dspi->base = devm_ioremap_resource(&pdev->dev, r);
935 if (IS_ERR(dspi->base)) {
936 ret = PTR_ERR(dspi->base);
940 init_completion(&dspi->done);
942 ret = platform_get_irq(pdev, 0);
949 ret = devm_request_threaded_irq(&pdev->dev, dspi->irq, davinci_spi_irq,
950 dummy_thread_fn, 0, dev_name(&pdev->dev), dspi);
954 dspi->bitbang.master = master;
956 dspi->clk = devm_clk_get(&pdev->dev, NULL);
957 if (IS_ERR(dspi->clk)) {
961 ret = clk_prepare_enable(dspi->clk);
965 master->dev.of_node = pdev->dev.of_node;
966 master->bus_num = pdev->id;
967 master->num_chipselect = pdata->num_chipselect;
968 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 16);
969 master->flags = SPI_MASTER_MUST_RX;
970 master->setup = davinci_spi_setup;
971 master->cleanup = davinci_spi_cleanup;
972 master->can_dma = davinci_spi_can_dma;
974 dspi->bitbang.chipselect = davinci_spi_chipselect;
975 dspi->bitbang.setup_transfer = davinci_spi_setup_transfer;
976 dspi->prescaler_limit = pdata->prescaler_limit;
977 dspi->version = pdata->version;
979 dspi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP | SPI_CS_WORD;
980 if (dspi->version == SPI_VERSION_2)
981 dspi->bitbang.flags |= SPI_READY;
983 if (pdev->dev.of_node) {
986 for (i = 0; i < pdata->num_chipselect; i++) {
987 int cs_gpio = of_get_named_gpio(pdev->dev.of_node,
990 if (cs_gpio == -EPROBE_DEFER) {
995 if (gpio_is_valid(cs_gpio)) {
996 ret = devm_gpio_request(&pdev->dev, cs_gpio,
997 dev_name(&pdev->dev));
1004 dspi->bitbang.txrx_bufs = davinci_spi_bufs;
1006 ret = davinci_spi_request_dma(dspi);
1007 if (ret == -EPROBE_DEFER) {
1010 dev_info(&pdev->dev, "DMA is not supported (%d)\n", ret);
1011 dspi->dma_rx = NULL;
1012 dspi->dma_tx = NULL;
1015 dspi->get_rx = davinci_spi_rx_buf_u8;
1016 dspi->get_tx = davinci_spi_tx_buf_u8;
1018 /* Reset In/OUT SPI module */
1019 iowrite32(0, dspi->base + SPIGCR0);
1021 iowrite32(1, dspi->base + SPIGCR0);
1023 /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */
1024 spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK;
1025 iowrite32(spipc0, dspi->base + SPIPC0);
1027 if (pdata->intr_line)
1028 iowrite32(SPI_INTLVL_1, dspi->base + SPILVL);
1030 iowrite32(SPI_INTLVL_0, dspi->base + SPILVL);
1032 iowrite32(CS_DEFAULT, dspi->base + SPIDEF);
1034 /* master mode default */
1035 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK);
1036 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_MASTER_MASK);
1037 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
1039 ret = spi_bitbang_start(&dspi->bitbang);
1043 dev_info(&pdev->dev, "Controller at 0x%p\n", dspi->base);
1049 dma_release_channel(dspi->dma_rx);
1050 dma_release_channel(dspi->dma_tx);
1053 clk_disable_unprepare(dspi->clk);
1055 spi_master_put(master);
1061 * davinci_spi_remove - remove function for SPI Master Controller
1062 * @pdev: platform_device structure which contains plateform specific data
1064 * This function will do the reverse action of davinci_spi_probe function
1065 * It will free the IRQ and SPI controller's memory region.
1066 * It will also call spi_bitbang_stop to destroy the work queue which was
1067 * created by spi_bitbang_start.
1069 static int davinci_spi_remove(struct platform_device *pdev)
1071 struct davinci_spi *dspi;
1072 struct spi_master *master;
1074 master = platform_get_drvdata(pdev);
1075 dspi = spi_master_get_devdata(master);
1077 spi_bitbang_stop(&dspi->bitbang);
1079 clk_disable_unprepare(dspi->clk);
1080 spi_master_put(master);
1083 dma_release_channel(dspi->dma_rx);
1084 dma_release_channel(dspi->dma_tx);
1090 static struct platform_driver davinci_spi_driver = {
1092 .name = "spi_davinci",
1093 .of_match_table = of_match_ptr(davinci_spi_of_match),
1095 .probe = davinci_spi_probe,
1096 .remove = davinci_spi_remove,
1098 module_platform_driver(davinci_spi_driver);
1100 MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver");
1101 MODULE_LICENSE("GPL");