drivers/spi/spi-dw-mid.c

   1 /*
   2  * Special handling for DW core on Intel MID platform
   3  *
   4  * Copyright (c) 2009, 2014 Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  */
  15
  16 #include <linux/dma-mapping.h>
  17 #include <linux/dmaengine.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/slab.h>
  20 #include <linux/spi/spi.h>
  21 #include <linux/types.h>
  22
  23 #include "spi-dw.h"
  24
  25 #ifdef CONFIG_SPI_DW_MID_DMA
  26 #include <linux/intel_mid_dma.h>
  27 #include <linux/pci.h>
  28
  29 #define RX_BUSY         0
  30 #define TX_BUSY         1
  31
  32 struct mid_dma {
  33         struct intel_mid_dma_slave      dmas_tx;
  34         struct intel_mid_dma_slave      dmas_rx;
  35 };
  36
  37 static bool mid_spi_dma_chan_filter(struct dma_chan *chan, void *param)
  38 {
  39         struct dw_spi *dws = param;
  40
  41         return dws->dma_dev == chan->device->dev;
  42 }
  43
  44 static int mid_spi_dma_init(struct dw_spi *dws)
  45 {
  46         struct mid_dma *dw_dma = dws->dma_priv;
  47         struct pci_dev *dma_dev;
  48         struct intel_mid_dma_slave *rxs, *txs;
  49         dma_cap_mask_t mask;
  50
  51         /*
  52          * Get pci device for DMA controller, currently it could only
  53          * be the DMA controller of Medfield
  54          */
  55         dma_dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x0827, NULL);
  56         if (!dma_dev)
  57                 return -ENODEV;
  58
  59         dws->dma_dev = &dma_dev->dev;
  60
  61         dma_cap_zero(mask);
  62         dma_cap_set(DMA_SLAVE, mask);
  63
  64         /* 1. Init rx channel */
  65         dws->rxchan = dma_request_channel(mask, mid_spi_dma_chan_filter, dws);
  66         if (!dws->rxchan)
  67                 goto err_exit;
  68         rxs = &dw_dma->dmas_rx;
  69         rxs->hs_mode = LNW_DMA_HW_HS;
  70         rxs->cfg_mode = LNW_DMA_PER_TO_MEM;
  71         dws->rxchan->private = rxs;
  72
  73         /* 2. Init tx channel */
  74         dws->txchan = dma_request_channel(mask, mid_spi_dma_chan_filter, dws);
  75         if (!dws->txchan)
  76                 goto free_rxchan;
  77         txs = &dw_dma->dmas_tx;
  78         txs->hs_mode = LNW_DMA_HW_HS;
  79         txs->cfg_mode = LNW_DMA_MEM_TO_PER;
  80         dws->txchan->private = txs;
  81
  82         dws->dma_inited = 1;
  83         return 0;
  84
  85 free_rxchan:
  86         dma_release_channel(dws->rxchan);
  87 err_exit:
  88         return -EBUSY;
  89 }
  90
  91 static void mid_spi_dma_exit(struct dw_spi *dws)
  92 {
  93         if (!dws->dma_inited)
  94                 return;
  95
  96         dmaengine_terminate_all(dws->txchan);
  97         dma_release_channel(dws->txchan);
  98
  99         dmaengine_terminate_all(dws->rxchan);
 100         dma_release_channel(dws->rxchan);
 101 }
 102
 103 /*
 104  * dws->dma_chan_busy is set before the dma transfer starts, callback for tx
 105  * channel will clear a corresponding bit.
 106  */
 107 static void dw_spi_dma_tx_done(void *arg)
 108 {
 109         struct dw_spi *dws = arg;
 110
 111         clear_bit(TX_BUSY, &dws->dma_chan_busy);
 112         if (test_bit(RX_BUSY, &dws->dma_chan_busy))
 113                 return;
 114         dw_spi_xfer_done(dws);
 115 }
 116
 117 static struct dma_async_tx_descriptor *dw_spi_dma_prepare_tx(struct dw_spi *dws)
 118 {
 119         struct dma_slave_config txconf;
 120         struct dma_async_tx_descriptor *txdesc;
 121
 122         if (!dws->tx_dma)
 123                 return NULL;
 124
 125         txconf.direction = DMA_MEM_TO_DEV;
 126         txconf.dst_addr = dws->dma_addr;
 127         txconf.dst_maxburst = LNW_DMA_MSIZE_16;
 128         txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 129         txconf.dst_addr_width = dws->dma_width;
 130         txconf.device_fc = false;
 131
 132         dmaengine_slave_config(dws->txchan, &txconf);
 133
 134         memset(&dws->tx_sgl, 0, sizeof(dws->tx_sgl));
 135         dws->tx_sgl.dma_address = dws->tx_dma;
 136         dws->tx_sgl.length = dws->len;
 137
 138         txdesc = dmaengine_prep_slave_sg(dws->txchan,
 139                                 &dws->tx_sgl,
 140                                 1,
 141                                 DMA_MEM_TO_DEV,
 142                                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 143         if (!txdesc)
 144                 return NULL;
 145
 146         txdesc->callback = dw_spi_dma_tx_done;
 147         txdesc->callback_param = dws;
 148
 149         return txdesc;
 150 }
 151
 152 /*
 153  * dws->dma_chan_busy is set before the dma transfer starts, callback for rx
 154  * channel will clear a corresponding bit.
 155  */
 156 static void dw_spi_dma_rx_done(void *arg)
 157 {
 158         struct dw_spi *dws = arg;
 159
 160         clear_bit(RX_BUSY, &dws->dma_chan_busy);
 161         if (test_bit(TX_BUSY, &dws->dma_chan_busy))
 162                 return;
 163         dw_spi_xfer_done(dws);
 164 }
 165
 166 static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws)
 167 {
 168         struct dma_slave_config rxconf;
 169         struct dma_async_tx_descriptor *rxdesc;
 170
 171         if (!dws->rx_dma)
 172                 return NULL;
 173
 174         rxconf.direction = DMA_DEV_TO_MEM;
 175         rxconf.src_addr = dws->dma_addr;
 176         rxconf.src_maxburst = LNW_DMA_MSIZE_16;
 177         rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 178         rxconf.src_addr_width = dws->dma_width;
 179         rxconf.device_fc = false;
 180
 181         dmaengine_slave_config(dws->rxchan, &rxconf);
 182
 183         memset(&dws->rx_sgl, 0, sizeof(dws->rx_sgl));
 184         dws->rx_sgl.dma_address = dws->rx_dma;
 185         dws->rx_sgl.length = dws->len;
 186
 187         rxdesc = dmaengine_prep_slave_sg(dws->rxchan,
 188                                 &dws->rx_sgl,
 189                                 1,
 190                                 DMA_DEV_TO_MEM,
 191                                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 192         if (!rxdesc)
 193                 return NULL;
 194
 195         rxdesc->callback = dw_spi_dma_rx_done;
 196         rxdesc->callback_param = dws;
 197
 198         return rxdesc;
 199 }
 200
 201 static void dw_spi_dma_setup(struct dw_spi *dws)
 202 {
 203         u16 dma_ctrl = 0;
 204
 205         spi_enable_chip(dws, 0);
 206
 207         dw_writew(dws, DW_SPI_DMARDLR, 0xf);
 208         dw_writew(dws, DW_SPI_DMATDLR, 0x10);
 209
 210         if (dws->tx_dma)
 211                 dma_ctrl |= SPI_DMA_TDMAE;
 212         if (dws->rx_dma)
 213                 dma_ctrl |= SPI_DMA_RDMAE;
 214         dw_writew(dws, DW_SPI_DMACR, dma_ctrl);
 215
 216         spi_enable_chip(dws, 1);
 217 }
 218
 219 static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change)
 220 {
 221         struct dma_async_tx_descriptor *txdesc, *rxdesc;
 222
 223         /* 1. setup DMA related registers */
 224         if (cs_change)
 225                 dw_spi_dma_setup(dws);
 226
 227         /* 2. Prepare the TX dma transfer */
 228         txdesc = dw_spi_dma_prepare_tx(dws);
 229
 230         /* 3. Prepare the RX dma transfer */
 231         rxdesc = dw_spi_dma_prepare_rx(dws);
 232
 233         /* rx must be started before tx due to spi instinct */
 234         if (rxdesc) {
 235                 set_bit(RX_BUSY, &dws->dma_chan_busy);
 236                 dmaengine_submit(rxdesc);
 237                 dma_async_issue_pending(dws->rxchan);
 238         }
 239
 240         if (txdesc) {
 241                 set_bit(TX_BUSY, &dws->dma_chan_busy);
 242                 dmaengine_submit(txdesc);
 243                 dma_async_issue_pending(dws->txchan);
 244         }
 245
 246         return 0;
 247 }
 248
 249 static struct dw_spi_dma_ops mid_dma_ops = {
 250         .dma_init       = mid_spi_dma_init,
 251         .dma_exit       = mid_spi_dma_exit,
 252         .dma_transfer   = mid_spi_dma_transfer,
 253 };
 254 #endif
 255
 256 /* Some specific info for SPI0 controller on Intel MID */
 257
 258 /* HW info for MRST Clk Control Unit, 32b reg per controller */
 259 #define MRST_SPI_CLK_BASE       100000000       /* 100m */
 260 #define MRST_CLK_SPI_REG        0xff11d86c
 261 #define CLK_SPI_BDIV_OFFSET     0
 262 #define CLK_SPI_BDIV_MASK       0x00000007
 263 #define CLK_SPI_CDIV_OFFSET     9
 264 #define CLK_SPI_CDIV_MASK       0x00000e00
 265 #define CLK_SPI_DISABLE_OFFSET  8
 266
 267 int dw_spi_mid_init(struct dw_spi *dws)
 268 {
 269         void __iomem *clk_reg;
 270         u32 clk_cdiv;
 271
 272         clk_reg = ioremap_nocache(MRST_CLK_SPI_REG, 16);
 273         if (!clk_reg)
 274                 return -ENOMEM;
 275
 276         /* Get SPI controller operating freq info */
 277         clk_cdiv = readl(clk_reg + dws->bus_num * sizeof(u32));
 278         clk_cdiv &= CLK_SPI_CDIV_MASK;
 279         clk_cdiv >>= CLK_SPI_CDIV_OFFSET;
 280         dws->max_freq = MRST_SPI_CLK_BASE / (clk_cdiv + 1);
 281
 282         iounmap(clk_reg);
 283
 284 #ifdef CONFIG_SPI_DW_MID_DMA
 285         dws->dma_priv = kzalloc(sizeof(struct mid_dma), GFP_KERNEL);
 286         if (!dws->dma_priv)
 287                 return -ENOMEM;
 288         dws->dma_ops = &mid_dma_ops;
 289 #endif
 290         return 0;
 291 }