2 * A driver for the ARM PL022 PrimeCell SSP/SPI bus master.
4 * Copyright (C) 2008-2012 ST-Ericsson AB
5 * Copyright (C) 2006 STMicroelectronics Pvt. Ltd.
7 * Author: Linus Walleij <linus.walleij@stericsson.com>
9 * Initial version inspired by:
10 * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c
11 * Initial adoption to PL022 by:
12 * Sachin Verma <sachin.verma@st.com>
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/device.h>
28 #include <linux/ioport.h>
29 #include <linux/errno.h>
30 #include <linux/interrupt.h>
31 #include <linux/spi/spi.h>
32 #include <linux/delay.h>
33 #include <linux/clk.h>
34 #include <linux/err.h>
35 #include <linux/amba/bus.h>
36 #include <linux/amba/pl022.h>
38 #include <linux/slab.h>
39 #include <linux/dmaengine.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/scatterlist.h>
42 #include <linux/pm_runtime.h>
43 #include <linux/gpio.h>
44 #include <linux/of_gpio.h>
45 #include <linux/pinctrl/consumer.h>
48 * This macro is used to define some register default values.
49 * reg is masked with mask, the OR:ed with an (again masked)
50 * val shifted sb steps to the left.
52 #define SSP_WRITE_BITS(reg, val, mask, sb) \
53 ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask))))
56 * This macro is also used to define some default values.
57 * It will just shift val by sb steps to the left and mask
58 * the result with mask.
60 #define GEN_MASK_BITS(val, mask, sb) \
61 (((val)<<(sb)) & (mask))
64 #define DO_NOT_DRIVE_TX 1
66 #define DO_NOT_QUEUE_DMA 0
73 * Macros to access SSP Registers with their offsets
75 #define SSP_CR0(r) (r + 0x000)
76 #define SSP_CR1(r) (r + 0x004)
77 #define SSP_DR(r) (r + 0x008)
78 #define SSP_SR(r) (r + 0x00C)
79 #define SSP_CPSR(r) (r + 0x010)
80 #define SSP_IMSC(r) (r + 0x014)
81 #define SSP_RIS(r) (r + 0x018)
82 #define SSP_MIS(r) (r + 0x01C)
83 #define SSP_ICR(r) (r + 0x020)
84 #define SSP_DMACR(r) (r + 0x024)
85 #define SSP_ITCR(r) (r + 0x080)
86 #define SSP_ITIP(r) (r + 0x084)
87 #define SSP_ITOP(r) (r + 0x088)
88 #define SSP_TDR(r) (r + 0x08C)
90 #define SSP_PID0(r) (r + 0xFE0)
91 #define SSP_PID1(r) (r + 0xFE4)
92 #define SSP_PID2(r) (r + 0xFE8)
93 #define SSP_PID3(r) (r + 0xFEC)
95 #define SSP_CID0(r) (r + 0xFF0)
96 #define SSP_CID1(r) (r + 0xFF4)
97 #define SSP_CID2(r) (r + 0xFF8)
98 #define SSP_CID3(r) (r + 0xFFC)
101 * SSP Control Register 0 - SSP_CR0
103 #define SSP_CR0_MASK_DSS (0x0FUL << 0)
104 #define SSP_CR0_MASK_FRF (0x3UL << 4)
105 #define SSP_CR0_MASK_SPO (0x1UL << 6)
106 #define SSP_CR0_MASK_SPH (0x1UL << 7)
107 #define SSP_CR0_MASK_SCR (0xFFUL << 8)
110 * The ST version of this block moves som bits
111 * in SSP_CR0 and extends it to 32 bits
113 #define SSP_CR0_MASK_DSS_ST (0x1FUL << 0)
114 #define SSP_CR0_MASK_HALFDUP_ST (0x1UL << 5)
115 #define SSP_CR0_MASK_CSS_ST (0x1FUL << 16)
116 #define SSP_CR0_MASK_FRF_ST (0x3UL << 21)
119 * SSP Control Register 0 - SSP_CR1
121 #define SSP_CR1_MASK_LBM (0x1UL << 0)
122 #define SSP_CR1_MASK_SSE (0x1UL << 1)
123 #define SSP_CR1_MASK_MS (0x1UL << 2)
124 #define SSP_CR1_MASK_SOD (0x1UL << 3)
127 * The ST version of this block adds some bits
130 #define SSP_CR1_MASK_RENDN_ST (0x1UL << 4)
131 #define SSP_CR1_MASK_TENDN_ST (0x1UL << 5)
132 #define SSP_CR1_MASK_MWAIT_ST (0x1UL << 6)
133 #define SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7)
134 #define SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10)
135 /* This one is only in the PL023 variant */
136 #define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13)
139 * SSP Status Register - SSP_SR
141 #define SSP_SR_MASK_TFE (0x1UL << 0) /* Transmit FIFO empty */
142 #define SSP_SR_MASK_TNF (0x1UL << 1) /* Transmit FIFO not full */
143 #define SSP_SR_MASK_RNE (0x1UL << 2) /* Receive FIFO not empty */
144 #define SSP_SR_MASK_RFF (0x1UL << 3) /* Receive FIFO full */
145 #define SSP_SR_MASK_BSY (0x1UL << 4) /* Busy Flag */
148 * SSP Clock Prescale Register - SSP_CPSR
150 #define SSP_CPSR_MASK_CPSDVSR (0xFFUL << 0)
153 * SSP Interrupt Mask Set/Clear Register - SSP_IMSC
155 #define SSP_IMSC_MASK_RORIM (0x1UL << 0) /* Receive Overrun Interrupt mask */
156 #define SSP_IMSC_MASK_RTIM (0x1UL << 1) /* Receive timeout Interrupt mask */
157 #define SSP_IMSC_MASK_RXIM (0x1UL << 2) /* Receive FIFO Interrupt mask */
158 #define SSP_IMSC_MASK_TXIM (0x1UL << 3) /* Transmit FIFO Interrupt mask */
161 * SSP Raw Interrupt Status Register - SSP_RIS
163 /* Receive Overrun Raw Interrupt status */
164 #define SSP_RIS_MASK_RORRIS (0x1UL << 0)
165 /* Receive Timeout Raw Interrupt status */
166 #define SSP_RIS_MASK_RTRIS (0x1UL << 1)
167 /* Receive FIFO Raw Interrupt status */
168 #define SSP_RIS_MASK_RXRIS (0x1UL << 2)
169 /* Transmit FIFO Raw Interrupt status */
170 #define SSP_RIS_MASK_TXRIS (0x1UL << 3)
173 * SSP Masked Interrupt Status Register - SSP_MIS
175 /* Receive Overrun Masked Interrupt status */
176 #define SSP_MIS_MASK_RORMIS (0x1UL << 0)
177 /* Receive Timeout Masked Interrupt status */
178 #define SSP_MIS_MASK_RTMIS (0x1UL << 1)
179 /* Receive FIFO Masked Interrupt status */
180 #define SSP_MIS_MASK_RXMIS (0x1UL << 2)
181 /* Transmit FIFO Masked Interrupt status */
182 #define SSP_MIS_MASK_TXMIS (0x1UL << 3)
185 * SSP Interrupt Clear Register - SSP_ICR
187 /* Receive Overrun Raw Clear Interrupt bit */
188 #define SSP_ICR_MASK_RORIC (0x1UL << 0)
189 /* Receive Timeout Clear Interrupt bit */
190 #define SSP_ICR_MASK_RTIC (0x1UL << 1)
193 * SSP DMA Control Register - SSP_DMACR
195 /* Receive DMA Enable bit */
196 #define SSP_DMACR_MASK_RXDMAE (0x1UL << 0)
197 /* Transmit DMA Enable bit */
198 #define SSP_DMACR_MASK_TXDMAE (0x1UL << 1)
201 * SSP Integration Test control Register - SSP_ITCR
203 #define SSP_ITCR_MASK_ITEN (0x1UL << 0)
204 #define SSP_ITCR_MASK_TESTFIFO (0x1UL << 1)
207 * SSP Integration Test Input Register - SSP_ITIP
209 #define ITIP_MASK_SSPRXD (0x1UL << 0)
210 #define ITIP_MASK_SSPFSSIN (0x1UL << 1)
211 #define ITIP_MASK_SSPCLKIN (0x1UL << 2)
212 #define ITIP_MASK_RXDMAC (0x1UL << 3)
213 #define ITIP_MASK_TXDMAC (0x1UL << 4)
214 #define ITIP_MASK_SSPTXDIN (0x1UL << 5)
217 * SSP Integration Test output Register - SSP_ITOP
219 #define ITOP_MASK_SSPTXD (0x1UL << 0)
220 #define ITOP_MASK_SSPFSSOUT (0x1UL << 1)
221 #define ITOP_MASK_SSPCLKOUT (0x1UL << 2)
222 #define ITOP_MASK_SSPOEn (0x1UL << 3)
223 #define ITOP_MASK_SSPCTLOEn (0x1UL << 4)
224 #define ITOP_MASK_RORINTR (0x1UL << 5)
225 #define ITOP_MASK_RTINTR (0x1UL << 6)
226 #define ITOP_MASK_RXINTR (0x1UL << 7)
227 #define ITOP_MASK_TXINTR (0x1UL << 8)
228 #define ITOP_MASK_INTR (0x1UL << 9)
229 #define ITOP_MASK_RXDMABREQ (0x1UL << 10)
230 #define ITOP_MASK_RXDMASREQ (0x1UL << 11)
231 #define ITOP_MASK_TXDMABREQ (0x1UL << 12)
232 #define ITOP_MASK_TXDMASREQ (0x1UL << 13)
235 * SSP Test Data Register - SSP_TDR
237 #define TDR_MASK_TESTDATA (0xFFFFFFFF)
241 * we use the spi_message.state (void *) pointer to
242 * hold a single state value, that's why all this
243 * (void *) casting is done here.
245 #define STATE_START ((void *) 0)
246 #define STATE_RUNNING ((void *) 1)
247 #define STATE_DONE ((void *) 2)
248 #define STATE_ERROR ((void *) -1)
251 * SSP State - Whether Enabled or Disabled
253 #define SSP_DISABLED (0)
254 #define SSP_ENABLED (1)
257 * SSP DMA State - Whether DMA Enabled or Disabled
259 #define SSP_DMA_DISABLED (0)
260 #define SSP_DMA_ENABLED (1)
265 #define SSP_DEFAULT_CLKRATE 0x2
266 #define SSP_DEFAULT_PRESCALE 0x40
269 * SSP Clock Parameter ranges
271 #define CPSDVR_MIN 0x02
272 #define CPSDVR_MAX 0xFE
277 * SSP Interrupt related Macros
279 #define DEFAULT_SSP_REG_IMSC 0x0UL
280 #define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC
281 #define ENABLE_ALL_INTERRUPTS (~DEFAULT_SSP_REG_IMSC)
283 #define CLEAR_ALL_INTERRUPTS 0x3
285 #define SPI_POLLING_TIMEOUT 1000
288 * The type of reading going on on this chip
298 * The type of writing going on on this chip
308 * struct vendor_data - vendor-specific config parameters
309 * for PL022 derivates
310 * @fifodepth: depth of FIFOs (both)
311 * @max_bpw: maximum number of bits per word
312 * @unidir: supports unidirection transfers
313 * @extended_cr: 32 bit wide control register 0 with extra
314 * features and extra features in CR1 as found in the ST variants
315 * @pl023: supports a subset of the ST extensions called "PL023"
327 * struct pl022 - This is the private SSP driver data structure
328 * @adev: AMBA device model hookup
329 * @vendor: vendor data for the IP block
330 * @phybase: the physical memory where the SSP device resides
331 * @virtbase: the virtual memory where the SSP is mapped
332 * @clk: outgoing clock "SPICLK" for the SPI bus
333 * @master: SPI framework hookup
334 * @master_info: controller-specific data from machine setup
335 * @kworker: thread struct for message pump
336 * @kworker_task: pointer to task for message pump kworker thread
337 * @pump_messages: work struct for scheduling work to the message pump
338 * @queue_lock: spinlock to syncronise access to message queue
339 * @queue: message queue
340 * @busy: message pump is busy
341 * @running: message pump is running
342 * @pump_transfers: Tasklet used in Interrupt Transfer mode
343 * @cur_msg: Pointer to current spi_message being processed
344 * @cur_transfer: Pointer to current spi_transfer
345 * @cur_chip: pointer to current clients chip(assigned from controller_state)
346 * @next_msg_cs_active: the next message in the queue has been examined
347 * and it was found that it uses the same chip select as the previous
348 * message, so we left it active after the previous transfer, and it's
350 * @tx: current position in TX buffer to be read
351 * @tx_end: end position in TX buffer to be read
352 * @rx: current position in RX buffer to be written
353 * @rx_end: end position in RX buffer to be written
354 * @read: the type of read currently going on
355 * @write: the type of write currently going on
356 * @exp_fifo_level: expected FIFO level
357 * @dma_rx_channel: optional channel for RX DMA
358 * @dma_tx_channel: optional channel for TX DMA
359 * @sgt_rx: scattertable for the RX transfer
360 * @sgt_tx: scattertable for the TX transfer
361 * @dummypage: a dummy page used for driving data on the bus with DMA
362 * @cur_cs: current chip select (gpio)
363 * @chipselects: list of chipselects (gpios)
366 struct amba_device *adev;
367 struct vendor_data *vendor;
368 resource_size_t phybase;
369 void __iomem *virtbase;
371 struct spi_master *master;
372 struct pl022_ssp_controller *master_info;
373 /* Message per-transfer pump */
374 struct tasklet_struct pump_transfers;
375 struct spi_message *cur_msg;
376 struct spi_transfer *cur_transfer;
377 struct chip_data *cur_chip;
378 bool next_msg_cs_active;
383 enum ssp_reading read;
384 enum ssp_writing write;
386 enum ssp_rx_level_trig rx_lev_trig;
387 enum ssp_tx_level_trig tx_lev_trig;
389 #ifdef CONFIG_DMA_ENGINE
390 struct dma_chan *dma_rx_channel;
391 struct dma_chan *dma_tx_channel;
392 struct sg_table sgt_rx;
393 struct sg_table sgt_tx;
402 * struct chip_data - To maintain runtime state of SSP for each client chip
403 * @cr0: Value of control register CR0 of SSP - on later ST variants this
404 * register is 32 bits wide rather than just 16
405 * @cr1: Value of control register CR1 of SSP
406 * @dmacr: Value of DMA control Register of SSP
407 * @cpsr: Value of Clock prescale register
408 * @n_bytes: how many bytes(power of 2) reqd for a given data width of client
409 * @enable_dma: Whether to enable DMA or not
410 * @read: function ptr to be used to read when doing xfer for this chip
411 * @write: function ptr to be used to write when doing xfer for this chip
412 * @cs_control: chip select callback provided by chip
413 * @xfer_type: polling/interrupt/DMA
415 * Runtime state of the SSP controller, maintained per chip,
416 * This would be set according to the current message that would be served
425 enum ssp_reading read;
426 enum ssp_writing write;
427 void (*cs_control) (u32 command);
432 * null_cs_control - Dummy chip select function
433 * @command: select/delect the chip
435 * If no chip select function is provided by client this is used as dummy
438 static void null_cs_control(u32 command)
440 pr_debug("pl022: dummy chip select control, CS=0x%x\n", command);
443 static void pl022_cs_control(struct pl022 *pl022, u32 command)
445 if (gpio_is_valid(pl022->cur_cs))
446 gpio_set_value(pl022->cur_cs, command);
448 pl022->cur_chip->cs_control(command);
452 * giveback - current spi_message is over, schedule next message and call
453 * callback of this message. Assumes that caller already
454 * set message->status; dma and pio irqs are blocked
455 * @pl022: SSP driver private data structure
457 static void giveback(struct pl022 *pl022)
459 struct spi_transfer *last_transfer;
460 pl022->next_msg_cs_active = false;
462 last_transfer = list_entry(pl022->cur_msg->transfers.prev,
466 /* Delay if requested before any change in chip select */
467 if (last_transfer->delay_usecs)
469 * FIXME: This runs in interrupt context.
470 * Is this really smart?
472 udelay(last_transfer->delay_usecs);
474 if (!last_transfer->cs_change) {
475 struct spi_message *next_msg;
478 * cs_change was not set. We can keep the chip select
479 * enabled if there is message in the queue and it is
480 * for the same spi device.
482 * We cannot postpone this until pump_messages, because
483 * after calling msg->complete (below) the driver that
484 * sent the current message could be unloaded, which
485 * could invalidate the cs_control() callback...
487 /* get a pointer to the next message, if any */
488 next_msg = spi_get_next_queued_message(pl022->master);
491 * see if the next and current messages point
492 * to the same spi device.
494 if (next_msg && next_msg->spi != pl022->cur_msg->spi)
496 if (!next_msg || pl022->cur_msg->state == STATE_ERROR)
497 pl022_cs_control(pl022, SSP_CHIP_DESELECT);
499 pl022->next_msg_cs_active = true;
503 pl022->cur_msg = NULL;
504 pl022->cur_transfer = NULL;
505 pl022->cur_chip = NULL;
506 spi_finalize_current_message(pl022->master);
508 /* disable the SPI/SSP operation */
509 writew((readw(SSP_CR1(pl022->virtbase)) &
510 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
515 * flush - flush the FIFO to reach a clean state
516 * @pl022: SSP driver private data structure
518 static int flush(struct pl022 *pl022)
520 unsigned long limit = loops_per_jiffy << 1;
522 dev_dbg(&pl022->adev->dev, "flush\n");
524 while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
525 readw(SSP_DR(pl022->virtbase));
526 } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--);
528 pl022->exp_fifo_level = 0;
534 * restore_state - Load configuration of current chip
535 * @pl022: SSP driver private data structure
537 static void restore_state(struct pl022 *pl022)
539 struct chip_data *chip = pl022->cur_chip;
541 if (pl022->vendor->extended_cr)
542 writel(chip->cr0, SSP_CR0(pl022->virtbase));
544 writew(chip->cr0, SSP_CR0(pl022->virtbase));
545 writew(chip->cr1, SSP_CR1(pl022->virtbase));
546 writew(chip->dmacr, SSP_DMACR(pl022->virtbase));
547 writew(chip->cpsr, SSP_CPSR(pl022->virtbase));
548 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
549 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
553 * Default SSP Register Values
555 #define DEFAULT_SSP_REG_CR0 ( \
556 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \
557 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 4) | \
558 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
559 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
560 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \
563 /* ST versions have slightly different bit layout */
564 #define DEFAULT_SSP_REG_CR0_ST ( \
565 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \
566 GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP_ST, 5) | \
567 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
568 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
569 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \
570 GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS_ST, 16) | \
571 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF_ST, 21) \
574 /* The PL023 version is slightly different again */
575 #define DEFAULT_SSP_REG_CR0_ST_PL023 ( \
576 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \
577 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
578 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
579 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \
582 #define DEFAULT_SSP_REG_CR1 ( \
583 GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \
584 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
585 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
586 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) \
589 /* ST versions extend this register to use all 16 bits */
590 #define DEFAULT_SSP_REG_CR1_ST ( \
591 DEFAULT_SSP_REG_CR1 | \
592 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \
593 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \
594 GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT_ST, 6) |\
595 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \
596 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) \
600 * The PL023 variant has further differences: no loopback mode, no microwire
601 * support, and a new clock feedback delay setting.
603 #define DEFAULT_SSP_REG_CR1_ST_PL023 ( \
604 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
605 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
606 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \
607 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \
608 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \
609 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \
610 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) | \
611 GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \
614 #define DEFAULT_SSP_REG_CPSR ( \
615 GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \
618 #define DEFAULT_SSP_REG_DMACR (\
619 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \
620 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \
624 * load_ssp_default_config - Load default configuration for SSP
625 * @pl022: SSP driver private data structure
627 static void load_ssp_default_config(struct pl022 *pl022)
629 if (pl022->vendor->pl023) {
630 writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase));
631 writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase));
632 } else if (pl022->vendor->extended_cr) {
633 writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase));
634 writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase));
636 writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase));
637 writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase));
639 writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase));
640 writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase));
641 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
642 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
646 * This will write to TX and read from RX according to the parameters
649 static void readwriter(struct pl022 *pl022)
653 * The FIFO depth is different between primecell variants.
654 * I believe filling in too much in the FIFO might cause
655 * errons in 8bit wide transfers on ARM variants (just 8 words
656 * FIFO, means only 8x8 = 64 bits in FIFO) at least.
658 * To prevent this issue, the TX FIFO is only filled to the
659 * unused RX FIFO fill length, regardless of what the TX
660 * FIFO status flag indicates.
662 dev_dbg(&pl022->adev->dev,
663 "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n",
664 __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end);
666 /* Read as much as you can */
667 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
668 && (pl022->rx < pl022->rx_end)) {
669 switch (pl022->read) {
671 readw(SSP_DR(pl022->virtbase));
674 *(u8 *) (pl022->rx) =
675 readw(SSP_DR(pl022->virtbase)) & 0xFFU;
678 *(u16 *) (pl022->rx) =
679 (u16) readw(SSP_DR(pl022->virtbase));
682 *(u32 *) (pl022->rx) =
683 readl(SSP_DR(pl022->virtbase));
686 pl022->rx += (pl022->cur_chip->n_bytes);
687 pl022->exp_fifo_level--;
690 * Write as much as possible up to the RX FIFO size
692 while ((pl022->exp_fifo_level < pl022->vendor->fifodepth)
693 && (pl022->tx < pl022->tx_end)) {
694 switch (pl022->write) {
696 writew(0x0, SSP_DR(pl022->virtbase));
699 writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase));
702 writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase));
705 writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase));
708 pl022->tx += (pl022->cur_chip->n_bytes);
709 pl022->exp_fifo_level++;
711 * This inner reader takes care of things appearing in the RX
712 * FIFO as we're transmitting. This will happen a lot since the
713 * clock starts running when you put things into the TX FIFO,
714 * and then things are continuously clocked into the RX FIFO.
716 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
717 && (pl022->rx < pl022->rx_end)) {
718 switch (pl022->read) {
720 readw(SSP_DR(pl022->virtbase));
723 *(u8 *) (pl022->rx) =
724 readw(SSP_DR(pl022->virtbase)) & 0xFFU;
727 *(u16 *) (pl022->rx) =
728 (u16) readw(SSP_DR(pl022->virtbase));
731 *(u32 *) (pl022->rx) =
732 readl(SSP_DR(pl022->virtbase));
735 pl022->rx += (pl022->cur_chip->n_bytes);
736 pl022->exp_fifo_level--;
740 * When we exit here the TX FIFO should be full and the RX FIFO
746 * next_transfer - Move to the Next transfer in the current spi message
747 * @pl022: SSP driver private data structure
749 * This function moves though the linked list of spi transfers in the
750 * current spi message and returns with the state of current spi
751 * message i.e whether its last transfer is done(STATE_DONE) or
752 * Next transfer is ready(STATE_RUNNING)
754 static void *next_transfer(struct pl022 *pl022)
756 struct spi_message *msg = pl022->cur_msg;
757 struct spi_transfer *trans = pl022->cur_transfer;
759 /* Move to next transfer */
760 if (trans->transfer_list.next != &msg->transfers) {
761 pl022->cur_transfer =
762 list_entry(trans->transfer_list.next,
763 struct spi_transfer, transfer_list);
764 return STATE_RUNNING;
770 * This DMA functionality is only compiled in if we have
771 * access to the generic DMA devices/DMA engine.
773 #ifdef CONFIG_DMA_ENGINE
774 static void unmap_free_dma_scatter(struct pl022 *pl022)
776 /* Unmap and free the SG tables */
777 dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl,
778 pl022->sgt_tx.nents, DMA_TO_DEVICE);
779 dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl,
780 pl022->sgt_rx.nents, DMA_FROM_DEVICE);
781 sg_free_table(&pl022->sgt_rx);
782 sg_free_table(&pl022->sgt_tx);
785 static void dma_callback(void *data)
787 struct pl022 *pl022 = data;
788 struct spi_message *msg = pl022->cur_msg;
790 BUG_ON(!pl022->sgt_rx.sgl);
794 * Optionally dump out buffers to inspect contents, this is
795 * good if you want to convince yourself that the loopback
796 * read/write contents are the same, when adopting to a new
800 struct scatterlist *sg;
803 dma_sync_sg_for_cpu(&pl022->adev->dev,
808 for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) {
809 dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i);
810 print_hex_dump(KERN_ERR, "SPI RX: ",
818 for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) {
819 dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i);
820 print_hex_dump(KERN_ERR, "SPI TX: ",
831 unmap_free_dma_scatter(pl022);
833 /* Update total bytes transferred */
834 msg->actual_length += pl022->cur_transfer->len;
835 if (pl022->cur_transfer->cs_change)
836 pl022_cs_control(pl022, SSP_CHIP_DESELECT);
838 /* Move to next transfer */
839 msg->state = next_transfer(pl022);
840 tasklet_schedule(&pl022->pump_transfers);
843 static void setup_dma_scatter(struct pl022 *pl022,
846 struct sg_table *sgtab)
848 struct scatterlist *sg;
849 int bytesleft = length;
855 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) {
857 * If there are less bytes left than what fits
858 * in the current page (plus page alignment offset)
859 * we just feed in this, else we stuff in as much
862 if (bytesleft < (PAGE_SIZE - offset_in_page(bufp)))
863 mapbytes = bytesleft;
865 mapbytes = PAGE_SIZE - offset_in_page(bufp);
866 sg_set_page(sg, virt_to_page(bufp),
867 mapbytes, offset_in_page(bufp));
869 bytesleft -= mapbytes;
870 dev_dbg(&pl022->adev->dev,
871 "set RX/TX target page @ %p, %d bytes, %d left\n",
872 bufp, mapbytes, bytesleft);
875 /* Map the dummy buffer on every page */
876 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) {
877 if (bytesleft < PAGE_SIZE)
878 mapbytes = bytesleft;
880 mapbytes = PAGE_SIZE;
881 sg_set_page(sg, virt_to_page(pl022->dummypage),
883 bytesleft -= mapbytes;
884 dev_dbg(&pl022->adev->dev,
885 "set RX/TX to dummy page %d bytes, %d left\n",
886 mapbytes, bytesleft);
894 * configure_dma - configures the channels for the next transfer
895 * @pl022: SSP driver's private data structure
897 static int configure_dma(struct pl022 *pl022)
899 struct dma_slave_config rx_conf = {
900 .src_addr = SSP_DR(pl022->phybase),
901 .direction = DMA_DEV_TO_MEM,
904 struct dma_slave_config tx_conf = {
905 .dst_addr = SSP_DR(pl022->phybase),
906 .direction = DMA_MEM_TO_DEV,
911 int rx_sglen, tx_sglen;
912 struct dma_chan *rxchan = pl022->dma_rx_channel;
913 struct dma_chan *txchan = pl022->dma_tx_channel;
914 struct dma_async_tx_descriptor *rxdesc;
915 struct dma_async_tx_descriptor *txdesc;
917 /* Check that the channels are available */
918 if (!rxchan || !txchan)
922 * If supplied, the DMA burstsize should equal the FIFO trigger level.
923 * Notice that the DMA engine uses one-to-one mapping. Since we can
924 * not trigger on 2 elements this needs explicit mapping rather than
927 switch (pl022->rx_lev_trig) {
928 case SSP_RX_1_OR_MORE_ELEM:
929 rx_conf.src_maxburst = 1;
931 case SSP_RX_4_OR_MORE_ELEM:
932 rx_conf.src_maxburst = 4;
934 case SSP_RX_8_OR_MORE_ELEM:
935 rx_conf.src_maxburst = 8;
937 case SSP_RX_16_OR_MORE_ELEM:
938 rx_conf.src_maxburst = 16;
940 case SSP_RX_32_OR_MORE_ELEM:
941 rx_conf.src_maxburst = 32;
944 rx_conf.src_maxburst = pl022->vendor->fifodepth >> 1;
948 switch (pl022->tx_lev_trig) {
949 case SSP_TX_1_OR_MORE_EMPTY_LOC:
950 tx_conf.dst_maxburst = 1;
952 case SSP_TX_4_OR_MORE_EMPTY_LOC:
953 tx_conf.dst_maxburst = 4;
955 case SSP_TX_8_OR_MORE_EMPTY_LOC:
956 tx_conf.dst_maxburst = 8;
958 case SSP_TX_16_OR_MORE_EMPTY_LOC:
959 tx_conf.dst_maxburst = 16;
961 case SSP_TX_32_OR_MORE_EMPTY_LOC:
962 tx_conf.dst_maxburst = 32;
965 tx_conf.dst_maxburst = pl022->vendor->fifodepth >> 1;
969 switch (pl022->read) {
971 /* Use the same as for writing */
972 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
975 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
978 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
981 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
985 switch (pl022->write) {
987 /* Use the same as for reading */
988 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
991 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
994 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
997 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1001 /* SPI pecularity: we need to read and write the same width */
1002 if (rx_conf.src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
1003 rx_conf.src_addr_width = tx_conf.dst_addr_width;
1004 if (tx_conf.dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
1005 tx_conf.dst_addr_width = rx_conf.src_addr_width;
1006 BUG_ON(rx_conf.src_addr_width != tx_conf.dst_addr_width);
1008 dmaengine_slave_config(rxchan, &rx_conf);
1009 dmaengine_slave_config(txchan, &tx_conf);
1011 /* Create sglists for the transfers */
1012 pages = DIV_ROUND_UP(pl022->cur_transfer->len, PAGE_SIZE);
1013 dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages);
1015 ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_ATOMIC);
1017 goto err_alloc_rx_sg;
1019 ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_ATOMIC);
1021 goto err_alloc_tx_sg;
1023 /* Fill in the scatterlists for the RX+TX buffers */
1024 setup_dma_scatter(pl022, pl022->rx,
1025 pl022->cur_transfer->len, &pl022->sgt_rx);
1026 setup_dma_scatter(pl022, pl022->tx,
1027 pl022->cur_transfer->len, &pl022->sgt_tx);
1029 /* Map DMA buffers */
1030 rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl,
1031 pl022->sgt_rx.nents, DMA_FROM_DEVICE);
1035 tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl,
1036 pl022->sgt_tx.nents, DMA_TO_DEVICE);
1040 /* Send both scatterlists */
1041 rxdesc = dmaengine_prep_slave_sg(rxchan,
1045 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1049 txdesc = dmaengine_prep_slave_sg(txchan,
1053 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1057 /* Put the callback on the RX transfer only, that should finish last */
1058 rxdesc->callback = dma_callback;
1059 rxdesc->callback_param = pl022;
1061 /* Submit and fire RX and TX with TX last so we're ready to read! */
1062 dmaengine_submit(rxdesc);
1063 dmaengine_submit(txdesc);
1064 dma_async_issue_pending(rxchan);
1065 dma_async_issue_pending(txchan);
1066 pl022->dma_running = true;
1071 dmaengine_terminate_all(txchan);
1073 dmaengine_terminate_all(rxchan);
1074 dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl,
1075 pl022->sgt_tx.nents, DMA_TO_DEVICE);
1077 dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl,
1078 pl022->sgt_tx.nents, DMA_FROM_DEVICE);
1080 sg_free_table(&pl022->sgt_tx);
1082 sg_free_table(&pl022->sgt_rx);
1087 static int pl022_dma_probe(struct pl022 *pl022)
1089 dma_cap_mask_t mask;
1091 /* Try to acquire a generic DMA engine slave channel */
1093 dma_cap_set(DMA_SLAVE, mask);
1095 * We need both RX and TX channels to do DMA, else do none
1098 pl022->dma_rx_channel = dma_request_channel(mask,
1099 pl022->master_info->dma_filter,
1100 pl022->master_info->dma_rx_param);
1101 if (!pl022->dma_rx_channel) {
1102 dev_dbg(&pl022->adev->dev, "no RX DMA channel!\n");
1106 pl022->dma_tx_channel = dma_request_channel(mask,
1107 pl022->master_info->dma_filter,
1108 pl022->master_info->dma_tx_param);
1109 if (!pl022->dma_tx_channel) {
1110 dev_dbg(&pl022->adev->dev, "no TX DMA channel!\n");
1114 pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL);
1115 if (!pl022->dummypage) {
1116 dev_dbg(&pl022->adev->dev, "no DMA dummypage!\n");
1117 goto err_no_dummypage;
1120 dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n",
1121 dma_chan_name(pl022->dma_rx_channel),
1122 dma_chan_name(pl022->dma_tx_channel));
1127 dma_release_channel(pl022->dma_tx_channel);
1129 dma_release_channel(pl022->dma_rx_channel);
1130 pl022->dma_rx_channel = NULL;
1132 dev_err(&pl022->adev->dev,
1133 "Failed to work in dma mode, work without dma!\n");
1137 static int pl022_dma_autoprobe(struct pl022 *pl022)
1139 struct device *dev = &pl022->adev->dev;
1141 /* automatically configure DMA channels from platform, normally using DT */
1142 pl022->dma_rx_channel = dma_request_slave_channel(dev, "rx");
1143 if (!pl022->dma_rx_channel)
1146 pl022->dma_tx_channel = dma_request_slave_channel(dev, "tx");
1147 if (!pl022->dma_tx_channel)
1150 pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL);
1151 if (!pl022->dummypage)
1152 goto err_no_dummypage;
1157 dma_release_channel(pl022->dma_tx_channel);
1158 pl022->dma_tx_channel = NULL;
1160 dma_release_channel(pl022->dma_rx_channel);
1161 pl022->dma_rx_channel = NULL;
1166 static void terminate_dma(struct pl022 *pl022)
1168 struct dma_chan *rxchan = pl022->dma_rx_channel;
1169 struct dma_chan *txchan = pl022->dma_tx_channel;
1171 dmaengine_terminate_all(rxchan);
1172 dmaengine_terminate_all(txchan);
1173 unmap_free_dma_scatter(pl022);
1174 pl022->dma_running = false;
1177 static void pl022_dma_remove(struct pl022 *pl022)
1179 if (pl022->dma_running)
1180 terminate_dma(pl022);
1181 if (pl022->dma_tx_channel)
1182 dma_release_channel(pl022->dma_tx_channel);
1183 if (pl022->dma_rx_channel)
1184 dma_release_channel(pl022->dma_rx_channel);
1185 kfree(pl022->dummypage);
1189 static inline int configure_dma(struct pl022 *pl022)
1194 static inline int pl022_dma_autoprobe(struct pl022 *pl022)
1199 static inline int pl022_dma_probe(struct pl022 *pl022)
1204 static inline void pl022_dma_remove(struct pl022 *pl022)
1210 * pl022_interrupt_handler - Interrupt handler for SSP controller
1212 * This function handles interrupts generated for an interrupt based transfer.
1213 * If a receive overrun (ROR) interrupt is there then we disable SSP, flag the
1214 * current message's state as STATE_ERROR and schedule the tasklet
1215 * pump_transfers which will do the postprocessing of the current message by
1216 * calling giveback(). Otherwise it reads data from RX FIFO till there is no
1217 * more data, and writes data in TX FIFO till it is not full. If we complete
1218 * the transfer we move to the next transfer and schedule the tasklet.
1220 static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id)
1222 struct pl022 *pl022 = dev_id;
1223 struct spi_message *msg = pl022->cur_msg;
1227 if (unlikely(!msg)) {
1228 dev_err(&pl022->adev->dev,
1229 "bad message state in interrupt handler");
1234 /* Read the Interrupt Status Register */
1235 irq_status = readw(SSP_MIS(pl022->virtbase));
1237 if (unlikely(!irq_status))
1241 * This handles the FIFO interrupts, the timeout
1242 * interrupts are flatly ignored, they cannot be
1245 if (unlikely(irq_status & SSP_MIS_MASK_RORMIS)) {
1247 * Overrun interrupt - bail out since our Data has been
1250 dev_err(&pl022->adev->dev, "FIFO overrun\n");
1251 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF)
1252 dev_err(&pl022->adev->dev,
1253 "RXFIFO is full\n");
1254 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_TNF)
1255 dev_err(&pl022->adev->dev,
1256 "TXFIFO is full\n");
1259 * Disable and clear interrupts, disable SSP,
1260 * mark message with bad status so it can be
1263 writew(DISABLE_ALL_INTERRUPTS,
1264 SSP_IMSC(pl022->virtbase));
1265 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
1266 writew((readw(SSP_CR1(pl022->virtbase)) &
1267 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
1268 msg->state = STATE_ERROR;
1270 /* Schedule message queue handler */
1271 tasklet_schedule(&pl022->pump_transfers);
1277 if ((pl022->tx == pl022->tx_end) && (flag == 0)) {
1279 /* Disable Transmit interrupt, enable receive interrupt */
1280 writew((readw(SSP_IMSC(pl022->virtbase)) &
1281 ~SSP_IMSC_MASK_TXIM) | SSP_IMSC_MASK_RXIM,
1282 SSP_IMSC(pl022->virtbase));
1286 * Since all transactions must write as much as shall be read,
1287 * we can conclude the entire transaction once RX is complete.
1288 * At this point, all TX will always be finished.
1290 if (pl022->rx >= pl022->rx_end) {
1291 writew(DISABLE_ALL_INTERRUPTS,
1292 SSP_IMSC(pl022->virtbase));
1293 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
1294 if (unlikely(pl022->rx > pl022->rx_end)) {
1295 dev_warn(&pl022->adev->dev, "read %u surplus "
1296 "bytes (did you request an odd "
1297 "number of bytes on a 16bit bus?)\n",
1298 (u32) (pl022->rx - pl022->rx_end));
1300 /* Update total bytes transferred */
1301 msg->actual_length += pl022->cur_transfer->len;
1302 if (pl022->cur_transfer->cs_change)
1303 pl022_cs_control(pl022, SSP_CHIP_DESELECT);
1304 /* Move to next transfer */
1305 msg->state = next_transfer(pl022);
1306 tasklet_schedule(&pl022->pump_transfers);
1314 * This sets up the pointers to memory for the next message to
1315 * send out on the SPI bus.
1317 static int set_up_next_transfer(struct pl022 *pl022,
1318 struct spi_transfer *transfer)
1322 /* Sanity check the message for this bus width */
1323 residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes;
1324 if (unlikely(residue != 0)) {
1325 dev_err(&pl022->adev->dev,
1326 "message of %u bytes to transmit but the current "
1327 "chip bus has a data width of %u bytes!\n",
1328 pl022->cur_transfer->len,
1329 pl022->cur_chip->n_bytes);
1330 dev_err(&pl022->adev->dev, "skipping this message\n");
1333 pl022->tx = (void *)transfer->tx_buf;
1334 pl022->tx_end = pl022->tx + pl022->cur_transfer->len;
1335 pl022->rx = (void *)transfer->rx_buf;
1336 pl022->rx_end = pl022->rx + pl022->cur_transfer->len;
1338 pl022->tx ? pl022->cur_chip->write : WRITING_NULL;
1339 pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL;
1344 * pump_transfers - Tasklet function which schedules next transfer
1345 * when running in interrupt or DMA transfer mode.
1346 * @data: SSP driver private data structure
1349 static void pump_transfers(unsigned long data)
1351 struct pl022 *pl022 = (struct pl022 *) data;
1352 struct spi_message *message = NULL;
1353 struct spi_transfer *transfer = NULL;
1354 struct spi_transfer *previous = NULL;
1356 /* Get current state information */
1357 message = pl022->cur_msg;
1358 transfer = pl022->cur_transfer;
1360 /* Handle for abort */
1361 if (message->state == STATE_ERROR) {
1362 message->status = -EIO;
1367 /* Handle end of message */
1368 if (message->state == STATE_DONE) {
1369 message->status = 0;
1374 /* Delay if requested at end of transfer before CS change */
1375 if (message->state == STATE_RUNNING) {
1376 previous = list_entry(transfer->transfer_list.prev,
1377 struct spi_transfer,
1379 if (previous->delay_usecs)
1381 * FIXME: This runs in interrupt context.
1382 * Is this really smart?
1384 udelay(previous->delay_usecs);
1386 /* Reselect chip select only if cs_change was requested */
1387 if (previous->cs_change)
1388 pl022_cs_control(pl022, SSP_CHIP_SELECT);
1391 message->state = STATE_RUNNING;
1394 if (set_up_next_transfer(pl022, transfer)) {
1395 message->state = STATE_ERROR;
1396 message->status = -EIO;
1400 /* Flush the FIFOs and let's go! */
1403 if (pl022->cur_chip->enable_dma) {
1404 if (configure_dma(pl022)) {
1405 dev_dbg(&pl022->adev->dev,
1406 "configuration of DMA failed, fall back to interrupt mode\n");
1407 goto err_config_dma;
1413 /* enable all interrupts except RX */
1414 writew(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM, SSP_IMSC(pl022->virtbase));
1417 static void do_interrupt_dma_transfer(struct pl022 *pl022)
1420 * Default is to enable all interrupts except RX -
1421 * this will be enabled once TX is complete
1423 u32 irqflags = ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM;
1425 /* Enable target chip, if not already active */
1426 if (!pl022->next_msg_cs_active)
1427 pl022_cs_control(pl022, SSP_CHIP_SELECT);
1429 if (set_up_next_transfer(pl022, pl022->cur_transfer)) {
1431 pl022->cur_msg->state = STATE_ERROR;
1432 pl022->cur_msg->status = -EIO;
1436 /* If we're using DMA, set up DMA here */
1437 if (pl022->cur_chip->enable_dma) {
1438 /* Configure DMA transfer */
1439 if (configure_dma(pl022)) {
1440 dev_dbg(&pl022->adev->dev,
1441 "configuration of DMA failed, fall back to interrupt mode\n");
1442 goto err_config_dma;
1444 /* Disable interrupts in DMA mode, IRQ from DMA controller */
1445 irqflags = DISABLE_ALL_INTERRUPTS;
1448 /* Enable SSP, turn on interrupts */
1449 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
1450 SSP_CR1(pl022->virtbase));
1451 writew(irqflags, SSP_IMSC(pl022->virtbase));
1454 static void do_polling_transfer(struct pl022 *pl022)
1456 struct spi_message *message = NULL;
1457 struct spi_transfer *transfer = NULL;
1458 struct spi_transfer *previous = NULL;
1459 struct chip_data *chip;
1460 unsigned long time, timeout;
1462 chip = pl022->cur_chip;
1463 message = pl022->cur_msg;
1465 while (message->state != STATE_DONE) {
1466 /* Handle for abort */
1467 if (message->state == STATE_ERROR)
1469 transfer = pl022->cur_transfer;
1471 /* Delay if requested at end of transfer */
1472 if (message->state == STATE_RUNNING) {
1474 list_entry(transfer->transfer_list.prev,
1475 struct spi_transfer, transfer_list);
1476 if (previous->delay_usecs)
1477 udelay(previous->delay_usecs);
1478 if (previous->cs_change)
1479 pl022_cs_control(pl022, SSP_CHIP_SELECT);
1482 message->state = STATE_RUNNING;
1483 if (!pl022->next_msg_cs_active)
1484 pl022_cs_control(pl022, SSP_CHIP_SELECT);
1487 /* Configuration Changing Per Transfer */
1488 if (set_up_next_transfer(pl022, transfer)) {
1490 message->state = STATE_ERROR;
1493 /* Flush FIFOs and enable SSP */
1495 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
1496 SSP_CR1(pl022->virtbase));
1498 dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n");
1500 timeout = jiffies + msecs_to_jiffies(SPI_POLLING_TIMEOUT);
1501 while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) {
1504 if (time_after(time, timeout)) {
1505 dev_warn(&pl022->adev->dev,
1506 "%s: timeout!\n", __func__);
1507 message->state = STATE_ERROR;
1513 /* Update total byte transferred */
1514 message->actual_length += pl022->cur_transfer->len;
1515 if (pl022->cur_transfer->cs_change)
1516 pl022_cs_control(pl022, SSP_CHIP_DESELECT);
1517 /* Move to next transfer */
1518 message->state = next_transfer(pl022);
1521 /* Handle end of message */
1522 if (message->state == STATE_DONE)
1523 message->status = 0;
1525 message->status = -EIO;
1531 static int pl022_transfer_one_message(struct spi_master *master,
1532 struct spi_message *msg)
1534 struct pl022 *pl022 = spi_master_get_devdata(master);
1536 /* Initial message state */
1537 pl022->cur_msg = msg;
1538 msg->state = STATE_START;
1540 pl022->cur_transfer = list_entry(msg->transfers.next,
1541 struct spi_transfer, transfer_list);
1543 /* Setup the SPI using the per chip configuration */
1544 pl022->cur_chip = spi_get_ctldata(msg->spi);
1545 pl022->cur_cs = pl022->chipselects[msg->spi->chip_select];
1547 restore_state(pl022);
1550 if (pl022->cur_chip->xfer_type == POLLING_TRANSFER)
1551 do_polling_transfer(pl022);
1553 do_interrupt_dma_transfer(pl022);
1558 static int pl022_unprepare_transfer_hardware(struct spi_master *master)
1560 struct pl022 *pl022 = spi_master_get_devdata(master);
1562 /* nothing more to do - disable spi/ssp and power off */
1563 writew((readw(SSP_CR1(pl022->virtbase)) &
1564 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
1569 static int verify_controller_parameters(struct pl022 *pl022,
1570 struct pl022_config_chip const *chip_info)
1572 if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI)
1573 || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) {
1574 dev_err(&pl022->adev->dev,
1575 "interface is configured incorrectly\n");
1578 if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) &&
1579 (!pl022->vendor->unidir)) {
1580 dev_err(&pl022->adev->dev,
1581 "unidirectional mode not supported in this "
1582 "hardware version\n");
1585 if ((chip_info->hierarchy != SSP_MASTER)
1586 && (chip_info->hierarchy != SSP_SLAVE)) {
1587 dev_err(&pl022->adev->dev,
1588 "hierarchy is configured incorrectly\n");
1591 if ((chip_info->com_mode != INTERRUPT_TRANSFER)
1592 && (chip_info->com_mode != DMA_TRANSFER)
1593 && (chip_info->com_mode != POLLING_TRANSFER)) {
1594 dev_err(&pl022->adev->dev,
1595 "Communication mode is configured incorrectly\n");
1598 switch (chip_info->rx_lev_trig) {
1599 case SSP_RX_1_OR_MORE_ELEM:
1600 case SSP_RX_4_OR_MORE_ELEM:
1601 case SSP_RX_8_OR_MORE_ELEM:
1602 /* These are always OK, all variants can handle this */
1604 case SSP_RX_16_OR_MORE_ELEM:
1605 if (pl022->vendor->fifodepth < 16) {
1606 dev_err(&pl022->adev->dev,
1607 "RX FIFO Trigger Level is configured incorrectly\n");
1611 case SSP_RX_32_OR_MORE_ELEM:
1612 if (pl022->vendor->fifodepth < 32) {
1613 dev_err(&pl022->adev->dev,
1614 "RX FIFO Trigger Level is configured incorrectly\n");
1619 dev_err(&pl022->adev->dev,
1620 "RX FIFO Trigger Level is configured incorrectly\n");
1623 switch (chip_info->tx_lev_trig) {
1624 case SSP_TX_1_OR_MORE_EMPTY_LOC:
1625 case SSP_TX_4_OR_MORE_EMPTY_LOC:
1626 case SSP_TX_8_OR_MORE_EMPTY_LOC:
1627 /* These are always OK, all variants can handle this */
1629 case SSP_TX_16_OR_MORE_EMPTY_LOC:
1630 if (pl022->vendor->fifodepth < 16) {
1631 dev_err(&pl022->adev->dev,
1632 "TX FIFO Trigger Level is configured incorrectly\n");
1636 case SSP_TX_32_OR_MORE_EMPTY_LOC:
1637 if (pl022->vendor->fifodepth < 32) {
1638 dev_err(&pl022->adev->dev,
1639 "TX FIFO Trigger Level is configured incorrectly\n");
1644 dev_err(&pl022->adev->dev,
1645 "TX FIFO Trigger Level is configured incorrectly\n");
1648 if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) {
1649 if ((chip_info->ctrl_len < SSP_BITS_4)
1650 || (chip_info->ctrl_len > SSP_BITS_32)) {
1651 dev_err(&pl022->adev->dev,
1652 "CTRL LEN is configured incorrectly\n");
1655 if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO)
1656 && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) {
1657 dev_err(&pl022->adev->dev,
1658 "Wait State is configured incorrectly\n");
1661 /* Half duplex is only available in the ST Micro version */
1662 if (pl022->vendor->extended_cr) {
1663 if ((chip_info->duplex !=
1664 SSP_MICROWIRE_CHANNEL_FULL_DUPLEX)
1665 && (chip_info->duplex !=
1666 SSP_MICROWIRE_CHANNEL_HALF_DUPLEX)) {
1667 dev_err(&pl022->adev->dev,
1668 "Microwire duplex mode is configured incorrectly\n");
1672 if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX)
1673 dev_err(&pl022->adev->dev,
1674 "Microwire half duplex mode requested,"
1675 " but this is only available in the"
1676 " ST version of PL022\n");
1683 static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr)
1685 return rate / (cpsdvsr * (1 + scr));
1688 static int calculate_effective_freq(struct pl022 *pl022, int freq, struct
1689 ssp_clock_params * clk_freq)
1691 /* Lets calculate the frequency parameters */
1692 u16 cpsdvsr = CPSDVR_MIN, scr = SCR_MIN;
1693 u32 rate, max_tclk, min_tclk, best_freq = 0, best_cpsdvsr = 0,
1694 best_scr = 0, tmp, found = 0;
1696 rate = clk_get_rate(pl022->clk);
1697 /* cpsdvscr = 2 & scr 0 */
1698 max_tclk = spi_rate(rate, CPSDVR_MIN, SCR_MIN);
1699 /* cpsdvsr = 254 & scr = 255 */
1700 min_tclk = spi_rate(rate, CPSDVR_MAX, SCR_MAX);
1702 if (freq > max_tclk)
1703 dev_warn(&pl022->adev->dev,
1704 "Max speed that can be programmed is %d Hz, you requested %d\n",
1707 if (freq < min_tclk) {
1708 dev_err(&pl022->adev->dev,
1709 "Requested frequency: %d Hz is less than minimum possible %d Hz\n",
1715 * best_freq will give closest possible available rate (<= requested
1716 * freq) for all values of scr & cpsdvsr.
1718 while ((cpsdvsr <= CPSDVR_MAX) && !found) {
1719 while (scr <= SCR_MAX) {
1720 tmp = spi_rate(rate, cpsdvsr, scr);
1723 /* we need lower freq */
1729 * If found exact value, mark found and break.
1730 * If found more closer value, update and break.
1732 if (tmp > best_freq) {
1734 best_cpsdvsr = cpsdvsr;
1741 * increased scr will give lower rates, which are not
1750 WARN(!best_freq, "pl022: Matching cpsdvsr and scr not found for %d Hz rate \n",
1753 clk_freq->cpsdvsr = (u8) (best_cpsdvsr & 0xFF);
1754 clk_freq->scr = (u8) (best_scr & 0xFF);
1755 dev_dbg(&pl022->adev->dev,
1756 "SSP Target Frequency is: %u, Effective Frequency is %u\n",
1758 dev_dbg(&pl022->adev->dev, "SSP cpsdvsr = %d, scr = %d\n",
1759 clk_freq->cpsdvsr, clk_freq->scr);
1765 * A piece of default chip info unless the platform
1768 static const struct pl022_config_chip pl022_default_chip_info = {
1769 .com_mode = POLLING_TRANSFER,
1770 .iface = SSP_INTERFACE_MOTOROLA_SPI,
1771 .hierarchy = SSP_SLAVE,
1772 .slave_tx_disable = DO_NOT_DRIVE_TX,
1773 .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM,
1774 .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC,
1775 .ctrl_len = SSP_BITS_8,
1776 .wait_state = SSP_MWIRE_WAIT_ZERO,
1777 .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
1778 .cs_control = null_cs_control,
1782 * pl022_setup - setup function registered to SPI master framework
1783 * @spi: spi device which is requesting setup
1785 * This function is registered to the SPI framework for this SPI master
1786 * controller. If it is the first time when setup is called by this device,
1787 * this function will initialize the runtime state for this chip and save
1788 * the same in the device structure. Else it will update the runtime info
1789 * with the updated chip info. Nothing is really being written to the
1790 * controller hardware here, that is not done until the actual transfer
1793 static int pl022_setup(struct spi_device *spi)
1795 struct pl022_config_chip const *chip_info;
1796 struct pl022_config_chip chip_info_dt;
1797 struct chip_data *chip;
1798 struct ssp_clock_params clk_freq = { .cpsdvsr = 0, .scr = 0};
1800 struct pl022 *pl022 = spi_master_get_devdata(spi->master);
1801 unsigned int bits = spi->bits_per_word;
1803 struct device_node *np = spi->dev.of_node;
1805 if (!spi->max_speed_hz)
1808 /* Get controller_state if one is supplied */
1809 chip = spi_get_ctldata(spi);
1812 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1815 "cannot allocate controller state\n");
1819 "allocated memory for controller's runtime state\n");
1822 /* Get controller data if one is supplied */
1823 chip_info = spi->controller_data;
1825 if (chip_info == NULL) {
1827 chip_info_dt = pl022_default_chip_info;
1829 chip_info_dt.hierarchy = SSP_MASTER;
1830 of_property_read_u32(np, "pl022,interface",
1831 &chip_info_dt.iface);
1832 of_property_read_u32(np, "pl022,com-mode",
1833 &chip_info_dt.com_mode);
1834 of_property_read_u32(np, "pl022,rx-level-trig",
1835 &chip_info_dt.rx_lev_trig);
1836 of_property_read_u32(np, "pl022,tx-level-trig",
1837 &chip_info_dt.tx_lev_trig);
1838 of_property_read_u32(np, "pl022,ctrl-len",
1839 &chip_info_dt.ctrl_len);
1840 of_property_read_u32(np, "pl022,wait-state",
1841 &chip_info_dt.wait_state);
1842 of_property_read_u32(np, "pl022,duplex",
1843 &chip_info_dt.duplex);
1845 chip_info = &chip_info_dt;
1847 chip_info = &pl022_default_chip_info;
1848 /* spi_board_info.controller_data not is supplied */
1850 "using default controller_data settings\n");
1854 "using user supplied controller_data settings\n");
1857 * We can override with custom divisors, else we use the board
1860 if ((0 == chip_info->clk_freq.cpsdvsr)
1861 && (0 == chip_info->clk_freq.scr)) {
1862 status = calculate_effective_freq(pl022,
1866 goto err_config_params;
1868 memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq));
1869 if ((clk_freq.cpsdvsr % 2) != 0)
1871 clk_freq.cpsdvsr - 1;
1873 if ((clk_freq.cpsdvsr < CPSDVR_MIN)
1874 || (clk_freq.cpsdvsr > CPSDVR_MAX)) {
1877 "cpsdvsr is configured incorrectly\n");
1878 goto err_config_params;
1881 status = verify_controller_parameters(pl022, chip_info);
1883 dev_err(&spi->dev, "controller data is incorrect");
1884 goto err_config_params;
1887 pl022->rx_lev_trig = chip_info->rx_lev_trig;
1888 pl022->tx_lev_trig = chip_info->tx_lev_trig;
1890 /* Now set controller state based on controller data */
1891 chip->xfer_type = chip_info->com_mode;
1892 if (!chip_info->cs_control) {
1893 chip->cs_control = null_cs_control;
1894 if (!gpio_is_valid(pl022->chipselects[spi->chip_select]))
1896 "invalid chip select\n");
1898 chip->cs_control = chip_info->cs_control;
1900 /* Check bits per word with vendor specific range */
1901 if ((bits <= 3) || (bits > pl022->vendor->max_bpw)) {
1903 dev_err(&spi->dev, "illegal data size for this controller!\n");
1904 dev_err(&spi->dev, "This controller can only handle 4 <= n <= %d bit words\n",
1905 pl022->vendor->max_bpw);
1906 goto err_config_params;
1907 } else if (bits <= 8) {
1908 dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n");
1910 chip->read = READING_U8;
1911 chip->write = WRITING_U8;
1912 } else if (bits <= 16) {
1913 dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n");
1915 chip->read = READING_U16;
1916 chip->write = WRITING_U16;
1918 dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n");
1920 chip->read = READING_U32;
1921 chip->write = WRITING_U32;
1924 /* Now Initialize all register settings required for this chip */
1929 if ((chip_info->com_mode == DMA_TRANSFER)
1930 && ((pl022->master_info)->enable_dma)) {
1931 chip->enable_dma = true;
1932 dev_dbg(&spi->dev, "DMA mode set in controller state\n");
1933 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
1934 SSP_DMACR_MASK_RXDMAE, 0);
1935 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
1936 SSP_DMACR_MASK_TXDMAE, 1);
1938 chip->enable_dma = false;
1939 dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n");
1940 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
1941 SSP_DMACR_MASK_RXDMAE, 0);
1942 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
1943 SSP_DMACR_MASK_TXDMAE, 1);
1946 chip->cpsr = clk_freq.cpsdvsr;
1948 /* Special setup for the ST micro extended control registers */
1949 if (pl022->vendor->extended_cr) {
1952 if (pl022->vendor->pl023) {
1953 /* These bits are only in the PL023 */
1954 SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay,
1955 SSP_CR1_MASK_FBCLKDEL_ST, 13);
1957 /* These bits are in the PL022 but not PL023 */
1958 SSP_WRITE_BITS(chip->cr0, chip_info->duplex,
1959 SSP_CR0_MASK_HALFDUP_ST, 5);
1960 SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len,
1961 SSP_CR0_MASK_CSS_ST, 16);
1962 SSP_WRITE_BITS(chip->cr0, chip_info->iface,
1963 SSP_CR0_MASK_FRF_ST, 21);
1964 SSP_WRITE_BITS(chip->cr1, chip_info->wait_state,
1965 SSP_CR1_MASK_MWAIT_ST, 6);
1967 SSP_WRITE_BITS(chip->cr0, bits - 1,
1968 SSP_CR0_MASK_DSS_ST, 0);
1970 if (spi->mode & SPI_LSB_FIRST) {
1977 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4);
1978 SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5);
1979 SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig,
1980 SSP_CR1_MASK_RXIFLSEL_ST, 7);
1981 SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig,
1982 SSP_CR1_MASK_TXIFLSEL_ST, 10);
1984 SSP_WRITE_BITS(chip->cr0, bits - 1,
1985 SSP_CR0_MASK_DSS, 0);
1986 SSP_WRITE_BITS(chip->cr0, chip_info->iface,
1987 SSP_CR0_MASK_FRF, 4);
1990 /* Stuff that is common for all versions */
1991 if (spi->mode & SPI_CPOL)
1992 tmp = SSP_CLK_POL_IDLE_HIGH;
1994 tmp = SSP_CLK_POL_IDLE_LOW;
1995 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6);
1997 if (spi->mode & SPI_CPHA)
1998 tmp = SSP_CLK_SECOND_EDGE;
2000 tmp = SSP_CLK_FIRST_EDGE;
2001 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7);
2003 SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8);
2004 /* Loopback is available on all versions except PL023 */
2005 if (pl022->vendor->loopback) {
2006 if (spi->mode & SPI_LOOP)
2007 tmp = LOOPBACK_ENABLED;
2009 tmp = LOOPBACK_DISABLED;
2010 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0);
2012 SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1);
2013 SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2);
2014 SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD,
2017 /* Save controller_state */
2018 spi_set_ctldata(spi, chip);
2021 spi_set_ctldata(spi, NULL);
2027 * pl022_cleanup - cleanup function registered to SPI master framework
2028 * @spi: spi device which is requesting cleanup
2030 * This function is registered to the SPI framework for this SPI master
2031 * controller. It will free the runtime state of chip.
2033 static void pl022_cleanup(struct spi_device *spi)
2035 struct chip_data *chip = spi_get_ctldata(spi);
2037 spi_set_ctldata(spi, NULL);
2041 static struct pl022_ssp_controller *
2042 pl022_platform_data_dt_get(struct device *dev)
2044 struct device_node *np = dev->of_node;
2045 struct pl022_ssp_controller *pd;
2049 dev_err(dev, "no dt node defined\n");
2053 pd = devm_kzalloc(dev, sizeof(struct pl022_ssp_controller), GFP_KERNEL);
2055 dev_err(dev, "cannot allocate platform data memory\n");
2061 of_property_read_u32(np, "num-cs", &tmp);
2062 pd->num_chipselect = tmp;
2063 of_property_read_u32(np, "pl022,autosuspend-delay",
2064 &pd->autosuspend_delay);
2065 pd->rt = of_property_read_bool(np, "pl022,rt");
2070 static int pl022_probe(struct amba_device *adev, const struct amba_id *id)
2072 struct device *dev = &adev->dev;
2073 struct pl022_ssp_controller *platform_info =
2074 dev_get_platdata(&adev->dev);
2075 struct spi_master *master;
2076 struct pl022 *pl022 = NULL; /*Data for this driver */
2077 struct device_node *np = adev->dev.of_node;
2078 int status = 0, i, num_cs;
2080 dev_info(&adev->dev,
2081 "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid);
2082 if (!platform_info && IS_ENABLED(CONFIG_OF))
2083 platform_info = pl022_platform_data_dt_get(dev);
2085 if (!platform_info) {
2086 dev_err(dev, "probe: no platform data defined\n");
2090 if (platform_info->num_chipselect) {
2091 num_cs = platform_info->num_chipselect;
2093 dev_err(dev, "probe: no chip select defined\n");
2097 /* Allocate master with space for data */
2098 master = spi_alloc_master(dev, sizeof(struct pl022));
2099 if (master == NULL) {
2100 dev_err(&adev->dev, "probe - cannot alloc SPI master\n");
2104 pl022 = spi_master_get_devdata(master);
2105 pl022->master = master;
2106 pl022->master_info = platform_info;
2108 pl022->vendor = id->data;
2109 pl022->chipselects = devm_kzalloc(dev, num_cs * sizeof(int),
2113 * Bus Number Which has been Assigned to this SSP controller
2116 master->bus_num = platform_info->bus_id;
2117 master->num_chipselect = num_cs;
2118 master->cleanup = pl022_cleanup;
2119 master->setup = pl022_setup;
2120 master->auto_runtime_pm = true;
2121 master->transfer_one_message = pl022_transfer_one_message;
2122 master->unprepare_transfer_hardware = pl022_unprepare_transfer_hardware;
2123 master->rt = platform_info->rt;
2124 master->dev.of_node = dev->of_node;
2126 if (platform_info->num_chipselect && platform_info->chipselects) {
2127 for (i = 0; i < num_cs; i++)
2128 pl022->chipselects[i] = platform_info->chipselects[i];
2129 } else if (IS_ENABLED(CONFIG_OF)) {
2130 for (i = 0; i < num_cs; i++) {
2131 int cs_gpio = of_get_named_gpio(np, "cs-gpios", i);
2133 if (cs_gpio == -EPROBE_DEFER) {
2134 status = -EPROBE_DEFER;
2138 pl022->chipselects[i] = cs_gpio;
2140 if (gpio_is_valid(cs_gpio)) {
2141 if (devm_gpio_request(dev, cs_gpio, "ssp-pl022"))
2143 "could not request %d gpio\n",
2145 else if (gpio_direction_output(cs_gpio, 1))
2147 "could set gpio %d as output\n",
2154 * Supports mode 0-3, loopback, and active low CS. Transfers are
2155 * always MS bit first on the original pl022.
2157 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
2158 if (pl022->vendor->extended_cr)
2159 master->mode_bits |= SPI_LSB_FIRST;
2161 dev_dbg(&adev->dev, "BUSNO: %d\n", master->bus_num);
2163 status = amba_request_regions(adev, NULL);
2165 goto err_no_ioregion;
2167 pl022->phybase = adev->res.start;
2168 pl022->virtbase = devm_ioremap(dev, adev->res.start,
2169 resource_size(&adev->res));
2170 if (pl022->virtbase == NULL) {
2172 goto err_no_ioremap;
2174 dev_info(&adev->dev, "mapped registers from %pa to %p\n",
2175 &adev->res.start, pl022->virtbase);
2177 pl022->clk = devm_clk_get(&adev->dev, NULL);
2178 if (IS_ERR(pl022->clk)) {
2179 status = PTR_ERR(pl022->clk);
2180 dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n");
2184 status = clk_prepare_enable(pl022->clk);
2186 dev_err(&adev->dev, "could not enable SSP/SPI bus clock\n");
2190 /* Initialize transfer pump */
2191 tasklet_init(&pl022->pump_transfers, pump_transfers,
2192 (unsigned long)pl022);
2195 writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)),
2196 SSP_CR1(pl022->virtbase));
2197 load_ssp_default_config(pl022);
2199 status = devm_request_irq(dev, adev->irq[0], pl022_interrupt_handler,
2202 dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status);
2206 /* Get DMA channels, try autoconfiguration first */
2207 status = pl022_dma_autoprobe(pl022);
2209 /* If that failed, use channels from platform_info */
2211 platform_info->enable_dma = 1;
2212 else if (platform_info->enable_dma) {
2213 status = pl022_dma_probe(pl022);
2215 platform_info->enable_dma = 0;
2218 /* Register with the SPI framework */
2219 amba_set_drvdata(adev, pl022);
2220 status = devm_spi_register_master(&adev->dev, master);
2223 "probe - problem registering spi master\n");
2224 goto err_spi_register;
2226 dev_dbg(dev, "probe succeeded\n");
2228 /* let runtime pm put suspend */
2229 if (platform_info->autosuspend_delay > 0) {
2230 dev_info(&adev->dev,
2231 "will use autosuspend for runtime pm, delay %dms\n",
2232 platform_info->autosuspend_delay);
2233 pm_runtime_set_autosuspend_delay(dev,
2234 platform_info->autosuspend_delay);
2235 pm_runtime_use_autosuspend(dev);
2237 pm_runtime_put(dev);
2242 if (platform_info->enable_dma)
2243 pl022_dma_remove(pl022);
2245 clk_disable_unprepare(pl022->clk);
2249 amba_release_regions(adev);
2252 spi_master_put(master);
2257 pl022_remove(struct amba_device *adev)
2259 struct pl022 *pl022 = amba_get_drvdata(adev);
2265 * undo pm_runtime_put() in probe. I assume that we're not
2266 * accessing the primecell here.
2268 pm_runtime_get_noresume(&adev->dev);
2270 load_ssp_default_config(pl022);
2271 if (pl022->master_info->enable_dma)
2272 pl022_dma_remove(pl022);
2274 clk_disable_unprepare(pl022->clk);
2275 amba_release_regions(adev);
2276 tasklet_disable(&pl022->pump_transfers);
2280 #ifdef CONFIG_PM_SLEEP
2281 static int pl022_suspend(struct device *dev)
2283 struct pl022 *pl022 = dev_get_drvdata(dev);
2286 ret = spi_master_suspend(pl022->master);
2288 dev_warn(dev, "cannot suspend master\n");
2292 ret = pm_runtime_force_suspend(dev);
2294 spi_master_resume(pl022->master);
2298 pinctrl_pm_select_sleep_state(dev);
2300 dev_dbg(dev, "suspended\n");
2304 static int pl022_resume(struct device *dev)
2306 struct pl022 *pl022 = dev_get_drvdata(dev);
2309 ret = pm_runtime_force_resume(dev);
2311 dev_err(dev, "problem resuming\n");
2313 /* Start the queue running */
2314 ret = spi_master_resume(pl022->master);
2316 dev_err(dev, "problem starting queue (%d)\n", ret);
2318 dev_dbg(dev, "resumed\n");
2325 static int pl022_runtime_suspend(struct device *dev)
2327 struct pl022 *pl022 = dev_get_drvdata(dev);
2329 clk_disable_unprepare(pl022->clk);
2330 pinctrl_pm_select_idle_state(dev);
2335 static int pl022_runtime_resume(struct device *dev)
2337 struct pl022 *pl022 = dev_get_drvdata(dev);
2339 pinctrl_pm_select_default_state(dev);
2340 clk_prepare_enable(pl022->clk);
2346 static const struct dev_pm_ops pl022_dev_pm_ops = {
2347 SET_SYSTEM_SLEEP_PM_OPS(pl022_suspend, pl022_resume)
2348 SET_PM_RUNTIME_PM_OPS(pl022_runtime_suspend, pl022_runtime_resume, NULL)
2351 static struct vendor_data vendor_arm = {
2355 .extended_cr = false,
2360 static struct vendor_data vendor_st = {
2364 .extended_cr = true,
2369 static struct vendor_data vendor_st_pl023 = {
2373 .extended_cr = true,
2378 static struct amba_id pl022_ids[] = {
2381 * ARM PL022 variant, this has a 16bit wide
2382 * and 8 locations deep TX/RX FIFO
2386 .data = &vendor_arm,
2390 * ST Micro derivative, this has 32bit wide
2391 * and 32 locations deep TX/RX FIFO
2399 * ST-Ericsson derivative "PL023" (this is not
2400 * an official ARM number), this is a PL022 SSP block
2401 * stripped to SPI mode only, it has 32bit wide
2402 * and 32 locations deep TX/RX FIFO but no extended
2407 .data = &vendor_st_pl023,
2412 MODULE_DEVICE_TABLE(amba, pl022_ids);
2414 static struct amba_driver pl022_driver = {
2416 .name = "ssp-pl022",
2417 .pm = &pl022_dev_pm_ops,
2419 .id_table = pl022_ids,
2420 .probe = pl022_probe,
2421 .remove = pl022_remove,
2424 static int __init pl022_init(void)
2426 return amba_driver_register(&pl022_driver);
2428 subsys_initcall(pl022_init);
2430 static void __exit pl022_exit(void)
2432 amba_driver_unregister(&pl022_driver);
2434 module_exit(pl022_exit);
2436 MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
2437 MODULE_DESCRIPTION("PL022 SSP Controller Driver");
2438 MODULE_LICENSE("GPL");