drivers/spi/spi-rockchip.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
   4  * Author: Addy Ke <addy.ke@rock-chips.com>
   5  */
   6
   7 #include <linux/clk.h>
   8 #include <linux/dmaengine.h>
   9 #include <linux/interrupt.h>
  10 #include <linux/module.h>
  11 #include <linux/of.h>
  12 #include <linux/pinctrl/consumer.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/spi/spi.h>
  15 #include <linux/pm_runtime.h>
  16 #include <linux/scatterlist.h>
  17
  18 #define DRIVER_NAME "rockchip-spi"
  19
  20 #define ROCKCHIP_SPI_CLR_BITS(reg, bits) \
  21                 writel_relaxed(readl_relaxed(reg) & ~(bits), reg)
  22 #define ROCKCHIP_SPI_SET_BITS(reg, bits) \
  23                 writel_relaxed(readl_relaxed(reg) | (bits), reg)
  24
  25 /* SPI register offsets */
  26 #define ROCKCHIP_SPI_CTRLR0                     0x0000
  27 #define ROCKCHIP_SPI_CTRLR1                     0x0004
  28 #define ROCKCHIP_SPI_SSIENR                     0x0008
  29 #define ROCKCHIP_SPI_SER                        0x000c
  30 #define ROCKCHIP_SPI_BAUDR                      0x0010
  31 #define ROCKCHIP_SPI_TXFTLR                     0x0014
  32 #define ROCKCHIP_SPI_RXFTLR                     0x0018
  33 #define ROCKCHIP_SPI_TXFLR                      0x001c
  34 #define ROCKCHIP_SPI_RXFLR                      0x0020
  35 #define ROCKCHIP_SPI_SR                         0x0024
  36 #define ROCKCHIP_SPI_IPR                        0x0028
  37 #define ROCKCHIP_SPI_IMR                        0x002c
  38 #define ROCKCHIP_SPI_ISR                        0x0030
  39 #define ROCKCHIP_SPI_RISR                       0x0034
  40 #define ROCKCHIP_SPI_ICR                        0x0038
  41 #define ROCKCHIP_SPI_DMACR                      0x003c
  42 #define ROCKCHIP_SPI_DMATDLR                    0x0040
  43 #define ROCKCHIP_SPI_DMARDLR                    0x0044
  44 #define ROCKCHIP_SPI_VERSION                    0x0048
  45 #define ROCKCHIP_SPI_TXDR                       0x0400
  46 #define ROCKCHIP_SPI_RXDR                       0x0800
  47
  48 /* Bit fields in CTRLR0 */
  49 #define CR0_DFS_OFFSET                          0
  50 #define CR0_DFS_4BIT                            0x0
  51 #define CR0_DFS_8BIT                            0x1
  52 #define CR0_DFS_16BIT                           0x2
  53
  54 #define CR0_CFS_OFFSET                          2
  55
  56 #define CR0_SCPH_OFFSET                         6
  57
  58 #define CR0_SCPOL_OFFSET                        7
  59
  60 #define CR0_CSM_OFFSET                          8
  61 #define CR0_CSM_KEEP                            0x0
  62 /* ss_n be high for half sclk_out cycles */
  63 #define CR0_CSM_HALF                            0X1
  64 /* ss_n be high for one sclk_out cycle */
  65 #define CR0_CSM_ONE                                     0x2
  66
  67 /* ss_n to sclk_out delay */
  68 #define CR0_SSD_OFFSET                          10
  69 /*
  70  * The period between ss_n active and
  71  * sclk_out active is half sclk_out cycles
  72  */
  73 #define CR0_SSD_HALF                            0x0
  74 /*
  75  * The period between ss_n active and
  76  * sclk_out active is one sclk_out cycle
  77  */
  78 #define CR0_SSD_ONE                                     0x1
  79
  80 #define CR0_EM_OFFSET                           11
  81 #define CR0_EM_LITTLE                           0x0
  82 #define CR0_EM_BIG                                      0x1
  83
  84 #define CR0_FBM_OFFSET                          12
  85 #define CR0_FBM_MSB                                     0x0
  86 #define CR0_FBM_LSB                                     0x1
  87
  88 #define CR0_BHT_OFFSET                          13
  89 #define CR0_BHT_16BIT                           0x0
  90 #define CR0_BHT_8BIT                            0x1
  91
  92 #define CR0_RSD_OFFSET                          14
  93 #define CR0_RSD_MAX                             0x3
  94
  95 #define CR0_FRF_OFFSET                          16
  96 #define CR0_FRF_SPI                                     0x0
  97 #define CR0_FRF_SSP                                     0x1
  98 #define CR0_FRF_MICROWIRE                       0x2
  99
 100 #define CR0_XFM_OFFSET                          18
 101 #define CR0_XFM_MASK                            (0x03 << SPI_XFM_OFFSET)
 102 #define CR0_XFM_TR                                      0x0
 103 #define CR0_XFM_TO                                      0x1
 104 #define CR0_XFM_RO                                      0x2
 105
 106 #define CR0_OPM_OFFSET                          20
 107 #define CR0_OPM_MASTER                          0x0
 108 #define CR0_OPM_SLAVE                           0x1
 109
 110 #define CR0_SOI_OFFSET                          23
 111
 112 #define CR0_MTM_OFFSET                          0x21
 113
 114 /* Bit fields in SER, 2bit */
 115 #define SER_MASK                                        0x3
 116
 117 /* Bit fields in BAUDR */
 118 #define BAUDR_SCKDV_MIN                         2
 119 #define BAUDR_SCKDV_MAX                         65534
 120
 121 /* Bit fields in SR, 6bit */
 122 #define SR_MASK                                         0x3f
 123 #define SR_BUSY                                         (1 << 0)
 124 #define SR_TF_FULL                                      (1 << 1)
 125 #define SR_TF_EMPTY                                     (1 << 2)
 126 #define SR_RF_EMPTY                                     (1 << 3)
 127 #define SR_RF_FULL                                      (1 << 4)
 128 #define SR_SLAVE_TX_BUSY                                (1 << 5)
 129
 130 /* Bit fields in ISR, IMR, ISR, RISR, 5bit */
 131 #define INT_MASK                                        0x1f
 132 #define INT_TF_EMPTY                            (1 << 0)
 133 #define INT_TF_OVERFLOW                         (1 << 1)
 134 #define INT_RF_UNDERFLOW                        (1 << 2)
 135 #define INT_RF_OVERFLOW                         (1 << 3)
 136 #define INT_RF_FULL                                     (1 << 4)
 137
 138 /* Bit fields in ICR, 4bit */
 139 #define ICR_MASK                                        0x0f
 140 #define ICR_ALL                                         (1 << 0)
 141 #define ICR_RF_UNDERFLOW                        (1 << 1)
 142 #define ICR_RF_OVERFLOW                         (1 << 2)
 143 #define ICR_TF_OVERFLOW                         (1 << 3)
 144
 145 /* Bit fields in DMACR */
 146 #define RF_DMA_EN                                       (1 << 0)
 147 #define TF_DMA_EN                                       (1 << 1)
 148
 149 /* Driver state flags */
 150 #define RXDMA                                   (1 << 0)
 151 #define TXDMA                                   (1 << 1)
 152
 153 /* sclk_out: spi master internal logic in rk3x can support 50Mhz */
 154 #define MAX_SCLK_OUT                            50000000U
 155
 156 /*
 157  * SPI_CTRLR1 is 16-bits, so we should support lengths of 0xffff + 1. However,
 158  * the controller seems to hang when given 0x10000, so stick with this for now.
 159  */
 160 #define ROCKCHIP_SPI_MAX_TRANLEN                0xffff
 161
 162 /* 2 for native cs, 2 for cs-gpio */
 163 #define ROCKCHIP_SPI_MAX_CS_NUM                 4
 164 #define ROCKCHIP_SPI_VER2_TYPE1                 0x05EC0002
 165 #define ROCKCHIP_SPI_VER2_TYPE2                 0x00110002
 166
 167 #define ROCKCHIP_AUTOSUSPEND_TIMEOUT            2000
 168
 169 struct rockchip_spi {
 170         struct device *dev;
 171
 172         struct clk *spiclk;
 173         struct clk *apb_pclk;
 174
 175         void __iomem *regs;
 176         dma_addr_t dma_addr_rx;
 177         dma_addr_t dma_addr_tx;
 178
 179         const void *tx;
 180         void *rx;
 181         unsigned int tx_left;
 182         unsigned int rx_left;
 183
 184         atomic_t state;
 185
 186         /*depth of the FIFO buffer */
 187         u32 fifo_len;
 188         /* frequency of spiclk */
 189         u32 freq;
 190
 191         u8 n_bytes;
 192         u8 rsd;
 193
 194         bool cs_asserted[ROCKCHIP_SPI_MAX_CS_NUM];
 195
 196         bool slave_abort;
 197 };
 198
 199 static inline void spi_enable_chip(struct rockchip_spi *rs, bool enable)
 200 {
 201         writel_relaxed((enable ? 1U : 0U), rs->regs + ROCKCHIP_SPI_SSIENR);
 202 }
 203
 204 static inline void wait_for_tx_idle(struct rockchip_spi *rs, bool slave_mode)
 205 {
 206         unsigned long timeout = jiffies + msecs_to_jiffies(5);
 207
 208         do {
 209                 if (slave_mode) {
 210                         if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_SLAVE_TX_BUSY) &&
 211                             !((readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY)))
 212                                 return;
 213                 } else {
 214                         if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY))
 215                                 return;
 216                 }
 217         } while (!time_after(jiffies, timeout));
 218
 219         dev_warn(rs->dev, "spi controller is in busy state!\n");
 220 }
 221
 222 static u32 get_fifo_len(struct rockchip_spi *rs)
 223 {
 224         u32 ver;
 225
 226         ver = readl_relaxed(rs->regs + ROCKCHIP_SPI_VERSION);
 227
 228         switch (ver) {
 229         case ROCKCHIP_SPI_VER2_TYPE1:
 230         case ROCKCHIP_SPI_VER2_TYPE2:
 231                 return 64;
 232         default:
 233                 return 32;
 234         }
 235 }
 236
 237 static void rockchip_spi_set_cs(struct spi_device *spi, bool enable)
 238 {
 239         struct spi_controller *ctlr = spi->controller;
 240         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 241         bool cs_asserted = spi->mode & SPI_CS_HIGH ? enable : !enable;
 242
 243         /* Return immediately for no-op */
 244         if (cs_asserted == rs->cs_asserted[spi->chip_select])
 245                 return;
 246
 247         if (cs_asserted) {
 248                 /* Keep things powered as long as CS is asserted */
 249                 pm_runtime_get_sync(rs->dev);
 250
 251                 if (spi->cs_gpiod)
 252                         ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, 1);
 253                 else
 254                         ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, BIT(spi->chip_select));
 255         } else {
 256                 if (spi->cs_gpiod)
 257                         ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, 1);
 258                 else
 259                         ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, BIT(spi->chip_select));
 260
 261                 /* Drop reference from when we first asserted CS */
 262                 pm_runtime_put(rs->dev);
 263         }
 264
 265         rs->cs_asserted[spi->chip_select] = cs_asserted;
 266 }
 267
 268 static void rockchip_spi_handle_err(struct spi_controller *ctlr,
 269                                     struct spi_message *msg)
 270 {
 271         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 272
 273         /* stop running spi transfer
 274          * this also flushes both rx and tx fifos
 275          */
 276         spi_enable_chip(rs, false);
 277
 278         /* make sure all interrupts are masked */
 279         writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
 280
 281         if (atomic_read(&rs->state) & TXDMA)
 282                 dmaengine_terminate_async(ctlr->dma_tx);
 283
 284         if (atomic_read(&rs->state) & RXDMA)
 285                 dmaengine_terminate_async(ctlr->dma_rx);
 286 }
 287
 288 static void rockchip_spi_pio_writer(struct rockchip_spi *rs)
 289 {
 290         u32 tx_free = rs->fifo_len - readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFLR);
 291         u32 words = min(rs->tx_left, tx_free);
 292
 293         rs->tx_left -= words;
 294         for (; words; words--) {
 295                 u32 txw;
 296
 297                 if (rs->n_bytes == 1)
 298                         txw = *(u8 *)rs->tx;
 299                 else
 300                         txw = *(u16 *)rs->tx;
 301
 302                 writel_relaxed(txw, rs->regs + ROCKCHIP_SPI_TXDR);
 303                 rs->tx += rs->n_bytes;
 304         }
 305 }
 306
 307 static void rockchip_spi_pio_reader(struct rockchip_spi *rs)
 308 {
 309         u32 words = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
 310         u32 rx_left = (rs->rx_left > words) ? rs->rx_left - words : 0;
 311
 312         /* the hardware doesn't allow us to change fifo threshold
 313          * level while spi is enabled, so instead make sure to leave
 314          * enough words in the rx fifo to get the last interrupt
 315          * exactly when all words have been received
 316          */
 317         if (rx_left) {
 318                 u32 ftl = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFTLR) + 1;
 319
 320                 if (rx_left < ftl) {
 321                         rx_left = ftl;
 322                         words = rs->rx_left - rx_left;
 323                 }
 324         }
 325
 326         rs->rx_left = rx_left;
 327         for (; words; words--) {
 328                 u32 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
 329
 330                 if (!rs->rx)
 331                         continue;
 332
 333                 if (rs->n_bytes == 1)
 334                         *(u8 *)rs->rx = (u8)rxw;
 335                 else
 336                         *(u16 *)rs->rx = (u16)rxw;
 337                 rs->rx += rs->n_bytes;
 338         }
 339 }
 340
 341 static irqreturn_t rockchip_spi_isr(int irq, void *dev_id)
 342 {
 343         struct spi_controller *ctlr = dev_id;
 344         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 345
 346         if (rs->tx_left)
 347                 rockchip_spi_pio_writer(rs);
 348
 349         rockchip_spi_pio_reader(rs);
 350         if (!rs->rx_left) {
 351                 spi_enable_chip(rs, false);
 352                 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
 353                 spi_finalize_current_transfer(ctlr);
 354         }
 355
 356         return IRQ_HANDLED;
 357 }
 358
 359 static int rockchip_spi_prepare_irq(struct rockchip_spi *rs,
 360                 struct spi_transfer *xfer)
 361 {
 362         rs->tx = xfer->tx_buf;
 363         rs->rx = xfer->rx_buf;
 364         rs->tx_left = rs->tx ? xfer->len / rs->n_bytes : 0;
 365         rs->rx_left = xfer->len / rs->n_bytes;
 366
 367         writel_relaxed(INT_RF_FULL, rs->regs + ROCKCHIP_SPI_IMR);
 368         spi_enable_chip(rs, true);
 369
 370         if (rs->tx_left)
 371                 rockchip_spi_pio_writer(rs);
 372
 373         /* 1 means the transfer is in progress */
 374         return 1;
 375 }
 376
 377 static void rockchip_spi_dma_rxcb(void *data)
 378 {
 379         struct spi_controller *ctlr = data;
 380         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 381         int state = atomic_fetch_andnot(RXDMA, &rs->state);
 382
 383         if (state & TXDMA && !rs->slave_abort)
 384                 return;
 385
 386         spi_enable_chip(rs, false);
 387         spi_finalize_current_transfer(ctlr);
 388 }
 389
 390 static void rockchip_spi_dma_txcb(void *data)
 391 {
 392         struct spi_controller *ctlr = data;
 393         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 394         int state = atomic_fetch_andnot(TXDMA, &rs->state);
 395
 396         if (state & RXDMA && !rs->slave_abort)
 397                 return;
 398
 399         /* Wait until the FIFO data completely. */
 400         wait_for_tx_idle(rs, ctlr->slave);
 401
 402         spi_enable_chip(rs, false);
 403         spi_finalize_current_transfer(ctlr);
 404 }
 405
 406 static u32 rockchip_spi_calc_burst_size(u32 data_len)
 407 {
 408         u32 i;
 409
 410         /* burst size: 1, 2, 4, 8 */
 411         for (i = 1; i < 8; i <<= 1) {
 412                 if (data_len & i)
 413                         break;
 414         }
 415
 416         return i;
 417 }
 418
 419 static int rockchip_spi_prepare_dma(struct rockchip_spi *rs,
 420                 struct spi_controller *ctlr, struct spi_transfer *xfer)
 421 {
 422         struct dma_async_tx_descriptor *rxdesc, *txdesc;
 423
 424         atomic_set(&rs->state, 0);
 425
 426         rxdesc = NULL;
 427         if (xfer->rx_buf) {
 428                 struct dma_slave_config rxconf = {
 429                         .direction = DMA_DEV_TO_MEM,
 430                         .src_addr = rs->dma_addr_rx,
 431                         .src_addr_width = rs->n_bytes,
 432                         .src_maxburst = rockchip_spi_calc_burst_size(xfer->len /
 433                                                                      rs->n_bytes),
 434                 };
 435
 436                 dmaengine_slave_config(ctlr->dma_rx, &rxconf);
 437
 438                 rxdesc = dmaengine_prep_slave_sg(
 439                                 ctlr->dma_rx,
 440                                 xfer->rx_sg.sgl, xfer->rx_sg.nents,
 441                                 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
 442                 if (!rxdesc)
 443                         return -EINVAL;
 444
 445                 rxdesc->callback = rockchip_spi_dma_rxcb;
 446                 rxdesc->callback_param = ctlr;
 447         }
 448
 449         txdesc = NULL;
 450         if (xfer->tx_buf) {
 451                 struct dma_slave_config txconf = {
 452                         .direction = DMA_MEM_TO_DEV,
 453                         .dst_addr = rs->dma_addr_tx,
 454                         .dst_addr_width = rs->n_bytes,
 455                         .dst_maxburst = rs->fifo_len / 4,
 456                 };
 457
 458                 dmaengine_slave_config(ctlr->dma_tx, &txconf);
 459
 460                 txdesc = dmaengine_prep_slave_sg(
 461                                 ctlr->dma_tx,
 462                                 xfer->tx_sg.sgl, xfer->tx_sg.nents,
 463                                 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
 464                 if (!txdesc) {
 465                         if (rxdesc)
 466                                 dmaengine_terminate_sync(ctlr->dma_rx);
 467                         return -EINVAL;
 468                 }
 469
 470                 txdesc->callback = rockchip_spi_dma_txcb;
 471                 txdesc->callback_param = ctlr;
 472         }
 473
 474         /* rx must be started before tx due to spi instinct */
 475         if (rxdesc) {
 476                 atomic_or(RXDMA, &rs->state);
 477                 dmaengine_submit(rxdesc);
 478                 dma_async_issue_pending(ctlr->dma_rx);
 479         }
 480
 481         spi_enable_chip(rs, true);
 482
 483         if (txdesc) {
 484                 atomic_or(TXDMA, &rs->state);
 485                 dmaengine_submit(txdesc);
 486                 dma_async_issue_pending(ctlr->dma_tx);
 487         }
 488
 489         /* 1 means the transfer is in progress */
 490         return 1;
 491 }
 492
 493 static int rockchip_spi_config(struct rockchip_spi *rs,
 494                 struct spi_device *spi, struct spi_transfer *xfer,
 495                 bool use_dma, bool slave_mode)
 496 {
 497         u32 cr0 = CR0_FRF_SPI  << CR0_FRF_OFFSET
 498                 | CR0_BHT_8BIT << CR0_BHT_OFFSET
 499                 | CR0_SSD_ONE  << CR0_SSD_OFFSET
 500                 | CR0_EM_BIG   << CR0_EM_OFFSET;
 501         u32 cr1;
 502         u32 dmacr = 0;
 503
 504         if (slave_mode)
 505                 cr0 |= CR0_OPM_SLAVE << CR0_OPM_OFFSET;
 506         rs->slave_abort = false;
 507
 508         cr0 |= rs->rsd << CR0_RSD_OFFSET;
 509         cr0 |= (spi->mode & 0x3U) << CR0_SCPH_OFFSET;
 510         if (spi->mode & SPI_LSB_FIRST)
 511                 cr0 |= CR0_FBM_LSB << CR0_FBM_OFFSET;
 512         if (spi->mode & SPI_CS_HIGH)
 513                 cr0 |= BIT(spi->chip_select) << CR0_SOI_OFFSET;
 514
 515         if (xfer->rx_buf && xfer->tx_buf)
 516                 cr0 |= CR0_XFM_TR << CR0_XFM_OFFSET;
 517         else if (xfer->rx_buf)
 518                 cr0 |= CR0_XFM_RO << CR0_XFM_OFFSET;
 519         else if (use_dma)
 520                 cr0 |= CR0_XFM_TO << CR0_XFM_OFFSET;
 521
 522         switch (xfer->bits_per_word) {
 523         case 4:
 524                 cr0 |= CR0_DFS_4BIT << CR0_DFS_OFFSET;
 525                 cr1 = xfer->len - 1;
 526                 break;
 527         case 8:
 528                 cr0 |= CR0_DFS_8BIT << CR0_DFS_OFFSET;
 529                 cr1 = xfer->len - 1;
 530                 break;
 531         case 16:
 532                 cr0 |= CR0_DFS_16BIT << CR0_DFS_OFFSET;
 533                 cr1 = xfer->len / 2 - 1;
 534                 break;
 535         default:
 536                 /* we only whitelist 4, 8 and 16 bit words in
 537                  * ctlr->bits_per_word_mask, so this shouldn't
 538                  * happen
 539                  */
 540                 dev_err(rs->dev, "unknown bits per word: %d\n",
 541                         xfer->bits_per_word);
 542                 return -EINVAL;
 543         }
 544
 545         if (use_dma) {
 546                 if (xfer->tx_buf)
 547                         dmacr |= TF_DMA_EN;
 548                 if (xfer->rx_buf)
 549                         dmacr |= RF_DMA_EN;
 550         }
 551
 552         writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
 553         writel_relaxed(cr1, rs->regs + ROCKCHIP_SPI_CTRLR1);
 554
 555         /* unfortunately setting the fifo threshold level to generate an
 556          * interrupt exactly when the fifo is full doesn't seem to work,
 557          * so we need the strict inequality here
 558          */
 559         if ((xfer->len / rs->n_bytes) < rs->fifo_len)
 560                 writel_relaxed(xfer->len / rs->n_bytes - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
 561         else
 562                 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
 563
 564         writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_DMATDLR);
 565         writel_relaxed(rockchip_spi_calc_burst_size(xfer->len / rs->n_bytes) - 1,
 566                        rs->regs + ROCKCHIP_SPI_DMARDLR);
 567         writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR);
 568
 569         /* the hardware only supports an even clock divisor, so
 570          * round divisor = spiclk / speed up to nearest even number
 571          * so that the resulting speed is <= the requested speed
 572          */
 573         writel_relaxed(2 * DIV_ROUND_UP(rs->freq, 2 * xfer->speed_hz),
 574                         rs->regs + ROCKCHIP_SPI_BAUDR);
 575
 576         return 0;
 577 }
 578
 579 static size_t rockchip_spi_max_transfer_size(struct spi_device *spi)
 580 {
 581         return ROCKCHIP_SPI_MAX_TRANLEN;
 582 }
 583
 584 static int rockchip_spi_slave_abort(struct spi_controller *ctlr)
 585 {
 586         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 587
 588         if (atomic_read(&rs->state) & RXDMA)
 589                 dmaengine_terminate_sync(ctlr->dma_rx);
 590         if (atomic_read(&rs->state) & TXDMA)
 591                 dmaengine_terminate_sync(ctlr->dma_tx);
 592         atomic_set(&rs->state, 0);
 593         spi_enable_chip(rs, false);
 594         rs->slave_abort = true;
 595         spi_finalize_current_transfer(ctlr);
 596
 597         return 0;
 598 }
 599
 600 static int rockchip_spi_transfer_one(
 601                 struct spi_controller *ctlr,
 602                 struct spi_device *spi,
 603                 struct spi_transfer *xfer)
 604 {
 605         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 606         int ret;
 607         bool use_dma;
 608
 609         /* Zero length transfers won't trigger an interrupt on completion */
 610         if (!xfer->len) {
 611                 spi_finalize_current_transfer(ctlr);
 612                 return 1;
 613         }
 614
 615         WARN_ON(readl_relaxed(rs->regs + ROCKCHIP_SPI_SSIENR) &&
 616                 (readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY));
 617
 618         if (!xfer->tx_buf && !xfer->rx_buf) {
 619                 dev_err(rs->dev, "No buffer for transfer\n");
 620                 return -EINVAL;
 621         }
 622
 623         if (xfer->len > ROCKCHIP_SPI_MAX_TRANLEN) {
 624                 dev_err(rs->dev, "Transfer is too long (%d)\n", xfer->len);
 625                 return -EINVAL;
 626         }
 627
 628         rs->n_bytes = xfer->bits_per_word <= 8 ? 1 : 2;
 629
 630         use_dma = ctlr->can_dma ? ctlr->can_dma(ctlr, spi, xfer) : false;
 631
 632         ret = rockchip_spi_config(rs, spi, xfer, use_dma, ctlr->slave);
 633         if (ret)
 634                 return ret;
 635
 636         if (use_dma)
 637                 return rockchip_spi_prepare_dma(rs, ctlr, xfer);
 638
 639         return rockchip_spi_prepare_irq(rs, xfer);
 640 }
 641
 642 static bool rockchip_spi_can_dma(struct spi_controller *ctlr,
 643                                  struct spi_device *spi,
 644                                  struct spi_transfer *xfer)
 645 {
 646         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 647         unsigned int bytes_per_word = xfer->bits_per_word <= 8 ? 1 : 2;
 648
 649         /* if the numbor of spi words to transfer is less than the fifo
 650          * length we can just fill the fifo and wait for a single irq,
 651          * so don't bother setting up dma
 652          */
 653         return xfer->len / bytes_per_word >= rs->fifo_len;
 654 }
 655
 656 static int rockchip_spi_probe(struct platform_device *pdev)
 657 {
 658         int ret;
 659         struct rockchip_spi *rs;
 660         struct spi_controller *ctlr;
 661         struct resource *mem;
 662         struct device_node *np = pdev->dev.of_node;
 663         u32 rsd_nsecs, num_cs;
 664         bool slave_mode;
 665
 666         slave_mode = of_property_read_bool(np, "spi-slave");
 667
 668         if (slave_mode)
 669                 ctlr = spi_alloc_slave(&pdev->dev,
 670                                 sizeof(struct rockchip_spi));
 671         else
 672                 ctlr = spi_alloc_master(&pdev->dev,
 673                                 sizeof(struct rockchip_spi));
 674
 675         if (!ctlr)
 676                 return -ENOMEM;
 677
 678         platform_set_drvdata(pdev, ctlr);
 679
 680         rs = spi_controller_get_devdata(ctlr);
 681         ctlr->slave = slave_mode;
 682
 683         /* Get basic io resource and map it */
 684         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 685         rs->regs = devm_ioremap_resource(&pdev->dev, mem);
 686         if (IS_ERR(rs->regs)) {
 687                 ret =  PTR_ERR(rs->regs);
 688                 goto err_put_ctlr;
 689         }
 690
 691         rs->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk");
 692         if (IS_ERR(rs->apb_pclk)) {
 693                 dev_err(&pdev->dev, "Failed to get apb_pclk\n");
 694                 ret = PTR_ERR(rs->apb_pclk);
 695                 goto err_put_ctlr;
 696         }
 697
 698         rs->spiclk = devm_clk_get(&pdev->dev, "spiclk");
 699         if (IS_ERR(rs->spiclk)) {
 700                 dev_err(&pdev->dev, "Failed to get spi_pclk\n");
 701                 ret = PTR_ERR(rs->spiclk);
 702                 goto err_put_ctlr;
 703         }
 704
 705         ret = clk_prepare_enable(rs->apb_pclk);
 706         if (ret < 0) {
 707                 dev_err(&pdev->dev, "Failed to enable apb_pclk\n");
 708                 goto err_put_ctlr;
 709         }
 710
 711         ret = clk_prepare_enable(rs->spiclk);
 712         if (ret < 0) {
 713                 dev_err(&pdev->dev, "Failed to enable spi_clk\n");
 714                 goto err_disable_apbclk;
 715         }
 716
 717         spi_enable_chip(rs, false);
 718
 719         ret = platform_get_irq(pdev, 0);
 720         if (ret < 0)
 721                 goto err_disable_spiclk;
 722
 723         ret = devm_request_threaded_irq(&pdev->dev, ret, rockchip_spi_isr, NULL,
 724                         IRQF_ONESHOT, dev_name(&pdev->dev), ctlr);
 725         if (ret)
 726                 goto err_disable_spiclk;
 727
 728         rs->dev = &pdev->dev;
 729         rs->freq = clk_get_rate(rs->spiclk);
 730
 731         if (!of_property_read_u32(pdev->dev.of_node, "rx-sample-delay-ns",
 732                                   &rsd_nsecs)) {
 733                 /* rx sample delay is expressed in parent clock cycles (max 3) */
 734                 u32 rsd = DIV_ROUND_CLOSEST(rsd_nsecs * (rs->freq >> 8),
 735                                 1000000000 >> 8);
 736                 if (!rsd) {
 737                         dev_warn(rs->dev, "%u Hz are too slow to express %u ns delay\n",
 738                                         rs->freq, rsd_nsecs);
 739                 } else if (rsd > CR0_RSD_MAX) {
 740                         rsd = CR0_RSD_MAX;
 741                         dev_warn(rs->dev, "%u Hz are too fast to express %u ns delay, clamping at %u ns\n",
 742                                         rs->freq, rsd_nsecs,
 743                                         CR0_RSD_MAX * 1000000000U / rs->freq);
 744                 }
 745                 rs->rsd = rsd;
 746         }
 747
 748         rs->fifo_len = get_fifo_len(rs);
 749         if (!rs->fifo_len) {
 750                 dev_err(&pdev->dev, "Failed to get fifo length\n");
 751                 ret = -EINVAL;
 752                 goto err_disable_spiclk;
 753         }
 754
 755         pm_runtime_set_autosuspend_delay(&pdev->dev, ROCKCHIP_AUTOSUSPEND_TIMEOUT);
 756         pm_runtime_use_autosuspend(&pdev->dev);
 757         pm_runtime_set_active(&pdev->dev);
 758         pm_runtime_enable(&pdev->dev);
 759
 760         ctlr->auto_runtime_pm = true;
 761         ctlr->bus_num = pdev->id;
 762         ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_LSB_FIRST;
 763         if (slave_mode) {
 764                 ctlr->mode_bits |= SPI_NO_CS;
 765                 ctlr->slave_abort = rockchip_spi_slave_abort;
 766         } else {
 767                 ctlr->flags = SPI_MASTER_GPIO_SS;
 768                 ctlr->max_native_cs = ROCKCHIP_SPI_MAX_CS_NUM;
 769                 /*
 770                  * rk spi0 has two native cs, spi1..5 one cs only
 771                  * if num-cs is missing in the dts, default to 1
 772                  */
 773                 if (of_property_read_u32(np, "num-cs", &num_cs))
 774                         num_cs = 1;
 775                 ctlr->num_chipselect = num_cs;
 776                 ctlr->use_gpio_descriptors = true;
 777         }
 778         ctlr->dev.of_node = pdev->dev.of_node;
 779         ctlr->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8) | SPI_BPW_MASK(4);
 780         ctlr->min_speed_hz = rs->freq / BAUDR_SCKDV_MAX;
 781         ctlr->max_speed_hz = min(rs->freq / BAUDR_SCKDV_MIN, MAX_SCLK_OUT);
 782
 783         ctlr->set_cs = rockchip_spi_set_cs;
 784         ctlr->transfer_one = rockchip_spi_transfer_one;
 785         ctlr->max_transfer_size = rockchip_spi_max_transfer_size;
 786         ctlr->handle_err = rockchip_spi_handle_err;
 787
 788         ctlr->dma_tx = dma_request_chan(rs->dev, "tx");
 789         if (IS_ERR(ctlr->dma_tx)) {
 790                 /* Check tx to see if we need defer probing driver */
 791                 if (PTR_ERR(ctlr->dma_tx) == -EPROBE_DEFER) {
 792                         ret = -EPROBE_DEFER;
 793                         goto err_disable_pm_runtime;
 794                 }
 795                 dev_warn(rs->dev, "Failed to request TX DMA channel\n");
 796                 ctlr->dma_tx = NULL;
 797         }
 798
 799         ctlr->dma_rx = dma_request_chan(rs->dev, "rx");
 800         if (IS_ERR(ctlr->dma_rx)) {
 801                 if (PTR_ERR(ctlr->dma_rx) == -EPROBE_DEFER) {
 802                         ret = -EPROBE_DEFER;
 803                         goto err_free_dma_tx;
 804                 }
 805                 dev_warn(rs->dev, "Failed to request RX DMA channel\n");
 806                 ctlr->dma_rx = NULL;
 807         }
 808
 809         if (ctlr->dma_tx && ctlr->dma_rx) {
 810                 rs->dma_addr_tx = mem->start + ROCKCHIP_SPI_TXDR;
 811                 rs->dma_addr_rx = mem->start + ROCKCHIP_SPI_RXDR;
 812                 ctlr->can_dma = rockchip_spi_can_dma;
 813         }
 814
 815         switch (readl_relaxed(rs->regs + ROCKCHIP_SPI_VERSION)) {
 816         case ROCKCHIP_SPI_VER2_TYPE2:
 817                 ctlr->mode_bits |= SPI_CS_HIGH;
 818                 break;
 819         default:
 820                 break;
 821         }
 822
 823         ret = devm_spi_register_controller(&pdev->dev, ctlr);
 824         if (ret < 0) {
 825                 dev_err(&pdev->dev, "Failed to register controller\n");
 826                 goto err_free_dma_rx;
 827         }
 828
 829         return 0;
 830
 831 err_free_dma_rx:
 832         if (ctlr->dma_rx)
 833                 dma_release_channel(ctlr->dma_rx);
 834 err_free_dma_tx:
 835         if (ctlr->dma_tx)
 836                 dma_release_channel(ctlr->dma_tx);
 837 err_disable_pm_runtime:
 838         pm_runtime_disable(&pdev->dev);
 839 err_disable_spiclk:
 840         clk_disable_unprepare(rs->spiclk);
 841 err_disable_apbclk:
 842         clk_disable_unprepare(rs->apb_pclk);
 843 err_put_ctlr:
 844         spi_controller_put(ctlr);
 845
 846         return ret;
 847 }
 848
 849 static int rockchip_spi_remove(struct platform_device *pdev)
 850 {
 851         struct spi_controller *ctlr = spi_controller_get(platform_get_drvdata(pdev));
 852         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 853
 854         pm_runtime_get_sync(&pdev->dev);
 855
 856         clk_disable_unprepare(rs->spiclk);
 857         clk_disable_unprepare(rs->apb_pclk);
 858
 859         pm_runtime_put_noidle(&pdev->dev);
 860         pm_runtime_disable(&pdev->dev);
 861         pm_runtime_set_suspended(&pdev->dev);
 862
 863         if (ctlr->dma_tx)
 864                 dma_release_channel(ctlr->dma_tx);
 865         if (ctlr->dma_rx)
 866                 dma_release_channel(ctlr->dma_rx);
 867
 868         spi_controller_put(ctlr);
 869
 870         return 0;
 871 }
 872
 873 #ifdef CONFIG_PM_SLEEP
 874 static int rockchip_spi_suspend(struct device *dev)
 875 {
 876         int ret;
 877         struct spi_controller *ctlr = dev_get_drvdata(dev);
 878
 879         ret = spi_controller_suspend(ctlr);
 880         if (ret < 0)
 881                 return ret;
 882
 883         ret = pm_runtime_force_suspend(dev);
 884         if (ret < 0)
 885                 return ret;
 886
 887         pinctrl_pm_select_sleep_state(dev);
 888
 889         return 0;
 890 }
 891
 892 static int rockchip_spi_resume(struct device *dev)
 893 {
 894         int ret;
 895         struct spi_controller *ctlr = dev_get_drvdata(dev);
 896         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 897
 898         pinctrl_pm_select_default_state(dev);
 899
 900         ret = pm_runtime_force_resume(dev);
 901         if (ret < 0)
 902                 return ret;
 903
 904         ret = spi_controller_resume(ctlr);
 905         if (ret < 0) {
 906                 clk_disable_unprepare(rs->spiclk);
 907                 clk_disable_unprepare(rs->apb_pclk);
 908         }
 909
 910         return 0;
 911 }
 912 #endif /* CONFIG_PM_SLEEP */
 913
 914 #ifdef CONFIG_PM
 915 static int rockchip_spi_runtime_suspend(struct device *dev)
 916 {
 917         struct spi_controller *ctlr = dev_get_drvdata(dev);
 918         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 919
 920         clk_disable_unprepare(rs->spiclk);
 921         clk_disable_unprepare(rs->apb_pclk);
 922
 923         return 0;
 924 }
 925
 926 static int rockchip_spi_runtime_resume(struct device *dev)
 927 {
 928         int ret;
 929         struct spi_controller *ctlr = dev_get_drvdata(dev);
 930         struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 931
 932         ret = clk_prepare_enable(rs->apb_pclk);
 933         if (ret < 0)
 934                 return ret;
 935
 936         ret = clk_prepare_enable(rs->spiclk);
 937         if (ret < 0)
 938                 clk_disable_unprepare(rs->apb_pclk);
 939
 940         return 0;
 941 }
 942 #endif /* CONFIG_PM */
 943
 944 static const struct dev_pm_ops rockchip_spi_pm = {
 945         SET_SYSTEM_SLEEP_PM_OPS(rockchip_spi_suspend, rockchip_spi_resume)
 946         SET_RUNTIME_PM_OPS(rockchip_spi_runtime_suspend,
 947                            rockchip_spi_runtime_resume, NULL)
 948 };
 949
 950 static const struct of_device_id rockchip_spi_dt_match[] = {
 951         { .compatible = "rockchip,px30-spi", },
 952         { .compatible = "rockchip,rk3036-spi", },
 953         { .compatible = "rockchip,rk3066-spi", },
 954         { .compatible = "rockchip,rk3188-spi", },
 955         { .compatible = "rockchip,rk3228-spi", },
 956         { .compatible = "rockchip,rk3288-spi", },
 957         { .compatible = "rockchip,rk3308-spi", },
 958         { .compatible = "rockchip,rk3328-spi", },
 959         { .compatible = "rockchip,rk3368-spi", },
 960         { .compatible = "rockchip,rk3399-spi", },
 961         { .compatible = "rockchip,rv1108-spi", },
 962         { .compatible = "rockchip,rv1126-spi", },
 963         { },
 964 };
 965 MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match);
 966
 967 static struct platform_driver rockchip_spi_driver = {
 968         .driver = {
 969                 .name   = DRIVER_NAME,
 970                 .pm = &rockchip_spi_pm,
 971                 .of_match_table = of_match_ptr(rockchip_spi_dt_match),
 972         },
 973         .probe = rockchip_spi_probe,
 974         .remove = rockchip_spi_remove,
 975 };
 976
 977 module_platform_driver(rockchip_spi_driver);
 978
 979 MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
 980 MODULE_DESCRIPTION("ROCKCHIP SPI Controller Driver");
 981 MODULE_LICENSE("GPL v2");