2 * Copyright (c) 2006 Ben Dooks
3 * Copyright 2006-2009 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
12 #include <linux/init.h>
13 #include <linux/spinlock.h>
14 #include <linux/workqueue.h>
15 #include <linux/interrupt.h>
16 #include <linux/delay.h>
17 #include <linux/errno.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
20 #include <linux/platform_device.h>
21 #include <linux/gpio.h>
23 #include <linux/slab.h>
25 #include <linux/spi/spi.h>
26 #include <linux/spi/spi_bitbang.h>
27 #include <linux/spi/s3c24xx.h>
28 #include <linux/module.h>
30 #include <plat/regs-spi.h>
35 #include "spi-s3c24xx-fiq.h"
38 * s3c24xx_spi_devstate - per device data
39 * @hz: Last frequency calculated for @sppre field.
40 * @mode: Last mode setting for the @spcon field.
41 * @spcon: Value to write to the SPCON register.
42 * @sppre: Value to write to the SPPRE register.
44 struct s3c24xx_spi_devstate {
59 /* bitbang has to be first */
60 struct spi_bitbang bitbang;
61 struct completion done;
68 struct fiq_handler fiq_handler;
69 enum spi_fiq_mode fiq_mode;
70 unsigned char fiq_inuse;
71 unsigned char fiq_claimed;
73 void (*set_cs)(struct s3c2410_spi_info *spi,
77 const unsigned char *tx;
81 struct spi_master *master;
82 struct spi_device *curdev;
84 struct s3c2410_spi_info *pdata;
88 #define SPCON_DEFAULT (S3C2410_SPCON_MSTR | S3C2410_SPCON_SMOD_INT)
89 #define SPPIN_DEFAULT (S3C2410_SPPIN_KEEP)
91 static inline struct s3c24xx_spi *to_hw(struct spi_device *sdev)
93 return spi_master_get_devdata(sdev->master);
96 static void s3c24xx_spi_gpiocs(struct s3c2410_spi_info *spi, int cs, int pol)
98 gpio_set_value(spi->pin_cs, pol);
101 static void s3c24xx_spi_chipsel(struct spi_device *spi, int value)
103 struct s3c24xx_spi_devstate *cs = spi->controller_state;
104 struct s3c24xx_spi *hw = to_hw(spi);
105 unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
107 /* change the chipselect state and the state of the spi engine clock */
110 case BITBANG_CS_INACTIVE:
111 hw->set_cs(hw->pdata, spi->chip_select, cspol^1);
112 writeb(cs->spcon, hw->regs + S3C2410_SPCON);
115 case BITBANG_CS_ACTIVE:
116 writeb(cs->spcon | S3C2410_SPCON_ENSCK,
117 hw->regs + S3C2410_SPCON);
118 hw->set_cs(hw->pdata, spi->chip_select, cspol);
123 static int s3c24xx_spi_update_state(struct spi_device *spi,
124 struct spi_transfer *t)
126 struct s3c24xx_spi *hw = to_hw(spi);
127 struct s3c24xx_spi_devstate *cs = spi->controller_state;
133 bpw = t ? t->bits_per_word : spi->bits_per_word;
134 hz = t ? t->speed_hz : spi->max_speed_hz;
140 hz = spi->max_speed_hz;
143 dev_err(&spi->dev, "invalid bits-per-word (%d)\n", bpw);
147 if (spi->mode != cs->mode) {
148 u8 spcon = SPCON_DEFAULT | S3C2410_SPCON_ENSCK;
150 if (spi->mode & SPI_CPHA)
151 spcon |= S3C2410_SPCON_CPHA_FMTB;
153 if (spi->mode & SPI_CPOL)
154 spcon |= S3C2410_SPCON_CPOL_HIGH;
156 cs->mode = spi->mode;
161 clk = clk_get_rate(hw->clk);
162 div = DIV_ROUND_UP(clk, hz * 2) - 1;
167 dev_dbg(&spi->dev, "pre-scaler=%d (wanted %d, got %ld)\n",
168 div, hz, clk / (2 * (div + 1)));
177 static int s3c24xx_spi_setupxfer(struct spi_device *spi,
178 struct spi_transfer *t)
180 struct s3c24xx_spi_devstate *cs = spi->controller_state;
181 struct s3c24xx_spi *hw = to_hw(spi);
184 ret = s3c24xx_spi_update_state(spi, t);
186 writeb(cs->sppre, hw->regs + S3C2410_SPPRE);
191 static int s3c24xx_spi_setup(struct spi_device *spi)
193 struct s3c24xx_spi_devstate *cs = spi->controller_state;
194 struct s3c24xx_spi *hw = to_hw(spi);
197 /* allocate settings on the first call */
199 cs = kzalloc(sizeof(struct s3c24xx_spi_devstate), GFP_KERNEL);
201 dev_err(&spi->dev, "no memory for controller state\n");
205 cs->spcon = SPCON_DEFAULT;
207 spi->controller_state = cs;
210 /* initialise the state from the device */
211 ret = s3c24xx_spi_update_state(spi, NULL);
215 spin_lock(&hw->bitbang.lock);
216 if (!hw->bitbang.busy) {
217 hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
218 /* need to ndelay for 0.5 clocktick ? */
220 spin_unlock(&hw->bitbang.lock);
225 static void s3c24xx_spi_cleanup(struct spi_device *spi)
227 kfree(spi->controller_state);
230 static inline unsigned int hw_txbyte(struct s3c24xx_spi *hw, int count)
232 return hw->tx ? hw->tx[count] : 0;
235 #ifdef CONFIG_SPI_S3C24XX_FIQ
236 /* Support for FIQ based pseudo-DMA to improve the transfer speed.
238 * This code uses the assembly helper in spi_s3c24xx_spi.S which is
239 * used by the FIQ core to move data between main memory and the peripheral
240 * block. Since this is code running on the processor, there is no problem
241 * with cache coherency of the buffers, so we can use any buffer we like.
245 * struct spi_fiq_code - FIQ code and header
246 * @length: The length of the code fragment, excluding this header.
247 * @ack_offset: The offset from @data to the word to place the IRQ ACK bit at.
248 * @data: The code itself to install as a FIQ handler.
250 struct spi_fiq_code {
256 extern struct spi_fiq_code s3c24xx_spi_fiq_txrx;
257 extern struct spi_fiq_code s3c24xx_spi_fiq_tx;
258 extern struct spi_fiq_code s3c24xx_spi_fiq_rx;
261 * ack_bit - turn IRQ into IRQ acknowledgement bit
262 * @irq: The interrupt number
264 * Returns the bit to write to the interrupt acknowledge register.
266 static inline u32 ack_bit(unsigned int irq)
268 return 1 << (irq - IRQ_EINT0);
272 * s3c24xx_spi_tryfiq - attempt to claim and setup FIQ for transfer
273 * @hw: The hardware state.
275 * Claim the FIQ handler (only one can be active at any one time) and
276 * then setup the correct transfer code for this transfer.
278 * This call updates all the necessary state information if successful,
279 * so the caller does not need to do anything more than start the transfer
280 * as normal, since the IRQ will have been re-routed to the FIQ handler.
282 static void s3c24xx_spi_tryfiq(struct s3c24xx_spi *hw)
285 enum spi_fiq_mode mode;
286 struct spi_fiq_code *code;
289 if (!hw->fiq_claimed) {
290 /* try and claim fiq if we haven't got it, and if not
291 * then return and simply use another transfer method */
293 ret = claim_fiq(&hw->fiq_handler);
298 if (hw->tx && !hw->rx)
300 else if (hw->rx && !hw->tx)
303 mode = FIQ_MODE_TXRX;
305 regs.uregs[fiq_rspi] = (long)hw->regs;
306 regs.uregs[fiq_rrx] = (long)hw->rx;
307 regs.uregs[fiq_rtx] = (long)hw->tx + 1;
308 regs.uregs[fiq_rcount] = hw->len - 1;
309 regs.uregs[fiq_rirq] = (long)S3C24XX_VA_IRQ;
313 if (hw->fiq_mode != mode) {
320 code = &s3c24xx_spi_fiq_tx;
323 code = &s3c24xx_spi_fiq_rx;
326 code = &s3c24xx_spi_fiq_txrx;
334 ack_ptr = (u32 *)&code->data[code->ack_offset];
335 *ack_ptr = ack_bit(hw->irq);
337 set_fiq_handler(&code->data, code->length);
340 s3c24xx_set_fiq(hw->irq, true);
347 * s3c24xx_spi_fiqop - FIQ core code callback
348 * @pw: Data registered with the handler
349 * @release: Whether this is a release or a return.
351 * Called by the FIQ code when another module wants to use the FIQ, so
352 * return whether we are currently using this or not and then update our
355 static int s3c24xx_spi_fiqop(void *pw, int release)
357 struct s3c24xx_spi *hw = pw;
364 /* note, we do not need to unroute the FIQ, as the FIQ
365 * vector code de-routes it to signal the end of transfer */
367 hw->fiq_mode = FIQ_MODE_NONE;
377 * s3c24xx_spi_initfiq - setup the information for the FIQ core
378 * @hw: The hardware state.
380 * Setup the fiq_handler block to pass to the FIQ core.
382 static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *hw)
384 hw->fiq_handler.dev_id = hw;
385 hw->fiq_handler.name = dev_name(hw->dev);
386 hw->fiq_handler.fiq_op = s3c24xx_spi_fiqop;
390 * s3c24xx_spi_usefiq - return if we should be using FIQ.
391 * @hw: The hardware state.
393 * Return true if the platform data specifies whether this channel is
394 * allowed to use the FIQ.
396 static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *hw)
398 return hw->pdata->use_fiq;
402 * s3c24xx_spi_usingfiq - return if channel is using FIQ
403 * @spi: The hardware state.
405 * Return whether the channel is currently using the FIQ (separate from
406 * whether the FIQ is claimed).
408 static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *spi)
410 return spi->fiq_inuse;
414 static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *s) { }
415 static inline void s3c24xx_spi_tryfiq(struct s3c24xx_spi *s) { }
416 static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *s) { return false; }
417 static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *s) { return false; }
419 #endif /* CONFIG_SPI_S3C24XX_FIQ */
421 static int s3c24xx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
423 struct s3c24xx_spi *hw = to_hw(spi);
430 init_completion(&hw->done);
433 if (s3c24xx_spi_usefiq(hw) && t->len >= 3)
434 s3c24xx_spi_tryfiq(hw);
436 /* send the first byte */
437 writeb(hw_txbyte(hw, 0), hw->regs + S3C2410_SPTDAT);
439 wait_for_completion(&hw->done);
443 static irqreturn_t s3c24xx_spi_irq(int irq, void *dev)
445 struct s3c24xx_spi *hw = dev;
446 unsigned int spsta = readb(hw->regs + S3C2410_SPSTA);
447 unsigned int count = hw->count;
449 if (spsta & S3C2410_SPSTA_DCOL) {
450 dev_dbg(hw->dev, "data-collision\n");
455 if (!(spsta & S3C2410_SPSTA_READY)) {
456 dev_dbg(hw->dev, "spi not ready for tx?\n");
461 if (!s3c24xx_spi_usingfiq(hw)) {
465 hw->rx[count] = readb(hw->regs + S3C2410_SPRDAT);
470 writeb(hw_txbyte(hw, count), hw->regs + S3C2410_SPTDAT);
478 hw->rx[hw->len-1] = readb(hw->regs + S3C2410_SPRDAT);
487 static void s3c24xx_spi_initialsetup(struct s3c24xx_spi *hw)
489 /* for the moment, permanently enable the clock */
493 /* program defaults into the registers */
495 writeb(0xff, hw->regs + S3C2410_SPPRE);
496 writeb(SPPIN_DEFAULT, hw->regs + S3C2410_SPPIN);
497 writeb(SPCON_DEFAULT, hw->regs + S3C2410_SPCON);
500 if (hw->set_cs == s3c24xx_spi_gpiocs)
501 gpio_direction_output(hw->pdata->pin_cs, 1);
503 if (hw->pdata->gpio_setup)
504 hw->pdata->gpio_setup(hw->pdata, 1);
508 static int s3c24xx_spi_probe(struct platform_device *pdev)
510 struct s3c2410_spi_info *pdata;
511 struct s3c24xx_spi *hw;
512 struct spi_master *master;
513 struct resource *res;
516 master = spi_alloc_master(&pdev->dev, sizeof(struct s3c24xx_spi));
517 if (master == NULL) {
518 dev_err(&pdev->dev, "No memory for spi_master\n");
522 hw = spi_master_get_devdata(master);
523 memset(hw, 0, sizeof(struct s3c24xx_spi));
526 hw->pdata = pdata = dev_get_platdata(&pdev->dev);
527 hw->dev = &pdev->dev;
530 dev_err(&pdev->dev, "No platform data supplied\n");
535 platform_set_drvdata(pdev, hw);
536 init_completion(&hw->done);
538 /* initialise fiq handler */
540 s3c24xx_spi_initfiq(hw);
542 /* setup the master state. */
544 /* the spi->mode bits understood by this driver: */
545 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
547 master->num_chipselect = hw->pdata->num_cs;
548 master->bus_num = pdata->bus_num;
550 /* setup the state for the bitbang driver */
552 hw->bitbang.master = hw->master;
553 hw->bitbang.setup_transfer = s3c24xx_spi_setupxfer;
554 hw->bitbang.chipselect = s3c24xx_spi_chipsel;
555 hw->bitbang.txrx_bufs = s3c24xx_spi_txrx;
557 hw->master->setup = s3c24xx_spi_setup;
558 hw->master->cleanup = s3c24xx_spi_cleanup;
560 dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang);
562 /* find and map our resources */
563 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
564 hw->regs = devm_ioremap_resource(&pdev->dev, res);
565 if (IS_ERR(hw->regs)) {
566 err = PTR_ERR(hw->regs);
570 hw->irq = platform_get_irq(pdev, 0);
572 dev_err(&pdev->dev, "No IRQ specified\n");
577 err = devm_request_irq(&pdev->dev, hw->irq, s3c24xx_spi_irq, 0,
580 dev_err(&pdev->dev, "Cannot claim IRQ\n");
584 hw->clk = devm_clk_get(&pdev->dev, "spi");
585 if (IS_ERR(hw->clk)) {
586 dev_err(&pdev->dev, "No clock for device\n");
587 err = PTR_ERR(hw->clk);
591 /* setup any gpio we can */
593 if (!pdata->set_cs) {
594 if (pdata->pin_cs < 0) {
595 dev_err(&pdev->dev, "No chipselect pin\n");
600 err = devm_gpio_request(&pdev->dev, pdata->pin_cs,
601 dev_name(&pdev->dev));
603 dev_err(&pdev->dev, "Failed to get gpio for cs\n");
607 hw->set_cs = s3c24xx_spi_gpiocs;
608 gpio_direction_output(pdata->pin_cs, 1);
610 hw->set_cs = pdata->set_cs;
612 s3c24xx_spi_initialsetup(hw);
614 /* register our spi controller */
616 err = spi_bitbang_start(&hw->bitbang);
618 dev_err(&pdev->dev, "Failed to register SPI master\n");
625 clk_disable(hw->clk);
628 spi_master_put(hw->master);
632 static int s3c24xx_spi_remove(struct platform_device *dev)
634 struct s3c24xx_spi *hw = platform_get_drvdata(dev);
636 spi_bitbang_stop(&hw->bitbang);
637 clk_disable(hw->clk);
638 spi_master_put(hw->master);
645 static int s3c24xx_spi_suspend(struct device *dev)
647 struct s3c24xx_spi *hw = dev_get_drvdata(dev);
649 if (hw->pdata && hw->pdata->gpio_setup)
650 hw->pdata->gpio_setup(hw->pdata, 0);
652 clk_disable(hw->clk);
656 static int s3c24xx_spi_resume(struct device *dev)
658 struct s3c24xx_spi *hw = dev_get_drvdata(dev);
660 s3c24xx_spi_initialsetup(hw);
664 static const struct dev_pm_ops s3c24xx_spi_pmops = {
665 .suspend = s3c24xx_spi_suspend,
666 .resume = s3c24xx_spi_resume,
669 #define S3C24XX_SPI_PMOPS &s3c24xx_spi_pmops
671 #define S3C24XX_SPI_PMOPS NULL
672 #endif /* CONFIG_PM */
674 MODULE_ALIAS("platform:s3c2410-spi");
675 static struct platform_driver s3c24xx_spi_driver = {
676 .probe = s3c24xx_spi_probe,
677 .remove = s3c24xx_spi_remove,
679 .name = "s3c2410-spi",
680 .owner = THIS_MODULE,
681 .pm = S3C24XX_SPI_PMOPS,
684 module_platform_driver(s3c24xx_spi_driver);
686 MODULE_DESCRIPTION("S3C24XX SPI Driver");
687 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
688 MODULE_LICENSE("GPL");